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ppc4xx: Set default PCI device ID for 405EP boards
[people/ms/u-boot.git] / cpu / ppc4xx / 4xx_pci.c
CommitLineData
c609719b
WD		 1/*-----------------------------------------------------------------------------+
2 *
3 * This source code has been made available to you by IBM on an AS-IS
4 * basis. Anyone receiving this source is licensed under IBM
5 * copyrights to use it in any way he or she deems fit, including
6 * copying it, modifying it, compiling it, and redistributing it either
7 * with or without modifications. No license under IBM patents or
8 * patent applications is to be implied by the copyright license.
9 *
10 * Any user of this software should understand that IBM cannot provide
11 * technical support for this software and will not be responsible for
12 * any consequences resulting from the use of this software.
13 *
14 * Any person who transfers this source code or any derivative work
15 * must include the IBM copyright notice, this paragraph, and the
16 * preceding two paragraphs in the transferred software.
17 *
18 * COPYRIGHT I B M CORPORATION 1995
19 * LICENSED MATERIAL - PROGRAM PROPERTY OF I B M
20 *-----------------------------------------------------------------------------*/
21/*----------------------------------------------------------------------------+
22 *
23 * File Name: 405gp_pci.c
24 *
25 * Function: Initialization code for the 405GP PCI Configuration regs.
26 *
27 * Author: Mark Game
28 *
29 * Change Activity-
30 *
31 * Date Description of Change BY
32 * --------- --------------------- ---
33 * 09-Sep-98 Created MCG
34 * 02-Nov-98 Removed External arbiter selected message JWB
35 * 27-Nov-98 Zero out PTMBAR2 and disable in PTM2MS JWB
36 * 04-Jan-99 Zero out other unused PMM and PTM regs. Change bus scan MCG
37 * from (0 to n) to (1 to n).
38 * 17-May-99 Port to Walnut JWB
39 * 17-Jun-99 Updated for VGA support JWB
40 * 21-Jun-99 Updated to allow SRAM region to be a target from PCI bus JWB
41 * 19-Jul-99 Updated for 405GP pass 1 errata #26 (Low PCI subsequent MCG
42 * target latency timer values are not supported).
43 * Should be fixed in pass 2.
44 * 09-Sep-99 Removed use of PTM2 since the SRAM region no longer needs JWB
45 * to be a PCI target. Zero out PTMBAR2 and disable in PTM2MS.
46 * 10-Dec-99 Updated PCI_Write_CFG_Reg for pass2 errata #6 JWB
47 * 11-Jan-00 Ensure PMMxMAs disabled before setting PMMxLAs. This is not
48 * really required after a reset since PMMxMAs are already
53677ef1 49 * disabled but is a good practice nonetheless. JWB
c609719b
WD		 50 * 12-Jun-01 stefan.roese@esd-electronics.com
51 * - PCI host/adapter handling reworked
52 * 09-Jul-01 stefan.roese@esd-electronics.com
53 * - PCI host now configures from device 0 (not 1) to max_dev,
54 * (host configures itself)
55 * - On CPCI-405 pci base address and size is generated from
56 * SDRAM and FLASH size (CFG regs not used anymore)
57 * - Some minor changes for CPCI-405-A (adapter version)
58 * 14-Sep-01 stefan.roese@esd-electronics.com
59 * - CONFIG_PCI_SCAN_SHOW added to print pci devices upon startup
60 * 28-Sep-01 stefan.roese@esd-electronics.com
61 * - Changed pci master configuration for linux compatibility
62 * (no need for bios_fixup() anymore)
63 * 26-Feb-02 stefan.roese@esd-electronics.com
64 * - Bug fixed in pci configuration (Andrew May)
65 * - Removed pci class code init for CPCI405 board
66 * 15-May-02 stefan.roese@esd-electronics.com
67 * - New vga device handling
68 * 29-May-02 stefan.roese@esd-electronics.com
69 * - PCI class code init added (if defined)
70 *----------------------------------------------------------------------------*/
71
72#include <common.h>
73#include <command.h>
c609719b 74#if !defined(CONFIG_440)
3048bcbf 75#include <asm/4xx_pci.h>
c609719b
WD		 76#endif
77#include <asm/processor.h>
78#include <pci.h>
79
5a1c9ff0
MF		 80#ifdef CONFIG_PCI
81
d87080b7
WD		 82DECLARE_GLOBAL_DATA_PTR;
83
5a1c9ff0
MF		 84/*
85 * Board-specific pci initialization
86 * Platform code can reimplement pci_pre_init() if needed
87 */
88int __pci_pre_init(struct pci_controller *hose)
89{
123f102e
MF		 90#if defined (CONFIG_405EP)
91 /*
92 * Enable the internal PCI arbiter by default.
93 *
94 * On 405EP CPUs the internal arbiter can be controlled
95 * by the I2C strapping EEPROM. If you want to do so
96 * or if you want to disable the arbiter pci_pre_init()
97 * must be reimplemented without enabling the arbiter.
98 * The arbiter is enabled in this place because of
99 * compatibility reasons.
100 */
101 mtdcr(cpc0_pci, mfdcr(cpc0_pci) | CPC0_PCI_ARBIT_EN);
102#endif /* CONFIG_405EP */
103
5a1c9ff0
MF		 104 return 1;
105}
106int pci_pre_init(struct pci_controller *hose) __attribute__((weak, alias("__pci_pre_init")));
c609719b 107
5a1c9ff0 108#if defined(CONFIG_405GP) || defined(CONFIG_405EP)
c609719b 109
2076d0a1
SR		 110#if defined(CONFIG_PMC405)
111ushort pmc405_pci_subsys_deviceid(void);
112#endif
113
c609719b
WD		 114/*#define DEBUG*/
115
d0a1364f
MF		 116int __is_pci_host(struct pci_controller *hose)
117{
118#if defined(CONFIG_405GP)
119 if (mfdcr(strap) & PSR_PCI_ARBIT_EN)
120 return 1;
121#elif defined (CONFIG_405EP)
122 if (mfdcr(cpc0_pci) & CPC0_PCI_ARBIT_EN)
123 return 1;
124#endif
125 return 0;
126}
127int is_pci_host(struct pci_controller *hose) __attribute__((weak, alias("__is_pci_host")));
128
c609719b
WD		 129/*-----------------------------------------------------------------------------+
130 * pci_init. Initializes the 405GP PCI Configuration regs.
131 *-----------------------------------------------------------------------------*/
132void pci_405gp_init(struct pci_controller *hose)
133{
c609719b
WD		 134 int i, reg_num = 0;
135 bd_t *bd = gd->bd;
136
137 unsigned short temp_short;
6d0f6bcf 138 unsigned long ptmpcila[2] = {CONFIG_SYS_PCI_PTM1PCI, CONFIG_SYS_PCI_PTM2PCI};
5e746fce 139#if defined(CONFIG_CPCI405) || defined(CONFIG_PMC405)
fddae7b8 140 char *ptmla_str, *ptmms_str;
2076d0a1 141#endif
6d0f6bcf
JCPV		 142 unsigned long ptmla[2] = {CONFIG_SYS_PCI_PTM1LA, CONFIG_SYS_PCI_PTM2LA};
143 unsigned long ptmms[2] = {CONFIG_SYS_PCI_PTM1MS, CONFIG_SYS_PCI_PTM2MS};
c609719b
WD		 144#if defined(CONFIG_PIP405) || defined (CONFIG_MIP405)
145 unsigned long pmmla[3] = {0x80000000, 0xA0000000, 0};
146 unsigned long pmmma[3] = {0xE0000001, 0xE0000001, 0};
147 unsigned long pmmpcila[3] = {0x80000000, 0x00000000, 0};
148 unsigned long pmmpciha[3] = {0x00000000, 0x00000000, 0};
149#else
150 unsigned long pmmla[3] = {0x80000000, 0,0};
151 unsigned long pmmma[3] = {0xC0000001, 0,0};
152 unsigned long pmmpcila[3] = {0x80000000, 0,0};
153 unsigned long pmmpciha[3] = {0x00000000, 0,0};
5e746fce
SR		 154#endif
155#ifdef CONFIG_PCI_PNP
156#if (CONFIG_PCI_HOST == PCI_HOST_AUTO)
157 char *s;
158#endif
c609719b
WD		 159#endif
160
fddae7b8
SR		 161#if defined(CONFIG_CPCI405) || defined(CONFIG_PMC405)
162 ptmla_str = getenv("ptm1la");
163 ptmms_str = getenv("ptm1ms");
164 if(NULL != ptmla_str && NULL != ptmms_str ) {
165 ptmla[0] = simple_strtoul (ptmla_str, NULL, 16);
166 ptmms[0] = simple_strtoul (ptmms_str, NULL, 16);
167 }
168
169 ptmla_str = getenv("ptm2la");
170 ptmms_str = getenv("ptm2ms");
171 if(NULL != ptmla_str && NULL != ptmms_str ) {
172 ptmla[1] = simple_strtoul (ptmla_str, NULL, 16);
173 ptmms[1] = simple_strtoul (ptmms_str, NULL, 16);
174 }
175#endif
176
c609719b
WD		 177 /*
178 * Register the hose
179 */
180 hose->first_busno = 0;
181 hose->last_busno = 0xff;
182
183 /* ISA/PCI I/O space */
184 pci_set_region(hose->regions + reg_num++,
185 MIN_PCI_PCI_IOADDR,
186 MIN_PLB_PCI_IOADDR,
187 0x10000,
188 PCI_REGION_IO);
189
190 /* PCI I/O space */
191 pci_set_region(hose->regions + reg_num++,
192 0x00800000,
193 0xe8800000,
194 0x03800000,
195 PCI_REGION_IO);
196
197 reg_num = 2;
198
199 /* Memory spaces */
200 for (i=0; i<2; i++)
201 if (ptmms[i] & 1)
202 {
203 if (!i) hose->pci_fb = hose->regions + reg_num;
204
205 pci_set_region(hose->regions + reg_num++,
206 ptmpcila[i], ptmla[i],
207 ~(ptmms[i] & 0xfffff000) + 1,
208 PCI_REGION_MEM |
ff4e66e9 209 PCI_REGION_SYS_MEMORY);
c609719b
WD		 210 }
211
212 /* PCI memory spaces */
213 for (i=0; i<3; i++)
214 if (pmmma[i] & 1)
215 {
216 pci_set_region(hose->regions + reg_num++,
217 pmmpcila[i], pmmla[i],
218 ~(pmmma[i] & 0xfffff000) + 1,
219 PCI_REGION_MEM);
220 }
221
222 hose->region_count = reg_num;
223
224 pci_setup_indirect(hose,
225 PCICFGADR,
226 PCICFGDATA);
227
228 if (hose->pci_fb)
229 pciauto_region_init(hose->pci_fb);
230
5a1c9ff0
MF		 231 /* Let board change/modify hose & do initial checks */
232 if (pci_pre_init (hose) == 0) {
233 printf("PCI: Board-specific initialization failed.\n");
234 printf("PCI: Configuration aborted.\n");
235 return;
236 }
237
c609719b
WD		 238 pci_register_hose(hose);
239
240 /*--------------------------------------------------------------------------+
241 * 405GP PCI Master configuration.
242 * Map one 512 MB range of PLB/processor addresses to PCI memory space.
243 * PLB address 0x80000000-0xBFFFFFFF ==> PCI address 0x80000000-0xBFFFFFFF
244 * Use byte reversed out routines to handle endianess.
245 *--------------------------------------------------------------------------*/
f3e0de60 246 out32r(PMM0MA, (pmmma[0]&~0x1)); /* disable, configure PMMxLA, PMMxPCILA first */
c609719b
WD		 247 out32r(PMM0LA, pmmla[0]);
248 out32r(PMM0PCILA, pmmpcila[0]);
249 out32r(PMM0PCIHA, pmmpciha[0]);
250 out32r(PMM0MA, pmmma[0]);
251
252 /*--------------------------------------------------------------------------+
253 * PMM1 is not used. Initialize them to zero.
254 *--------------------------------------------------------------------------*/
f3e0de60 255 out32r(PMM1MA, (pmmma[1]&~0x1));
c609719b
WD		 256 out32r(PMM1LA, pmmla[1]);
257 out32r(PMM1PCILA, pmmpcila[1]);
258 out32r(PMM1PCIHA, pmmpciha[1]);
259 out32r(PMM1MA, pmmma[1]);
260
261 /*--------------------------------------------------------------------------+
262 * PMM2 is not used. Initialize them to zero.
263 *--------------------------------------------------------------------------*/
8bde7f77 264 out32r(PMM2MA, (pmmma[2]&~0x1));
c609719b
WD		 265 out32r(PMM2LA, pmmla[2]);
266 out32r(PMM2PCILA, pmmpcila[2]);
267 out32r(PMM2PCIHA, pmmpciha[2]);
268 out32r(PMM2MA, pmmma[2]);
269
270 /*--------------------------------------------------------------------------+
271 * 405GP PCI Target configuration. (PTM1)
272 * Note: PTM1MS is hardwire enabled but we set the enable bit anyway.
273 *--------------------------------------------------------------------------*/
274 out32r(PTM1LA, ptmla[0]); /* insert address */
275 out32r(PTM1MS, ptmms[0]); /* insert size, enable bit is 1 */
4654af27 276 pci_write_config_dword(PCIDEVID_405GP, PCI_BASE_ADDRESS_1, ptmpcila[0]);
c609719b
WD		 277
278 /*--------------------------------------------------------------------------+
279 * 405GP PCI Target configuration. (PTM2)
280 *--------------------------------------------------------------------------*/
281 out32r(PTM2LA, ptmla[1]); /* insert address */
4654af27
WD		 282 pci_write_config_dword(PCIDEVID_405GP, PCI_BASE_ADDRESS_2, ptmpcila[1]);
283
c609719b
WD		 284 if (ptmms[1] == 0)
285 {
286 out32r(PTM2MS, 0x00000001); /* set enable bit */
287 pci_write_config_dword(PCIDEVID_405GP, PCI_BASE_ADDRESS_2, 0x00000000);
288 out32r(PTM2MS, 0x00000000); /* disable */
289 }
290 else
291 {
292 out32r(PTM2MS, ptmms[1]); /* insert size, enable bit is 1 */
293 }
294
295 /*
296 * Insert Subsystem Vendor and Device ID
297 */
6d0f6bcf 298 pci_write_config_word(PCIDEVID_405GP, PCI_SUBSYSTEM_VENDOR_ID, CONFIG_SYS_PCI_SUBSYS_VENDORID);
c609719b 299#ifdef CONFIG_CPCI405
d0a1364f 300 if (is_pci_host(hose))
6d0f6bcf 301 pci_write_config_word(PCIDEVID_405GP, PCI_SUBSYSTEM_ID, CONFIG_SYS_PCI_SUBSYS_DEVICEID);
c609719b 302 else
6d0f6bcf 303 pci_write_config_word(PCIDEVID_405GP, PCI_SUBSYSTEM_ID, CONFIG_SYS_PCI_SUBSYS_DEVICEID2);
c609719b 304#else
6d0f6bcf 305 pci_write_config_word(PCIDEVID_405GP, PCI_SUBSYSTEM_ID, CONFIG_SYS_PCI_SUBSYS_DEVICEID);
c609719b
WD		 306#endif
307
308 /*
309 * Insert Class-code
310 */
6d0f6bcf
JCPV		 311#ifdef CONFIG_SYS_PCI_CLASSCODE
312 pci_write_config_word(PCIDEVID_405GP, PCI_CLASS_SUB_CODE, CONFIG_SYS_PCI_CLASSCODE);
313#endif /* CONFIG_SYS_PCI_CLASSCODE */
c609719b
WD		 314
315 /*--------------------------------------------------------------------------+
8ed44d91 316 * If PCI speed = 66MHz, set 66MHz capable bit.
c609719b
WD		 317 *--------------------------------------------------------------------------*/
318 if (bd->bi_pci_busfreq >= 66000000) {
319 pci_read_config_word(PCIDEVID_405GP, PCI_STATUS, &temp_short);
320 pci_write_config_word(PCIDEVID_405GP,PCI_STATUS,(temp_short|PCI_STATUS_66MHZ));
321 }
322
323#if (CONFIG_PCI_HOST != PCI_HOST_ADAPTER)
4654af27 324#if (CONFIG_PCI_HOST == PCI_HOST_AUTO)
d0a1364f 325 if (is_pci_host(hose) ||
5e746fce 326 (((s = getenv("pciscan")) != NULL) && (strcmp(s, "yes") == 0)))
c609719b
WD		 327#endif
328 {
329 /*--------------------------------------------------------------------------+
330 * Write the 405GP PCI Configuration regs.
331 * Enable 405GP to be a master on the PCI bus (PMM).
332 * Enable 405GP to act as a PCI memory target (PTM).
333 *--------------------------------------------------------------------------*/
334 pci_read_config_word(PCIDEVID_405GP, PCI_COMMAND, &temp_short);
335 pci_write_config_word(PCIDEVID_405GP, PCI_COMMAND, temp_short |
336 PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY);
337 }
338#endif
339
632e9b67
MF		 340#if defined(CONFIG_405EP)
341 /*
342 * on ppc405ep vendor/device id is not set
343 * The user manual says 0x1014 (IBM) / 0x0156 (405GP!)
344 * are the correct values.
345 */
346 pci_write_config_word(PCIDEVID_405GP, PCI_VENDOR_ID, PCI_VENDOR_ID_IBM);
347 pci_write_config_word(PCIDEVID_405GP,
348 PCI_DEVICE_ID, PCI_DEVICE_ID_IBM_405GP);
428c5639
SR		 349#endif
350
c609719b
WD		 351 /*
352 * Set HCE bit (Host Configuration Enabled)
353 */
354 pci_read_config_word(PCIDEVID_405GP, PCIBRDGOPT2, &temp_short);
355 pci_write_config_word(PCIDEVID_405GP, PCIBRDGOPT2, (temp_short | 0x0001));
356
357#ifdef CONFIG_PCI_PNP
358 /*--------------------------------------------------------------------------+
359 * Scan the PCI bus and configure devices found.
360 *--------------------------------------------------------------------------*/
361#if (CONFIG_PCI_HOST == PCI_HOST_AUTO)
d0a1364f 362 if (is_pci_host(hose) ||
5e746fce 363 (((s = getenv("pciscan")) != NULL) && (strcmp(s, "yes") == 0)))
c609719b
WD		 364#endif
365 {
366#ifdef CONFIG_PCI_SCAN_SHOW
367 printf("PCI: Bus Dev VenId DevId Class Int\n");
368#endif
c609719b
WD		 369 hose->last_busno = pci_hose_scan(hose);
370 }
371#endif /* CONFIG_PCI_PNP */
372
373}
374
375/*
7817cb20 376 * drivers/pci/pci.c skips every host bridge but the 405GP since it could
c609719b
WD		 377 * be set as an Adapter.
378 *
379 * I (Andrew May) don't know what we should do here, but I don't want
380 * the auto setup of a PCI device disabling what is done pci_405gp_init
381 * as has happened before.
382 */
383void pci_405gp_setup_bridge(struct pci_controller *hose, pci_dev_t dev,
384 struct pci_config_table *entry)
385{
386#ifdef DEBUG
8bde7f77 387 printf("405gp_setup_bridge\n");
c609719b
WD		 388#endif
389}
390
391/*
392 *
393 */
394
395void pci_405gp_fixup_irq(struct pci_controller *hose, pci_dev_t dev)
396{
397 unsigned char int_line = 0xff;
398
399 /*
400 * Write pci interrupt line register (cpci405 specific)
401 */
402 switch (PCI_DEV(dev) & 0x03)
403 {
404 case 0:
405 int_line = 27 + 2;
406 break;
407 case 1:
408 int_line = 27 + 3;
409 break;
410 case 2:
411 int_line = 27 + 0;
412 break;
413 case 3:
414 int_line = 27 + 1;
415 break;
416 }
417
418 pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE, int_line);
419}
420
421void pci_405gp_setup_vga(struct pci_controller *hose, pci_dev_t dev,
422 struct pci_config_table *entry)
423{
424 unsigned int cmdstat = 0;
425
f3fecfe6 426 pciauto_setup_device(hose, dev, 6, hose->pci_mem, hose->pci_prefetch, hose->pci_io);
c609719b
WD		 427
428 /* always enable io space on vga boards */
429 pci_hose_read_config_dword(hose, dev, PCI_COMMAND, &cmdstat);
430 cmdstat |= PCI_COMMAND_IO;
431 pci_hose_write_config_dword(hose, dev, PCI_COMMAND, cmdstat);
432}
433
9045f33c 434#if !(defined(CONFIG_PIP405) || defined (CONFIG_MIP405)) && !(defined (CONFIG_SC3))
c609719b
WD		 435
436/*
437 *As is these functs get called out of flash Not a horrible
438 *thing, but something to keep in mind. (no statics?)
439 */
440static struct pci_config_table pci_405gp_config_table[] = {
441/*if VendID is 0 it terminates the table search (ie Walnut)*/
6d0f6bcf
JCPV		 442#ifdef CONFIG_SYS_PCI_SUBSYS_VENDORID
443 {CONFIG_SYS_PCI_SUBSYS_VENDORID, PCI_ANY_ID, PCI_CLASS_BRIDGE_HOST,
c609719b
WD		 444 PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, pci_405gp_setup_bridge},
445#endif
446 {PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_DISPLAY_VGA,
447 PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, pci_405gp_setup_vga},
448
449 {PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_NOT_DEFINED_VGA,
450 PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, pci_405gp_setup_vga},
451
452 { }
453};
454
455static struct pci_controller hose = {
456 fixup_irq: pci_405gp_fixup_irq,
457 config_table: pci_405gp_config_table,
458};
459
ad10dd9a 460void pci_init_board(void)
c609719b
WD		 461{
462 /*we want the ptrs to RAM not flash (ie don't use init list)*/
463 hose.fixup_irq = pci_405gp_fixup_irq;
464 hose.config_table = pci_405gp_config_table;
465 pci_405gp_init(&hose);
466}
467
468#endif
469
c609719b
WD		 470#endif /* CONFIG_405GP */
471
472/*-----------------------------------------------------------------------------+
473 * CONFIG_440
474 *-----------------------------------------------------------------------------*/
5a1c9ff0 475#if defined(CONFIG_440)
c609719b
WD		 476
477static struct pci_controller ppc440_hose = {0};
478
479
7f191393 480int pci_440_init (struct pci_controller *hose)
c609719b
WD		 481{
482 int reg_num = 0;
c609719b 483
5568e613 484#ifndef CONFIG_DISABLE_PISE_TEST
c609719b
WD		 485 /*--------------------------------------------------------------------------+
486 * The PCI initialization sequence enable bit must be set ... if not abort
3c74e32a 487 * pci setup since updating the bit requires chip reset.
c609719b 488 *--------------------------------------------------------------------------*/
6c5879f3 489#if defined(CONFIG_440GX) || defined(CONFIG_440SP) || defined(CONFIG_440SPE)
5568e613
SR		 490 unsigned long strap;
491
3c74e32a 492 mfsdr(sdr_sdstp1,strap);
6e7fb6ea 493 if ((strap & SDR0_SDSTP1_PISE_MASK) == 0) {
3c74e32a
WD		 494 printf("PCI: SDR0_STRP1[PISE] not set.\n");
495 printf("PCI: Configuration aborted.\n");
7f191393 496 return -1;
3c74e32a 497 }
5568e613
SR		 498#elif defined(CONFIG_440GP)
499 unsigned long strap;
500
3c74e32a 501 strap = mfdcr(cpc0_strp1);
6e7fb6ea 502 if ((strap & CPC0_STRP1_PISE_MASK) == 0) {
3c74e32a
WD		 503 printf("PCI: CPC0_STRP1[PISE] not set.\n");
504 printf("PCI: Configuration aborted.\n");
7f191393 505 return -1;
3c74e32a
WD		 506 }
507#endif
5568e613
SR		 508#endif /* CONFIG_DISABLE_PISE_TEST */
509
c609719b
WD		 510 /*--------------------------------------------------------------------------+
511 * PCI controller init
512 *--------------------------------------------------------------------------*/
513 hose->first_busno = 0;
7f191393 514 hose->last_busno = 0;
c609719b 515
fbb0b559 516 /* PCI I/O space */
c609719b
WD		 517 pci_set_region(hose->regions + reg_num++,
518 0x00000000,
6e7fb6ea
SR		 519 PCIX0_IOBASE,
520 0x10000,
521 PCI_REGION_IO);
c609719b 522
fbb0b559 523 /* PCI memory space */
c609719b 524 pci_set_region(hose->regions + reg_num++,
6d0f6bcf
JCPV		 525 CONFIG_SYS_PCI_TARGBASE,
526 CONFIG_SYS_PCI_MEMBASE,
527#ifdef CONFIG_SYS_PCI_MEMSIZE
528 CONFIG_SYS_PCI_MEMSIZE,
899620c2 529#else
6e7fb6ea 530 0x10000000,
899620c2 531#endif
6e7fb6ea 532 PCI_REGION_MEM );
fbb0b559
MB		 533
534#if defined(CONFIG_PCI_SYS_MEM_BUS) && defined(CONFIG_PCI_SYS_MEM_PHYS) && \
535 defined(CONFIG_PCI_SYS_MEM_SIZE)
536 /* System memory space */
537 pci_set_region(hose->regions + reg_num++,
538 CONFIG_PCI_SYS_MEM_BUS,
539 CONFIG_PCI_SYS_MEM_PHYS,
540 CONFIG_PCI_SYS_MEM_SIZE,
ff4e66e9 541 PCI_REGION_MEM | PCI_REGION_SYS_MEMORY );
fbb0b559
MB		 542#endif
543
c609719b
WD		 544 hose->region_count = reg_num;
545
546 pci_setup_indirect(hose, PCIX0_CFGADR, PCIX0_CFGDATA);
547
6e7fb6ea
SR		 548 /* Let board change/modify hose & do initial checks */
549 if (pci_pre_init (hose) == 0) {
550 printf("PCI: Board-specific initialization failed.\n");
551 printf("PCI: Configuration aborted.\n");
7f191393 552 return -1;
6e7fb6ea 553 }
c609719b
WD		 554
555 pci_register_hose( hose );
556
557 /*--------------------------------------------------------------------------+
558 * PCI target init
559 *--------------------------------------------------------------------------*/
6d0f6bcf 560#if defined(CONFIG_SYS_PCI_TARGET_INIT)
c609719b
WD		 561 pci_target_init(hose); /* Let board setup pci target */
562#else
6d0f6bcf
JCPV		 563 out16r( PCIX0_SBSYSVID, CONFIG_SYS_PCI_SUBSYS_VENDORID );
564 out16r( PCIX0_SBSYSID, CONFIG_SYS_PCI_SUBSYS_ID );
6e7fb6ea 565 out16r( PCIX0_CLS, 0x00060000 ); /* Bridge, host bridge */
c609719b
WD		 566#endif
567
8ac41e3e
SR		 568#if defined(CONFIG_440GX) || defined(CONFIG_440SPE) || \
569 defined(CONFIG_460EX) || defined(CONFIG_460GT)
3c74e32a
WD		 570 out32r( PCIX0_BRDGOPT1, 0x04000060 ); /* PLB Rq pri highest */
571 out32r( PCIX0_BRDGOPT2, in32(PCIX0_BRDGOPT2) | 0x83 ); /* Enable host config, clear Timeout, ensure int src1 */
c157d8e2 572#elif defined(PCIX0_BRDGOPT1)
3c74e32a
WD		 573 out32r( PCIX0_BRDGOPT1, 0x10000060 ); /* PLB Rq pri highest */
574 out32r( PCIX0_BRDGOPT2, in32(PCIX0_BRDGOPT2) | 1 ); /* Enable host config */
575#endif
c609719b
WD		 576
577 /*--------------------------------------------------------------------------+
578 * PCI master init: default is one 256MB region for PCI memory:
6d0f6bcf 579 * 0x3_00000000 - 0x3_0FFFFFFF ==> CONFIG_SYS_PCI_MEMBASE
c609719b 580 *--------------------------------------------------------------------------*/
6d0f6bcf 581#if defined(CONFIG_SYS_PCI_MASTER_INIT)
c609719b
WD		 582 pci_master_init(hose); /* Let board setup pci master */
583#else
584 out32r( PCIX0_POM0SA, 0 ); /* disable */
585 out32r( PCIX0_POM1SA, 0 ); /* disable */
586 out32r( PCIX0_POM2SA, 0 ); /* disable */
f8853d10 587#if defined(CONFIG_440SPE)
6c5879f3
MB		 588 out32r( PCIX0_POM0LAL, 0x10000000 );
589 out32r( PCIX0_POM0LAH, 0x0000000c );
f8853d10
AG		 590#elif defined(CONFIG_460EX) || defined(CONFIG_460GT)
591 out32r( PCIX0_POM0LAL, 0x20000000 );
592 out32r( PCIX0_POM0LAH, 0x0000000c );
6c5879f3 593#else
c609719b
WD		 594 out32r( PCIX0_POM0LAL, 0x00000000 );
595 out32r( PCIX0_POM0LAH, 0x00000003 );
6c5879f3 596#endif
6d0f6bcf 597 out32r( PCIX0_POM0PCIAL, CONFIG_SYS_PCI_MEMBASE );
c609719b
WD		 598 out32r( PCIX0_POM0PCIAH, 0x00000000 );
599 out32r( PCIX0_POM0SA, 0xf0000001 ); /* 256MB, enabled */
6e7fb6ea 600 out32r( PCIX0_STS, in32r( PCIX0_STS ) & ~0x0000fff8 );
c609719b
WD		 601#endif
602
603 /*--------------------------------------------------------------------------+
604 * PCI host configuration -- we don't make any assumptions here ... the
6e7fb6ea
SR		 605 * _board_must_indicate_ what to do -- there's just too many runtime
606 * scenarios in environments like cPCI, PPMC, etc. to make a determination
607 * based on hard-coded values or state of arbiter enable.
c609719b 608 *--------------------------------------------------------------------------*/
6e7fb6ea 609 if (is_pci_host(hose)) {
c609719b 610#ifdef CONFIG_PCI_SCAN_SHOW
6e7fb6ea 611 printf("PCI: Bus Dev VenId DevId Class Int\n");
c609719b 612#endif
887e2ec9
SR		 613#if !defined(CONFIG_440EP) && !defined(CONFIG_440GR) && \
614 !defined(CONFIG_440EPX) && !defined(CONFIG_440GRX)
6e7fb6ea 615 out16r( PCIX0_CMD, in16r( PCIX0_CMD ) | PCI_COMMAND_MASTER);
c157d8e2 616#endif
6e7fb6ea
SR		 617 hose->last_busno = pci_hose_scan(hose);
618 }
7f191393 619 return hose->last_busno;
c609719b
WD		 620}
621
ad10dd9a 622void pci_init_board(void)
c609719b 623{
7f191393
GB		 624 int busno;
625
626 busno = pci_440_init (&ppc440_hose);
59d1bda7
DE		 627#if (defined(CONFIG_440SPE) || \
628 defined(CONFIG_460EX) || defined(CONFIG_460GT)) && \
629 !defined(CONFIG_PCI_DISABLE_PCIE)
7f191393 630 pcie_setup_hoses(busno + 1);
692519b1 631#endif
c609719b
WD		 632}
633
5a1c9ff0 634#endif /* CONFIG_440 */
1d7b874e
SR		 635
636#if defined(CONFIG_405EX)
637void pci_init_board(void)
638{
639#ifdef CONFIG_PCI_SCAN_SHOW
640 printf("PCI: Bus Dev VenId DevId Class Int\n");
641#endif
642 pcie_setup_hoses(0);
643}
644#endif /* CONFIG_405EX */
645
5a1c9ff0 646#endif /* CONFIG_PCI */
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