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rename CFG_ macros to CONFIG_SYS
[people/ms/u-boot.git] / cpu / ppc4xx / 4xx_pcie.c
CommitLineData
692519b1 1/*
8ac41e3e 2 * (C) Copyright 2006 - 2008
692519b1
RJ
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * Copyright (c) 2005 Cisco Systems. All rights reserved.
6 * Roland Dreier <rolandd@cisco.com>
7 *
8 * See file CREDITS for list of people who contributed to this
9 * project.
10 *
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of
14 * the License, or (at your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 */
22
4dbee8a9 23/* define DEBUG for debugging output (obviously ;-)) */
ff68f66b 24#if 0
4dbee8a9
SR
25#define DEBUG
26#endif
27
692519b1
RJ
28#include <common.h>
29#include <pci.h>
b578fb47
SR
30#include <ppc4xx.h>
31#include <asm/processor.h>
32#include <asm-ppc/io.h>
692519b1 33
8ac41e3e
SR
34#if (defined(CONFIG_440SPE) || defined(CONFIG_405EX) || \
35 defined(CONFIG_460EX) || defined(CONFIG_460GT)) && \
97923770 36 defined(CONFIG_PCI)
692519b1 37
c7c6da23 38#include <asm/4xx_pcie.h>
692519b1
RJ
39
40enum {
41 PTYPE_ENDPOINT = 0x0,
42 PTYPE_LEGACY_ENDPOINT = 0x1,
43 PTYPE_ROOT_PORT = 0x4,
44
45 LNKW_X1 = 0x1,
46 LNKW_X4 = 0x4,
47 LNKW_X8 = 0x8
48};
49
d4cb2d17
SR
50static int validate_endpoint(struct pci_controller *hose)
51{
6d0f6bcf 52 if (hose->cfg_data == (u8 *)CONFIG_SYS_PCIE0_CFGBASE)
d4cb2d17 53 return (is_end_point(0));
6d0f6bcf 54 else if (hose->cfg_data == (u8 *)CONFIG_SYS_PCIE1_CFGBASE)
d4cb2d17 55 return (is_end_point(1));
6d0f6bcf
JCPV
56#if CONFIG_SYS_PCIE_NR_PORTS > 2
57 else if (hose->cfg_data == (u8 *)CONFIG_SYS_PCIE2_CFGBASE)
d4cb2d17
SR
58 return (is_end_point(2));
59#endif
60
61 return 0;
62}
63
7f191393
GB
64static u8* pcie_get_base(struct pci_controller *hose, unsigned int devfn)
65{
66 u8 *base = (u8*)hose->cfg_data;
67
68 /* use local configuration space for the first bus */
69 if (PCI_BUS(devfn) == 0) {
6d0f6bcf
JCPV
70 if (hose->cfg_data == (u8*)CONFIG_SYS_PCIE0_CFGBASE)
71 base = (u8*)CONFIG_SYS_PCIE0_XCFGBASE;
72 if (hose->cfg_data == (u8*)CONFIG_SYS_PCIE1_CFGBASE)
73 base = (u8*)CONFIG_SYS_PCIE1_XCFGBASE;
74#if CONFIG_SYS_PCIE_NR_PORTS > 2
75 if (hose->cfg_data == (u8*)CONFIG_SYS_PCIE2_CFGBASE)
76 base = (u8*)CONFIG_SYS_PCIE2_XCFGBASE;
97923770 77#endif
7f191393
GB
78 }
79
80 return base;
81}
82
15ee4734 83static void pcie_dmer_disable(void)
c9240981 84{
15ee4734
GB
85 mtdcr (DCRN_PEGPL_CFG(DCRN_PCIE0_BASE),
86 mfdcr (DCRN_PEGPL_CFG(DCRN_PCIE0_BASE)) | GPL_DMER_MASK_DISA);
87 mtdcr (DCRN_PEGPL_CFG(DCRN_PCIE1_BASE),
88 mfdcr (DCRN_PEGPL_CFG(DCRN_PCIE1_BASE)) | GPL_DMER_MASK_DISA);
6d0f6bcf 89#if CONFIG_SYS_PCIE_NR_PORTS > 2
15ee4734
GB
90 mtdcr (DCRN_PEGPL_CFG(DCRN_PCIE2_BASE),
91 mfdcr (DCRN_PEGPL_CFG(DCRN_PCIE2_BASE)) | GPL_DMER_MASK_DISA);
97923770 92#endif
c9240981
GB
93}
94
15ee4734 95static void pcie_dmer_enable(void)
c9240981 96{
15ee4734
GB
97 mtdcr (DCRN_PEGPL_CFG (DCRN_PCIE0_BASE),
98 mfdcr (DCRN_PEGPL_CFG(DCRN_PCIE0_BASE)) & ~GPL_DMER_MASK_DISA);
99 mtdcr (DCRN_PEGPL_CFG (DCRN_PCIE1_BASE),
100 mfdcr (DCRN_PEGPL_CFG(DCRN_PCIE1_BASE)) & ~GPL_DMER_MASK_DISA);
6d0f6bcf 101#if CONFIG_SYS_PCIE_NR_PORTS > 2
15ee4734
GB
102 mtdcr (DCRN_PEGPL_CFG (DCRN_PCIE2_BASE),
103 mfdcr (DCRN_PEGPL_CFG(DCRN_PCIE2_BASE)) & ~GPL_DMER_MASK_DISA);
97923770 104#endif
c9240981
GB
105}
106
692519b1
RJ
107static int pcie_read_config(struct pci_controller *hose, unsigned int devfn,
108 int offset, int len, u32 *val) {
109
7f191393 110 u8 *address;
692519b1 111 *val = 0;
7f191393 112
d4cb2d17
SR
113 if (validate_endpoint(hose))
114 return 0; /* No upstream config access */
115
7f191393
GB
116 /*
117 * Bus numbers are relative to hose->first_busno
118 */
119 devfn -= PCI_BDF(hose->first_busno, 0, 0);
120
692519b1 121 /*
7f191393
GB
122 * NOTICE: configuration space ranges are currenlty mapped only for
123 * the first 16 buses, so such limit must be imposed. In case more
124 * buses are required the TLB settings in board/amcc/<board>/init.S
125 * need to be altered accordingly (one bus takes 1 MB of memory space).
692519b1 126 */
7f191393 127 if (PCI_BUS(devfn) >= 16)
692519b1
RJ
128 return 0;
129
7f191393
GB
130 /*
131 * Only single device/single function is supported for the primary and
132 * secondary buses of the 440SPe host bridge.
133 */
134 if ((!((PCI_FUNC(devfn) == 0) && (PCI_DEV(devfn) == 0))) &&
135 ((PCI_BUS(devfn) == 0) || (PCI_BUS(devfn) == 1)))
136 return 0;
738815c0 137
7f191393 138 address = pcie_get_base(hose, devfn);
692519b1
RJ
139 offset += devfn << 4;
140
15ee4734
GB
141 /*
142 * Reading from configuration space of non-existing device can
143 * generate transaction errors. For the read duration we suppress
144 * assertion of machine check exceptions to avoid those.
145 */
146 pcie_dmer_disable ();
147
97923770 148 debug("%s: cfg_data=%08x offset=%08x\n", __func__, hose->cfg_data, offset);
692519b1
RJ
149 switch (len) {
150 case 1:
15ee4734 151 *val = in_8(hose->cfg_data + offset);
692519b1
RJ
152 break;
153 case 2:
15ee4734 154 *val = in_le16((u16 *)(hose->cfg_data + offset));
692519b1
RJ
155 break;
156 default:
15ee4734 157 *val = in_le32((u32*)(hose->cfg_data + offset));
692519b1
RJ
158 break;
159 }
15ee4734
GB
160
161 pcie_dmer_enable ();
162
692519b1
RJ
163 return 0;
164}
165
166static int pcie_write_config(struct pci_controller *hose, unsigned int devfn,
167 int offset, int len, u32 val) {
168
7f191393 169 u8 *address;
738815c0 170
d4cb2d17
SR
171 if (validate_endpoint(hose))
172 return 0; /* No upstream config access */
173
692519b1 174 /*
7f191393 175 * Bus numbers are relative to hose->first_busno
692519b1 176 */
7f191393 177 devfn -= PCI_BDF(hose->first_busno, 0, 0);
738815c0 178
7f191393
GB
179 /*
180 * Same constraints as in pcie_read_config().
181 */
182 if (PCI_BUS(devfn) >= 16)
692519b1
RJ
183 return 0;
184
7f191393
GB
185 if ((!((PCI_FUNC(devfn) == 0) && (PCI_DEV(devfn) == 0))) &&
186 ((PCI_BUS(devfn) == 0) || (PCI_BUS(devfn) == 1)))
187 return 0;
738815c0 188
7f191393 189 address = pcie_get_base(hose, devfn);
692519b1
RJ
190 offset += devfn << 4;
191
15ee4734
GB
192 /*
193 * Suppress MCK exceptions, similar to pcie_read_config()
194 */
195 pcie_dmer_disable ();
196
692519b1
RJ
197 switch (len) {
198 case 1:
199 out_8(hose->cfg_data + offset, val);
200 break;
201 case 2:
202 out_le16((u16 *)(hose->cfg_data + offset), val);
203 break;
204 default:
205 out_le32((u32 *)(hose->cfg_data + offset), val);
206 break;
207 }
15ee4734
GB
208
209 pcie_dmer_enable ();
210
692519b1
RJ
211 return 0;
212}
213
214int pcie_read_config_byte(struct pci_controller *hose,pci_dev_t dev,int offset,u8 *val)
215{
216 u32 v;
217 int rv;
218
7f191393 219 rv = pcie_read_config(hose, dev, offset, 1, &v);
692519b1
RJ
220 *val = (u8)v;
221 return rv;
222}
223
224int pcie_read_config_word(struct pci_controller *hose,pci_dev_t dev,int offset,u16 *val)
225{
226 u32 v;
227 int rv;
228
229 rv = pcie_read_config(hose, dev, offset, 2, &v);
230 *val = (u16)v;
231 return rv;
232}
233
234int pcie_read_config_dword(struct pci_controller *hose,pci_dev_t dev,int offset,u32 *val)
235{
236 u32 v;
237 int rv;
238
239 rv = pcie_read_config(hose, dev, offset, 3, &v);
240 *val = (u32)v;
241 return rv;
242}
243
244int pcie_write_config_byte(struct pci_controller *hose,pci_dev_t dev,int offset,u8 val)
245{
246 return pcie_write_config(hose,(u32)dev,offset,1,val);
247}
248
249int pcie_write_config_word(struct pci_controller *hose,pci_dev_t dev,int offset,u16 val)
250{
251 return pcie_write_config(hose,(u32)dev,offset,2,(u32 )val);
252}
253
254int pcie_write_config_dword(struct pci_controller *hose,pci_dev_t dev,int offset,u32 val)
255{
256 return pcie_write_config(hose,(u32)dev,offset,3,(u32 )val);
257}
258
97923770 259#if defined(CONFIG_440SPE)
026f7110 260static void ppc4xx_setup_utl(u32 port) {
692519b1
RJ
261
262 volatile void *utl_base = NULL;
263
264 /*
265 * Map UTL registers
266 */
267 switch (port) {
268 case 0:
36b904a7
RJ
269 mtdcr(DCRN_PEGPL_REGBAH(PCIE0), 0x0000000c);
270 mtdcr(DCRN_PEGPL_REGBAL(PCIE0), 0x20000000);
271 mtdcr(DCRN_PEGPL_REGMSK(PCIE0), 0x00007001);
692519b1 272 mtdcr(DCRN_PEGPL_SPECIAL(PCIE0), 0x68782800);
692519b1
RJ
273 break;
274
275 case 1:
36b904a7
RJ
276 mtdcr(DCRN_PEGPL_REGBAH(PCIE1), 0x0000000c);
277 mtdcr(DCRN_PEGPL_REGBAL(PCIE1), 0x20001000);
278 mtdcr(DCRN_PEGPL_REGMSK(PCIE1), 0x00007001);
692519b1 279 mtdcr(DCRN_PEGPL_SPECIAL(PCIE1), 0x68782800);
692519b1
RJ
280 break;
281
282 case 2:
36b904a7
RJ
283 mtdcr(DCRN_PEGPL_REGBAH(PCIE2), 0x0000000c);
284 mtdcr(DCRN_PEGPL_REGBAL(PCIE2), 0x20002000);
285 mtdcr(DCRN_PEGPL_REGMSK(PCIE2), 0x00007001);
692519b1 286 mtdcr(DCRN_PEGPL_SPECIAL(PCIE2), 0x68782800);
692519b1
RJ
287 break;
288 }
6d0f6bcf 289 utl_base = (unsigned int *)(CONFIG_SYS_PCIE_BASE + 0x1000 * port);
16850919 290
692519b1
RJ
291 /*
292 * Set buffer allocations and then assert VRB and TXE.
293 */
294 out_be32(utl_base + PEUTL_OUTTR, 0x08000000);
295 out_be32(utl_base + PEUTL_INTR, 0x02000000);
296 out_be32(utl_base + PEUTL_OPDBSZ, 0x10000000);
297 out_be32(utl_base + PEUTL_PBBSZ, 0x53000000);
298 out_be32(utl_base + PEUTL_IPHBSZ, 0x08000000);
299 out_be32(utl_base + PEUTL_IPDBSZ, 0x10000000);
300 out_be32(utl_base + PEUTL_RCIRQEN, 0x00f00000);
36b904a7 301 out_be32(utl_base + PEUTL_PCTL, 0x80800066);
692519b1
RJ
302}
303
304static int check_error(void)
305{
306 u32 valPE0, valPE1, valPE2;
307 int err = 0;
308
309 /* SDR0_PEGPLLLCT1 reset */
8ac41e3e 310 if (!(valPE0 = SDR_READ(PESDR0_PLLLCT1) & 0x01000000))
692519b1 311 printf("PCIE: SDR0_PEGPLLLCT1 reset error 0x%x\n", valPE0);
692519b1
RJ
312
313 valPE0 = SDR_READ(PESDR0_RCSSET);
314 valPE1 = SDR_READ(PESDR1_RCSSET);
315 valPE2 = SDR_READ(PESDR2_RCSSET);
316
317 /* SDR0_PExRCSSET rstgu */
318 if (!(valPE0 & 0x01000000) ||
319 !(valPE1 & 0x01000000) ||
320 !(valPE2 & 0x01000000)) {
321 printf("PCIE: SDR0_PExRCSSET rstgu error\n");
322 err = -1;
323 }
324
325 /* SDR0_PExRCSSET rstdl */
326 if (!(valPE0 & 0x00010000) ||
327 !(valPE1 & 0x00010000) ||
328 !(valPE2 & 0x00010000)) {
329 printf("PCIE: SDR0_PExRCSSET rstdl error\n");
330 err = -1;
331 }
332
333 /* SDR0_PExRCSSET rstpyn */
334 if ((valPE0 & 0x00001000) ||
335 (valPE1 & 0x00001000) ||
336 (valPE2 & 0x00001000)) {
337 printf("PCIE: SDR0_PExRCSSET rstpyn error\n");
338 err = -1;
339 }
340
341 /* SDR0_PExRCSSET hldplb */
342 if ((valPE0 & 0x10000000) ||
343 (valPE1 & 0x10000000) ||
344 (valPE2 & 0x10000000)) {
345 printf("PCIE: SDR0_PExRCSSET hldplb error\n");
346 err = -1;
347 }
348
349 /* SDR0_PExRCSSET rdy */
350 if ((valPE0 & 0x00100000) ||
351 (valPE1 & 0x00100000) ||
352 (valPE2 & 0x00100000)) {
353 printf("PCIE: SDR0_PExRCSSET rdy error\n");
354 err = -1;
355 }
356
357 /* SDR0_PExRCSSET shutdown */
358 if ((valPE0 & 0x00000100) ||
359 (valPE1 & 0x00000100) ||
360 (valPE2 & 0x00000100)) {
361 printf("PCIE: SDR0_PExRCSSET shutdown error\n");
362 err = -1;
363 }
364 return err;
365}
366
367/*
368 * Initialize PCI Express core
369 */
026f7110 370int ppc4xx_init_pcie(void)
692519b1
RJ
371{
372 int time_out = 20;
373
374 /* Set PLL clock receiver to LVPECL */
375 SDR_WRITE(PESDR0_PLLLCT1, SDR_READ(PESDR0_PLLLCT1) | 1 << 28);
376
377 if (check_error())
378 return -1;
379
380 if (!(SDR_READ(PESDR0_PLLLCT2) & 0x10000))
381 {
382 printf("PCIE: PESDR_PLLCT2 resistance calibration failed (0x%08x)\n",
383 SDR_READ(PESDR0_PLLLCT2));
384 return -1;
385 }
386 /* De-assert reset of PCIe PLL, wait for lock */
387 SDR_WRITE(PESDR0_PLLLCT1, SDR_READ(PESDR0_PLLLCT1) & ~(1 << 24));
388 udelay(3);
389
2b393b0f 390 while (time_out) {
692519b1
RJ
391 if (!(SDR_READ(PESDR0_PLLLCT3) & 0x10000000)) {
392 time_out--;
393 udelay(1);
394 } else
395 break;
396 }
397 if (!time_out) {
398 printf("PCIE: VCO output not locked\n");
399 return -1;
400 }
401 return 0;
402}
8ac41e3e
SR
403#endif
404
405#if defined(CONFIG_460EX) || defined(CONFIG_460GT)
406static void ppc4xx_setup_utl(u32 port)
407{
408 volatile void *utl_base = NULL;
409
410 /*
411 * Map UTL registers at 0x0801_n000 (4K 0xfff mask) PEGPLn_REGMSK
412 */
413 switch (port) {
414 case 0:
6d0f6bcf
JCPV
415 mtdcr(DCRN_PEGPL_REGBAH(PCIE0), U64_TO_U32_HIGH(CONFIG_SYS_PCIE0_UTLBASE));
416 mtdcr(DCRN_PEGPL_REGBAL(PCIE0), U64_TO_U32_LOW(CONFIG_SYS_PCIE0_UTLBASE));
8ac41e3e
SR
417 mtdcr(DCRN_PEGPL_REGMSK(PCIE0), 0x00007001); /* BAM 11100000=4KB */
418 mtdcr(DCRN_PEGPL_SPECIAL(PCIE0), 0);
419 break;
420
421 case 1:
6d0f6bcf
JCPV
422 mtdcr(DCRN_PEGPL_REGBAH(PCIE1), U64_TO_U32_HIGH(CONFIG_SYS_PCIE0_UTLBASE));
423 mtdcr(DCRN_PEGPL_REGBAL(PCIE1), U64_TO_U32_LOW(CONFIG_SYS_PCIE0_UTLBASE)
8ac41e3e
SR
424 + 0x1000);
425 mtdcr(DCRN_PEGPL_REGMSK(PCIE1), 0x00007001); /* BAM 11100000=4KB */
426 mtdcr(DCRN_PEGPL_SPECIAL(PCIE1), 0);
427 break;
428 }
6d0f6bcf 429 utl_base = (unsigned int *)(CONFIG_SYS_PCIE_BASE + 0x1000 * port);
8ac41e3e
SR
430
431 /*
432 * Set buffer allocations and then assert VRB and TXE.
433 */
434 out_be32(utl_base + PEUTL_PBCTL, 0x0800000c); /* PLBME, CRRE */
435 out_be32(utl_base + PEUTL_OUTTR, 0x08000000);
436 out_be32(utl_base + PEUTL_INTR, 0x02000000);
437 out_be32(utl_base + PEUTL_OPDBSZ, 0x04000000); /* OPD = 512 Bytes */
438 out_be32(utl_base + PEUTL_PBBSZ, 0x00000000); /* Max 512 Bytes */
439 out_be32(utl_base + PEUTL_IPHBSZ, 0x02000000);
440 out_be32(utl_base + PEUTL_IPDBSZ, 0x04000000); /* IPD = 512 Bytes */
441 out_be32(utl_base + PEUTL_RCIRQEN, 0x00f00000);
442 out_be32(utl_base + PEUTL_PCTL, 0x80800066); /* VRB,TXE,timeout=default */
443}
444
445/*
446 * TODO: double check PCI express SDR based on the latest user manual
53677ef1
WD
447 * Some registers specified here no longer exist.. has to be
448 * updated based on the final EAS spec.
8ac41e3e
SR
449 */
450static int check_error(void)
451{
452 u32 valPE0, valPE1;
453 int err = 0;
454
455 valPE0 = SDR_READ(SDRN_PESDR_RCSSET(0));
456 valPE1 = SDR_READ(SDRN_PESDR_RCSSET(1));
457
458 /* SDR0_PExRCSSET rstgu */
459 if (!(valPE0 & PESDRx_RCSSET_RSTGU) || !(valPE1 & PESDRx_RCSSET_RSTGU)) {
460 printf("PCIE: SDR0_PExRCSSET rstgu error\n");
461 err = -1;
462 }
463
464 /* SDR0_PExRCSSET rstdl */
465 if (!(valPE0 & PESDRx_RCSSET_RSTDL) || !(valPE1 & PESDRx_RCSSET_RSTDL)) {
466 printf("PCIE: SDR0_PExRCSSET rstdl error\n");
467 err = -1;
468 }
469
470 /* SDR0_PExRCSSET rstpyn */
471 if ((valPE0 & PESDRx_RCSSET_RSTPYN) || (valPE1 & PESDRx_RCSSET_RSTPYN)) {
472 printf("PCIE: SDR0_PExRCSSET rstpyn error\n");
473 err = -1;
474 }
475
476 /* SDR0_PExRCSSET hldplb */
477 if ((valPE0 & PESDRx_RCSSET_HLDPLB) || (valPE1 & PESDRx_RCSSET_HLDPLB)) {
478 printf("PCIE: SDR0_PExRCSSET hldplb error\n");
479 err = -1;
480 }
481
482 /* SDR0_PExRCSSET rdy */
483 if ((valPE0 & PESDRx_RCSSET_RDY) || (valPE1 & PESDRx_RCSSET_RDY)) {
484 printf("PCIE: SDR0_PExRCSSET rdy error\n");
485 err = -1;
486 }
487
488 return err;
489}
490
491/*
492 * Initialize PCI Express core as described in User Manual
493 * TODO: double check PE SDR PLL Register with the updated user manual.
494 */
495int ppc4xx_init_pcie(void)
496{
497 if (check_error())
498 return -1;
499
500 return 0;
501}
502#endif /* CONFIG_460EX */
503
504#if defined(CONFIG_405EX)
f31d38b9
SR
505static void ppc4xx_setup_utl(u32 port)
506{
507 u32 utl_base;
508
509 /*
510 * Map UTL registers at 0xef4f_n000 (4K 0xfff mask) PEGPLn_REGMSK
511 */
512 switch (port) {
513 case 0:
514 mtdcr(DCRN_PEGPL_REGBAH(PCIE0), 0x00000000);
6d0f6bcf 515 mtdcr(DCRN_PEGPL_REGBAL(PCIE0), CONFIG_SYS_PCIE0_UTLBASE);
653811a3 516 mtdcr(DCRN_PEGPL_REGMSK(PCIE0), 0x00007001); /* 4k region, valid */
f31d38b9
SR
517 mtdcr(DCRN_PEGPL_SPECIAL(PCIE0), 0);
518 break;
519
520 case 1:
521 mtdcr(DCRN_PEGPL_REGBAH(PCIE1), 0x00000000);
6d0f6bcf 522 mtdcr(DCRN_PEGPL_REGBAL(PCIE1), CONFIG_SYS_PCIE1_UTLBASE);
653811a3 523 mtdcr(DCRN_PEGPL_REGMSK(PCIE1), 0x00007001); /* 4k region, valid */
f31d38b9
SR
524 mtdcr(DCRN_PEGPL_SPECIAL(PCIE1), 0);
525
526 break;
527 }
6d0f6bcf 528 utl_base = (port==0) ? CONFIG_SYS_PCIE0_UTLBASE : CONFIG_SYS_PCIE1_UTLBASE;
f31d38b9
SR
529
530 /*
531 * Set buffer allocations and then assert VRB and TXE.
532 */
533 out_be32((u32 *)(utl_base + PEUTL_OUTTR), 0x02000000);
534 out_be32((u32 *)(utl_base + PEUTL_INTR), 0x02000000);
535 out_be32((u32 *)(utl_base + PEUTL_OPDBSZ), 0x04000000);
536 out_be32((u32 *)(utl_base + PEUTL_PBBSZ), 0x21000000);
537 out_be32((u32 *)(utl_base + PEUTL_IPHBSZ), 0x02000000);
538 out_be32((u32 *)(utl_base + PEUTL_IPDBSZ), 0x04000000);
539 out_be32((u32 *)(utl_base + PEUTL_RCIRQEN), 0x00f00000);
540 out_be32((u32 *)(utl_base + PEUTL_PCTL), 0x80800066);
541
542 out_be32((u32 *)(utl_base + PEUTL_PBCTL), 0x0800000c);
543 out_be32((u32 *)(utl_base + PEUTL_RCSTA),
544 in_be32((u32 *)(utl_base + PEUTL_RCSTA)) | 0x000040000);
545}
546
97923770
SR
547int ppc4xx_init_pcie(void)
548{
549 /*
550 * Nothing to do on 405EX
551 */
552 return 0;
553}
8ac41e3e 554#endif /* CONFIG_405EX */
692519b1 555
2b393b0f 556/*
03d344bb
SR
557 * Board-specific pcie initialization
558 * Platform code can reimplement ppc4xx_init_pcie_port_hw() if needed
559 */
560
561/*
562 * Initialize various parts of the PCI Express core for our port:
563 *
564 * - Set as a root port and enable max width
565 * (PXIE0 -> X8, PCIE1 and PCIE2 -> X4).
566 * - Set up UTL configuration.
567 * - Increase SERDES drive strength to levels suggested by AMCC.
568 * - De-assert RSTPYN, RSTDL and RSTGU.
569 *
570 * NOTICE for 440SPE revB chip: PESDRn_UTLSET2 is not set - we leave it
571 * with default setting 0x11310000. The register has new fields,
572 * PESDRn_UTLSET2[LKINE] in particular: clearing it leads to PCIE core
573 * hang.
574 */
575#if defined(CONFIG_440SPE)
576int __ppc4xx_init_pcie_port_hw(int port, int rootport)
577{
578 u32 val = 1 << 24;
579 u32 utlset1;
580
581 if (rootport) {
582 val = PTYPE_ROOT_PORT << 20;
583 utlset1 = 0x21222222;
584 } else {
585 val = PTYPE_LEGACY_ENDPOINT << 20;
586 utlset1 = 0x20222222;
587 }
588
589 if (port == 0)
590 val |= LNKW_X8 << 12;
591 else
592 val |= LNKW_X4 << 12;
593
594 SDR_WRITE(SDRN_PESDR_DLPSET(port), val);
595 SDR_WRITE(SDRN_PESDR_UTLSET1(port), utlset1);
596 if (!ppc440spe_revB())
597 SDR_WRITE(SDRN_PESDR_UTLSET2(port), 0x11000000);
598 SDR_WRITE(SDRN_PESDR_HSSL0SET1(port), 0x35000000);
599 SDR_WRITE(SDRN_PESDR_HSSL1SET1(port), 0x35000000);
600 SDR_WRITE(SDRN_PESDR_HSSL2SET1(port), 0x35000000);
601 SDR_WRITE(SDRN_PESDR_HSSL3SET1(port), 0x35000000);
602 if (port == 0) {
603 SDR_WRITE(PESDR0_HSSL4SET1, 0x35000000);
604 SDR_WRITE(PESDR0_HSSL5SET1, 0x35000000);
605 SDR_WRITE(PESDR0_HSSL6SET1, 0x35000000);
606 SDR_WRITE(PESDR0_HSSL7SET1, 0x35000000);
607 }
608 SDR_WRITE(SDRN_PESDR_RCSSET(port), (SDR_READ(SDRN_PESDR_RCSSET(port)) &
609 ~(1 << 24 | 1 << 16)) | 1 << 12);
610
611 return 0;
612}
613#endif /* CONFIG_440SPE */
614
8ac41e3e
SR
615#if defined(CONFIG_460EX) || defined(CONFIG_460GT)
616int __ppc4xx_init_pcie_port_hw(int port, int rootport)
617{
dd1c5523 618 u32 val;
8ac41e3e
SR
619 u32 utlset1;
620
dd1c5523 621 if (rootport)
8ac41e3e 622 val = PTYPE_ROOT_PORT << 20;
dd1c5523 623 else
8ac41e3e 624 val = PTYPE_LEGACY_ENDPOINT << 20;
8ac41e3e
SR
625
626 if (port == 0) {
627 val |= LNKW_X1 << 12;
dd1c5523 628 utlset1 = 0x20000000;
8ac41e3e
SR
629 } else {
630 val |= LNKW_X4 << 12;
dd1c5523 631 utlset1 = 0x20101101;
8ac41e3e
SR
632 }
633
634 SDR_WRITE(SDRN_PESDR_DLPSET(port), val);
635 SDR_WRITE(SDRN_PESDR_UTLSET1(port), utlset1);
636 SDR_WRITE(SDRN_PESDR_UTLSET2(port), 0x01210000);
637
638 switch (port) {
639 case 0:
640 SDR_WRITE(PESDR0_L0CDRCTL, 0x00003230);
5d4b3d2b 641 SDR_WRITE(PESDR0_L0DRV, 0x00000130);
8ac41e3e
SR
642 SDR_WRITE(PESDR0_L0CLK, 0x00000006);
643
644 SDR_WRITE(PESDR0_PHY_CTL_RST,0x10000000);
645 break;
646
647 case 1:
648 SDR_WRITE(PESDR1_L0CDRCTL, 0x00003230);
649 SDR_WRITE(PESDR1_L1CDRCTL, 0x00003230);
650 SDR_WRITE(PESDR1_L2CDRCTL, 0x00003230);
651 SDR_WRITE(PESDR1_L3CDRCTL, 0x00003230);
5d4b3d2b
TM
652 SDR_WRITE(PESDR1_L0DRV, 0x00000130);
653 SDR_WRITE(PESDR1_L1DRV, 0x00000130);
654 SDR_WRITE(PESDR1_L2DRV, 0x00000130);
655 SDR_WRITE(PESDR1_L3DRV, 0x00000130);
8ac41e3e
SR
656 SDR_WRITE(PESDR1_L0CLK, 0x00000006);
657 SDR_WRITE(PESDR1_L1CLK, 0x00000006);
658 SDR_WRITE(PESDR1_L2CLK, 0x00000006);
659 SDR_WRITE(PESDR1_L3CLK, 0x00000006);
660
661 SDR_WRITE(PESDR1_PHY_CTL_RST,0x10000000);
662 break;
663 }
664
665 SDR_WRITE(SDRN_PESDR_RCSSET(port), SDR_READ(SDRN_PESDR_RCSSET(port)) |
666 (PESDRx_RCSSET_RSTGU | PESDRx_RCSSET_RSTPYN));
667
668 /* Poll for PHY reset */
669 switch (port) {
670 case 0:
671 while (!(SDR_READ(PESDR0_RSTSTA) & 0x1))
672 udelay(10);
673 break;
674 case 1:
675 while (!(SDR_READ(PESDR1_RSTSTA) & 0x1))
676 udelay(10);
677 break;
678 }
679
680 SDR_WRITE(SDRN_PESDR_RCSSET(port),
681 (SDR_READ(SDRN_PESDR_RCSSET(port)) &
682 ~(PESDRx_RCSSET_RSTGU | PESDRx_RCSSET_RSTDL)) |
683 PESDRx_RCSSET_RSTPYN);
684
685 return 0;
686}
687#endif /* CONFIG_440SPE */
688
03d344bb
SR
689#if defined(CONFIG_405EX)
690int __ppc4xx_init_pcie_port_hw(int port, int rootport)
691{
692 u32 val;
693
694 if (rootport)
695 val = 0x00401000;
696 else
697 val = 0x00101000;
698
699 SDR_WRITE(SDRN_PESDR_DLPSET(port), val);
7d0a4066
SR
700 SDR_WRITE(SDRN_PESDR_UTLSET1(port), 0x00000000);
701 SDR_WRITE(SDRN_PESDR_UTLSET2(port), 0x01010000);
03d344bb
SR
702 SDR_WRITE(SDRN_PESDR_PHYSET1(port), 0x720F0000);
703 SDR_WRITE(SDRN_PESDR_PHYSET2(port), 0x70600003);
704
705 /* Assert the PE0_PHY reset */
706 SDR_WRITE(SDRN_PESDR_RCSSET(port), 0x01010000);
707 udelay(1000);
708
709 /* deassert the PE0_hotreset */
5cb4af47
SR
710 if (is_end_point(port))
711 SDR_WRITE(SDRN_PESDR_RCSSET(port), 0x01111000);
712 else
713 SDR_WRITE(SDRN_PESDR_RCSSET(port), 0x01101000);
03d344bb
SR
714
715 /* poll for phy !reset */
716 while (!(SDR_READ(SDRN_PESDR_PHYSTA(port)) & 0x00001000))
717 ;
718
719 /* deassert the PE0_gpl_utl_reset */
720 SDR_WRITE(SDRN_PESDR_RCSSET(port), 0x00101000);
721
722 if (port == 0)
723 mtdcr(DCRN_PEGPL_CFG(PCIE0), 0x10000000); /* guarded on */
724 else
725 mtdcr(DCRN_PEGPL_CFG(PCIE1), 0x10000000); /* guarded on */
726
727 return 0;
728}
729#endif /* CONFIG_405EX */
730
731int ppc4xx_init_pcie_port_hw(int port, int rootport)
653811a3 732__attribute__((weak, alias("__ppc4xx_init_pcie_port_hw")));
03d344bb
SR
733
734/*
735 * We map PCI Express configuration access into the 512MB regions
736 *
737 * NOTICE: revB is very strict about PLB real addressess and ranges to
738 * be mapped for config space; it seems to only work with d_nnnn_nnnn
739 * range (hangs the core upon config transaction attempts when set
740 * otherwise) while revA uses c_nnnn_nnnn.
741 *
8ac41e3e 742 * For 440SPe revA:
03d344bb
SR
743 * PCIE0: 0xc_4000_0000
744 * PCIE1: 0xc_8000_0000
745 * PCIE2: 0xc_c000_0000
746 *
8ac41e3e 747 * For 440SPe revB:
03d344bb
SR
748 * PCIE0: 0xd_0000_0000
749 * PCIE1: 0xd_2000_0000
750 * PCIE2: 0xd_4000_0000
751 *
752 * For 405EX:
753 * PCIE0: 0xa000_0000
754 * PCIE1: 0xc000_0000
8ac41e3e
SR
755 *
756 * For 460EX/GT:
757 * PCIE0: 0xd_0000_0000
758 * PCIE1: 0xd_2000_0000
03d344bb
SR
759 */
760static inline u64 ppc4xx_get_cfgaddr(int port)
761{
762#if defined(CONFIG_405EX)
763 if (port == 0)
6d0f6bcf 764 return (u64)CONFIG_SYS_PCIE0_CFGBASE;
03d344bb 765 else
6d0f6bcf 766 return (u64)CONFIG_SYS_PCIE1_CFGBASE;
03d344bb
SR
767#endif
768#if defined(CONFIG_440SPE)
769 if (ppc440spe_revB()) {
770 switch (port) {
771 default: /* to satisfy compiler */
772 case 0:
773 return 0x0000000d00000000ULL;
774 case 1:
775 return 0x0000000d20000000ULL;
776 case 2:
777 return 0x0000000d40000000ULL;
778 }
779 } else {
780 switch (port) {
781 default: /* to satisfy compiler */
782 case 0:
783 return 0x0000000c40000000ULL;
784 case 1:
785 return 0x0000000c80000000ULL;
786 case 2:
787 return 0x0000000cc0000000ULL;
788 }
789 }
790#endif
8ac41e3e
SR
791#if defined(CONFIG_460EX) || defined(CONFIG_460GT)
792 if (port == 0)
793 return 0x0000000d00000000ULL;
794 else
795 return 0x0000000d20000000ULL;
796#endif
03d344bb
SR
797}
798
799/*
800 * 4xx boards as end point and root point setup
2b393b0f
SR
801 * and
802 * testing inbound and out bound windows
803 *
03d344bb 804 * 4xx boards can be plugged into another 4xx boards or you can get PCI-E
2b393b0f
SR
805 * cable which can be used to setup loop back from one port to another port.
806 * Please rememeber that unless there is a endpoint plugged in to root port it
807 * will not initialize. It is the same in case of endpoint , unless there is
808 * root port attached it will not initialize.
809 *
810 * In this release of software all the PCI-E ports are configured as either
811 * endpoint or rootpoint.In future we will have support for selective ports
812 * setup as endpoint and root point in single board.
813 *
814 * Once your board came up as root point , you can verify by reading
815 * /proc/bus/pci/devices. Where you can see the configuration registers
816 * of end point device attached to the port.
817 *
03d344bb
SR
818 * Enpoint cofiguration can be verified by connecting 4xx board to any
819 * host or another 4xx board. Then try to scan the device. In case of
2b393b0f
SR
820 * linux use "lspci" or appripriate os command.
821 *
03d344bb 822 * How do I verify the inbound and out bound windows ? (4xx to 4xx)
2b393b0f
SR
823 * in this configuration inbound and outbound windows are setup to access
824 * sram memroy area. SRAM is at 0x4 0000 0000 , on PLB bus. This address
825 * is mapped at 0x90000000. From u-boot prompt write data 0xb000 0000,
826 * This is waere your POM(PLB out bound memory window) mapped. then
03d344bb 827 * read the data from other 4xx board's u-boot prompt at address
2b393b0f
SR
828 * 0x9000 0000(SRAM). Data should match.
829 * In case of inbound , write data to u-boot command prompt at 0xb000 0000
830 * which is mapped to 0x4 0000 0000. Now on rootpoint yucca u-boot prompt check
831 * data at 0x9000 0000(SRAM).Data should match.
832 */
03d344bb 833int ppc4xx_init_pcie_port(int port, int rootport)
692519b1
RJ
834{
835 static int core_init;
836 volatile u32 val = 0;
837 int attempts;
03d344bb
SR
838 u64 addr;
839 u32 low, high;
692519b1
RJ
840
841 if (!core_init) {
026f7110 842 if (ppc4xx_init_pcie())
692519b1 843 return -1;
d4cb2d17 844 ++core_init;
692519b1
RJ
845 }
846
847 /*
03d344bb 848 * Initialize various parts of the PCI Express core for our port
692519b1 849 */
03d344bb 850 ppc4xx_init_pcie_port_hw(port, rootport);
692519b1 851
2b393b0f
SR
852 /*
853 * Notice: the following delay has critical impact on device
854 * initialization - if too short (<50ms) the link doesn't get up.
855 */
856 mdelay(100);
857
6d952892 858 val = SDR_READ(SDRN_PESDR_RCSSTS(port));
2b393b0f
SR
859 if (val & (1 << 20)) {
860 printf("PCIE%d: PGRST failed %08x\n", port, val);
861 return -1;
862 }
863
864 /*
865 * Verify link is up
866 */
6d952892 867 val = SDR_READ(SDRN_PESDR_LOOP(port));
2b393b0f
SR
868 if (!(val & 0x00001000)) {
869 printf("PCIE%d: link is not up.\n", port);
870 return -1;
871 }
872
873 /*
874 * Setup UTL registers - but only on revA!
875 * We use default settings for revB chip.
876 */
877 if (!ppc440spe_revB())
026f7110 878 ppc4xx_setup_utl(port);
2b393b0f
SR
879
880 /*
881 * We map PCI Express configuration access into the 512MB regions
2b393b0f 882 */
03d344bb 883 addr = ppc4xx_get_cfgaddr(port);
97923770
SR
884 low = U64_TO_U32_LOW(addr);
885 high = U64_TO_U32_HIGH(addr);
2b393b0f
SR
886
887 switch (port) {
888 case 0:
03d344bb
SR
889 mtdcr(DCRN_PEGPL_CFGBAH(PCIE0), high);
890 mtdcr(DCRN_PEGPL_CFGBAL(PCIE0), low);
2b393b0f
SR
891 mtdcr(DCRN_PEGPL_CFGMSK(PCIE0), 0xe0000001); /* 512MB region, valid */
892 break;
2b393b0f 893 case 1:
03d344bb
SR
894 mtdcr(DCRN_PEGPL_CFGBAH(PCIE1), high);
895 mtdcr(DCRN_PEGPL_CFGBAL(PCIE1), low);
2b393b0f
SR
896 mtdcr(DCRN_PEGPL_CFGMSK(PCIE1), 0xe0000001); /* 512MB region, valid */
897 break;
6d0f6bcf 898#if CONFIG_SYS_PCIE_NR_PORTS > 2
2b393b0f 899 case 2:
03d344bb
SR
900 mtdcr(DCRN_PEGPL_CFGBAH(PCIE2), high);
901 mtdcr(DCRN_PEGPL_CFGBAL(PCIE2), low);
2b393b0f
SR
902 mtdcr(DCRN_PEGPL_CFGMSK(PCIE2), 0xe0000001); /* 512MB region, valid */
903 break;
97923770 904#endif
2b393b0f
SR
905 }
906
907 /*
908 * Check for VC0 active and assert RDY.
909 */
910 attempts = 10;
6d952892 911 while(!(SDR_READ(SDRN_PESDR_RCSSTS(port)) & (1 << 16))) {
03d344bb
SR
912 if (!(attempts--)) {
913 printf("PCIE%d: VC0 not active\n", port);
914 return -1;
2b393b0f 915 }
03d344bb 916 mdelay(1000);
2b393b0f 917 }
6d952892
SR
918 SDR_WRITE(SDRN_PESDR_RCSSET(port),
919 SDR_READ(SDRN_PESDR_RCSSET(port)) | 1 << 20);
2b393b0f
SR
920 mdelay(100);
921
922 return 0;
923}
924
03d344bb 925int ppc4xx_init_pcie_rootport(int port)
2b393b0f 926{
03d344bb
SR
927 return ppc4xx_init_pcie_port(port, 1);
928}
692519b1 929
03d344bb
SR
930int ppc4xx_init_pcie_endport(int port)
931{
932 return ppc4xx_init_pcie_port(port, 0);
692519b1
RJ
933}
934
026f7110 935void ppc4xx_setup_pcie_rootpoint(struct pci_controller *hose, int port)
692519b1
RJ
936{
937 volatile void *mbase = NULL;
2b393b0f 938 volatile void *rmbase = NULL;
692519b1
RJ
939
940 pci_set_ops(hose,
03d344bb
SR
941 pcie_read_config_byte,
942 pcie_read_config_word,
943 pcie_read_config_dword,
944 pcie_write_config_byte,
945 pcie_write_config_word,
946 pcie_write_config_dword);
2b393b0f
SR
947
948 switch (port) {
692519b1 949 case 0:
6d0f6bcf
JCPV
950 mbase = (u32 *)CONFIG_SYS_PCIE0_XCFGBASE;
951 rmbase = (u32 *)CONFIG_SYS_PCIE0_CFGBASE;
952 hose->cfg_data = (u8 *)CONFIG_SYS_PCIE0_CFGBASE;
692519b1
RJ
953 break;
954 case 1:
6d0f6bcf
JCPV
955 mbase = (u32 *)CONFIG_SYS_PCIE1_XCFGBASE;
956 rmbase = (u32 *)CONFIG_SYS_PCIE1_CFGBASE;
957 hose->cfg_data = (u8 *)CONFIG_SYS_PCIE1_CFGBASE;
692519b1 958 break;
6d0f6bcf 959#if CONFIG_SYS_PCIE_NR_PORTS > 2
692519b1 960 case 2:
6d0f6bcf
JCPV
961 mbase = (u32 *)CONFIG_SYS_PCIE2_XCFGBASE;
962 rmbase = (u32 *)CONFIG_SYS_PCIE2_CFGBASE;
963 hose->cfg_data = (u8 *)CONFIG_SYS_PCIE2_CFGBASE;
692519b1 964 break;
97923770 965#endif
692519b1
RJ
966 }
967
968 /*
969 * Set bus numbers on our root port
970 */
7f191393
GB
971 out_8((u8 *)mbase + PCI_PRIMARY_BUS, 0);
972 out_8((u8 *)mbase + PCI_SECONDARY_BUS, 1);
973 out_8((u8 *)mbase + PCI_SUBORDINATE_BUS, 1);
692519b1
RJ
974
975 /*
976 * Set up outbound translation to hose->mem_space from PLB
977 * addresses at an offset of 0xd_0000_0000. We set the low
978 * bits of the mask to 11 to turn off splitting into 8
979 * subregions and to enable the outbound translation.
980 */
981 out_le32(mbase + PECFG_POM0LAH, 0x00000000);
6d0f6bcf
JCPV
982 out_le32(mbase + PECFG_POM0LAL, CONFIG_SYS_PCIE_MEMBASE +
983 port * CONFIG_SYS_PCIE_MEMSIZE);
4dbee8a9
SR
984 debug("PECFG_POM0LA=%08x.%08x\n", in_le32(mbase + PECFG_POM0LAH),
985 in_le32(mbase + PECFG_POM0LAL));
692519b1
RJ
986
987 switch (port) {
988 case 0:
6d0f6bcf
JCPV
989 mtdcr(DCRN_PEGPL_OMR1BAH(PCIE0), CONFIG_SYS_PCIE_ADDR_HIGH);
990 mtdcr(DCRN_PEGPL_OMR1BAL(PCIE0), CONFIG_SYS_PCIE_MEMBASE +
991 port * CONFIG_SYS_PCIE_MEMSIZE);
692519b1
RJ
992 mtdcr(DCRN_PEGPL_OMR1MSKH(PCIE0), 0x7fffffff);
993 mtdcr(DCRN_PEGPL_OMR1MSKL(PCIE0),
6d0f6bcf 994 ~(CONFIG_SYS_PCIE_MEMSIZE - 1) | 3);
4dbee8a9
SR
995 debug("0:PEGPL_OMR1BA=%08x.%08x MSK=%08x.%08x\n",
996 mfdcr(DCRN_PEGPL_OMR1BAH(PCIE0)),
997 mfdcr(DCRN_PEGPL_OMR1BAL(PCIE0)),
998 mfdcr(DCRN_PEGPL_OMR1MSKH(PCIE0)),
999 mfdcr(DCRN_PEGPL_OMR1MSKL(PCIE0)));
692519b1
RJ
1000 break;
1001 case 1:
6d0f6bcf
JCPV
1002 mtdcr(DCRN_PEGPL_OMR1BAH(PCIE1), CONFIG_SYS_PCIE_ADDR_HIGH);
1003 mtdcr(DCRN_PEGPL_OMR1BAL(PCIE1), CONFIG_SYS_PCIE_MEMBASE +
1004 port * CONFIG_SYS_PCIE_MEMSIZE);
692519b1
RJ
1005 mtdcr(DCRN_PEGPL_OMR1MSKH(PCIE1), 0x7fffffff);
1006 mtdcr(DCRN_PEGPL_OMR1MSKL(PCIE1),
6d0f6bcf 1007 ~(CONFIG_SYS_PCIE_MEMSIZE - 1) | 3);
4dbee8a9
SR
1008 debug("1:PEGPL_OMR1BA=%08x.%08x MSK=%08x.%08x\n",
1009 mfdcr(DCRN_PEGPL_OMR1BAH(PCIE1)),
1010 mfdcr(DCRN_PEGPL_OMR1BAL(PCIE1)),
1011 mfdcr(DCRN_PEGPL_OMR1MSKH(PCIE1)),
1012 mfdcr(DCRN_PEGPL_OMR1MSKL(PCIE1)));
692519b1 1013 break;
6d0f6bcf 1014#if CONFIG_SYS_PCIE_NR_PORTS > 2
692519b1 1015 case 2:
6d0f6bcf
JCPV
1016 mtdcr(DCRN_PEGPL_OMR1BAH(PCIE2), CONFIG_SYS_PCIE_ADDR_HIGH);
1017 mtdcr(DCRN_PEGPL_OMR1BAL(PCIE2), CONFIG_SYS_PCIE_MEMBASE +
1018 port * CONFIG_SYS_PCIE_MEMSIZE);
692519b1
RJ
1019 mtdcr(DCRN_PEGPL_OMR1MSKH(PCIE2), 0x7fffffff);
1020 mtdcr(DCRN_PEGPL_OMR1MSKL(PCIE2),
6d0f6bcf 1021 ~(CONFIG_SYS_PCIE_MEMSIZE - 1) | 3);
4dbee8a9
SR
1022 debug("2:PEGPL_OMR1BA=%08x.%08x MSK=%08x.%08x\n",
1023 mfdcr(DCRN_PEGPL_OMR1BAH(PCIE2)),
1024 mfdcr(DCRN_PEGPL_OMR1BAL(PCIE2)),
1025 mfdcr(DCRN_PEGPL_OMR1MSKH(PCIE2)),
1026 mfdcr(DCRN_PEGPL_OMR1MSKL(PCIE2)));
692519b1 1027 break;
97923770 1028#endif
692519b1
RJ
1029 }
1030
1031 /* Set up 16GB inbound memory window at 0 */
1032 out_le32(mbase + PCI_BASE_ADDRESS_0, 0);
1033 out_le32(mbase + PCI_BASE_ADDRESS_1, 0);
1034 out_le32(mbase + PECFG_BAR0HMPA, 0x7fffffc);
1035 out_le32(mbase + PECFG_BAR0LMPA, 0);
2b393b0f
SR
1036
1037 out_le32(mbase + PECFG_PIM01SAH, 0xffff0000);
1038 out_le32(mbase + PECFG_PIM01SAL, 0x00000000);
692519b1
RJ
1039 out_le32(mbase + PECFG_PIM0LAL, 0);
1040 out_le32(mbase + PECFG_PIM0LAH, 0);
97923770
SR
1041 out_le32(mbase + PECFG_PIM1LAL, 0x00000000);
1042 out_le32(mbase + PECFG_PIM1LAH, 0x00000004);
2b393b0f
SR
1043 out_le32(mbase + PECFG_PIMEN, 0x1);
1044
1045 /* Enable I/O, Mem, and Busmaster cycles */
1046 out_le16((u16 *)(mbase + PCI_COMMAND),
1047 in_le16((u16 *)(mbase + PCI_COMMAND)) |
1048 PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
738815c0 1049
7f191393 1050 /* Set Device and Vendor Id */
97923770
SR
1051 out_le16(mbase + 0x200, 0xaaa0 + port);
1052 out_le16(mbase + 0x202, 0xbed0 + port);
7f191393
GB
1053
1054 /* Set Class Code to PCI-PCI bridge and Revision Id to 1 */
1055 out_le32(mbase + 0x208, 0x06040001);
1056
19e93b1e 1057 printf("PCIE%d: successfully set as root-complex\n", port);
2b393b0f
SR
1058}
1059
026f7110 1060int ppc4xx_setup_pcie_endpoint(struct pci_controller *hose, int port)
2b393b0f
SR
1061{
1062 volatile void *mbase = NULL;
1063 int attempts = 0;
1064
1065 pci_set_ops(hose,
1066 pcie_read_config_byte,
1067 pcie_read_config_word,
1068 pcie_read_config_dword,
1069 pcie_write_config_byte,
1070 pcie_write_config_word,
1071 pcie_write_config_dword);
1072
1073 switch (port) {
1074 case 0:
6d0f6bcf
JCPV
1075 mbase = (u32 *)CONFIG_SYS_PCIE0_XCFGBASE;
1076 hose->cfg_data = (u8 *)CONFIG_SYS_PCIE0_CFGBASE;
2b393b0f
SR
1077 break;
1078 case 1:
6d0f6bcf
JCPV
1079 mbase = (u32 *)CONFIG_SYS_PCIE1_XCFGBASE;
1080 hose->cfg_data = (u8 *)CONFIG_SYS_PCIE1_CFGBASE;
2b393b0f 1081 break;
6d0f6bcf 1082#if defined(CONFIG_SYS_PCIE2_CFGBASE)
2b393b0f 1083 case 2:
6d0f6bcf
JCPV
1084 mbase = (u32 *)CONFIG_SYS_PCIE2_XCFGBASE;
1085 hose->cfg_data = (u8 *)CONFIG_SYS_PCIE2_CFGBASE;
2b393b0f 1086 break;
97923770 1087#endif
2b393b0f
SR
1088 }
1089
1090 /*
1091 * Set up outbound translation to hose->mem_space from PLB
1092 * addresses at an offset of 0xd_0000_0000. We set the low
1093 * bits of the mask to 11 to turn off splitting into 8
1094 * subregions and to enable the outbound translation.
1095 */
1096 out_le32(mbase + PECFG_POM0LAH, 0x00001ff8);
1097 out_le32(mbase + PECFG_POM0LAL, 0x00001000);
1098
1099 switch (port) {
1100 case 0:
6d0f6bcf
JCPV
1101 mtdcr(DCRN_PEGPL_OMR1BAH(PCIE0), CONFIG_SYS_PCIE_ADDR_HIGH);
1102 mtdcr(DCRN_PEGPL_OMR1BAL(PCIE0), CONFIG_SYS_PCIE_MEMBASE +
1103 port * CONFIG_SYS_PCIE_MEMSIZE);
2b393b0f
SR
1104 mtdcr(DCRN_PEGPL_OMR1MSKH(PCIE0), 0x7fffffff);
1105 mtdcr(DCRN_PEGPL_OMR1MSKL(PCIE0),
6d0f6bcf 1106 ~(CONFIG_SYS_PCIE_MEMSIZE - 1) | 3);
2b393b0f
SR
1107 break;
1108 case 1:
6d0f6bcf
JCPV
1109 mtdcr(DCRN_PEGPL_OMR1BAH(PCIE1), CONFIG_SYS_PCIE_ADDR_HIGH);
1110 mtdcr(DCRN_PEGPL_OMR1BAL(PCIE1), CONFIG_SYS_PCIE_MEMBASE +
1111 port * CONFIG_SYS_PCIE_MEMSIZE);
2b393b0f
SR
1112 mtdcr(DCRN_PEGPL_OMR1MSKH(PCIE1), 0x7fffffff);
1113 mtdcr(DCRN_PEGPL_OMR1MSKL(PCIE1),
6d0f6bcf 1114 ~(CONFIG_SYS_PCIE_MEMSIZE - 1) | 3);
2b393b0f 1115 break;
6d0f6bcf 1116#if CONFIG_SYS_PCIE_NR_PORTS > 2
2b393b0f 1117 case 2:
6d0f6bcf
JCPV
1118 mtdcr(DCRN_PEGPL_OMR1BAH(PCIE2), CONFIG_SYS_PCIE_ADDR_HIGH);
1119 mtdcr(DCRN_PEGPL_OMR1BAL(PCIE2), CONFIG_SYS_PCIE_MEMBASE +
1120 port * CONFIG_SYS_PCIE_MEMSIZE);
2b393b0f
SR
1121 mtdcr(DCRN_PEGPL_OMR1MSKH(PCIE2), 0x7fffffff);
1122 mtdcr(DCRN_PEGPL_OMR1MSKL(PCIE2),
6d0f6bcf 1123 ~(CONFIG_SYS_PCIE_MEMSIZE - 1) | 3);
2b393b0f 1124 break;
97923770 1125#endif
2b393b0f
SR
1126 }
1127
5cb4af47 1128 /* Set up 64MB inbound memory window at 0 */
2b393b0f
SR
1129 out_le32(mbase + PCI_BASE_ADDRESS_0, 0);
1130 out_le32(mbase + PCI_BASE_ADDRESS_1, 0);
5cb4af47
SR
1131
1132 out_le32(mbase + PECFG_PIM01SAH, 0xffffffff);
1133 out_le32(mbase + PECFG_PIM01SAL, 0xfc000000);
1134
1135 /* Setup BAR0 */
1136 out_le32(mbase + PECFG_BAR0HMPA, 0x7fffffff);
1137 out_le32(mbase + PECFG_BAR0LMPA, 0xfc000000 | PCI_BASE_ADDRESS_MEM_TYPE_64);
1138
1139 /* Disable BAR1 & BAR2 */
1140 out_le32(mbase + PECFG_BAR1MPA, 0);
1141 out_le32(mbase + PECFG_BAR2HMPA, 0);
1142 out_le32(mbase + PECFG_BAR2LMPA, 0);
1143
6d0f6bcf
JCPV
1144 out_le32(mbase + PECFG_PIM0LAL, U64_TO_U32_LOW(CONFIG_SYS_PCIE_INBOUND_BASE));
1145 out_le32(mbase + PECFG_PIM0LAH, U64_TO_U32_HIGH(CONFIG_SYS_PCIE_INBOUND_BASE));
692519b1
RJ
1146 out_le32(mbase + PECFG_PIMEN, 0x1);
1147
1148 /* Enable I/O, Mem, and Busmaster cycles */
1149 out_le16((u16 *)(mbase + PCI_COMMAND),
03d344bb
SR
1150 in_le16((u16 *)(mbase + PCI_COMMAND)) |
1151 PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
97923770
SR
1152 out_le16(mbase + 0x200, 0xcaad); /* Setting vendor ID */
1153 out_le16(mbase + 0x202, 0xfeed); /* Setting device ID */
03d344bb 1154
5cb4af47
SR
1155 /* Set Class Code to Processor/PPC */
1156 out_le32(mbase + 0x208, 0x0b200001);
1157
2b393b0f 1158 attempts = 10;
6d952892 1159 while(!(SDR_READ(SDRN_PESDR_RCSSTS(port)) & (1 << 8))) {
03d344bb
SR
1160 if (!(attempts--)) {
1161 printf("PCIE%d: BME not active\n", port);
1162 return -1;
2b393b0f 1163 }
03d344bb 1164 mdelay(1000);
2b393b0f 1165 }
03d344bb 1166
19e93b1e 1167 printf("PCIE%d: successfully set as endpoint\n", port);
2b393b0f
SR
1168
1169 return 0;
692519b1 1170}
5fb692ca 1171#endif /* CONFIG_440SPE && CONFIG_PCI */