]> git.ipfire.org Git - people/ms/u-boot.git/blame - cpu/ppc4xx/cpu.c
rename CFG_ macros to CONFIG_SYS
[people/ms/u-boot.git] / cpu / ppc4xx / cpu.c
CommitLineData
c609719b 1/*
dbbd1257 2 * (C) Copyright 2000-2007
c609719b
WD
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24/*
c609719b
WD
25 * CPU specific code
26 *
27 * written or collected and sometimes rewritten by
28 * Magnus Damm <damm@bitsmart.com>
29 *
30 * minor modifications by
31 * Wolfgang Denk <wd@denx.de>
32 */
33
34#include <common.h>
35#include <watchdog.h>
36#include <command.h>
37#include <asm/cache.h>
38#include <ppc4xx.h>
39
d87080b7 40DECLARE_GLOBAL_DATA_PTR;
d87080b7 41
f3443867 42void board_reset(void);
f3443867 43
887e2ec9
SR
44#if defined(CONFIG_405GP) || \
45 defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
46 defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
6e7fb6ea
SR
47
48#define PCI_ASYNC
49
c7f69c34 50static int pci_async_enabled(void)
6e7fb6ea
SR
51{
52#if defined(CONFIG_405GP)
53 return (mfdcr(strap) & PSR_PCI_ASYNC_EN);
3d9569b2
SR
54#endif
55
887e2ec9 56#if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
2801b2d2
SR
57 defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
58 defined(CONFIG_460EX) || defined(CONFIG_460GT)
6e7fb6ea
SR
59 unsigned long val;
60
7481266e 61 mfsdr(sdr_sdstp1, val);
6e7fb6ea
SR
62 return (val & SDR0_SDSTP1_PAME_MASK);
63#endif
64}
65#endif
66
dbbd1257
SR
67#if defined(CONFIG_PCI) && !defined(CONFIG_IOP480) && \
68 !defined(CONFIG_405) && !defined(CONFIG_405EX)
c7f69c34 69static int pci_arbiter_enabled(void)
6e7fb6ea
SR
70{
71#if defined(CONFIG_405GP)
72 return (mfdcr(strap) & PSR_PCI_ARBIT_EN);
73#endif
3d9569b2 74
6e7fb6ea
SR
75#if defined(CONFIG_405EP)
76 return (mfdcr(cpc0_pci) & CPC0_PCI_ARBIT_EN);
3d9569b2
SR
77#endif
78
79#if defined(CONFIG_440GP)
6e7fb6ea
SR
80 return (mfdcr(cpc0_strp1) & CPC0_STRP1_PAE_MASK);
81#endif
82
7372ca68 83#if defined(CONFIG_440GX) || defined(CONFIG_440SP) || defined(CONFIG_440SPE)
6e7fb6ea 84 unsigned long val;
3d9569b2 85
7372ca68
SR
86 mfsdr(sdr_xcr, val);
87 return (val & 0x80000000);
88#endif
89#if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
2801b2d2
SR
90 defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
91 defined(CONFIG_460EX) || defined(CONFIG_460GT)
7372ca68
SR
92 unsigned long val;
93
94 mfsdr(sdr_pci0, val);
95 return (val & 0x80000000);
3d9569b2 96#endif
6e7fb6ea
SR
97}
98#endif
99
c7f69c34 100#if defined(CONFIG_405EP)
6e7fb6ea 101#define I2C_BOOTROM
3d9569b2 102
c7f69c34 103static int i2c_bootrom_enabled(void)
6e7fb6ea
SR
104{
105#if defined(CONFIG_405EP)
106 return (mfdcr(cpc0_boot) & CPC0_BOOT_SEP);
887e2ec9 107#else
6e7fb6ea
SR
108 unsigned long val;
109
110 mfsdr(sdr_sdcs, val);
111 return (val & SDR0_SDCS_SDD);
112#endif
113}
90e6f41c 114#endif
887e2ec9
SR
115
116#if defined(CONFIG_440GX)
117#define SDR0_PINSTP_SHIFT 29
118static char *bootstrap_str[] = {
119 "EBC (16 bits)",
120 "EBC (8 bits)",
121 "EBC (32 bits)",
122 "EBC (8 bits)",
123 "PCI",
124 "I2C (Addr 0x54)",
125 "Reserved",
126 "I2C (Addr 0x50)",
127};
e3cbe1f9 128static char bootstrap_char[] = { 'A', 'B', 'C', 'B', 'D', 'E', 'x', 'F' };
887e2ec9
SR
129#endif
130
131#if defined(CONFIG_440SP) || defined(CONFIG_440SPE)
132#define SDR0_PINSTP_SHIFT 30
133static char *bootstrap_str[] = {
134 "EBC (8 bits)",
135 "PCI",
136 "I2C (Addr 0x54)",
137 "I2C (Addr 0x50)",
138};
e3cbe1f9 139static char bootstrap_char[] = { 'A', 'B', 'C', 'D'};
887e2ec9
SR
140#endif
141
142#if defined(CONFIG_440EP) || defined(CONFIG_440GR)
143#define SDR0_PINSTP_SHIFT 29
144static char *bootstrap_str[] = {
145 "EBC (8 bits)",
146 "PCI",
147 "NAND (8 bits)",
148 "EBC (16 bits)",
149 "EBC (16 bits)",
150 "I2C (Addr 0x54)",
151 "PCI",
152 "I2C (Addr 0x52)",
153};
e3cbe1f9 154static char bootstrap_char[] = { 'A', 'B', 'C', 'D', 'E', 'G', 'F', 'H' };
887e2ec9
SR
155#endif
156
157#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
158#define SDR0_PINSTP_SHIFT 29
159static char *bootstrap_str[] = {
160 "EBC (8 bits)",
161 "EBC (16 bits)",
162 "EBC (16 bits)",
163 "NAND (8 bits)",
164 "PCI",
165 "I2C (Addr 0x54)",
166 "PCI",
167 "I2C (Addr 0x52)",
168};
e3cbe1f9 169static char bootstrap_char[] = { 'A', 'B', 'C', 'D', 'E', 'G', 'F', 'H' };
887e2ec9
SR
170#endif
171
2801b2d2
SR
172#if defined(CONFIG_460EX) || defined(CONFIG_460GT)
173#define SDR0_PINSTP_SHIFT 29
174static char *bootstrap_str[] = {
175 "EBC (8 bits)",
176 "EBC (16 bits)",
177 "PCI",
178 "PCI",
179 "EBC (16 bits)",
180 "NAND (8 bits)",
181 "I2C (Addr 0x54)", /* A8 */
182 "I2C (Addr 0x52)", /* A4 */
183};
184static char bootstrap_char[] = { 'A', 'B', 'C', 'D', 'E', 'G', 'F', 'H' };
185#endif
186
7d307936
FK
187#if defined(CONFIG_460SX)
188#define SDR0_PINSTP_SHIFT 29
189static char *bootstrap_str[] = {
190 "EBC (8 bits)",
191 "EBC (16 bits)",
192 "EBC (32 bits)",
193 "NAND (8 bits)",
194 "I2C (Addr 0x54)", /* A8 */
195 "I2C (Addr 0x52)", /* A4 */
196};
197static char bootstrap_char[] = { 'A', 'B', 'C', 'D', 'E', 'G' };
198#endif
199
90e6f41c
SR
200#if defined(CONFIG_405EZ)
201#define SDR0_PINSTP_SHIFT 28
202static char *bootstrap_str[] = {
203 "EBC (8 bits)",
204 "SPI (fast)",
205 "NAND (512 page, 4 addr cycle)",
206 "I2C (Addr 0x50)",
207 "EBC (32 bits)",
208 "I2C (Addr 0x50)",
209 "NAND (2K page, 5 addr cycle)",
210 "I2C (Addr 0x50)",
211 "EBC (16 bits)",
212 "Reserved",
213 "NAND (2K page, 4 addr cycle)",
214 "I2C (Addr 0x50)",
215 "NAND (512 page, 3 addr cycle)",
216 "I2C (Addr 0x50)",
217 "SPI (slow)",
218 "I2C (Addr 0x50)",
219};
e3cbe1f9
BM
220static char bootstrap_char[] = { 'A', 'B', 'C', 'D', 'E', 'F', 'G', 'H', \
221 'I', 'x', 'K', 'L', 'M', 'N', 'O', 'P' };
90e6f41c
SR
222#endif
223
dbbd1257
SR
224#if defined(CONFIG_405EX)
225#define SDR0_PINSTP_SHIFT 29
226static char *bootstrap_str[] = {
227 "EBC (8 bits)",
228 "EBC (16 bits)",
229 "EBC (16 bits)",
230 "NAND (8 bits)",
231 "NAND (8 bits)",
232 "I2C (Addr 0x54)",
233 "EBC (8 bits)",
234 "I2C (Addr 0x52)",
235};
236static char bootstrap_char[] = { 'A', 'B', 'C', 'D', 'E', 'G', 'F', 'H' };
237#endif
238
887e2ec9
SR
239#if defined(SDR0_PINSTP_SHIFT)
240static int bootstrap_option(void)
241{
242 unsigned long val;
243
90e6f41c
SR
244 mfsdr(SDR_PINSTP, val);
245 return ((val & 0xf0000000) >> SDR0_PINSTP_SHIFT);
887e2ec9
SR
246}
247#endif /* SDR0_PINSTP_SHIFT */
3d9569b2
SR
248
249
c609719b 250#if defined(CONFIG_440)
c7f69c34
SR
251static int do_chip_reset (unsigned long sys0, unsigned long sys1)
252{
253 /* Changes to cpc0_sys0 and cpc0_sys1 require chip
254 * reset.
255 */
256 mtdcr (cntrl0, mfdcr (cntrl0) | 0x80000000); /* Set SWE */
257 mtdcr (cpc0_sys0, sys0);
258 mtdcr (cpc0_sys1, sys1);
259 mtdcr (cntrl0, mfdcr (cntrl0) & ~0x80000000); /* Clr SWE */
260 mtspr (dbcr0, 0x20000000); /* Reset the chip */
261
262 return 1;
263}
c609719b
WD
264#endif
265
c609719b
WD
266
267int checkcpu (void)
268{
3d9569b2 269#if !defined(CONFIG_405) /* not used on Xilinx 405 FPGA implementations */
3d9569b2 270 uint pvr = get_pvr();
c609719b
WD
271 ulong clock = gd->cpu_clk;
272 char buf[32];
c609719b 273
3d9569b2 274#if !defined(CONFIG_IOP480)
ba999c53 275 char addstr[64] = "";
3d9569b2 276 sys_info_t sys_info;
c609719b
WD
277
278 puts ("CPU: ");
279
280 get_sys_info(&sys_info);
281
d865fd09
RR
282#if defined(CONFIG_XILINX_440)
283 puts("IBM PowerPC 4");
284#else
3d9569b2 285 puts("AMCC PowerPC 4");
d865fd09 286#endif
3d9569b2 287
e01bd218 288#if defined(CONFIG_405GP) || defined(CONFIG_405CR) || \
dbbd1257
SR
289 defined(CONFIG_405EP) || defined(CONFIG_405EZ) || \
290 defined(CONFIG_405EX)
3d9569b2 291 puts("05");
b867d705 292#endif
3d9569b2 293#if defined(CONFIG_440)
2801b2d2
SR
294#if defined(CONFIG_460EX) || defined(CONFIG_460GT)
295 puts("60");
296#else
3d9569b2 297 puts("40");
2801b2d2 298#endif
c609719b 299#endif
3d9569b2 300
c609719b
WD
301 switch (pvr) {
302 case PVR_405GP_RB:
3d9569b2 303 puts("GP Rev. B");
c609719b 304 break;
3d9569b2 305
c609719b 306 case PVR_405GP_RC:
3d9569b2 307 puts("GP Rev. C");
c609719b 308 break;
3d9569b2 309
c609719b 310 case PVR_405GP_RD:
3d9569b2 311 puts("GP Rev. D");
c609719b 312 break;
3d9569b2 313
42dfe7a1 314#ifdef CONFIG_405GP
3d9569b2
SR
315 case PVR_405GP_RE: /* 405GP rev E and 405CR rev C have same PVR */
316 puts("GP Rev. E");
c609719b
WD
317 break;
318#endif
3d9569b2 319
c609719b 320 case PVR_405CR_RA:
3d9569b2 321 puts("CR Rev. A");
c609719b 322 break;
3d9569b2 323
c609719b 324 case PVR_405CR_RB:
3d9569b2 325 puts("CR Rev. B");
c609719b 326 break;
c609719b 327
3d9569b2
SR
328#ifdef CONFIG_405CR
329 case PVR_405CR_RC: /* 405GP rev E and 405CR rev C have same PVR */
330 puts("CR Rev. C");
331 break;
c609719b
WD
332#endif
333
3d9569b2
SR
334 case PVR_405GPR_RB:
335 puts("GPr Rev. B");
336 break;
c609719b 337
3d9569b2
SR
338 case PVR_405EP_RB:
339 puts("EP Rev. B");
340 break;
c609719b 341
e01bd218
SR
342 case PVR_405EZ_RA:
343 puts("EZ Rev. A");
344 break;
345
dbbd1257
SR
346 case PVR_405EX1_RA:
347 puts("EX Rev. A");
348 strcpy(addstr, "Security support");
349 break;
350
351 case PVR_405EX2_RA:
352 puts("EX Rev. A");
353 strcpy(addstr, "No Security support");
354 break;
355
356 case PVR_405EXR1_RA:
357 puts("EXr Rev. A");
358 strcpy(addstr, "Security support");
359 break;
360
361 case PVR_405EXR2_RA:
362 puts("EXr Rev. A");
363 strcpy(addstr, "No Security support");
364 break;
365
70fab190
SR
366 case PVR_405EX1_RC:
367 puts("EX Rev. C");
368 strcpy(addstr, "Security support");
369 break;
370
371 case PVR_405EX2_RC:
372 puts("EX Rev. C");
373 strcpy(addstr, "No Security support");
374 break;
375
376 case PVR_405EXR1_RC:
377 puts("EXr Rev. C");
378 strcpy(addstr, "Security support");
379 break;
380
381 case PVR_405EXR2_RC:
382 puts("EXr Rev. C");
383 strcpy(addstr, "No Security support");
384 break;
385
c609719b 386#if defined(CONFIG_440)
8bde7f77 387 case PVR_440GP_RB:
c157d8e2 388 puts("GP Rev. B");
4d816774
WD
389 /* See errata 1.12: CHIP_4 */
390 if ((mfdcr(cpc0_sys0) != mfdcr(cpc0_strp0)) ||
391 (mfdcr(cpc0_sys1) != mfdcr(cpc0_strp1)) ){
392 puts ( "\n\t CPC0_SYSx DCRs corrupted. "
393 "Resetting chip ...\n");
394 udelay( 1000 * 1000 ); /* Give time for serial buf to clear */
395 do_chip_reset ( mfdcr(cpc0_strp0),
396 mfdcr(cpc0_strp1) );
397 }
c609719b 398 break;
3d9569b2 399
8bde7f77 400 case PVR_440GP_RC:
c157d8e2 401 puts("GP Rev. C");
ba56f625 402 break;
3d9569b2 403
ba56f625 404 case PVR_440GX_RA:
c157d8e2 405 puts("GX Rev. A");
ba56f625 406 break;
3d9569b2 407
ba56f625 408 case PVR_440GX_RB:
c157d8e2 409 puts("GX Rev. B");
c609719b 410 break;
3d9569b2 411
0a7c5391 412 case PVR_440GX_RC:
c157d8e2 413 puts("GX Rev. C");
0a7c5391 414 break;
3d9569b2 415
57275b69
SR
416 case PVR_440GX_RF:
417 puts("GX Rev. F");
418 break;
3d9569b2 419
c157d8e2
SR
420 case PVR_440EP_RA:
421 puts("EP Rev. A");
422 break;
3d9569b2 423
9a8d82fd
SR
424#ifdef CONFIG_440EP
425 case PVR_440EP_RB: /* 440EP rev B and 440GR rev A have same PVR */
c157d8e2
SR
426 puts("EP Rev. B");
427 break;
512f8d5d
SR
428
429 case PVR_440EP_RC: /* 440EP rev C and 440GR rev B have same PVR */
430 puts("EP Rev. C");
431 break;
9a8d82fd 432#endif /* CONFIG_440EP */
3d9569b2 433
9a8d82fd
SR
434#ifdef CONFIG_440GR
435 case PVR_440GR_RA: /* 440EP rev B and 440GR rev A have same PVR */
436 puts("GR Rev. A");
437 break;
512f8d5d 438
5770a1e4 439 case PVR_440GR_RB: /* 440EP rev C and 440GR rev B have same PVR */
512f8d5d
SR
440 puts("GR Rev. B");
441 break;
9a8d82fd 442#endif /* CONFIG_440GR */
3d9569b2
SR
443#endif /* CONFIG_440 */
444
2902fada
SR
445#ifdef CONFIG_440EPX
446 case PVR_440EPX1_RA: /* 440EPx rev A and 440GRx rev A have same PVR */
edf0b543
SR
447 puts("EPx Rev. A");
448 strcpy(addstr, "Security/Kasumi support");
887e2ec9
SR
449 break;
450
2902fada 451 case PVR_440EPX2_RA: /* 440EPx rev A and 440GRx rev A have same PVR */
edf0b543
SR
452 puts("EPx Rev. A");
453 strcpy(addstr, "No Security/Kasumi support");
887e2ec9 454 break;
2902fada 455#endif /* CONFIG_440EPX */
887e2ec9 456
2902fada
SR
457#ifdef CONFIG_440GRX
458 case PVR_440GRX1_RA: /* 440EPx rev A and 440GRx rev A have same PVR */
edf0b543
SR
459 puts("GRx Rev. A");
460 strcpy(addstr, "Security/Kasumi support");
887e2ec9
SR
461 break;
462
2902fada 463 case PVR_440GRX2_RA: /* 440EPx rev A and 440GRx rev A have same PVR */
edf0b543
SR
464 puts("GRx Rev. A");
465 strcpy(addstr, "No Security/Kasumi support");
887e2ec9 466 break;
2902fada 467#endif /* CONFIG_440GRX */
887e2ec9 468
95981778
SR
469 case PVR_440SP_6_RAB:
470 puts("SP Rev. A/B");
471 strcpy(addstr, "RAID 6 support");
6e7fb6ea
SR
472 break;
473
95981778
SR
474 case PVR_440SP_RAB:
475 puts("SP Rev. A/B");
476 strcpy(addstr, "No RAID 6 support");
477 break;
478
479 case PVR_440SP_6_RC:
480 puts("SP Rev. C");
481 strcpy(addstr, "RAID 6 support");
6e7fb6ea
SR
482 break;
483
e732faec
SR
484 case PVR_440SP_RC:
485 puts("SP Rev. C");
95981778
SR
486 strcpy(addstr, "No RAID 6 support");
487 break;
488
489 case PVR_440SPe_6_RA:
490 puts("SPe Rev. A");
491 strcpy(addstr, "RAID 6 support");
e732faec
SR
492 break;
493
6c5879f3 494 case PVR_440SPe_RA:
fe84b48a 495 puts("SPe Rev. A");
95981778
SR
496 strcpy(addstr, "No RAID 6 support");
497 break;
498
499 case PVR_440SPe_6_RB:
500 puts("SPe Rev. B");
501 strcpy(addstr, "RAID 6 support");
6c5879f3 502 break;
fe84b48a 503
6c5879f3 504 case PVR_440SPe_RB:
fe84b48a 505 puts("SPe Rev. B");
95981778 506 strcpy(addstr, "No RAID 6 support");
6c5879f3 507 break;
fe84b48a 508
2801b2d2
SR
509 case PVR_460EX_RA:
510 puts("EX Rev. A");
511 strcpy(addstr, "No Security/Kasumi support");
512 break;
513
514 case PVR_460EX_SE_RA:
515 puts("EX Rev. A");
516 strcpy(addstr, "Security/Kasumi support");
517 break;
518
519 case PVR_460GT_RA:
520 puts("GT Rev. A");
521 strcpy(addstr, "No Security/Kasumi support");
522 break;
523
524 case PVR_460GT_SE_RA:
525 puts("GT Rev. A");
526 strcpy(addstr, "Security/Kasumi support");
527 break;
528
7d307936
FK
529 case PVR_460SX_RA:
530 puts("SX Rev. A");
531 strcpy(addstr, "Security support");
532 break;
533
534 case PVR_460SX_RA_V1:
535 puts("SX Rev. A");
536 strcpy(addstr, "No Security support");
537 break;
538
539 case PVR_460GX_RA:
540 puts("GX Rev. A");
541 strcpy(addstr, "Security support");
542 break;
543
544 case PVR_460GX_RA_V1:
545 puts("GX Rev. A");
546 strcpy(addstr, "No Security support");
547 break;
548
d865fd09
RR
549 case PVR_VIRTEX5:
550 puts("x5 VIRTEX5");
551 break;
552
8bde7f77 553 default:
17f50f22 554 printf (" UNKNOWN (PVR=%08x)", pvr);
c609719b
WD
555 break;
556 }
3d9569b2
SR
557
558 printf (" at %s MHz (PLB=%lu, OPB=%lu, EBC=%lu MHz)\n", strmhz(buf, clock),
e01bd218
SR
559 sys_info.freqPLB / 1000000,
560 get_OPB_freq() / 1000000,
dbbd1257 561 sys_info.freqEBC / 1000000);
3d9569b2 562
edf0b543
SR
563 if (addstr[0] != 0)
564 printf(" %s\n", addstr);
565
6e7fb6ea
SR
566#if defined(I2C_BOOTROM)
567 printf (" I2C boot EEPROM %sabled\n", i2c_bootrom_enabled() ? "en" : "dis");
90e6f41c 568#endif /* I2C_BOOTROM */
887e2ec9 569#if defined(SDR0_PINSTP_SHIFT)
e3cbe1f9 570 printf (" Bootstrap Option %c - ", bootstrap_char[bootstrap_option()]);
887e2ec9 571 printf ("Boot ROM Location %s\n", bootstrap_str[bootstrap_option()]);
ba999c53 572#endif /* SDR0_PINSTP_SHIFT */
3d9569b2 573
dbbd1257 574#if defined(CONFIG_PCI) && !defined(CONFIG_405EX)
6e7fb6ea 575 printf (" Internal PCI arbiter %sabled", pci_arbiter_enabled() ? "en" : "dis");
3d9569b2
SR
576#endif
577
6e7fb6ea
SR
578#if defined(PCI_ASYNC)
579 if (pci_async_enabled()) {
3d9569b2
SR
580 printf (", PCI async ext clock used");
581 } else {
582 printf (", PCI sync clock at %lu MHz",
583 sys_info.freqPLB / sys_info.pllPciDiv / 1000000);
584 }
c609719b 585#endif
3d9569b2 586
dbbd1257 587#if defined(CONFIG_PCI) && !defined(CONFIG_405EX)
3d9569b2
SR
588 putc('\n');
589#endif
590
dbbd1257 591#if defined(CONFIG_405EP) || defined(CONFIG_405EZ) || defined(CONFIG_405EX)
3d9569b2
SR
592 printf (" 16 kB I-Cache 16 kB D-Cache");
593#elif defined(CONFIG_440)
594 printf (" 32 kB I-Cache 32 kB D-Cache");
595#else
596 printf (" 16 kB I-Cache %d kB D-Cache",
597 ((pvr | 0x00000001) == PVR_405GPR_RB) ? 16 : 8);
598#endif
599#endif /* !defined(CONFIG_IOP480) */
600
601#if defined(CONFIG_IOP480)
602 printf ("PLX IOP480 (PVR=%08x)", pvr);
603 printf (" at %s MHz:", strmhz(buf, clock));
604 printf (" %u kB I-Cache", 4);
605 printf (" %u kB D-Cache", 2);
606#endif
607
608#endif /* !defined(CONFIG_405) */
609
610 putc ('\n');
c609719b
WD
611
612 return 0;
613}
614
692519b1
RJ
615int ppc440spe_revB() {
616 unsigned int pvr;
617
618 pvr = get_pvr();
5a5c5698 619 if ((pvr == PVR_440SPe_6_RB) || (pvr == PVR_440SPe_RB))
692519b1
RJ
620 return 1;
621 else
622 return 0;
623}
c609719b
WD
624
625/* ------------------------------------------------------------------------- */
626
8bde7f77 627int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
c609719b 628{
1f94d162
SR
629#if defined(CONFIG_BOARD_RESET)
630 board_reset();
1729b92c 631#else
6d0f6bcf
JCPV
632#if defined(CONFIG_SYS_4xx_RESET_TYPE)
633 mtspr(dbcr0, CONFIG_SYS_4xx_RESET_TYPE << 28);
c157d8e2 634#else
8bde7f77
WD
635 /*
636 * Initiate system reset in debug control register DBCR
637 */
f3443867 638 mtspr(dbcr0, 0x30000000);
6d0f6bcf 639#endif /* defined(CONFIG_SYS_4xx_RESET_TYPE) */
f3443867 640#endif /* defined(CONFIG_BOARD_RESET) */
c157d8e2 641
c609719b
WD
642 return 1;
643}
644
c609719b
WD
645
646/*
647 * Get timebase clock frequency
648 */
649unsigned long get_tbclk (void)
650{
3d9569b2 651#if !defined(CONFIG_IOP480)
c609719b
WD
652 sys_info_t sys_info;
653
654 get_sys_info(&sys_info);
655 return (sys_info.freqProcessor);
c609719b 656#else
3d9569b2 657 return (66000000);
c609719b
WD
658#endif
659
660}
661
662
663#if defined(CONFIG_WATCHDOG)
c7f69c34 664void watchdog_reset(void)
c609719b
WD
665{
666 int re_enable = disable_interrupts();
667 reset_4xx_watchdog();
668 if (re_enable) enable_interrupts();
669}
670
c7f69c34 671void reset_4xx_watchdog(void)
c609719b
WD
672{
673 /*
674 * Clear TSR(WIS) bit
675 */
676 mtspr(tsr, 0x40000000);
677}
678#endif /* CONFIG_WATCHDOG */