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PPC4xx: Minimal changes to add vxWorks support
[people/ms/u-boot.git] / cpu / ppc4xx / start.S
CommitLineData
0442ed86
WD		 1/*
2 * Copyright (C) 1998 Dan Malek <dmalek@jlc.net>
3 * Copyright (C) 1999 Magnus Damm <kieraypc01.p.y.kie.era.ericsson.se>
4 * Copyright (C) 2000,2001,2002 Wolfgang Denk <wd@denx.de>
3cb86f3e 5 * Copyright (C) 2007 Stefan Roese <sr@denx.de>, DENX Software Engineering
0442ed86
WD		 6 *
7 * See file CREDITS for list of people who contributed to this
8 * project.
9 *
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
23 * MA 02111-1307 USA
24 */
83b4cfa3
WD		 25/*------------------------------------------------------------------------------+
26 *
27 * This source code has been made available to you by IBM on an AS-IS
28 * basis. Anyone receiving this source is licensed under IBM
29 * copyrights to use it in any way he or she deems fit, including
30 * copying it, modifying it, compiling it, and redistributing it either
31 * with or without modifications. No license under IBM patents or
32 * patent applications is to be implied by the copyright license.
33 *
34 * Any user of this software should understand that IBM cannot provide
35 * technical support for this software and will not be responsible for
36 * any consequences resulting from the use of this software.
37 *
38 * Any person who transfers this source code or any derivative work
39 * must include the IBM copyright notice, this paragraph, and the
40 * preceding two paragraphs in the transferred software.
41 *
42 * COPYRIGHT I B M CORPORATION 1995
43 * LICENSED MATERIAL - PROGRAM PROPERTY OF I B M
44 *-------------------------------------------------------------------------------
45 */
0442ed86 46
0c8721a4 47/* U-Boot - Startup Code for AMCC 4xx PowerPC based Embedded Boards
0442ed86
WD		 48 *
49 *
50 * The processor starts at 0xfffffffc and the code is executed
51 * from flash/rom.
52 * in memory, but as long we don't jump around before relocating.
53 * board_init lies at a quite high address and when the cpu has
54 * jumped there, everything is ok.
55 * This works because the cpu gives the FLASH (CS0) the whole
56 * address space at startup, and board_init lies as a echo of
57 * the flash somewhere up there in the memorymap.
58 *
59 * board_init will change CS0 to be positioned at the correct
60 * address and (s)dram will be positioned at address 0
61 */
62#include <config.h>
0442ed86
WD		 63#include <ppc4xx.h>
64#include <version.h>
65
66#define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */
67
68#include <ppc_asm.tmpl>
69#include <ppc_defs.h>
70
71#include <asm/cache.h>
72#include <asm/mmu.h>
73
74#ifndef CONFIG_IDENT_STRING
75#define CONFIG_IDENT_STRING ""
76#endif
77
78#ifdef CFG_INIT_DCACHE_CS
79# if (CFG_INIT_DCACHE_CS == 0)
80# define PBxAP pb0ap
81# define PBxCR pb0cr
82# endif
83# if (CFG_INIT_DCACHE_CS == 1)
84# define PBxAP pb1ap
85# define PBxCR pb1cr
86# endif
87# if (CFG_INIT_DCACHE_CS == 2)
88# define PBxAP pb2ap
89# define PBxCR pb2cr
90# endif
91# if (CFG_INIT_DCACHE_CS == 3)
92# define PBxAP pb3ap
93# define PBxCR pb3cr
94# endif
95# if (CFG_INIT_DCACHE_CS == 4)
96# define PBxAP pb4ap
97# define PBxCR pb4cr
98# endif
99# if (CFG_INIT_DCACHE_CS == 5)
100# define PBxAP pb5ap
101# define PBxCR pb5cr
102# endif
103# if (CFG_INIT_DCACHE_CS == 6)
104# define PBxAP pb6ap
105# define PBxCR pb6cr
106# endif
107# if (CFG_INIT_DCACHE_CS == 7)
108# define PBxAP pb7ap
109# define PBxCR pb7cr
110# endif
111#endif /* CFG_INIT_DCACHE_CS */
112
83b4cfa3 113#define function_prolog(func_name) .text; \
cf959c7d
SR		 114 .align 2; \
115 .globl func_name; \
116 func_name:
83b4cfa3 117#define function_epilog(func_name) .type func_name,@function; \
cf959c7d
SR		 118 .size func_name,.-func_name
119
0442ed86
WD		 120/* We don't want the MMU yet.
121*/
122#undef MSR_KERNEL
123#define MSR_KERNEL ( MSR_ME ) /* Machine Check */
124
125
126 .extern ext_bus_cntlr_init
127 .extern sdram_init
887e2ec9
SR		 128#ifdef CONFIG_NAND_U_BOOT
129 .extern reconfig_tlb0
130#endif
0442ed86
WD		 131
132/*
133 * Set up GOT: Global Offset Table
134 *
135 * Use r14 to access the GOT
136 */
887e2ec9 137#if !defined(CONFIG_NAND_SPL)
0442ed86
WD		 138 START_GOT
139 GOT_ENTRY(_GOT2_TABLE_)
140 GOT_ENTRY(_FIXUP_TABLE_)
141
142 GOT_ENTRY(_start)
143 GOT_ENTRY(_start_of_vectors)
144 GOT_ENTRY(_end_of_vectors)
145 GOT_ENTRY(transfer_to_handler)
146
3b57fe0a 147 GOT_ENTRY(__init_end)
0442ed86 148 GOT_ENTRY(_end)
5d232d0e 149 GOT_ENTRY(__bss_start)
0442ed86 150 END_GOT
887e2ec9
SR		 151#endif /* CONFIG_NAND_SPL */
152
153#if defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
154 /*
155 * NAND U-Boot image is started from offset 0
156 */
157 .text
c440bfe6 158#if defined(CONFIG_440)
887e2ec9 159 bl reconfig_tlb0
c440bfe6 160#endif
887e2ec9
SR		 161 GET_GOT
162 bl cpu_init_f /* run low-level CPU init code (from Flash) */
163 bl board_init_f
164#endif
0442ed86
WD		 165
166/*
167 * 440 Startup -- on reset only the top 4k of the effective
168 * address space is mapped in by an entry in the instruction
169 * and data shadow TLB. The .bootpg section is located in the
170 * top 4k & does only what's necessary to map in the the rest
171 * of the boot rom. Once the boot rom is mapped in we can
172 * proceed with normal startup.
173 *
174 * NOTE: CS0 only covers the top 2MB of the effective address
175 * space after reset.
176 */
177
178#if defined(CONFIG_440)
887e2ec9 179#if !defined(CONFIG_NAND_SPL)
0442ed86 180 .section .bootpg,"ax"
887e2ec9 181#endif
0442ed86
WD		 182 .globl _start_440
183
184/**************************************************************************/
185_start_440:
511d0c72
WD		 186 /*--------------------------------------------------------------------+
187 | 440EPX BUP Change - Hardware team request
188 +--------------------------------------------------------------------*/
887e2ec9
SR		 189#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
190 sync
191 nop
192 nop
193#endif
6c5879f3
MB		 194 /*----------------------------------------------------------------+
195 | Core bug fix. Clear the esr
196 +-----------------------------------------------------------------*/
edd6cf20 197 li r0,0
b87dfd28 198 mtspr esr,r0
0442ed86
WD		 199 /*----------------------------------------------------------------*/
200 /* Clear and set up some registers. */
201 /*----------------------------------------------------------------*/
f901a83b
WD		 202 iccci r0,r0 /* NOTE: operands not used for 440 */
203 dccci r0,r0 /* NOTE: operands not used for 440 */
0442ed86
WD		 204 sync
205 li r0,0
206 mtspr srr0,r0
207 mtspr srr1,r0
208 mtspr csrr0,r0
209 mtspr csrr1,r0
887e2ec9
SR		 210 /* NOTE: 440GX adds machine check status regs */
211#if defined(CONFIG_440) && !defined(CONFIG_440GP)
f901a83b
WD		 212 mtspr mcsrr0,r0
213 mtspr mcsrr1,r0
887e2ec9 214 mfspr r1,mcsr
f901a83b 215 mtspr mcsr,r1
ba56f625 216#endif
20532833
SR		 217
218 /*----------------------------------------------------------------*/
219 /* CCR0 init */
220 /*----------------------------------------------------------------*/
221 /* Disable store gathering & broadcast, guarantee inst/data
222 * cache block touch, force load/store alignment
223 * (see errata 1.12: 440_33)
224 */
225 lis r1,0x0030 /* store gathering & broadcast disable */
226 ori r1,r1,0x6000 /* cache touch */
227 mtspr ccr0,r1
228
0442ed86
WD		 229 /*----------------------------------------------------------------*/
230 /* Initialize debug */
231 /*----------------------------------------------------------------*/
887e2ec9
SR		 232 mfspr r1,dbcr0
233 andis. r1, r1, 0x8000 /* test DBCR0[EDM] bit */
234 bne skip_debug_init /* if set, don't clear debug register */
0442ed86
WD		 235 mtspr dbcr0,r0
236 mtspr dbcr1,r0
237 mtspr dbcr2,r0
238 mtspr iac1,r0
239 mtspr iac2,r0
240 mtspr iac3,r0
241 mtspr dac1,r0
242 mtspr dac2,r0
243 mtspr dvc1,r0
244 mtspr dvc2,r0
245
246 mfspr r1,dbsr
247 mtspr dbsr,r1 /* Clear all valid bits */
887e2ec9 248skip_debug_init:
0442ed86 249
6c5879f3
MB		 250#if defined (CONFIG_440SPE)
251 /*----------------------------------------------------------------+
252 | Initialize Core Configuration Reg1.
253 | a. ICDPEI: Record even parity. Normal operation.
254 | b. ICTPEI: Record even parity. Normal operation.
255 | c. DCTPEI: Record even parity. Normal operation.
256 | d. DCDPEI: Record even parity. Normal operation.
257 | e. DCUPEI: Record even parity. Normal operation.
258 | f. DCMPEI: Record even parity. Normal operation.
259 | g. FCOM: Normal operation
260 | h. MMUPEI: Record even parity. Normal operation.
261 | i. FFF: Flush only as much data as necessary.
edd6cf20 262 | j. TCS: Timebase increments from CPU clock.
6c5879f3 263 +-----------------------------------------------------------------*/
edd6cf20 264 li r0,0
6c5879f3
MB		 265 mtspr ccr1, r0
266
267 /*----------------------------------------------------------------+
268 | Reset the timebase.
269 | The previous write to CCR1 sets the timebase source.
270 +-----------------------------------------------------------------*/
6c5879f3
MB		 271 mtspr tbl, r0
272 mtspr tbu, r0
273#endif
274
0442ed86
WD		 275 /*----------------------------------------------------------------*/
276 /* Setup interrupt vectors */
277 /*----------------------------------------------------------------*/
278 mtspr ivpr,r0 /* Vectors start at 0x0000_0000 */
f901a83b 279 li r1,0x0100
0442ed86 280 mtspr ivor0,r1 /* Critical input */
f901a83b 281 li r1,0x0200
0442ed86 282 mtspr ivor1,r1 /* Machine check */
f901a83b 283 li r1,0x0300
0442ed86 284 mtspr ivor2,r1 /* Data storage */
f901a83b 285 li r1,0x0400
0442ed86
WD		 286 mtspr ivor3,r1 /* Instruction storage */
287 li r1,0x0500
288 mtspr ivor4,r1 /* External interrupt */
289 li r1,0x0600
290 mtspr ivor5,r1 /* Alignment */
291 li r1,0x0700
292 mtspr ivor6,r1 /* Program check */
293 li r1,0x0800
294 mtspr ivor7,r1 /* Floating point unavailable */
295 li r1,0x0c00
296 mtspr ivor8,r1 /* System call */
efa35cf1 297 li r1,0x0a00
83b4cfa3 298 mtspr ivor9,r1 /* Auxiliary Processor unavailable */
efa35cf1
GB		 299 li r1,0x0900
300 mtspr ivor10,r1 /* Decrementer */
0442ed86 301 li r1,0x1300
efa35cf1
GB		 302 mtspr ivor13,r1 /* Data TLB error */
303 li r1,0x1400
0442ed86
WD		 304 mtspr ivor14,r1 /* Instr TLB error */
305 li r1,0x2000
306 mtspr ivor15,r1 /* Debug */
307
308 /*----------------------------------------------------------------*/
309 /* Configure cache regions */
310 /*----------------------------------------------------------------*/
311 mtspr inv0,r0
312 mtspr inv1,r0
313 mtspr inv2,r0
314 mtspr inv3,r0
315 mtspr dnv0,r0
316 mtspr dnv1,r0
317 mtspr dnv2,r0
318 mtspr dnv3,r0
319 mtspr itv0,r0
320 mtspr itv1,r0
321 mtspr itv2,r0
322 mtspr itv3,r0
323 mtspr dtv0,r0
324 mtspr dtv1,r0
325 mtspr dtv2,r0
326 mtspr dtv3,r0
327
328 /*----------------------------------------------------------------*/
329 /* Cache victim limits */
330 /*----------------------------------------------------------------*/
331 /* floors 0, ceiling max to use the entire cache -- nothing locked
332 */
333 lis r1,0x0001
334 ori r1,r1,0xf800
335 mtspr ivlim,r1
336 mtspr dvlim,r1
337
6c5879f3
MB		 338 /*----------------------------------------------------------------+
339 |Initialize MMUCR[STID] = 0.
340 +-----------------------------------------------------------------*/
341 mfspr r0,mmucr
342 addis r1,0,0xFFFF
343 ori r1,r1,0xFF00
344 and r0,r0,r1
345 mtspr mmucr,r0
346
0442ed86
WD		 347 /*----------------------------------------------------------------*/
348 /* Clear all TLB entries -- TID = 0, TS = 0 */
349 /*----------------------------------------------------------------*/
6c5879f3 350 addis r0,0,0x0000
0442ed86
WD		 351 li r1,0x003f /* 64 TLB entries */
352 mtctr r1
6c5879f3
MB		 353rsttlb: tlbwe r0,r1,0x0000 /* Invalidate all entries (V=0)*/
354 tlbwe r0,r1,0x0001
355 tlbwe r0,r1,0x0002
0442ed86 356 subi r1,r1,0x0001
6c5879f3 357 bdnz rsttlb
0442ed86
WD		 358
359 /*----------------------------------------------------------------*/
360 /* TLB entry setup -- step thru tlbtab */
361 /*----------------------------------------------------------------*/
692519b1
RJ		 362#if defined(CONFIG_440SPE)
363 /*----------------------------------------------------------------*/
364 /* We have different TLB tables for revA and rev B of 440SPe */
365 /*----------------------------------------------------------------*/
366 mfspr r1, PVR
367 lis r0,0x5342
368 ori r0,r0,0x1891
369 cmpw r7,r1,r0
370 bne r7,..revA
371 bl tlbtabB
372 b ..goon
373..revA:
374 bl tlbtabA
375..goon:
376#else
0442ed86 377 bl tlbtab /* Get tlbtab pointer */
692519b1 378#endif
0442ed86
WD		 379 mr r5,r0
380 li r1,0x003f /* 64 TLB entries max */
381 mtctr r1
382 li r4,0 /* TLB # */
383
384 addi r5,r5,-4
3851: lwzu r0,4(r5)
386 cmpwi r0,0
387 beq 2f /* 0 marks end */
388 lwzu r1,4(r5)
389 lwzu r2,4(r5)
390 tlbwe r0,r4,0 /* TLB Word 0 */
391 tlbwe r1,r4,1 /* TLB Word 1 */
392 tlbwe r2,r4,2 /* TLB Word 2 */
393 addi r4,r4,1 /* Next TLB */
394 bdnz 1b
395
396 /*----------------------------------------------------------------*/
397 /* Continue from 'normal' start */
398 /*----------------------------------------------------------------*/
887e2ec9
SR		 3992:
400
401#if defined(CONFIG_NAND_SPL)
cf959c7d 402#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
887e2ec9 403 /*
cf959c7d 404 * Enable internal SRAM (only on 440EPx/GRx, 440EP/GR have no OCM)
887e2ec9
SR		 405 */
406 lis r2,0x7fff
407 ori r2,r2,0xffff
408 mfdcr r1,isram0_dpc
409 and r1,r1,r2 /* Disable parity check */
410 mtdcr isram0_dpc,r1
411 mfdcr r1,isram0_pmeg
412 and r1,r1,r2 /* Disable pwr mgmt */
413 mtdcr isram0_pmeg,r1
cf959c7d
SR		 414#endif
415#if defined(CONFIG_440EP)
416 /*
417 * On 440EP with no internal SRAM, we setup SDRAM very early
418 * and copy the NAND_SPL to SDRAM and jump to it
419 */
420 /* Clear Dcache to use as RAM */
421 addis r3,r0,CFG_INIT_RAM_ADDR@h
422 ori r3,r3,CFG_INIT_RAM_ADDR@l
423 addis r4,r0,CFG_INIT_RAM_END@h
424 ori r4,r4,CFG_INIT_RAM_END@l
425 rlwinm. r5,r4,0,27,31
426 rlwinm r5,r4,27,5,31
427 beq ..d_ran3
428 addi r5,r5,0x0001
429..d_ran3:
430 mtctr r5
431..d_ag3:
432 dcbz r0,r3
433 addi r3,r3,32
434 bdnz ..d_ag3
435 /*----------------------------------------------------------------*/
436 /* Setup the stack in internal SRAM */
437 /*----------------------------------------------------------------*/
438 lis r1,CFG_INIT_RAM_ADDR@h
439 ori r1,r1,CFG_INIT_SP_OFFSET@l
440 li r0,0
441 stwu r0,-4(r1)
442 stwu r0,-4(r1) /* Terminate call chain */
443
444 stwu r1,-8(r1) /* Save back chain and move SP */
445 lis r0,RESET_VECTOR@h /* Address of reset vector */
446 ori r0,r0, RESET_VECTOR@l
447 stwu r1,-8(r1) /* Save back chain and move SP */
448 stw r0,+12(r1) /* Save return addr (underflow vect) */
449 sync
450 bl early_sdram_init
451 sync
452#endif /* CONFIG_440EP */
887e2ec9
SR		 453
454 /*
455 * Copy SPL from cache into internal SRAM
456 */
457 li r4,(CFG_NAND_BOOT_SPL_SIZE >> 2) - 1
458 mtctr r4
459 lis r2,CFG_NAND_BOOT_SPL_SRC@h
460 ori r2,r2,CFG_NAND_BOOT_SPL_SRC@l
461 lis r3,CFG_NAND_BOOT_SPL_DST@h
462 ori r3,r3,CFG_NAND_BOOT_SPL_DST@l
463spl_loop:
464 lwzu r4,4(r2)
465 stwu r4,4(r3)
466 bdnz spl_loop
467
468 /*
469 * Jump to code in RAM
470 */
471 bl 00f
47200: mflr r10
473 lis r3,(CFG_NAND_BOOT_SPL_SRC - CFG_NAND_BOOT_SPL_DST)@h
474 ori r3,r3,(CFG_NAND_BOOT_SPL_SRC - CFG_NAND_BOOT_SPL_DST)@l
475 sub r10,r10,r3
476 addi r10,r10,28
477 mtlr r10
478 blr
479
480start_ram:
481 sync
482 isync
cf959c7d 483#endif /* CONFIG_NAND_SPL */
887e2ec9
SR		 484
485 bl 3f
0442ed86
WD		 486 b _start
487
4883: li r0,0
489 mtspr srr1,r0 /* Keep things disabled for now */
490 mflr r1
491 mtspr srr0,r1
492 rfi
b867d705 493#endif /* CONFIG_440 */
0442ed86
WD		 494
495/*
496 * r3 - 1st arg to board_init(): IMMP pointer
497 * r4 - 2nd arg to board_init(): boot flag
498 */
887e2ec9 499#ifndef CONFIG_NAND_SPL
0442ed86
WD		 500 .text
501 .long 0x27051956 /* U-Boot Magic Number */
502 .globl version_string
503version_string:
504 .ascii U_BOOT_VERSION
505 .ascii " (", __DATE__, " - ", __TIME__, ")"
506 .ascii CONFIG_IDENT_STRING, "\0"
507
0442ed86 508 . = EXC_OFF_SYS_RESET
efa35cf1
GB		 509 .globl _start_of_vectors
510_start_of_vectors:
511
512/* Critical input. */
513 CRIT_EXCEPTION(0x100, CritcalInput, UnknownException)
514
515#ifdef CONFIG_440
516/* Machine check */
83b4cfa3 517 MCK_EXCEPTION(0x200, MachineCheck, MachineCheckException)
efa35cf1 518#else
83b4cfa3 519 CRIT_EXCEPTION(0x200, MachineCheck, MachineCheckException)
efa35cf1
GB		 520#endif /* CONFIG_440 */
521
522/* Data Storage exception. */
523 STD_EXCEPTION(0x300, DataStorage, UnknownException)
524
525/* Instruction Storage exception. */
526 STD_EXCEPTION(0x400, InstStorage, UnknownException)
527
528/* External Interrupt exception. */
529 STD_EXCEPTION(0x500, ExtInterrupt, external_interrupt)
530
531/* Alignment exception. */
532 . = 0x600
533Alignment:
534 EXCEPTION_PROLOG(SRR0, SRR1)
535 mfspr r4,DAR
536 stw r4,_DAR(r21)
537 mfspr r5,DSISR
538 stw r5,_DSISR(r21)
539 addi r3,r1,STACK_FRAME_OVERHEAD
540 li r20,MSR_KERNEL
541 rlwimi r20,r23,0,16,16 /* copy EE bit from saved MSR */
542 lwz r6,GOT(transfer_to_handler)
543 mtlr r6
544 blrl
545.L_Alignment:
546 .long AlignmentException - _start + _START_OFFSET
547 .long int_return - _start + _START_OFFSET
548
549/* Program check exception */
550 . = 0x700
551ProgramCheck:
552 EXCEPTION_PROLOG(SRR0, SRR1)
553 addi r3,r1,STACK_FRAME_OVERHEAD
554 li r20,MSR_KERNEL
555 rlwimi r20,r23,0,16,16 /* copy EE bit from saved MSR */
556 lwz r6,GOT(transfer_to_handler)
557 mtlr r6
558 blrl
559.L_ProgramCheck:
560 .long ProgramCheckException - _start + _START_OFFSET
561 .long int_return - _start + _START_OFFSET
562
563#ifdef CONFIG_440
564 STD_EXCEPTION(0x800, FPUnavailable, UnknownException)
565 STD_EXCEPTION(0x900, Decrementer, DecrementerPITException)
566 STD_EXCEPTION(0xa00, APU, UnknownException)
df8a24cd 567#endif
efa35cf1
GB		 568 STD_EXCEPTION(0xc00, SystemCall, UnknownException)
569
570#ifdef CONFIG_440
571 STD_EXCEPTION(0x1300, DataTLBError, UnknownException)
572 STD_EXCEPTION(0x1400, InstructionTLBError, UnknownException)
573#else
574 STD_EXCEPTION(0x1000, PIT, DecrementerPITException)
575 STD_EXCEPTION(0x1100, InstructionTLBMiss, UnknownException)
576 STD_EXCEPTION(0x1200, DataTLBMiss, UnknownException)
577#endif
578 CRIT_EXCEPTION(0x2000, DebugBreakpoint, DebugException )
579
580 .globl _end_of_vectors
581_end_of_vectors:
582 . = _START_OFFSET
887e2ec9 583#endif
0442ed86
WD		 584 .globl _start
585_start:
586
587/*****************************************************************************/
588#if defined(CONFIG_440)
589
590 /*----------------------------------------------------------------*/
591 /* Clear and set up some registers. */
592 /*----------------------------------------------------------------*/
593 li r0,0x0000
594 lis r1,0xffff
595 mtspr dec,r0 /* prevent dec exceptions */
596 mtspr tbl,r0 /* prevent fit & wdt exceptions */
597 mtspr tbu,r0
598 mtspr tsr,r1 /* clear all timer exception status */
599 mtspr tcr,r0 /* disable all */
600 mtspr esr,r0 /* clear exception syndrome register */
601 mtxer r0 /* clear integer exception register */
0442ed86
WD		 602
603 /*----------------------------------------------------------------*/
604 /* Debug setup -- some (not very good) ice's need an event*/
605 /* to establish control :-( Define CFG_INIT_DBCR to the dbsr */
606 /* value you need in this case 0x8cff 0000 should do the trick */
607 /*----------------------------------------------------------------*/
608#if defined(CFG_INIT_DBCR)
609 lis r1,0xffff
610 ori r1,r1,0xffff
611 mtspr dbsr,r1 /* Clear all status bits */
612 lis r0,CFG_INIT_DBCR@h
613 ori r0,r0,CFG_INIT_DBCR@l
614 mtspr dbcr0,r0
615 isync
616#endif
617
618 /*----------------------------------------------------------------*/
619 /* Setup the internal SRAM */
620 /*----------------------------------------------------------------*/
621 li r0,0
887e2ec9
SR		 622
623#ifdef CFG_INIT_RAM_DCACHE
c157d8e2 624 /* Clear Dcache to use as RAM */
f901a83b
WD		 625 addis r3,r0,CFG_INIT_RAM_ADDR@h
626 ori r3,r3,CFG_INIT_RAM_ADDR@l
627 addis r4,r0,CFG_INIT_RAM_END@h
628 ori r4,r4,CFG_INIT_RAM_END@l
c157d8e2 629 rlwinm. r5,r4,0,27,31
f901a83b
WD		 630 rlwinm r5,r4,27,5,31
631 beq ..d_ran
632 addi r5,r5,0x0001
c157d8e2 633..d_ran:
f901a83b 634 mtctr r5
c157d8e2 635..d_ag:
f901a83b
WD		 636 dcbz r0,r3
637 addi r3,r3,32
638 bdnz ..d_ag
887e2ec9
SR		 639#endif /* CFG_INIT_RAM_DCACHE */
640
641 /* 440EP & 440GR are only 440er PPC's without internal SRAM */
642#if !defined(CONFIG_440EP) && !defined(CONFIG_440GR)
643 /* not all PPC's have internal SRAM usable as L2-cache */
644#if defined(CONFIG_440GX) || defined(CONFIG_440SP) || defined(CONFIG_440SPE)
f901a83b 645 mtdcr l2_cache_cfg,r0 /* Ensure L2 Cache is off */
ba56f625 646#endif
0442ed86 647
887e2ec9 648 lis r2,0x7fff
0442ed86
WD		 649 ori r2,r2,0xffff
650 mfdcr r1,isram0_dpc
651 and r1,r1,r2 /* Disable parity check */
652 mtdcr isram0_dpc,r1
653 mfdcr r1,isram0_pmeg
887e2ec9 654 and r1,r1,r2 /* Disable pwr mgmt */
0442ed86
WD		 655 mtdcr isram0_pmeg,r1
656
657 lis r1,0x8000 /* BAS = 8000_0000 */
6e7fb6ea 658#if defined(CONFIG_440GX) || defined(CONFIG_440SP)
ba56f625 659 ori r1,r1,0x0980 /* first 64k */
f901a83b 660 mtdcr isram0_sb0cr,r1
ba56f625
WD		 661 lis r1,0x8001
662 ori r1,r1,0x0980 /* second 64k */
f901a83b 663 mtdcr isram0_sb1cr,r1
ba56f625
WD		 664 lis r1, 0x8002
665 ori r1,r1, 0x0980 /* third 64k */
f901a83b 666 mtdcr isram0_sb2cr,r1
ba56f625
WD		 667 lis r1, 0x8003
668 ori r1,r1, 0x0980 /* fourth 64k */
f901a83b 669 mtdcr isram0_sb3cr,r1
6c5879f3
MB		 670#elif defined(CONFIG_440SPE)
671 lis r1,0x0000 /* BAS = 0000_0000 */
672 ori r1,r1,0x0984 /* first 64k */
673 mtdcr isram0_sb0cr,r1
674 lis r1,0x0001
675 ori r1,r1,0x0984 /* second 64k */
676 mtdcr isram0_sb1cr,r1
677 lis r1, 0x0002
678 ori r1,r1, 0x0984 /* third 64k */
679 mtdcr isram0_sb2cr,r1
680 lis r1, 0x0003
681 ori r1,r1, 0x0984 /* fourth 64k */
682 mtdcr isram0_sb3cr,r1
887e2ec9 683#elif defined(CONFIG_440GP)
0442ed86
WD		 684 ori r1,r1,0x0380 /* 8k rw */
685 mtdcr isram0_sb0cr,r1
887e2ec9 686 mtdcr isram0_sb1cr,r0 /* Disable bank 1 */
c157d8e2 687#endif
887e2ec9 688#endif /* #if !defined(CONFIG_440EP) && !defined(CONFIG_440GR) */
0442ed86
WD		 689
690 /*----------------------------------------------------------------*/
691 /* Setup the stack in internal SRAM */
692 /*----------------------------------------------------------------*/
693 lis r1,CFG_INIT_RAM_ADDR@h
694 ori r1,r1,CFG_INIT_SP_OFFSET@l
0442ed86
WD		 695 li r0,0
696 stwu r0,-4(r1)
697 stwu r0,-4(r1) /* Terminate call chain */
698
699 stwu r1,-8(r1) /* Save back chain and move SP */
700 lis r0,RESET_VECTOR@h /* Address of reset vector */
701 ori r0,r0, RESET_VECTOR@l
702 stwu r1,-8(r1) /* Save back chain and move SP */
703 stw r0,+12(r1) /* Save return addr (underflow vect) */
704
887e2ec9
SR		 705#ifdef CONFIG_NAND_SPL
706 bl nand_boot /* will not return */
707#else
0442ed86 708 GET_GOT
5568e613
SR		 709
710 bl cpu_init_f /* run low-level CPU init code (from Flash) */
0442ed86 711 bl board_init_f
887e2ec9 712#endif
0442ed86
WD		 713
714#endif /* CONFIG_440 */
715
716/*****************************************************************************/
717#ifdef CONFIG_IOP480
718 /*----------------------------------------------------------------------- */
719 /* Set up some machine state registers. */
720 /*----------------------------------------------------------------------- */
721 addi r0,r0,0x0000 /* initialize r0 to zero */
722 mtspr esr,r0 /* clear Exception Syndrome Reg */
723 mttcr r0 /* timer control register */
724 mtexier r0 /* disable all interrupts */
0442ed86
WD		 725 addis r4,r0,0xFFFF /* set r4 to 0xFFFFFFFF (status in the */
726 ori r4,r4,0xFFFF /* dbsr is cleared by setting bits to 1) */
727 mtdbsr r4 /* clear/reset the dbsr */
728 mtexisr r4 /* clear all pending interrupts */
729 addis r4,r0,0x8000
730 mtexier r4 /* enable critical exceptions */
731 addis r4,r0,0x0000 /* assume 403GCX - enable core clk */
732 ori r4,r4,0x4020 /* dbling (no harm done on GA and GC */
733 mtiocr r4 /* since bit not used) & DRC to latch */
734 /* data bus on rising edge of CAS */
735 /*----------------------------------------------------------------------- */
736 /* Clear XER. */
737 /*----------------------------------------------------------------------- */
738 mtxer r0
739 /*----------------------------------------------------------------------- */
740 /* Invalidate i-cache and d-cache TAG arrays. */
741 /*----------------------------------------------------------------------- */
742 addi r3,0,1024 /* 1/4 of I-cache size, half of D-cache */
743 addi r4,0,1024 /* 1/4 of I-cache */
744..cloop:
745 iccci 0,r3
746 iccci r4,r3
747 dccci 0,r3
748 addic. r3,r3,-16 /* move back one cache line */
749 bne ..cloop /* loop back to do rest until r3 = 0 */
750
751 /* */
752 /* initialize IOP480 so it can read 1 MB code area for SRAM spaces */
753 /* this requires enabling MA[17..0], by default only MA[12..0] are enabled. */
754 /* */
755
756 /* first copy IOP480 register base address into r3 */
757 addis r3,0,0x5000 /* IOP480 register base address hi */
758/* ori r3,r3,0x0000 / IOP480 register base address lo */
759
760#ifdef CONFIG_ADCIOP
761 /* use r4 as the working variable */
762 /* turn on CS3 (LOCCTL.7) */
763 lwz r4,0x84(r3) /* LOCTL is at offset 0x84 */
764 andi. r4,r4,0xff7f /* make bit 7 = 0 -- CS3 mode */
765 stw r4,0x84(r3) /* LOCTL is at offset 0x84 */
766#endif
767
768#ifdef CONFIG_DASA_SIM
769 /* use r4 as the working variable */
770 /* turn on MA17 (LOCCTL.7) */
771 lwz r4,0x84(r3) /* LOCTL is at offset 0x84 */
772 ori r4,r4,0x80 /* make bit 7 = 1 -- MA17 mode */
773 stw r4,0x84(r3) /* LOCTL is at offset 0x84 */
774#endif
775
776 /* turn on MA16..13 (LCS0BRD.12 = 0) */
777 lwz r4,0x100(r3) /* LCS0BRD is at offset 0x100 */
778 andi. r4,r4,0xefff /* make bit 12 = 0 */
779 stw r4,0x100(r3) /* LCS0BRD is at offset 0x100 */
780
781 /* make sure above stores all comlete before going on */
782 sync
783
784 /* last thing, set local init status done bit (DEVINIT.31) */
785 lwz r4,0x80(r3) /* DEVINIT is at offset 0x80 */
786 oris r4,r4,0x8000 /* make bit 31 = 1 */
787 stw r4,0x80(r3) /* DEVINIT is at offset 0x80 */
788
789 /* clear all pending interrupts and disable all interrupts */
790 li r4,-1 /* set p1 to 0xffffffff */
791 stw r4,0x1b0(r3) /* clear all pending interrupts */
792 stw r4,0x1b8(r3) /* clear all pending interrupts */
793 li r4,0 /* set r4 to 0 */
794 stw r4,0x1b4(r3) /* disable all interrupts */
795 stw r4,0x1bc(r3) /* disable all interrupts */
796
797 /* make sure above stores all comlete before going on */
798 sync
799
800 /*----------------------------------------------------------------------- */
801 /* Enable two 128MB cachable regions. */
802 /*----------------------------------------------------------------------- */
dbbd1257 803 addis r1,r0,0xc000
0442ed86
WD		 804 addi r1,r1,0x0001
805 mticcr r1 /* instruction cache */
806
807 addis r1,r0,0x0000
808 addi r1,r1,0x0000
809 mtdccr r1 /* data cache */
810
811 addis r1,r0,CFG_INIT_RAM_ADDR@h
812 ori r1,r1,CFG_INIT_SP_OFFSET /* set up the stack to SDRAM */
813 li r0, 0 /* Make room for stack frame header and */
814 stwu r0, -4(r1) /* clear final stack frame so that */
815 stwu r0, -4(r1) /* stack backtraces terminate cleanly */
816
817 GET_GOT /* initialize GOT access */
818
819 bl board_init_f /* run first part of init code (from Flash) */
820
821#endif /* CONFIG_IOP480 */
822
823/*****************************************************************************/
e01bd218
SR		 824#if defined(CONFIG_405GP) || defined(CONFIG_405CR) || \
825 defined(CONFIG_405EP) || defined(CONFIG_405EZ) || \
dbbd1257 826 defined(CONFIG_405EX) || defined(CONFIG_405)
0442ed86
WD		 827 /*----------------------------------------------------------------------- */
828 /* Clear and set up some registers. */
829 /*----------------------------------------------------------------------- */
830 addi r4,r0,0x0000
dbbd1257 831#if !defined(CONFIG_405EX)
0442ed86 832 mtspr sgr,r4
dbbd1257
SR		 833#else
834 /*
835 * On 405EX, completely clearing the SGR leads to PPC hangup
836 * upon PCIe configuration access. The PCIe memory regions
837 * need to be guarded!
838 */
839 lis r3,0x0000
840 ori r3,r3,0x7FFC
841 mtspr sgr,r3
842#endif
0442ed86
WD		 843 mtspr dcwr,r4
844 mtesr r4 /* clear Exception Syndrome Reg */
845 mttcr r4 /* clear Timer Control Reg */
846 mtxer r4 /* clear Fixed-Point Exception Reg */
847 mtevpr r4 /* clear Exception Vector Prefix Reg */
0442ed86
WD		 848 addi r4,r0,(0xFFFF-0x10000) /* set r4 to 0xFFFFFFFF (status in the */
849 /* dbsr is cleared by setting bits to 1) */
850 mtdbsr r4 /* clear/reset the dbsr */
851
852 /*----------------------------------------------------------------------- */
853 /* Invalidate I and D caches. Enable I cache for defined memory regions */
854 /* to speed things up. Leave the D cache disabled for now. It will be */
855 /* enabled/left disabled later based on user selected menu options. */
856 /* Be aware that the I cache may be disabled later based on the menu */
857 /* options as well. See miscLib/main.c. */
858 /*----------------------------------------------------------------------- */
859 bl invalidate_icache
860 bl invalidate_dcache
861
862 /*----------------------------------------------------------------------- */
863 /* Enable two 128MB cachable regions. */
864 /*----------------------------------------------------------------------- */
dbbd1257 865 lis r4,0xc000
e01bd218 866 ori r4,r4,0x0001
0442ed86
WD		 867 mticcr r4 /* instruction cache */
868 isync
869
e01bd218
SR		 870 lis r4,0x0000
871 ori r4,r4,0x0000
0442ed86
WD		 872 mtdccr r4 /* data cache */
873
dbbd1257 874#if !(defined(CFG_EBC_PB0AP) && defined(CFG_EBC_PB0CR)) || defined(CONFIG_405EX)
0442ed86
WD		 875 /*----------------------------------------------------------------------- */
876 /* Tune the speed and size for flash CS0 */
877 /*----------------------------------------------------------------------- */
878 bl ext_bus_cntlr_init
879#endif
dbbd1257
SR		 880#if !(defined(CFG_INIT_DCACHE_CS) || defined(CFG_TEMP_STACK_OCM))
881 /*
882 * Boards like the Kilauea (405EX) don't have OCM and can't use
883 * DCache for init-ram. So setup stack here directly after the
884 * SDRAM is initialized.
885 */
886 lis r1, CFG_INIT_RAM_ADDR@h
887 ori r1,r1,CFG_INIT_SP_OFFSET /* set up the stack in SDRAM */
888
889 li r0, 0 /* Make room for stack frame header and */
890 stwu r0, -4(r1) /* clear final stack frame so that */
891 stwu r0, -4(r1) /* stack backtraces terminate cleanly */
892 /*
893 * Set up a dummy frame to store reset vector as return address.
894 * this causes stack underflow to reset board.
895 */
896 stwu r1, -8(r1) /* Save back chain and move SP */
897 lis r0, RESET_VECTOR@h /* Address of reset vector */
898 ori r0, r0, RESET_VECTOR@l
899 stwu r1, -8(r1) /* Save back chain and move SP */
900 stw r0, +12(r1) /* Save return addr (underflow vect) */
901#endif /* !(CFG_INIT_DCACHE_CS || !CFG_TEM_STACK_OCM) */
0442ed86 902
b867d705
SR		 903#if defined(CONFIG_405EP)
904 /*----------------------------------------------------------------------- */
905 /* DMA Status, clear to come up clean */
906 /*----------------------------------------------------------------------- */
f901a83b
WD		 907 addis r3,r0, 0xFFFF /* Clear all existing DMA status */
908 ori r3,r3, 0xFFFF
909 mtdcr dmasr, r3
b867d705 910
f901a83b 911 bl ppc405ep_init /* do ppc405ep specific init */
b867d705
SR		 912#endif /* CONFIG_405EP */
913
0442ed86 914#if defined(CFG_OCM_DATA_ADDR) && defined(CFG_OCM_DATA_SIZE)
e01bd218
SR		 915#if defined(CONFIG_405EZ)
916 /********************************************************************
917 * Setup OCM - On Chip Memory - PPC405EZ uses OCM Controller V2
918 *******************************************************************/
919 /*
920 * We can map the OCM on the PLB3, so map it at
921 * CFG_OCM_DATA_ADDR + 0x8000
922 */
923 lis r3,CFG_OCM_DATA_ADDR@h /* OCM location */
924 ori r3,r3,CFG_OCM_DATA_ADDR@l
df8a24cd 925 ori r3,r3,0x0270 /* 16K for Bank 1, R/W/Enable */
e01bd218
SR		 926 mtdcr ocmplb3cr1,r3 /* Set PLB Access */
927 ori r3,r3,0x4000 /* Add 0x4000 for bank 2 */
928 mtdcr ocmplb3cr2,r3 /* Set PLB Access */
929 isync
930
83b4cfa3 931 lis r3,CFG_OCM_DATA_ADDR@h /* OCM location */
e01bd218 932 ori r3,r3,CFG_OCM_DATA_ADDR@l
83b4cfa3
WD		 933 ori r3,r3,0x0270 /* 16K for Bank 1, R/W/Enable */
934 mtdcr ocmdscr1, r3 /* Set Data Side */
935 mtdcr ocmiscr1, r3 /* Set Instruction Side */
e01bd218 936 ori r3,r3,0x4000 /* Add 0x4000 for bank 2 */
83b4cfa3
WD		 937 mtdcr ocmdscr2, r3 /* Set Data Side */
938 mtdcr ocmiscr2, r3 /* Set Instruction Side */
939 addis r3,0,0x0800 /* OCM Data Parity Disable - 1 Wait State */
d7568947 940 mtdcr ocmdsisdpc,r3
e01bd218
SR		 941
942 isync
3cb86f3e 943#else /* CONFIG_405EZ */
0442ed86
WD		 944 /********************************************************************
945 * Setup OCM - On Chip Memory
946 *******************************************************************/
947 /* Setup OCM */
8bde7f77
WD		 948 lis r0, 0x7FFF
949 ori r0, r0, 0xFFFF
f901a83b 950 mfdcr r3, ocmiscntl /* get instr-side IRAM config */
3cb86f3e
SR		 951 mfdcr r4, ocmdscntl /* get data-side IRAM config */
952 and r3, r3, r0 /* disable data-side IRAM */
953 and r4, r4, r0 /* disable data-side IRAM */
954 mtdcr ocmiscntl, r3 /* set instr-side IRAM config */
955 mtdcr ocmdscntl, r4 /* set data-side IRAM config */
8bde7f77 956 isync
0442ed86 957
83b4cfa3 958 lis r3,CFG_OCM_DATA_ADDR@h /* OCM location */
3cb86f3e 959 ori r3,r3,CFG_OCM_DATA_ADDR@l
0442ed86
WD		 960 mtdcr ocmdsarc, r3
961 addis r4, 0, 0xC000 /* OCM data area enabled */
962 mtdcr ocmdscntl, r4
8bde7f77 963 isync
e01bd218 964#endif /* CONFIG_405EZ */
0442ed86
WD		 965#endif
966
c440bfe6
SR		 967#ifdef CONFIG_NAND_SPL
968 /*
969 * Copy SPL from cache into internal SRAM
970 */
971 li r4,(CFG_NAND_BOOT_SPL_SIZE >> 2) - 1
972 mtctr r4
973 lis r2,CFG_NAND_BOOT_SPL_SRC@h
974 ori r2,r2,CFG_NAND_BOOT_SPL_SRC@l
975 lis r3,CFG_NAND_BOOT_SPL_DST@h
976 ori r3,r3,CFG_NAND_BOOT_SPL_DST@l
977spl_loop:
978 lwzu r4,4(r2)
979 stwu r4,4(r3)
980 bdnz spl_loop
981
982 /*
983 * Jump to code in RAM
984 */
985 bl 00f
98600: mflr r10
987 lis r3,(CFG_NAND_BOOT_SPL_SRC - CFG_NAND_BOOT_SPL_DST)@h
988 ori r3,r3,(CFG_NAND_BOOT_SPL_SRC - CFG_NAND_BOOT_SPL_DST)@l
989 sub r10,r10,r3
990 addi r10,r10,28
991 mtlr r10
992 blr
993
994start_ram:
995 sync
996 isync
997#endif /* CONFIG_NAND_SPL */
998
0442ed86
WD		 999 /*----------------------------------------------------------------------- */
1000 /* Setup temporary stack in DCACHE or OCM if needed for SDRAM SPD. */
1001 /*----------------------------------------------------------------------- */
1002#ifdef CFG_INIT_DCACHE_CS
1003 /*----------------------------------------------------------------------- */
1004 /* Memory Bank x (nothingness) initialization 1GB+64MEG */
1005 /* used as temporary stack pointer for stage0 */
1006 /*----------------------------------------------------------------------- */
1007 li r4,PBxAP
1008 mtdcr ebccfga,r4
1009 lis r4,0x0380
1010 ori r4,r4,0x0480
1011 mtdcr ebccfgd,r4
1012
1013 addi r4,0,PBxCR
1014 mtdcr ebccfga,r4
1015 lis r4,0x400D
1016 ori r4,r4,0xa000
1017 mtdcr ebccfgd,r4
1018
dbbd1257 1019 /* turn on data cache for this region */
0442ed86
WD		 1020 lis r4,0x0080
1021 mtdccr r4
1022
1023 /* set stack pointer and clear stack to known value */
1024
1025 lis r1,CFG_INIT_RAM_ADDR@h
f901a83b 1026 ori r1,r1,CFG_INIT_SP_OFFSET@l
0442ed86
WD		 1027
1028 li r4,2048 /* we store 2048 words to stack */
1029 mtctr r4
1030
1031 lis r2,CFG_INIT_RAM_ADDR@h /* we also clear data area */
f901a83b 1032 ori r2,r2,CFG_INIT_RAM_END@l /* so cant copy value from r1 */
0442ed86
WD		 1033
1034 lis r4,0xdead /* we store 0xdeaddead in the stack */
1035 ori r4,r4,0xdead
1036
1037..stackloop:
1038 stwu r4,-4(r2)
1039 bdnz ..stackloop
1040
1041 li r0, 0 /* Make room for stack frame header and */
1042 stwu r0, -4(r1) /* clear final stack frame so that */
1043 stwu r0, -4(r1) /* stack backtraces terminate cleanly */
1044 /*
1045 * Set up a dummy frame to store reset vector as return address.
1046 * this causes stack underflow to reset board.
1047 */
1048 stwu r1, -8(r1) /* Save back chain and move SP */
1049 addis r0, 0, RESET_VECTOR@h /* Address of reset vector */
1050 ori r0, r0, RESET_VECTOR@l
1051 stwu r1, -8(r1) /* Save back chain and move SP */
1052 stw r0, +12(r1) /* Save return addr (underflow vect) */
1053
1054#elif defined(CFG_TEMP_STACK_OCM) && \
1055 (defined(CFG_OCM_DATA_ADDR) && defined(CFG_OCM_DATA_SIZE))
1056 /*
1057 * Stack in OCM.
1058 */
1059
1060 /* Set up Stack at top of OCM */
1061 lis r1, (CFG_INIT_RAM_ADDR + CFG_INIT_SP_OFFSET)@h
1062 ori r1, r1, (CFG_INIT_RAM_ADDR + CFG_INIT_SP_OFFSET)@l
1063
1064 /* Set up a zeroized stack frame so that backtrace works right */
1065 li r0, 0
1066 stwu r0, -4(r1)
1067 stwu r0, -4(r1)
1068
1069 /*
1070 * Set up a dummy frame to store reset vector as return address.
1071 * this causes stack underflow to reset board.
1072 */
1073 stwu r1, -8(r1) /* Save back chain and move SP */
1074 lis r0, RESET_VECTOR@h /* Address of reset vector */
1075 ori r0, r0, RESET_VECTOR@l
1076 stwu r1, -8(r1) /* Save back chain and move SP */
1077 stw r0, +12(r1) /* Save return addr (underflow vect) */
1078#endif /* CFG_INIT_DCACHE_CS */
1079
1080 /*----------------------------------------------------------------------- */
f901a83b 1081 /* Initialize SDRAM Controller */
0442ed86
WD		 1082 /*----------------------------------------------------------------------- */
1083 bl sdram_init
1084
c440bfe6
SR		 1085#ifdef CONFIG_NAND_SPL
1086 bl nand_boot /* will not return */
1087#else
0442ed86
WD		 1088 GET_GOT /* initialize GOT access */
1089
f901a83b 1090 bl cpu_init_f /* run low-level CPU init code (from Flash) */
0442ed86
WD		 1091
1092 /* NEVER RETURNS! */
1093 bl board_init_f /* run first part of init code (from Flash) */
c440bfe6 1094#endif /* CONFIG_NAND_SPL */
0442ed86 1095
12f34241
WD		 1096#endif /* CONFIG_405GP || CONFIG_405CR || CONFIG_405 || CONFIG_405EP */
1097 /*----------------------------------------------------------------------- */
0442ed86
WD		 1098
1099
887e2ec9 1100#ifndef CONFIG_NAND_SPL
0442ed86
WD		 1101/*
1102 * This code finishes saving the registers to the exception frame
1103 * and jumps to the appropriate handler for the exception.
1104 * Register r21 is pointer into trap frame, r1 has new stack pointer.
1105 */
1106 .globl transfer_to_handler
1107transfer_to_handler:
1108 stw r22,_NIP(r21)
1109 lis r22,MSR_POW@h
1110 andc r23,r23,r22
1111 stw r23,_MSR(r21)
1112 SAVE_GPR(7, r21)
1113 SAVE_4GPRS(8, r21)
1114 SAVE_8GPRS(12, r21)
1115 SAVE_8GPRS(24, r21)
0442ed86
WD		 1116 mflr r23
1117 andi. r24,r23,0x3f00 /* get vector offset */
1118 stw r24,TRAP(r21)
1119 li r22,0
1120 stw r22,RESULT(r21)
1121 mtspr SPRG2,r22 /* r1 is now kernel sp */
0442ed86
WD		 1122 lwz r24,0(r23) /* virtual address of handler */
1123 lwz r23,4(r23) /* where to go when done */
1124 mtspr SRR0,r24
1125 mtspr SRR1,r20
1126 mtlr r23
1127 SYNC
1128 rfi /* jump to handler, enable MMU */
1129
1130int_return:
1131 mfmsr r28 /* Disable interrupts */
1132 li r4,0
1133 ori r4,r4,MSR_EE
1134 andc r28,r28,r4
1135 SYNC /* Some chip revs need this... */
1136 mtmsr r28
1137 SYNC
1138 lwz r2,_CTR(r1)
1139 lwz r0,_LINK(r1)
1140 mtctr r2
1141 mtlr r0
1142 lwz r2,_XER(r1)
1143 lwz r0,_CCR(r1)
1144 mtspr XER,r2
1145 mtcrf 0xFF,r0
1146 REST_10GPRS(3, r1)
1147 REST_10GPRS(13, r1)
1148 REST_8GPRS(23, r1)
1149 REST_GPR(31, r1)
1150 lwz r2,_NIP(r1) /* Restore environment */
1151 lwz r0,_MSR(r1)
1152 mtspr SRR0,r2
1153 mtspr SRR1,r0
1154 lwz r0,GPR0(r1)
1155 lwz r2,GPR2(r1)
1156 lwz r1,GPR1(r1)
1157 SYNC
1158 rfi
1159
1160crit_return:
1161 mfmsr r28 /* Disable interrupts */
1162 li r4,0
1163 ori r4,r4,MSR_EE
1164 andc r28,r28,r4
1165 SYNC /* Some chip revs need this... */
1166 mtmsr r28
1167 SYNC
1168 lwz r2,_CTR(r1)
1169 lwz r0,_LINK(r1)
1170 mtctr r2
1171 mtlr r0
1172 lwz r2,_XER(r1)
1173 lwz r0,_CCR(r1)
1174 mtspr XER,r2
1175 mtcrf 0xFF,r0
1176 REST_10GPRS(3, r1)
1177 REST_10GPRS(13, r1)
1178 REST_8GPRS(23, r1)
1179 REST_GPR(31, r1)
1180 lwz r2,_NIP(r1) /* Restore environment */
1181 lwz r0,_MSR(r1)
83b4cfa3
WD		 1182 mtspr csrr0,r2
1183 mtspr csrr1,r0
0442ed86
WD		 1184 lwz r0,GPR0(r1)
1185 lwz r2,GPR2(r1)
1186 lwz r1,GPR1(r1)
1187 SYNC
1188 rfci
1189
efa35cf1
GB		 1190#ifdef CONFIG_440
1191mck_return:
83b4cfa3
WD		 1192 mfmsr r28 /* Disable interrupts */
1193 li r4,0
1194 ori r4,r4,MSR_EE
1195 andc r28,r28,r4
1196 SYNC /* Some chip revs need this... */
1197 mtmsr r28
1198 SYNC
1199 lwz r2,_CTR(r1)
1200 lwz r0,_LINK(r1)
1201 mtctr r2
1202 mtlr r0
1203 lwz r2,_XER(r1)
1204 lwz r0,_CCR(r1)
1205 mtspr XER,r2
1206 mtcrf 0xFF,r0
1207 REST_10GPRS(3, r1)
1208 REST_10GPRS(13, r1)
1209 REST_8GPRS(23, r1)
1210 REST_GPR(31, r1)
1211 lwz r2,_NIP(r1) /* Restore environment */
1212 lwz r0,_MSR(r1)
1213 mtspr mcsrr0,r2
1214 mtspr mcsrr1,r0
1215 lwz r0,GPR0(r1)
1216 lwz r2,GPR2(r1)
1217 lwz r1,GPR1(r1)
1218 SYNC
1219 rfmci
efa35cf1
GB		 1220#endif /* CONFIG_440 */
1221
1222
0442ed86
WD		 1223 .globl get_pvr
1224get_pvr:
1225 mfspr r3, PVR
1226 blr
1227
0442ed86
WD		 1228/*------------------------------------------------------------------------------- */
1229/* Function: out16 */
1230/* Description: Output 16 bits */
1231/*------------------------------------------------------------------------------- */
1232 .globl out16
1233out16:
1234 sth r4,0x0000(r3)
1235 blr
1236
1237/*------------------------------------------------------------------------------- */
1238/* Function: out16r */
1239/* Description: Byte reverse and output 16 bits */
1240/*------------------------------------------------------------------------------- */
1241 .globl out16r
1242out16r:
1243 sthbrx r4,r0,r3
1244 blr
1245
0442ed86
WD		 1246/*------------------------------------------------------------------------------- */
1247/* Function: out32r */
1248/* Description: Byte reverse and output 32 bits */
1249/*------------------------------------------------------------------------------- */
1250 .globl out32r
1251out32r:
1252 stwbrx r4,r0,r3
1253 blr
1254
1255/*------------------------------------------------------------------------------- */
1256/* Function: in16 */
1257/* Description: Input 16 bits */
1258/*------------------------------------------------------------------------------- */
1259 .globl in16
1260in16:
1261 lhz r3,0x0000(r3)
1262 blr
1263
1264/*------------------------------------------------------------------------------- */
1265/* Function: in16r */
1266/* Description: Input 16 bits and byte reverse */
1267/*------------------------------------------------------------------------------- */
1268 .globl in16r
1269in16r:
1270 lhbrx r3,r0,r3
1271 blr
1272
0442ed86
WD		 1273/*------------------------------------------------------------------------------- */
1274/* Function: in32r */
1275/* Description: Input 32 bits and byte reverse */
1276/*------------------------------------------------------------------------------- */
1277 .globl in32r
1278in32r:
1279 lwbrx r3,r0,r3
1280 blr
1281
1282/*------------------------------------------------------------------------------- */
1283/* Function: ppcDcbf */
1284/* Description: Data Cache block flush */
1285/* Input: r3 = effective address */
1286/* Output: none. */
1287/*------------------------------------------------------------------------------- */
1288 .globl ppcDcbf
1289ppcDcbf:
1290 dcbf r0,r3
1291 blr
1292
1293/*------------------------------------------------------------------------------- */
1294/* Function: ppcDcbi */
1295/* Description: Data Cache block Invalidate */
1296/* Input: r3 = effective address */
1297/* Output: none. */
1298/*------------------------------------------------------------------------------- */
1299 .globl ppcDcbi
1300ppcDcbi:
1301 dcbi r0,r3
1302 blr
1303
1304/*------------------------------------------------------------------------------- */
1305/* Function: ppcSync */
1306/* Description: Processor Synchronize */
1307/* Input: none. */
1308/* Output: none. */
1309/*------------------------------------------------------------------------------- */
1310 .globl ppcSync
1311ppcSync:
1312 sync
1313 blr
1314
0442ed86
WD		 1315/*
1316 * void relocate_code (addr_sp, gd, addr_moni)
1317 *
1318 * This "function" does not return, instead it continues in RAM
1319 * after relocating the monitor code.
1320 *
1321 * r3 = dest
1322 * r4 = src
1323 * r5 = length in bytes
1324 * r6 = cachelinesize
1325 */
1326 .globl relocate_code
1327relocate_code:
9b94ac61
SR		 1328#ifdef CONFIG_4xx_DCACHE
1329 /*
1330 * We need to flush the Init Data before the dcache will be
1331 * invalidated
1332 */
1333
1334 /* save regs */
1335 mr r9,r3
1336 mr r10,r4
1337 mr r11,r5
1338
1339 mr r3,r4
1340 addi r4,r4,0x200 /* should be enough for init data */
1341 bl flush_dcache_range
1342
1343 /* restore regs */
1344 mr r3,r9
1345 mr r4,r10
1346 mr r5,r11
1347#endif
887e2ec9
SR		 1348#if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
1349 defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
00cdb4ce 1350 defined(CONFIG_440SP) || defined(CONFIG_440SPE)
a4c8d138
SR		 1351 /*
1352 * On some 440er platforms the cache is enabled in the first TLB (Boot-CS)
1353 * to speed up the boot process. Now this cache needs to be disabled.
1354 */
1355 iccci 0,0 /* Invalidate inst cache */
1356 dccci 0,0 /* Invalidate data cache, now no longer our stack */
c157d8e2 1357 sync
a4c8d138 1358 isync
85dc2a7f
NG		 1359#ifdef CFG_TLB_FOR_BOOT_FLASH
1360 addi r1,r0,CFG_TLB_FOR_BOOT_FLASH /* Use defined TLB */
1361#else
1362 addi r1,r0,0x0000 /* Default TLB entry is #0 */
1363#endif
c157d8e2 1364 tlbre r0,r1,0x0002 /* Read contents */
6e7fb6ea 1365 ori r0,r0,0x0c00 /* Or in the inhibit, write through bit */
f901a83b 1366 tlbwe r0,r1,0x0002 /* Save it out */
a4c8d138 1367 sync
c157d8e2
SR		 1368 isync
1369#endif
0442ed86
WD		 1370 mr r1, r3 /* Set new stack pointer */
1371 mr r9, r4 /* Save copy of Init Data pointer */
1372 mr r10, r5 /* Save copy of Destination Address */
1373
1374 mr r3, r5 /* Destination Address */
1375 lis r4, CFG_MONITOR_BASE@h /* Source Address */
1376 ori r4, r4, CFG_MONITOR_BASE@l
3b57fe0a
WD		 1377 lwz r5, GOT(__init_end)
1378 sub r5, r5, r4
9b94ac61 1379 li r6, L1_CACHE_BYTES /* Cache Line Size */
0442ed86
WD		 1380
1381 /*
1382 * Fix GOT pointer:
1383 *
1384 * New GOT-PTR = (old GOT-PTR - CFG_MONITOR_BASE) + Destination Address
1385 *
1386 * Offset:
1387 */
1388 sub r15, r10, r4
1389
1390 /* First our own GOT */
1391 add r14, r14, r15
1392 /* the the one used by the C code */
1393 add r30, r30, r15
1394
1395 /*
1396 * Now relocate code
1397 */
1398
1399 cmplw cr1,r3,r4
1400 addi r0,r5,3
1401 srwi. r0,r0,2
1402 beq cr1,4f /* In place copy is not necessary */
1403 beq 7f /* Protect against 0 count */
1404 mtctr r0
1405 bge cr1,2f
1406
1407 la r8,-4(r4)
1408 la r7,-4(r3)
14091: lwzu r0,4(r8)
1410 stwu r0,4(r7)
1411 bdnz 1b
1412 b 4f
1413
14142: slwi r0,r0,2
1415 add r8,r4,r0
1416 add r7,r3,r0
14173: lwzu r0,-4(r8)
1418 stwu r0,-4(r7)
1419 bdnz 3b
1420
1421/*
1422 * Now flush the cache: note that we must start from a cache aligned
1423 * address. Otherwise we might miss one cache line.
1424 */
14254: cmpwi r6,0
1426 add r5,r3,r5
1427 beq 7f /* Always flush prefetch queue in any case */
1428 subi r0,r6,1
1429 andc r3,r3,r0
1430 mr r4,r3
14315: dcbst 0,r4
1432 add r4,r4,r6
1433 cmplw r4,r5
1434 blt 5b
1435 sync /* Wait for all dcbst to complete on bus */
1436 mr r4,r3
14376: icbi 0,r4
1438 add r4,r4,r6
1439 cmplw r4,r5
1440 blt 6b
14417: sync /* Wait for all icbi to complete on bus */
1442 isync
1443
1444/*
1445 * We are done. Do not return, instead branch to second part of board
1446 * initialization, now running from RAM.
1447 */
1448
efa35cf1 1449 addi r0, r10, in_ram - _start + _START_OFFSET
0442ed86
WD		 1450 mtlr r0
1451 blr /* NEVER RETURNS! */
1452
1453in_ram:
1454
1455 /*
1456 * Relocation Function, r14 point to got2+0x8000
1457 *
1458 * Adjust got2 pointers, no need to check for 0, this code
1459 * already puts a few entries in the table.
1460 */
1461 li r0,__got2_entries@sectoff@l
1462 la r3,GOT(_GOT2_TABLE_)
1463 lwz r11,GOT(_GOT2_TABLE_)
1464 mtctr r0
1465 sub r11,r3,r11
1466 addi r3,r3,-4
14671: lwzu r0,4(r3)
1468 add r0,r0,r11
1469 stw r0,0(r3)
1470 bdnz 1b
1471
1472 /*
1473 * Now adjust the fixups and the pointers to the fixups
1474 * in case we need to move ourselves again.
1475 */
14762: li r0,__fixup_entries@sectoff@l
1477 lwz r3,GOT(_FIXUP_TABLE_)
1478 cmpwi r0,0
1479 mtctr r0
1480 addi r3,r3,-4
1481 beq 4f
14823: lwzu r4,4(r3)
1483 lwzux r0,r4,r11
1484 add r0,r0,r11
1485 stw r10,0(r3)
1486 stw r0,0(r4)
1487 bdnz 3b
14884:
1489clear_bss:
1490 /*
1491 * Now clear BSS segment
1492 */
5d232d0e 1493 lwz r3,GOT(__bss_start)
0442ed86
WD		 1494 lwz r4,GOT(_end)
1495
1496 cmplw 0, r3, r4
1497 beq 6f
1498
1499 li r0, 0
15005:
1501 stw r0, 0(r3)
1502 addi r3, r3, 4
1503 cmplw 0, r3, r4
1504 bne 5b
15056:
1506
1507 mr r3, r9 /* Init Data pointer */
1508 mr r4, r10 /* Destination Address */
1509 bl board_init_r
1510
0442ed86
WD		 1511 /*
1512 * Copy exception vector code to low memory
1513 *
1514 * r3: dest_addr
1515 * r7: source address, r8: end address, r9: target address
1516 */
1517 .globl trap_init
1518trap_init:
efa35cf1 1519 lwz r7, GOT(_start_of_vectors)
0442ed86
WD		 1520 lwz r8, GOT(_end_of_vectors)
1521
682011ff 1522 li r9, 0x100 /* reset vector always at 0x100 */
0442ed86
WD		 1523
1524 cmplw 0, r7, r8
1525 bgelr /* return if r7>=r8 - just in case */
1526
1527 mflr r4 /* save link register */
15281:
1529 lwz r0, 0(r7)
1530 stw r0, 0(r9)
1531 addi r7, r7, 4
1532 addi r9, r9, 4
1533 cmplw 0, r7, r8
1534 bne 1b
1535
1536 /*
1537 * relocate `hdlr' and `int_return' entries
1538 */
efa35cf1
GB		 1539 li r7, .L_MachineCheck - _start + _START_OFFSET
1540 li r8, Alignment - _start + _START_OFFSET
0442ed86
WD		 15412:
1542 bl trap_reloc
efa35cf1 1543 addi r7, r7, 0x100 /* next exception vector */
0442ed86
WD		 1544 cmplw 0, r7, r8
1545 blt 2b
1546
efa35cf1 1547 li r7, .L_Alignment - _start + _START_OFFSET
0442ed86
WD		 1548 bl trap_reloc
1549
efa35cf1 1550 li r7, .L_ProgramCheck - _start + _START_OFFSET
0442ed86
WD		 1551 bl trap_reloc
1552
efa35cf1
GB		 1553#ifdef CONFIG_440
1554 li r7, .L_FPUnavailable - _start + _START_OFFSET
83b4cfa3 1555 bl trap_reloc
0442ed86 1556
efa35cf1 1557 li r7, .L_Decrementer - _start + _START_OFFSET
83b4cfa3 1558 bl trap_reloc
efa35cf1
GB		 1559
1560 li r7, .L_APU - _start + _START_OFFSET
83b4cfa3 1561 bl trap_reloc
df8a24cd 1562
83b4cfa3
WD		 1563 li r7, .L_InstructionTLBError - _start + _START_OFFSET
1564 bl trap_reloc
efa35cf1 1565
83b4cfa3
WD		 1566 li r7, .L_DataTLBError - _start + _START_OFFSET
1567 bl trap_reloc
efa35cf1
GB		 1568#else /* CONFIG_440 */
1569 li r7, .L_PIT - _start + _START_OFFSET
83b4cfa3 1570 bl trap_reloc
efa35cf1
GB		 1571
1572 li r7, .L_InstructionTLBMiss - _start + _START_OFFSET
83b4cfa3 1573 bl trap_reloc
efa35cf1
GB		 1574
1575 li r7, .L_DataTLBMiss - _start + _START_OFFSET
83b4cfa3 1576 bl trap_reloc
efa35cf1
GB		 1577#endif /* CONFIG_440 */
1578
83b4cfa3
WD		 1579 li r7, .L_DebugBreakpoint - _start + _START_OFFSET
1580 bl trap_reloc
0442ed86 1581
887e2ec9 1582#if !defined(CONFIG_440)
9a7b408c
SR		 1583 addi r7,r0,0x1000 /* set ME bit (Machine Exceptions) */
1584 oris r7,r7,0x0002 /* set CE bit (Critical Exceptions) */
1585 mtmsr r7 /* change MSR */
1586#else
887e2ec9
SR		 1587 bl __440_msr_set
1588 b __440_msr_continue
9a7b408c 1589
887e2ec9 1590__440_msr_set:
9a7b408c
SR		 1591 addi r7,r0,0x1000 /* set ME bit (Machine Exceptions) */
1592 oris r7,r7,0x0002 /* set CE bit (Critical Exceptions) */
1593 mtspr srr1,r7
1594 mflr r7
1595 mtspr srr0,r7
1596 rfi
887e2ec9 1597__440_msr_continue:
9a7b408c
SR		 1598#endif
1599
0442ed86
WD		 1600 mtlr r4 /* restore link register */
1601 blr
1602
1603 /*
1604 * Function: relocate entries for one exception vector
1605 */
1606trap_reloc:
1607 lwz r0, 0(r7) /* hdlr ... */
1608 add r0, r0, r3 /* ... += dest_addr */
1609 stw r0, 0(r7)
1610
1611 lwz r0, 4(r7) /* int_return ... */
1612 add r0, r0, r3 /* ... += dest_addr */
1613 stw r0, 4(r7)
1614
1615 blr
cf959c7d
SR		 1616
1617#if defined(CONFIG_440)
1618/*----------------------------------------------------------------------------+
1619| dcbz_area.
1620+----------------------------------------------------------------------------*/
1621 function_prolog(dcbz_area)
1622 rlwinm. r5,r4,0,27,31
83b4cfa3
WD		 1623 rlwinm r5,r4,27,5,31
1624 beq ..d_ra2
1625 addi r5,r5,0x0001
1626..d_ra2:mtctr r5
1627..d_ag2:dcbz r0,r3
1628 addi r3,r3,32
1629 bdnz ..d_ag2
cf959c7d
SR		 1630 sync
1631 blr
1632 function_epilog(dcbz_area)
1633
1634/*----------------------------------------------------------------------------+
1635| dflush. Assume 32K at vector address is cachable.
1636+----------------------------------------------------------------------------*/
1637 function_prolog(dflush)
83b4cfa3
WD		 1638 mfmsr r9
1639 rlwinm r8,r9,0,15,13
1640 rlwinm r8,r8,0,17,15
1641 mtmsr r8
1642 addi r3,r0,0x0000
1643 mtspr dvlim,r3
1644 mfspr r3,ivpr
1645 addi r4,r0,1024
1646 mtctr r4
cf959c7d 1647..dflush_loop:
83b4cfa3
WD		 1648 lwz r6,0x0(r3)
1649 addi r3,r3,32
1650 bdnz ..dflush_loop
1651 addi r3,r3,-32
1652 mtctr r4
1653..ag: dcbf r0,r3
1654 addi r3,r3,-32
1655 bdnz ..ag
cf959c7d 1656 sync
83b4cfa3 1657 mtmsr r9
cf959c7d
SR		 1658 blr
1659 function_epilog(dflush)
1660#endif /* CONFIG_440 */
887e2ec9 1661#endif /* CONFIG_NAND_SPL */
b867d705 1662
cf959c7d
SR		 1663/*------------------------------------------------------------------------------- */
1664/* Function: in8 */
1665/* Description: Input 8 bits */
1666/*------------------------------------------------------------------------------- */
1667 .globl in8
1668in8:
1669 lbz r3,0x0000(r3)
1670 blr
1671
1672/*------------------------------------------------------------------------------- */
1673/* Function: out8 */
1674/* Description: Output 8 bits */
1675/*------------------------------------------------------------------------------- */
1676 .globl out8
1677out8:
1678 stb r4,0x0000(r3)
1679 blr
1680
1681/*------------------------------------------------------------------------------- */
1682/* Function: out32 */
1683/* Description: Output 32 bits */
1684/*------------------------------------------------------------------------------- */
1685 .globl out32
1686out32:
1687 stw r4,0x0000(r3)
1688 blr
1689
1690/*------------------------------------------------------------------------------- */
1691/* Function: in32 */
1692/* Description: Input 32 bits */
1693/*------------------------------------------------------------------------------- */
1694 .globl in32
1695in32:
1696 lwz 3,0x0000(3)
1697 blr
b867d705
SR		 1698
1699/**************************************************************************/
f901a83b 1700/* PPC405EP specific stuff */
b867d705
SR		 1701/**************************************************************************/
1702#ifdef CONFIG_405EP
1703ppc405ep_init:
b828dda6 1704
c157d8e2 1705#ifdef CONFIG_BUBINGA
b828dda6
SR		 1706 /*
1707 * Initialize EBC chip selects 1 & 4 and GPIO pins (for alternate
1708 * function) to support FPGA and NVRAM accesses below.
1709 */
1710
1711 lis r3,GPIO0_OSRH@h /* config GPIO output select */
1712 ori r3,r3,GPIO0_OSRH@l
1713 lis r4,CFG_GPIO0_OSRH@h
1714 ori r4,r4,CFG_GPIO0_OSRH@l
1715 stw r4,0(r3)
1716 lis r3,GPIO0_OSRL@h
1717 ori r3,r3,GPIO0_OSRL@l
1718 lis r4,CFG_GPIO0_OSRL@h
1719 ori r4,r4,CFG_GPIO0_OSRL@l
1720 stw r4,0(r3)
1721
1722 lis r3,GPIO0_ISR1H@h /* config GPIO input select */
1723 ori r3,r3,GPIO0_ISR1H@l
1724 lis r4,CFG_GPIO0_ISR1H@h
1725 ori r4,r4,CFG_GPIO0_ISR1H@l
1726 stw r4,0(r3)
1727 lis r3,GPIO0_ISR1L@h
1728 ori r3,r3,GPIO0_ISR1L@l
1729 lis r4,CFG_GPIO0_ISR1L@h
1730 ori r4,r4,CFG_GPIO0_ISR1L@l
1731 stw r4,0(r3)
1732
1733 lis r3,GPIO0_TSRH@h /* config GPIO three-state select */
1734 ori r3,r3,GPIO0_TSRH@l
1735 lis r4,CFG_GPIO0_TSRH@h
1736 ori r4,r4,CFG_GPIO0_TSRH@l
1737 stw r4,0(r3)
1738 lis r3,GPIO0_TSRL@h
1739 ori r3,r3,GPIO0_TSRL@l
1740 lis r4,CFG_GPIO0_TSRL@h
1741 ori r4,r4,CFG_GPIO0_TSRL@l
1742 stw r4,0(r3)
1743
1744 lis r3,GPIO0_TCR@h /* config GPIO driver output enables */
1745 ori r3,r3,GPIO0_TCR@l
1746 lis r4,CFG_GPIO0_TCR@h
1747 ori r4,r4,CFG_GPIO0_TCR@l
1748 stw r4,0(r3)
1749
1750 li r3,pb1ap /* program EBC bank 1 for RTC access */
1751 mtdcr ebccfga,r3
1752 lis r3,CFG_EBC_PB1AP@h
1753 ori r3,r3,CFG_EBC_PB1AP@l
1754 mtdcr ebccfgd,r3
1755 li r3,pb1cr
1756 mtdcr ebccfga,r3
1757 lis r3,CFG_EBC_PB1CR@h
1758 ori r3,r3,CFG_EBC_PB1CR@l
1759 mtdcr ebccfgd,r3
1760
1761 li r3,pb1ap /* program EBC bank 1 for RTC access */
1762 mtdcr ebccfga,r3
1763 lis r3,CFG_EBC_PB1AP@h
1764 ori r3,r3,CFG_EBC_PB1AP@l
1765 mtdcr ebccfgd,r3
1766 li r3,pb1cr
1767 mtdcr ebccfga,r3
1768 lis r3,CFG_EBC_PB1CR@h
1769 ori r3,r3,CFG_EBC_PB1CR@l
1770 mtdcr ebccfgd,r3
1771
1772 li r3,pb4ap /* program EBC bank 4 for FPGA access */
1773 mtdcr ebccfga,r3
1774 lis r3,CFG_EBC_PB4AP@h
1775 ori r3,r3,CFG_EBC_PB4AP@l
1776 mtdcr ebccfgd,r3
1777 li r3,pb4cr
1778 mtdcr ebccfga,r3
1779 lis r3,CFG_EBC_PB4CR@h
1780 ori r3,r3,CFG_EBC_PB4CR@l
1781 mtdcr ebccfgd,r3
1782#endif
8bde7f77
WD		 1783
1784 /*
1785 !-----------------------------------------------------------------------
1786 ! Check to see if chip is in bypass mode.
1787 ! If so, write stored CPC0_PLLMR0 and CPC0_PLLMR1 values and perform a
1788 ! CPU reset Otherwise, skip this step and keep going.
f901a83b
WD		 1789 ! Note: Running BIOS in bypass mode is not supported since PLB speed
1790 ! will not be fast enough for the SDRAM (min 66MHz)
8bde7f77 1791 !-----------------------------------------------------------------------
b867d705 1792 */
f901a83b
WD		 1793 mfdcr r5, CPC0_PLLMR1
1794 rlwinm r4,r5,1,0x1 /* get system clock source (SSCS) */
1795 cmpi cr0,0,r4,0x1
b867d705 1796
f901a83b 1797 beq pll_done /* if SSCS =b'1' then PLL has */
8bde7f77
WD		 1798 /* already been set */
1799 /* and CPU has been reset */
1800 /* so skip to next section */
b867d705 1801
c157d8e2 1802#ifdef CONFIG_BUBINGA
b867d705 1803 /*
8bde7f77
WD		 1804 !-----------------------------------------------------------------------
1805 ! Read NVRAM to get value to write in PLLMR.
1806 ! If value has not been correctly saved, write default value
1807 ! Default config values (assuming on-board 33MHz SYS_CLK) are above.
1808 ! See CPU_DEFAULT_200 and CPU_DEFAULT_266 above.
1809 !
1810 ! WARNING: This code assumes the first three words in the nvram_t
f901a83b
WD		 1811 ! structure in openbios.h. Changing the beginning of
1812 ! the structure will break this code.
8bde7f77
WD		 1813 !
1814 !-----------------------------------------------------------------------
b867d705 1815 */
f901a83b
WD		 1816 addis r3,0,NVRAM_BASE@h
1817 addi r3,r3,NVRAM_BASE@l
1818
1819 lwz r4, 0(r3)
1820 addis r5,0,NVRVFY1@h
1821 addi r5,r5,NVRVFY1@l
1822 cmp cr0,0,r4,r5 /* Compare 1st NVRAM Magic number*/
1823 bne ..no_pllset
1824 addi r3,r3,4
1825 lwz r4, 0(r3)
1826 addis r5,0,NVRVFY2@h
1827 addi r5,r5,NVRVFY2@l
1828 cmp cr0,0,r4,r5 /* Compare 2 NVRAM Magic number */
1829 bne ..no_pllset
1830 addi r3,r3,8 /* Skip over conf_size */
1831 lwz r4, 4(r3) /* Load PLLMR1 value from NVRAM */
1832 lwz r3, 0(r3) /* Load PLLMR0 value from NVRAM */
1833 rlwinm r5,r4,1,0x1 /* get system clock source (SSCS) */
1834 cmpi cr0,0,r5,1 /* See if PLL is locked */
1835 beq pll_write
b867d705 1836..no_pllset:
c157d8e2 1837#endif /* CONFIG_BUBINGA */
b867d705 1838
d4024bb7
JO		 1839#ifdef CONFIG_TAIHU
1840 mfdcr r4, CPC0_BOOT
1841 andi. r5, r4, CPC0_BOOT_SEP@l
1842 bne strap_1 /* serial eeprom present */
1843 addis r5,0,CPLD_REG0_ADDR@h
1844 ori r5,r5,CPLD_REG0_ADDR@l
1845 andi. r5, r5, 0x10
1846 bne _pci_66mhz
1847#endif /* CONFIG_TAIHU */
1848
779e9751
SR		 1849#if defined(CONFIG_ZEUS)
1850 mfdcr r4, CPC0_BOOT
1851 andi. r5, r4, CPC0_BOOT_SEP@l
1852 bne strap_1 /* serial eeprom present */
1853 lis r3,0x0000
1854 addi r3,r3,0x3030
1855 lis r4,0x8042
1856 addi r4,r4,0x223e
1857 b 1f
1858strap_1:
1859 mfdcr r3, CPC0_PLLMR0
1860 mfdcr r4, CPC0_PLLMR1
1861 b 1f
1862#endif
1863
f901a83b
WD		 1864 addis r3,0,PLLMR0_DEFAULT@h /* PLLMR0 default value */
1865 ori r3,r3,PLLMR0_DEFAULT@l /* */
1866 addis r4,0,PLLMR1_DEFAULT@h /* PLLMR1 default value */
1867 ori r4,r4,PLLMR1_DEFAULT@l /* */
b867d705 1868
d4024bb7
JO		 1869#ifdef CONFIG_TAIHU
1870 b 1f
1871_pci_66mhz:
1872 addis r3,0,PLLMR0_DEFAULT_PCI66@h
1873 ori r3,r3,PLLMR0_DEFAULT_PCI66@l
1874 addis r4,0,PLLMR1_DEFAULT_PCI66@h
1875 ori r4,r4,PLLMR1_DEFAULT_PCI66@l
1876 b 1f
1877strap_1:
1878 mfdcr r3, CPC0_PLLMR0
1879 mfdcr r4, CPC0_PLLMR1
d4024bb7
JO		 1880#endif /* CONFIG_TAIHU */
1881
779e9751 18821:
f901a83b 1883 b pll_write /* Write the CPC0_PLLMR with new value */
b867d705
SR		 1884
1885pll_done:
8bde7f77
WD		 1886 /*
1887 !-----------------------------------------------------------------------
1888 ! Clear Soft Reset Register
1889 ! This is needed to enable PCI if not booting from serial EPROM
1890 !-----------------------------------------------------------------------
b867d705 1891 */
f901a83b
WD		 1892 addi r3, 0, 0x0
1893 mtdcr CPC0_SRR, r3
b867d705 1894
f901a83b
WD		 1895 addis r3,0,0x0010
1896 mtctr r3
b867d705 1897pci_wait:
f901a83b 1898 bdnz pci_wait
b867d705
SR		 1899
1900 blr /* return to main code */
1901
1902/*
1903!-----------------------------------------------------------------------------
f901a83b
WD		 1904! Function: pll_write
1905! Description: Updates the value of the CPC0_PLLMR according to CMOS27E documentation
1906! That is:
1907! 1. Pll is first disabled (de-activated by putting in bypass mode)
1908! 2. PLL is reset
1909! 3. Clock dividers are set while PLL is held in reset and bypassed
1910! 4. PLL Reset is cleared
1911! 5. Wait 100us for PLL to lock
1912! 6. A core reset is performed
b867d705
SR		 1913! Input: r3 = Value to write to CPC0_PLLMR0
1914! Input: r4 = Value to write to CPC0_PLLMR1
1915! Output r3 = none
1916!-----------------------------------------------------------------------------
1917*/
1918pll_write:
8bde7f77
WD		 1919 mfdcr r5, CPC0_UCR
1920 andis. r5,r5,0xFFFF
f901a83b
WD		 1921 ori r5,r5,0x0101 /* Stop the UART clocks */
1922 mtdcr CPC0_UCR,r5 /* Before changing PLL */
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WD		 1923
1924 mfdcr r5, CPC0_PLLMR1
f901a83b
WD		 1925 rlwinm r5,r5,0,0x7FFFFFFF /* Disable PLL */
1926 mtdcr CPC0_PLLMR1,r5
1927 oris r5,r5,0x4000 /* Set PLL Reset */
1928 mtdcr CPC0_PLLMR1,r5
1929
1930 mtdcr CPC0_PLLMR0,r3 /* Set clock dividers */
1931 rlwinm r5,r4,0,0x3FFFFFFF /* Reset & Bypass new PLL dividers */
1932 oris r5,r5,0x4000 /* Set PLL Reset */
1933 mtdcr CPC0_PLLMR1,r5 /* Set clock dividers */
1934 rlwinm r5,r5,0,0xBFFFFFFF /* Clear PLL Reset */
1935 mtdcr CPC0_PLLMR1,r5
b867d705
SR		 1936
1937 /*
8bde7f77
WD		 1938 ! Wait min of 100us for PLL to lock.
1939 ! See CMOS 27E databook for more info.
1940 ! At 200MHz, that means waiting 20,000 instructions
b867d705 1941 */
f901a83b
WD		 1942 addi r3,0,20000 /* 2000 = 0x4e20 */
1943 mtctr r3
b867d705 1944pll_wait:
f901a83b 1945 bdnz pll_wait
8bde7f77 1946
f901a83b
WD		 1947 oris r5,r5,0x8000 /* Enable PLL */
1948 mtdcr CPC0_PLLMR1,r5 /* Engage */
8bde7f77
WD		 1949
1950 /*
1951 * Reset CPU to guarantee timings are OK
1952 * Not sure if this is needed...
1953 */
1954 addis r3,0,0x1000
f901a83b 1955 mtspr dbcr0,r3 /* This will cause a CPU core reset, and */
8bde7f77
WD		 1956 /* execution will continue from the poweron */
1957 /* vector of 0xfffffffc */
b867d705 1958#endif /* CONFIG_405EP */
4745acaa
SR		 1959
1960#if defined(CONFIG_440)
4745acaa
SR		 1961/*----------------------------------------------------------------------------+
1962| mttlb3.
1963+----------------------------------------------------------------------------*/
1964 function_prolog(mttlb3)
1965 TLBWE(4,3,2)
1966 blr
1967 function_epilog(mttlb3)
1968
1969/*----------------------------------------------------------------------------+
1970| mftlb3.
1971+----------------------------------------------------------------------------*/
1972 function_prolog(mftlb3)
74357114 1973 TLBRE(3,3,2)
4745acaa
SR		 1974 blr
1975 function_epilog(mftlb3)
1976
1977/*----------------------------------------------------------------------------+
1978| mttlb2.
1979+----------------------------------------------------------------------------*/
1980 function_prolog(mttlb2)
1981 TLBWE(4,3,1)
1982 blr
1983 function_epilog(mttlb2)
1984
1985/*----------------------------------------------------------------------------+
1986| mftlb2.
1987+----------------------------------------------------------------------------*/
1988 function_prolog(mftlb2)
74357114 1989 TLBRE(3,3,1)
4745acaa
SR		 1990 blr
1991 function_epilog(mftlb2)
1992
1993/*----------------------------------------------------------------------------+
1994| mttlb1.
1995+----------------------------------------------------------------------------*/
1996 function_prolog(mttlb1)
1997 TLBWE(4,3,0)
1998 blr
1999 function_epilog(mttlb1)
2000
2001/*----------------------------------------------------------------------------+
2002| mftlb1.
2003+----------------------------------------------------------------------------*/
2004 function_prolog(mftlb1)
74357114 2005 TLBRE(3,3,0)
4745acaa
SR		 2006 blr
2007 function_epilog(mftlb1)
2008#endif /* CONFIG_440 */
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