[people/ms/u-boot.git] / cpu / ppc4xx / tlb.c

/*
 * (C) Copyright 2007
 * Stefan Roese, DENX Software Engineering, sr@denx.de.
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#include <common.h>

#if defined(CONFIG_440)

#include <ppc4xx.h>
#include <ppc440.h>
#include <asm/io.h>
#include <asm/mmu.h>

typedef struct region {
	unsigned long base;
	unsigned long size;
	unsigned long tlb_word2_i_value;
} region_t;

static int add_tlb_entry(unsigned long phys_addr,
			 unsigned long virt_addr,
			 unsigned long tlb_word0_size_value,
			 unsigned long tlb_word2_i_value)
{
	int i;
	unsigned long tlb_word0_value;
	unsigned long tlb_word1_value;
	unsigned long tlb_word2_value;

	/* First, find the index of a TLB entry not being used */
	for (i=0; i<PPC4XX_TLB_SIZE; i++) {
		tlb_word0_value = mftlb1(i);
		if ((tlb_word0_value & TLB_WORD0_V_MASK) == TLB_WORD0_V_DISABLE)
			break;
	}
	if (i >= PPC4XX_TLB_SIZE)
		return -1;

	/* Second, create the TLB entry */
	tlb_word0_value = TLB_WORD0_EPN_ENCODE(virt_addr) | TLB_WORD0_V_ENABLE |
		TLB_WORD0_TS_0 | tlb_word0_size_value;
	tlb_word1_value = TLB_WORD1_RPN_ENCODE(phys_addr) | TLB_WORD1_ERPN_ENCODE(0);
	tlb_word2_value = TLB_WORD2_U0_DISABLE | TLB_WORD2_U1_DISABLE |
		TLB_WORD2_U2_DISABLE | TLB_WORD2_U3_DISABLE |
		TLB_WORD2_W_DISABLE | tlb_word2_i_value |
		TLB_WORD2_M_DISABLE | TLB_WORD2_G_DISABLE |
		TLB_WORD2_E_DISABLE | TLB_WORD2_UX_ENABLE |
		TLB_WORD2_UW_ENABLE | TLB_WORD2_UR_ENABLE |
		TLB_WORD2_SX_ENABLE | TLB_WORD2_SW_ENABLE |
		TLB_WORD2_SR_ENABLE;

	/* Wait for all memory accesses to complete */
	sync();

	/* Third, add the TLB entries */
	mttlb1(i, tlb_word0_value);
	mttlb2(i, tlb_word1_value);
	mttlb3(i, tlb_word2_value);

	/* Execute an ISYNC instruction so that the new TLB entry takes effect */
	asm("isync");

	return 0;
}

static void program_tlb_addr(unsigned long phys_addr,
			     unsigned long virt_addr,
			     unsigned long mem_size,
			     unsigned long tlb_word2_i_value)
{
	int rc;
	int tlb_i;

	tlb_i = tlb_word2_i_value;
	while (mem_size != 0) {
		rc = 0;
		/* Add the TLB entries in to map the region. */
		if (((phys_addr & TLB_256MB_ALIGN_MASK) == phys_addr) &&
		    (mem_size >= TLB_256MB_SIZE)) {
			/* Add a 256MB TLB entry */
			if ((rc = add_tlb_entry(phys_addr, virt_addr,
						TLB_WORD0_SIZE_256MB, tlb_i)) == 0) {
				mem_size -= TLB_256MB_SIZE;
				phys_addr += TLB_256MB_SIZE;
				virt_addr += TLB_256MB_SIZE;
			}
		} else if (((phys_addr & TLB_16MB_ALIGN_MASK) == phys_addr) &&
			   (mem_size >= TLB_16MB_SIZE)) {
			/* Add a 16MB TLB entry */
			if ((rc = add_tlb_entry(phys_addr, virt_addr,
						TLB_WORD0_SIZE_16MB, tlb_i)) == 0) {
				mem_size -= TLB_16MB_SIZE;
				phys_addr += TLB_16MB_SIZE;
				virt_addr += TLB_16MB_SIZE;
			}
		} else if (((phys_addr & TLB_1MB_ALIGN_MASK) == phys_addr) &&
			   (mem_size >= TLB_1MB_SIZE)) {
			/* Add a 1MB TLB entry */
			if ((rc = add_tlb_entry(phys_addr, virt_addr,
						TLB_WORD0_SIZE_1MB, tlb_i)) == 0) {
				mem_size -= TLB_1MB_SIZE;
				phys_addr += TLB_1MB_SIZE;
				virt_addr += TLB_1MB_SIZE;
			}
		} else if (((phys_addr & TLB_256KB_ALIGN_MASK) == phys_addr) &&
			   (mem_size >= TLB_256KB_SIZE)) {
			/* Add a 256KB TLB entry */
			if ((rc = add_tlb_entry(phys_addr, virt_addr,
						TLB_WORD0_SIZE_256KB, tlb_i)) == 0) {
				mem_size -= TLB_256KB_SIZE;
				phys_addr += TLB_256KB_SIZE;
				virt_addr += TLB_256KB_SIZE;
			}
		} else if (((phys_addr & TLB_64KB_ALIGN_MASK) == phys_addr) &&
			   (mem_size >= TLB_64KB_SIZE)) {
			/* Add a 64KB TLB entry */
			if ((rc = add_tlb_entry(phys_addr, virt_addr,
						TLB_WORD0_SIZE_64KB, tlb_i)) == 0) {
				mem_size -= TLB_64KB_SIZE;
				phys_addr += TLB_64KB_SIZE;
				virt_addr += TLB_64KB_SIZE;
			}
		} else if (((phys_addr & TLB_16KB_ALIGN_MASK) == phys_addr) &&
			   (mem_size >= TLB_16KB_SIZE)) {
			/* Add a 16KB TLB entry */
			if ((rc = add_tlb_entry(phys_addr, virt_addr,
						TLB_WORD0_SIZE_16KB, tlb_i)) == 0) {
				mem_size -= TLB_16KB_SIZE;
				phys_addr += TLB_16KB_SIZE;
				virt_addr += TLB_16KB_SIZE;
			}
		} else if (((phys_addr & TLB_4KB_ALIGN_MASK) == phys_addr) &&
			   (mem_size >= TLB_4KB_SIZE)) {
			/* Add a 4KB TLB entry */
			if ((rc = add_tlb_entry(phys_addr, virt_addr,
						TLB_WORD0_SIZE_4KB, tlb_i)) == 0) {
				mem_size -= TLB_4KB_SIZE;
				phys_addr += TLB_4KB_SIZE;
				virt_addr += TLB_4KB_SIZE;
			}
		} else if (((phys_addr & TLB_1KB_ALIGN_MASK) == phys_addr) &&
			   (mem_size >= TLB_1KB_SIZE)) {
			/* Add a 1KB TLB entry */
			if ((rc = add_tlb_entry(phys_addr, virt_addr,
						TLB_WORD0_SIZE_1KB, tlb_i)) == 0) {
				mem_size -= TLB_1KB_SIZE;
				phys_addr += TLB_1KB_SIZE;
				virt_addr += TLB_1KB_SIZE;
			}
		} else {
			printf("ERROR: no TLB size exists for the base address 0x%0X.\n",
				phys_addr);
		}

		if (rc != 0)
			printf("ERROR: no TLB entries available for the base addr 0x%0X.\n",
				phys_addr);
	}

	return;
}

/*
 * Program one (or multiple) TLB entries for one memory region
 *
 * Common usage for boards with SDRAM DIMM modules to dynamically
 * configure the TLB's for the SDRAM
 */
void program_tlb(u32 phys_addr, u32 virt_addr, u32 size, u32 tlb_word2_i_value)
{
	region_t region_array;

	region_array.base = phys_addr;
	region_array.size = size;
	region_array.tlb_word2_i_value = tlb_word2_i_value;	/* en-/disable cache */

	/* Call the routine to add in the tlb entries for the memory regions */
	program_tlb_addr(region_array.base, virt_addr, region_array.size,
			 region_array.tlb_word2_i_value);

	return;
}

#endif /* CONFIG_440 */
Commit	Line	Data
4037ed3b SR	1	/*
	2	* (C) Copyright 2007
	3	* Stefan Roese, DENX Software Engineering, sr@denx.de.
	4	*
	5	* See file CREDITS for list of people who contributed to this
	6	* project.
	7	*
	8	* This program is free software; you can redistribute it and/or
	9	* modify it under the terms of the GNU General Public License as
	10	* published by the Free Software Foundation; either version 2 of
	11	* the License, or (at your option) any later version.
	12	*
	13	* This program is distributed in the hope that it will be useful,
	14	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	* GNU General Public License for more details.
	17	*
	18	* You should have received a copy of the GNU General Public License
	19	* along with this program; if not, write to the Free Software
	20	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	21	* MA 02111-1307 USA
	22	*/
	23
	24	#include <common.h>
	25
	26	#if defined(CONFIG_440)
	27
	28	#include <ppc4xx.h>
	29	#include <ppc440.h>
	30	#include <asm/io.h>
	31	#include <asm/mmu.h>
	32
	33	typedef struct region {
	34	unsigned long base;
	35	unsigned long size;
	36	unsigned long tlb_word2_i_value;
	37	} region_t;
	38
dbca2085 SR	39	static int add_tlb_entry(unsigned long phys_addr,
dbca2085 SR	40	unsigned long virt_addr,
74357114 WD	41	unsigned long tlb_word0_size_value,
74357114 WD	42	unsigned long tlb_word2_i_value)
4037ed3b SR	43	{
	44	int i;
	45	unsigned long tlb_word0_value;
	46	unsigned long tlb_word1_value;
	47	unsigned long tlb_word2_value;
	48
	49	/* First, find the index of a TLB entry not being used */
	50	for (i=0; i<PPC4XX_TLB_SIZE; i++) {
	51	tlb_word0_value = mftlb1(i);
	52	if ((tlb_word0_value & TLB_WORD0_V_MASK) == TLB_WORD0_V_DISABLE)
	53	break;
	54	}
	55	if (i >= PPC4XX_TLB_SIZE)
	56	return -1;
	57
	58	/* Second, create the TLB entry */
dbca2085	59	tlb_word0_value = TLB_WORD0_EPN_ENCODE(virt_addr) \| TLB_WORD0_V_ENABLE \|
4037ed3b	60	TLB_WORD0_TS_0 \| tlb_word0_size_value;
dbca2085	61	tlb_word1_value = TLB_WORD1_RPN_ENCODE(phys_addr) \| TLB_WORD1_ERPN_ENCODE(0);
4037ed3b SR	62	tlb_word2_value = TLB_WORD2_U0_DISABLE \| TLB_WORD2_U1_DISABLE \|
	63	TLB_WORD2_U2_DISABLE \| TLB_WORD2_U3_DISABLE \|
	64	TLB_WORD2_W_DISABLE \| tlb_word2_i_value \|
	65	TLB_WORD2_M_DISABLE \| TLB_WORD2_G_DISABLE \|
	66	TLB_WORD2_E_DISABLE \| TLB_WORD2_UX_ENABLE \|
	67	TLB_WORD2_UW_ENABLE \| TLB_WORD2_UR_ENABLE \|
	68	TLB_WORD2_SX_ENABLE \| TLB_WORD2_SW_ENABLE \|
	69	TLB_WORD2_SR_ENABLE;
	70
	71	/* Wait for all memory accesses to complete */
	72	sync();
	73
	74	/* Third, add the TLB entries */
	75	mttlb1(i, tlb_word0_value);
	76	mttlb2(i, tlb_word1_value);
	77	mttlb3(i, tlb_word2_value);
	78
	79	/* Execute an ISYNC instruction so that the new TLB entry takes effect */
	80	asm("isync");
	81
	82	return 0;
	83	}
	84
dbca2085 SR	85	static void program_tlb_addr(unsigned long phys_addr,
	86	unsigned long virt_addr,
	87	unsigned long mem_size,
74357114	88	unsigned long tlb_word2_i_value)
4037ed3b SR	89	{
	90	int rc;
	91	int tlb_i;
	92
	93	tlb_i = tlb_word2_i_value;
	94	while (mem_size != 0) {
	95	rc = 0;
	96	/* Add the TLB entries in to map the region. */
dbca2085	97	if (((phys_addr & TLB_256MB_ALIGN_MASK) == phys_addr) &&
4037ed3b SR	98	(mem_size >= TLB_256MB_SIZE)) {
4037ed3b SR	99	/* Add a 256MB TLB entry */
dbca2085 SR	100	if ((rc = add_tlb_entry(phys_addr, virt_addr,
dbca2085 SR	101	TLB_WORD0_SIZE_256MB, tlb_i)) == 0) {
4037ed3b	102	mem_size -= TLB_256MB_SIZE;
dbca2085	103	phys_addr += TLB_256MB_SIZE;
3a1f5c81	104	virt_addr += TLB_256MB_SIZE;
4037ed3b	105	}
dbca2085	106	} else if (((phys_addr & TLB_16MB_ALIGN_MASK) == phys_addr) &&
4037ed3b SR	107	(mem_size >= TLB_16MB_SIZE)) {
4037ed3b SR	108	/* Add a 16MB TLB entry */
dbca2085 SR	109	if ((rc = add_tlb_entry(phys_addr, virt_addr,
dbca2085 SR	110	TLB_WORD0_SIZE_16MB, tlb_i)) == 0) {
4037ed3b	111	mem_size -= TLB_16MB_SIZE;
dbca2085	112	phys_addr += TLB_16MB_SIZE;
3a1f5c81	113	virt_addr += TLB_16MB_SIZE;
4037ed3b	114	}
dbca2085	115	} else if (((phys_addr & TLB_1MB_ALIGN_MASK) == phys_addr) &&
4037ed3b SR	116	(mem_size >= TLB_1MB_SIZE)) {
4037ed3b SR	117	/* Add a 1MB TLB entry */
dbca2085 SR	118	if ((rc = add_tlb_entry(phys_addr, virt_addr,
dbca2085 SR	119	TLB_WORD0_SIZE_1MB, tlb_i)) == 0) {
4037ed3b	120	mem_size -= TLB_1MB_SIZE;
dbca2085	121	phys_addr += TLB_1MB_SIZE;
3a1f5c81	122	virt_addr += TLB_1MB_SIZE;
4037ed3b	123	}
dbca2085	124	} else if (((phys_addr & TLB_256KB_ALIGN_MASK) == phys_addr) &&
4037ed3b SR	125	(mem_size >= TLB_256KB_SIZE)) {
4037ed3b SR	126	/* Add a 256KB TLB entry */
dbca2085 SR	127	if ((rc = add_tlb_entry(phys_addr, virt_addr,
dbca2085 SR	128	TLB_WORD0_SIZE_256KB, tlb_i)) == 0) {
4037ed3b	129	mem_size -= TLB_256KB_SIZE;
dbca2085	130	phys_addr += TLB_256KB_SIZE;
3a1f5c81	131	virt_addr += TLB_256KB_SIZE;
4037ed3b	132	}
dbca2085	133	} else if (((phys_addr & TLB_64KB_ALIGN_MASK) == phys_addr) &&
4037ed3b SR	134	(mem_size >= TLB_64KB_SIZE)) {
4037ed3b SR	135	/* Add a 64KB TLB entry */
dbca2085 SR	136	if ((rc = add_tlb_entry(phys_addr, virt_addr,
dbca2085 SR	137	TLB_WORD0_SIZE_64KB, tlb_i)) == 0) {
4037ed3b	138	mem_size -= TLB_64KB_SIZE;
dbca2085	139	phys_addr += TLB_64KB_SIZE;
3a1f5c81	140	virt_addr += TLB_64KB_SIZE;
4037ed3b	141	}
dbca2085	142	} else if (((phys_addr & TLB_16KB_ALIGN_MASK) == phys_addr) &&
4037ed3b SR	143	(mem_size >= TLB_16KB_SIZE)) {
4037ed3b SR	144	/* Add a 16KB TLB entry */
dbca2085 SR	145	if ((rc = add_tlb_entry(phys_addr, virt_addr,
dbca2085 SR	146	TLB_WORD0_SIZE_16KB, tlb_i)) == 0) {
4037ed3b	147	mem_size -= TLB_16KB_SIZE;
dbca2085	148	phys_addr += TLB_16KB_SIZE;
3a1f5c81	149	virt_addr += TLB_16KB_SIZE;
4037ed3b	150	}
dbca2085	151	} else if (((phys_addr & TLB_4KB_ALIGN_MASK) == phys_addr) &&
4037ed3b SR	152	(mem_size >= TLB_4KB_SIZE)) {
4037ed3b SR	153	/* Add a 4KB TLB entry */
dbca2085 SR	154	if ((rc = add_tlb_entry(phys_addr, virt_addr,
dbca2085 SR	155	TLB_WORD0_SIZE_4KB, tlb_i)) == 0) {
4037ed3b	156	mem_size -= TLB_4KB_SIZE;
dbca2085	157	phys_addr += TLB_4KB_SIZE;
3a1f5c81	158	virt_addr += TLB_4KB_SIZE;
4037ed3b	159	}
dbca2085	160	} else if (((phys_addr & TLB_1KB_ALIGN_MASK) == phys_addr) &&
4037ed3b SR	161	(mem_size >= TLB_1KB_SIZE)) {
4037ed3b SR	162	/* Add a 1KB TLB entry */
dbca2085 SR	163	if ((rc = add_tlb_entry(phys_addr, virt_addr,
dbca2085 SR	164	TLB_WORD0_SIZE_1KB, tlb_i)) == 0) {
4037ed3b	165	mem_size -= TLB_1KB_SIZE;
dbca2085	166	phys_addr += TLB_1KB_SIZE;
3a1f5c81	167	virt_addr += TLB_1KB_SIZE;
4037ed3b SR	168	}
	169	} else {
	170	printf("ERROR: no TLB size exists for the base address 0x%0X.\n",
dbca2085	171	phys_addr);
4037ed3b SR	172	}
	173
	174	if (rc != 0)
	175	printf("ERROR: no TLB entries available for the base addr 0x%0X.\n",
dbca2085	176	phys_addr);
4037ed3b SR	177	}
	178
	179	return;
	180	}
	181
	182	/*
	183	* Program one (or multiple) TLB entries for one memory region
	184	*
	185	* Common usage for boards with SDRAM DIMM modules to dynamically
	186	* configure the TLB's for the SDRAM
	187	*/
dbca2085	188	void program_tlb(u32 phys_addr, u32 virt_addr, u32 size, u32 tlb_word2_i_value)
4037ed3b SR	189	{
	190	region_t region_array;
	191
dbca2085	192	region_array.base = phys_addr;
4037ed3b	193	region_array.size = size;
ba58e4c9	194	region_array.tlb_word2_i_value = tlb_word2_i_value; /* en-/disable cache */
4037ed3b SR	195
4037ed3b SR	196	/* Call the routine to add in the tlb entries for the memory regions */
dbca2085	197	program_tlb_addr(region_array.base, virt_addr, region_array.size,
4037ed3b SR	198	region_array.tlb_word2_i_value);
	199
	200	return;
	201	}
	202
	203	#endif /* CONFIG_440 */