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CommitLineData
d9f24bf5
PB
1/*
2 * Target-specific parts of the CPU object
3 *
4 * Copyright (c) 2003 Fabrice Bellard
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19
20#include "qemu/osdep.h"
d9f24bf5
PB
21#include "qapi/error.h"
22
23#include "exec/target_page.h"
24#include "hw/qdev-core.h"
25#include "hw/qdev-properties.h"
26#include "qemu/error-report.h"
dfa47531 27#include "qemu/qemu-print.h"
d9f24bf5
PB
28#include "migration/vmstate.h"
29#ifdef CONFIG_USER_ONLY
30#include "qemu.h"
31#else
8b80bd28 32#include "hw/core/sysemu-cpu-ops.h"
d9f24bf5 33#include "exec/address-spaces.h"
5f8d88bd 34#include "exec/memory.h"
d9f24bf5 35#endif
412ae126 36#include "sysemu/cpus.h"
d9f24bf5 37#include "sysemu/tcg.h"
5b5968c4 38#include "exec/replay-core.h"
377bf6f3 39#include "exec/cpu-common.h"
3b04508c 40#include "exec/exec-all.h"
548c9609 41#include "exec/tb-flush.h"
3b9bd3f4 42#include "exec/translate-all.h"
d9f24bf5 43#include "exec/log.h"
30565f10 44#include "hw/core/accel-cpu.h"
ad1a706f 45#include "trace/trace-root.h"
3b04508c 46#include "qemu/accel.h"
d9f24bf5 47
d9f24bf5
PB
48#ifndef CONFIG_USER_ONLY
49static int cpu_common_post_load(void *opaque, int version_id)
50{
51 CPUState *cpu = opaque;
52
53 /* 0x01 was CPU_INTERRUPT_EXIT. This line can be removed when the
54 version_id is increased. */
55 cpu->interrupt_request &= ~0x01;
56 tlb_flush(cpu);
57
58 /* loadvm has just updated the content of RAM, bypassing the
59 * usual mechanisms that ensure we flush TBs for writes to
60 * memory we've translated code from. So we must flush all TBs,
61 * which will now be stale.
62 */
63 tb_flush(cpu);
64
65 return 0;
66}
67
68static int cpu_common_pre_load(void *opaque)
69{
70 CPUState *cpu = opaque;
71
72 cpu->exception_index = -1;
73
74 return 0;
75}
76
77static bool cpu_common_exception_index_needed(void *opaque)
78{
79 CPUState *cpu = opaque;
80
81 return tcg_enabled() && cpu->exception_index != -1;
82}
83
84static const VMStateDescription vmstate_cpu_common_exception_index = {
85 .name = "cpu_common/exception_index",
86 .version_id = 1,
87 .minimum_version_id = 1,
88 .needed = cpu_common_exception_index_needed,
ee1381ce 89 .fields = (const VMStateField[]) {
d9f24bf5
PB
90 VMSTATE_INT32(exception_index, CPUState),
91 VMSTATE_END_OF_LIST()
92 }
93};
94
95static bool cpu_common_crash_occurred_needed(void *opaque)
96{
97 CPUState *cpu = opaque;
98
99 return cpu->crash_occurred;
100}
101
102static const VMStateDescription vmstate_cpu_common_crash_occurred = {
103 .name = "cpu_common/crash_occurred",
104 .version_id = 1,
105 .minimum_version_id = 1,
106 .needed = cpu_common_crash_occurred_needed,
ee1381ce 107 .fields = (const VMStateField[]) {
d9f24bf5
PB
108 VMSTATE_BOOL(crash_occurred, CPUState),
109 VMSTATE_END_OF_LIST()
110 }
111};
112
113const VMStateDescription vmstate_cpu_common = {
114 .name = "cpu_common",
115 .version_id = 1,
116 .minimum_version_id = 1,
117 .pre_load = cpu_common_pre_load,
118 .post_load = cpu_common_post_load,
ee1381ce 119 .fields = (const VMStateField[]) {
d9f24bf5
PB
120 VMSTATE_UINT32(halted, CPUState),
121 VMSTATE_UINT32(interrupt_request, CPUState),
122 VMSTATE_END_OF_LIST()
123 },
ee1381ce 124 .subsections = (const VMStateDescription * const []) {
d9f24bf5
PB
125 &vmstate_cpu_common_exception_index,
126 &vmstate_cpu_common_crash_occurred,
127 NULL
128 }
129};
130#endif
131
79a99091 132bool cpu_exec_realizefn(CPUState *cpu, Error **errp)
d9f24bf5 133{
6fbdff87
AB
134 /* cache the cpu class for the hotpath */
135 cpu->cc = CPU_GET_CLASS(cpu);
d9f24bf5 136
bd684b2f 137 if (!accel_cpu_common_realize(cpu, errp)) {
79a99091 138 return false;
9ea057dc 139 }
4e4fa6c1 140
4e4fa6c1
RH
141 /* Wait until cpu initialization complete before exposing cpu. */
142 cpu_list_add(cpu);
143
7df5e3d6 144#ifdef CONFIG_USER_ONLY
4336073b
PMD
145 assert(qdev_get_vmsd(DEVICE(cpu)) == NULL ||
146 qdev_get_vmsd(DEVICE(cpu))->unmigratable);
7df5e3d6
CF
147#else
148 if (qdev_get_vmsd(DEVICE(cpu)) == NULL) {
149 vmstate_register(NULL, cpu->cpu_index, &vmstate_cpu_common, cpu);
150 }
6fbdff87
AB
151 if (cpu->cc->sysemu_ops->legacy_vmsd != NULL) {
152 vmstate_register(NULL, cpu->cpu_index, cpu->cc->sysemu_ops->legacy_vmsd, cpu);
7df5e3d6
CF
153 }
154#endif /* CONFIG_USER_ONLY */
79a99091
PMD
155
156 return true;
7df5e3d6
CF
157}
158
159void cpu_exec_unrealizefn(CPUState *cpu)
160{
feece4d0 161#ifndef CONFIG_USER_ONLY
7df5e3d6 162 CPUClass *cc = CPU_GET_CLASS(cpu);
d9f24bf5 163
feece4d0
PMD
164 if (cc->sysemu_ops->legacy_vmsd != NULL) {
165 vmstate_unregister(NULL, cc->sysemu_ops->legacy_vmsd, cpu);
d9f24bf5
PB
166 }
167 if (qdev_get_vmsd(DEVICE(cpu)) == NULL) {
168 vmstate_unregister(NULL, &vmstate_cpu_common, cpu);
169 }
d9f24bf5 170#endif
4731f89b 171
7df5e3d6 172 cpu_list_remove(cpu);
4731f89b
EC
173 /*
174 * Now that the vCPU has been removed from the RCU list, we can call
1aa1d830 175 * accel_cpu_common_unrealize, which may free fields using call_rcu.
4731f89b 176 */
1aa1d830 177 accel_cpu_common_unrealize(cpu);
d9f24bf5
PB
178}
179
6e8dcacd
RH
180/*
181 * This can't go in hw/core/cpu.c because that file is compiled only
182 * once for both user-mode and system builds.
183 */
995b87de 184static Property cpu_common_props[] = {
6e8dcacd
RH
185#ifdef CONFIG_USER_ONLY
186 /*
187 * Create a property for the user-only object, so users can
188 * adjust prctl(PR_SET_UNALIGN) from the command-line.
189 * Has no effect if the target does not support the feature.
190 */
191 DEFINE_PROP_BOOL("prctl-unalign-sigbus", CPUState,
192 prctl_unalign_sigbus, false),
193#else
995b87de 194 /*
54b99122 195 * Create a memory property for system CPU object, so users can
6e8dcacd 196 * wire up its memory. The default if no link is set up is to use
995b87de
RH
197 * the system address space.
198 */
199 DEFINE_PROP_LINK("memory", CPUState, memory, TYPE_MEMORY_REGION,
200 MemoryRegion *),
201#endif
995b87de
RH
202 DEFINE_PROP_END_OF_LIST(),
203};
204
0f9237f4 205#ifndef CONFIG_USER_ONLY
0c3c25fc
PM
206static bool cpu_get_start_powered_off(Object *obj, Error **errp)
207{
208 CPUState *cpu = CPU(obj);
209 return cpu->start_powered_off;
210}
211
212static void cpu_set_start_powered_off(Object *obj, bool value, Error **errp)
213{
214 CPUState *cpu = CPU(obj);
215 cpu->start_powered_off = value;
216}
0f9237f4 217#endif
0c3c25fc 218
995b87de
RH
219void cpu_class_init_props(DeviceClass *dc)
220{
0f9237f4 221#ifndef CONFIG_USER_ONLY
0c3c25fc
PM
222 ObjectClass *oc = OBJECT_CLASS(dc);
223
0c3c25fc
PM
224 /*
225 * We can't use DEFINE_PROP_BOOL in the Property array for this
226 * property, because we want this to be settable after realize.
227 */
228 object_class_property_add_bool(oc, "start-powered-off",
229 cpu_get_start_powered_off,
230 cpu_set_start_powered_off);
0f9237f4
PMD
231#endif
232
233 device_class_set_props(dc, cpu_common_props);
995b87de
RH
234}
235
d9f24bf5
PB
236void cpu_exec_initfn(CPUState *cpu)
237{
238 cpu->as = NULL;
239 cpu->num_ases = 0;
240
241#ifndef CONFIG_USER_ONLY
242 cpu->thread_id = qemu_get_thread_id();
243 cpu->memory = get_system_memory();
244 object_ref(OBJECT(cpu->memory));
245#endif
246}
247
445946f4
GS
248char *cpu_model_from_type(const char *typename)
249{
250 const char *suffix = "-" CPU_RESOLVING_TYPE;
251
252 if (!object_class_by_name(typename)) {
253 return NULL;
254 }
255
256 if (g_str_has_suffix(typename, suffix)) {
257 return g_strndup(typename, strlen(typename) - strlen(suffix));
258 }
259
260 return g_strdup(typename);
261}
262
d9f24bf5
PB
263const char *parse_cpu_option(const char *cpu_option)
264{
265 ObjectClass *oc;
266 CPUClass *cc;
267 gchar **model_pieces;
268 const char *cpu_type;
269
270 model_pieces = g_strsplit(cpu_option, ",", 2);
271 if (!model_pieces[0]) {
272 error_report("-cpu option cannot be empty");
273 exit(1);
274 }
275
276 oc = cpu_class_by_name(CPU_RESOLVING_TYPE, model_pieces[0]);
277 if (oc == NULL) {
278 error_report("unable to find CPU model '%s'", model_pieces[0]);
279 g_strfreev(model_pieces);
280 exit(EXIT_FAILURE);
281 }
282
283 cpu_type = object_class_get_name(oc);
284 cc = CPU_CLASS(oc);
285 cc->parse_features(cpu_type, model_pieces[1], &error_fatal);
286 g_strfreev(model_pieces);
287 return cpu_type;
288}
289
dfa47531
GS
290#ifndef cpu_list
291static void cpu_list_entry(gpointer data, gpointer user_data)
292{
293 CPUClass *cc = CPU_CLASS(OBJECT_CLASS(data));
294 const char *typename = object_class_get_name(OBJECT_CLASS(data));
295 g_autofree char *model = cpu_model_from_type(typename);
296
297 if (cc->deprecation_note) {
298 qemu_printf(" %s (deprecated)\n", model);
299 } else {
300 qemu_printf(" %s\n", model);
301 }
302}
303
304static void cpu_list(void)
305{
306 GSList *list;
307
308 list = object_class_get_list_sorted(TYPE_CPU, false);
309 qemu_printf("Available CPUs:\n");
310 g_slist_foreach(list, cpu_list_entry, NULL);
311 g_slist_free(list);
312}
313#endif
314
c138c3b8 315void list_cpus(void)
377bf6f3 316{
377bf6f3 317 cpu_list();
377bf6f3
PMD
318}
319
d9f24bf5
PB
320/* enable or disable single step mode. EXCP_DEBUG is returned by the
321 CPU loop after each instruction */
322void cpu_single_step(CPUState *cpu, int enabled)
323{
324 if (cpu->singlestep_enabled != enabled) {
325 cpu->singlestep_enabled = enabled;
412ae126
MY
326
327#if !defined(CONFIG_USER_ONLY)
328 const AccelOpsClass *ops = cpus_get_accel();
329 if (ops->update_guest_debug) {
330 ops->update_guest_debug(cpu);
d9f24bf5 331 }
412ae126
MY
332#endif
333
ad1a706f 334 trace_breakpoint_singlestep(cpu->cpu_index, enabled);
d9f24bf5
PB
335 }
336}
337
338void cpu_abort(CPUState *cpu, const char *fmt, ...)
339{
340 va_list ap;
341 va_list ap2;
342
343 va_start(ap, fmt);
344 va_copy(ap2, ap);
345 fprintf(stderr, "qemu: fatal: ");
346 vfprintf(stderr, fmt, ap);
347 fprintf(stderr, "\n");
348 cpu_dump_state(cpu, stderr, CPU_DUMP_FPU | CPU_DUMP_CCOP);
349 if (qemu_log_separate()) {
c60f599b 350 FILE *logfile = qemu_log_trylock();
78b54858
RH
351 if (logfile) {
352 fprintf(logfile, "qemu: fatal: ");
353 vfprintf(logfile, fmt, ap2);
354 fprintf(logfile, "\n");
355 cpu_dump_state(cpu, logfile, CPU_DUMP_FPU | CPU_DUMP_CCOP);
78b54858
RH
356 qemu_log_unlock(logfile);
357 }
d9f24bf5
PB
358 }
359 va_end(ap2);
360 va_end(ap);
361 replay_finish();
362#if defined(CONFIG_USER_ONLY)
363 {
364 struct sigaction act;
365 sigfillset(&act.sa_mask);
366 act.sa_handler = SIG_DFL;
367 act.sa_flags = 0;
368 sigaction(SIGABRT, &act, NULL);
369 }
370#endif
371 abort();
372}
373
374/* physical memory access (slow version, mainly for debug) */
375#if defined(CONFIG_USER_ONLY)
73842ef0
PMD
376int cpu_memory_rw_debug(CPUState *cpu, vaddr addr,
377 void *ptr, size_t len, bool is_write)
d9f24bf5
PB
378{
379 int flags;
73842ef0 380 vaddr l, page;
d9f24bf5
PB
381 void * p;
382 uint8_t *buf = ptr;
87ab2704
IL
383 ssize_t written;
384 int ret = -1;
385 int fd = -1;
d9f24bf5
PB
386
387 while (len > 0) {
388 page = addr & TARGET_PAGE_MASK;
389 l = (page + TARGET_PAGE_SIZE) - addr;
390 if (l > len)
391 l = len;
392 flags = page_get_flags(page);
87ab2704
IL
393 if (!(flags & PAGE_VALID)) {
394 goto out_close;
395 }
d9f24bf5 396 if (is_write) {
87ab2704
IL
397 if (flags & PAGE_WRITE) {
398 /* XXX: this code should not depend on lock_user */
399 p = lock_user(VERIFY_WRITE, addr, l, 0);
400 if (!p) {
401 goto out_close;
402 }
403 memcpy(p, buf, l);
404 unlock_user(p, addr, l);
405 } else {
406 /* Bypass the host page protection using ptrace. */
407 if (fd == -1) {
408 fd = open("/proc/self/mem", O_WRONLY);
409 if (fd == -1) {
410 goto out;
411 }
412 }
413 /*
414 * If there is a TranslationBlock and we weren't bypassing the
415 * host page protection, the memcpy() above would SEGV,
416 * ultimately leading to page_unprotect(). So invalidate the
417 * translations manually. Both invalidation and pwrite() must
418 * be under mmap_lock() in order to prevent the creation of
419 * another TranslationBlock in between.
420 */
421 mmap_lock();
422 tb_invalidate_phys_range(addr, addr + l - 1);
423 written = pwrite(fd, buf, l,
424 (off_t)(uintptr_t)g2h_untagged(addr));
425 mmap_unlock();
426 if (written != l) {
427 goto out_close;
428 }
429 }
430 } else if (flags & PAGE_READ) {
d9f24bf5 431 /* XXX: this code should not depend on lock_user */
87ab2704
IL
432 p = lock_user(VERIFY_READ, addr, l, 1);
433 if (!p) {
434 goto out_close;
435 }
d9f24bf5
PB
436 memcpy(buf, p, l);
437 unlock_user(p, addr, 0);
87ab2704
IL
438 } else {
439 /* Bypass the host page protection using ptrace. */
440 if (fd == -1) {
441 fd = open("/proc/self/mem", O_RDONLY);
442 if (fd == -1) {
443 goto out;
444 }
445 }
446 if (pread(fd, buf, l,
447 (off_t)(uintptr_t)g2h_untagged(addr)) != l) {
448 goto out_close;
449 }
d9f24bf5
PB
450 }
451 len -= l;
452 buf += l;
453 addr += l;
454 }
87ab2704
IL
455 ret = 0;
456out_close:
457 if (fd != -1) {
458 close(fd);
459 }
460out:
461 return ret;
d9f24bf5
PB
462}
463#endif
464
465bool target_words_bigendian(void)
466{
ded625e7 467 return TARGET_BIG_ENDIAN;
d9f24bf5
PB
468}
469
1077f50b
TH
470const char *target_name(void)
471{
472 return TARGET_NAME;
473}