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Fix drbg_ossl_ctx_free() and drbg_nonce_ossl_ctx_free() to handle NULL
[thirdparty/openssl.git] / crypto / include / internal / aes_platform.h
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1/*
2 * Copyright 2019 The OpenSSL Project Authors. All Rights Reserved.
3 *
4 * Licensed under the Apache License 2.0 (the "License"). You may not use
5 * this file except in compliance with the License. You can obtain a copy
6 * in the file LICENSE in the source distribution or at
7 * https://www.openssl.org/source/license.html
8 */
9
10#ifndef HEADER_INTERNAL_AES_PLATFORM_H
11# define HEADER_INTERNAL_AES_PLATFORM_H
12
13# ifdef VPAES_ASM
14int vpaes_set_encrypt_key(const unsigned char *userKey, int bits,
15 AES_KEY *key);
16int vpaes_set_decrypt_key(const unsigned char *userKey, int bits,
17 AES_KEY *key);
18void vpaes_encrypt(const unsigned char *in, unsigned char *out,
19 const AES_KEY *key);
20void vpaes_decrypt(const unsigned char *in, unsigned char *out,
21 const AES_KEY *key);
22void vpaes_cbc_encrypt(const unsigned char *in,
23 unsigned char *out,
24 size_t length,
25 const AES_KEY *key, unsigned char *ivec, int enc);
26# endif /* VPAES_ASM */
27
28# ifdef BSAES_ASM
29void bsaes_cbc_encrypt(const unsigned char *in, unsigned char *out,
30 size_t length, const AES_KEY *key,
31 unsigned char ivec[16], int enc);
32void bsaes_ctr32_encrypt_blocks(const unsigned char *in, unsigned char *out,
33 size_t len, const AES_KEY *key,
34 const unsigned char ivec[16]);
35void bsaes_xts_encrypt(const unsigned char *inp, unsigned char *out,
36 size_t len, const AES_KEY *key1,
37 const AES_KEY *key2, const unsigned char iv[16]);
38void bsaes_xts_decrypt(const unsigned char *inp, unsigned char *out,
39 size_t len, const AES_KEY *key1,
40 const AES_KEY *key2, const unsigned char iv[16]);
41# endif /* BSAES_ASM */
42
43# ifdef AES_CTR_ASM
44void AES_ctr32_encrypt(const unsigned char *in, unsigned char *out,
45 size_t blocks, const AES_KEY *key,
46 const unsigned char ivec[AES_BLOCK_SIZE]);
47# endif /* AES_CTR_ASM */
48
49# ifdef AES_XTS_ASM
50void AES_xts_encrypt(const unsigned char *inp, unsigned char *out, size_t len,
51 const AES_KEY *key1, const AES_KEY *key2,
52 const unsigned char iv[16]);
53void AES_xts_decrypt(const unsigned char *inp, unsigned char *out, size_t len,
54 const AES_KEY *key1, const AES_KEY *key2,
55 const unsigned char iv[16]);
56# endif /* AES_XTS_ASM */
57
58# if defined(OPENSSL_CPUID_OBJ)
59# if (defined(__powerpc__) || defined(__ppc__) || defined(_ARCH_PPC))
60# include "ppc_arch.h"
61# ifdef VPAES_ASM
62# define VPAES_CAPABLE (OPENSSL_ppccap_P & PPC_ALTIVEC)
63# endif
64# define HWAES_CAPABLE (OPENSSL_ppccap_P & PPC_CRYPTO207)
65# define HWAES_set_encrypt_key aes_p8_set_encrypt_key
66# define HWAES_set_decrypt_key aes_p8_set_decrypt_key
67# define HWAES_encrypt aes_p8_encrypt
68# define HWAES_decrypt aes_p8_decrypt
69# define HWAES_cbc_encrypt aes_p8_cbc_encrypt
70# define HWAES_ctr32_encrypt_blocks aes_p8_ctr32_encrypt_blocks
71# define HWAES_xts_encrypt aes_p8_xts_encrypt
72# define HWAES_xts_decrypt aes_p8_xts_decrypt
73# endif /* PPC */
74
75# if (defined(__arm__) || defined(__arm) || defined(__aarch64__))
76# include "arm_arch.h"
77# if __ARM_MAX_ARCH__>=7
78# if defined(BSAES_ASM)
79# define BSAES_CAPABLE (OPENSSL_armcap_P & ARMV7_NEON)
80# endif
81# if defined(VPAES_ASM)
82# define VPAES_CAPABLE (OPENSSL_armcap_P & ARMV7_NEON)
83# endif
84# define HWAES_CAPABLE (OPENSSL_armcap_P & ARMV8_AES)
85# define HWAES_set_encrypt_key aes_v8_set_encrypt_key
86# define HWAES_set_decrypt_key aes_v8_set_decrypt_key
87# define HWAES_encrypt aes_v8_encrypt
88# define HWAES_decrypt aes_v8_decrypt
89# define HWAES_cbc_encrypt aes_v8_cbc_encrypt
90# define HWAES_ctr32_encrypt_blocks aes_v8_ctr32_encrypt_blocks
91# endif
92# endif
93# endif /* OPENSSL_CPUID_OBJ */
94
95# if defined(AES_ASM) && !defined(I386_ONLY) && ( \
96 ((defined(__i386) || defined(__i386__) || \
97 defined(_M_IX86)) && defined(OPENSSL_IA32_SSE2))|| \
98 defined(__x86_64) || defined(__x86_64__) || \
99 defined(_M_AMD64) || defined(_M_X64) )
100
101/* AES-NI section */
102extern unsigned int OPENSSL_ia32cap_P[];
103
104# define AESNI_CAPABLE (OPENSSL_ia32cap_P[1]&(1<<(57-32)))
105# ifdef VPAES_ASM
106# define VPAES_CAPABLE (OPENSSL_ia32cap_P[1]&(1<<(41-32)))
107# endif
108# ifdef BSAES_ASM
109# define BSAES_CAPABLE (OPENSSL_ia32cap_P[1]&(1<<(41-32)))
110# endif
111
112int aesni_set_encrypt_key(const unsigned char *userKey, int bits,
113 AES_KEY *key);
114int aesni_set_decrypt_key(const unsigned char *userKey, int bits,
115 AES_KEY *key);
116
117void aesni_encrypt(const unsigned char *in, unsigned char *out,
118 const AES_KEY *key);
119void aesni_decrypt(const unsigned char *in, unsigned char *out,
120 const AES_KEY *key);
121
122void aesni_ecb_encrypt(const unsigned char *in,
123 unsigned char *out,
124 size_t length, const AES_KEY *key, int enc);
125void aesni_cbc_encrypt(const unsigned char *in,
126 unsigned char *out,
127 size_t length,
128 const AES_KEY *key, unsigned char *ivec, int enc);
129# ifndef OPENSSL_NO_OCB
130void aesni_ocb_encrypt(const unsigned char *in, unsigned char *out,
131 size_t blocks, const void *key,
132 size_t start_block_num,
133 unsigned char offset_i[16],
134 const unsigned char L_[][16],
135 unsigned char checksum[16]);
136void aesni_ocb_decrypt(const unsigned char *in, unsigned char *out,
137 size_t blocks, const void *key,
138 size_t start_block_num,
139 unsigned char offset_i[16],
140 const unsigned char L_[][16],
141 unsigned char checksum[16]);
142# endif /* OPENSSL_NO_OCB */
143
144void aesni_ctr32_encrypt_blocks(const unsigned char *in,
145 unsigned char *out,
146 size_t blocks,
147 const void *key, const unsigned char *ivec);
148
149void aesni_xts_encrypt(const unsigned char *in,
150 unsigned char *out,
151 size_t length,
152 const AES_KEY *key1, const AES_KEY *key2,
153 const unsigned char iv[16]);
154
155void aesni_xts_decrypt(const unsigned char *in,
156 unsigned char *out,
157 size_t length,
158 const AES_KEY *key1, const AES_KEY *key2,
159 const unsigned char iv[16]);
160
161void aesni_ccm64_encrypt_blocks(const unsigned char *in,
162 unsigned char *out,
163 size_t blocks,
164 const void *key,
165 const unsigned char ivec[16],
166 unsigned char cmac[16]);
167
168void aesni_ccm64_decrypt_blocks(const unsigned char *in,
169 unsigned char *out,
170 size_t blocks,
171 const void *key,
172 const unsigned char ivec[16],
173 unsigned char cmac[16]);
174
175# if defined(__x86_64) || defined(__x86_64__) || defined(_M_AMD64) || defined(_M_X64)
176size_t aesni_gcm_encrypt(const unsigned char *in, unsigned char *out, size_t len,
177 const void *key, unsigned char ivec[16], u64 *Xi);
178size_t aesni_gcm_decrypt(const unsigned char *in, unsigned char *out, size_t len,
179 const void *key, unsigned char ivec[16], u64 *Xi);
180void gcm_ghash_avx(u64 Xi[2], const u128 Htable[16], const u8 *in, size_t len);
181
182# define AES_GCM_ASM(ctx) (ctx->ctr == aesni_ctr32_encrypt_blocks && \
183 ctx->gcm.ghash == gcm_ghash_avx)
184# endif
185
186
187# elif defined(AES_ASM) && (defined(__sparc) || defined(__sparc__))
188
189/* Fujitsu SPARC64 X support */
190extern unsigned int OPENSSL_sparcv9cap_P[];
191# include "sparc_arch.h"
192# define SPARC_AES_CAPABLE (OPENSSL_sparcv9cap_P[1] & CFR_AES)
193# define HWAES_CAPABLE (OPENSSL_sparcv9cap_P[0] & SPARCV9_FJAESX)
194# define HWAES_set_encrypt_key aes_fx_set_encrypt_key
195# define HWAES_set_decrypt_key aes_fx_set_decrypt_key
196# define HWAES_encrypt aes_fx_encrypt
197# define HWAES_decrypt aes_fx_decrypt
198# define HWAES_cbc_encrypt aes_fx_cbc_encrypt
199# define HWAES_ctr32_encrypt_blocks aes_fx_ctr32_encrypt_blocks
200
201void aes_t4_set_encrypt_key(const unsigned char *key, int bits, AES_KEY *ks);
202void aes_t4_set_decrypt_key(const unsigned char *key, int bits, AES_KEY *ks);
203void aes_t4_encrypt(const unsigned char *in, unsigned char *out,
204 const AES_KEY *key);
205void aes_t4_decrypt(const unsigned char *in, unsigned char *out,
206 const AES_KEY *key);
207/*
208 * Key-length specific subroutines were chosen for following reason.
209 * Each SPARC T4 core can execute up to 8 threads which share core's
210 * resources. Loading as much key material to registers allows to
211 * minimize references to shared memory interface, as well as amount
212 * of instructions in inner loops [much needed on T4]. But then having
213 * non-key-length specific routines would require conditional branches
214 * either in inner loops or on subroutines' entries. Former is hardly
215 * acceptable, while latter means code size increase to size occupied
216 * by multiple key-length specific subroutines, so why fight?
217 */
218void aes128_t4_cbc_encrypt(const unsigned char *in, unsigned char *out,
219 size_t len, const AES_KEY *key,
220 unsigned char *ivec);
221void aes128_t4_cbc_decrypt(const unsigned char *in, unsigned char *out,
222 size_t len, const AES_KEY *key,
223 unsigned char *ivec);
224void aes192_t4_cbc_encrypt(const unsigned char *in, unsigned char *out,
225 size_t len, const AES_KEY *key,
226 unsigned char *ivec);
227void aes192_t4_cbc_decrypt(const unsigned char *in, unsigned char *out,
228 size_t len, const AES_KEY *key,
229 unsigned char *ivec);
230void aes256_t4_cbc_encrypt(const unsigned char *in, unsigned char *out,
231 size_t len, const AES_KEY *key,
232 unsigned char *ivec);
233void aes256_t4_cbc_decrypt(const unsigned char *in, unsigned char *out,
234 size_t len, const AES_KEY *key,
235 unsigned char *ivec);
236void aes128_t4_ctr32_encrypt(const unsigned char *in, unsigned char *out,
237 size_t blocks, const AES_KEY *key,
238 unsigned char *ivec);
239void aes192_t4_ctr32_encrypt(const unsigned char *in, unsigned char *out,
240 size_t blocks, const AES_KEY *key,
241 unsigned char *ivec);
242void aes256_t4_ctr32_encrypt(const unsigned char *in, unsigned char *out,
243 size_t blocks, const AES_KEY *key,
244 unsigned char *ivec);
245void aes128_t4_xts_encrypt(const unsigned char *in, unsigned char *out,
246 size_t blocks, const AES_KEY *key1,
247 const AES_KEY *key2, const unsigned char *ivec);
248void aes128_t4_xts_decrypt(const unsigned char *in, unsigned char *out,
249 size_t blocks, const AES_KEY *key1,
250 const AES_KEY *key2, const unsigned char *ivec);
251void aes256_t4_xts_encrypt(const unsigned char *in, unsigned char *out,
252 size_t blocks, const AES_KEY *key1,
253 const AES_KEY *key2, const unsigned char *ivec);
254void aes256_t4_xts_decrypt(const unsigned char *in, unsigned char *out,
255 size_t blocks, const AES_KEY *key1,
256 const AES_KEY *key2, const unsigned char *ivec);
257
258# elif defined(OPENSSL_CPUID_OBJ) && defined(__s390__)
259/* IBM S390X support */
260# include "s390x_arch.h"
261
262
263/* Convert key size to function code: [16,24,32] -> [18,19,20]. */
264# define S390X_AES_FC(keylen) (S390X_AES_128 + ((((keylen) << 3) - 128) >> 6))
265
266/* Most modes of operation need km for partial block processing. */
267# define S390X_aes_128_CAPABLE (OPENSSL_s390xcap_P.km[0] & \
268 S390X_CAPBIT(S390X_AES_128))
269# define S390X_aes_192_CAPABLE (OPENSSL_s390xcap_P.km[0] & \
270 S390X_CAPBIT(S390X_AES_192))
271# define S390X_aes_256_CAPABLE (OPENSSL_s390xcap_P.km[0] & \
272 S390X_CAPBIT(S390X_AES_256))
273
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274# define S390X_aes_128_cbc_CAPABLE 1 /* checked by callee */
275# define S390X_aes_192_cbc_CAPABLE 1
276# define S390X_aes_256_cbc_CAPABLE 1
459b15d4 277
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278# define S390X_aes_128_ecb_CAPABLE S390X_aes_128_CAPABLE
279# define S390X_aes_192_ecb_CAPABLE S390X_aes_192_CAPABLE
280# define S390X_aes_256_ecb_CAPABLE S390X_aes_256_CAPABLE
459b15d4 281
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282# define S390X_aes_128_ofb_CAPABLE (S390X_aes_128_CAPABLE && \
283 (OPENSSL_s390xcap_P.kmo[0] & \
459b15d4 284 S390X_CAPBIT(S390X_AES_128)))
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285# define S390X_aes_192_ofb_CAPABLE (S390X_aes_192_CAPABLE && \
286 (OPENSSL_s390xcap_P.kmo[0] & \
459b15d4 287 S390X_CAPBIT(S390X_AES_192)))
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288# define S390X_aes_256_ofb_CAPABLE (S390X_aes_256_CAPABLE && \
289 (OPENSSL_s390xcap_P.kmo[0] & \
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290 S390X_CAPBIT(S390X_AES_256)))
291
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292# define S390X_aes_128_cfb_CAPABLE (S390X_aes_128_CAPABLE && \
293 (OPENSSL_s390xcap_P.kmf[0] & \
459b15d4 294 S390X_CAPBIT(S390X_AES_128)))
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295# define S390X_aes_192_cfb_CAPABLE (S390X_aes_192_CAPABLE && \
296 (OPENSSL_s390xcap_P.kmf[0] & \
459b15d4 297 S390X_CAPBIT(S390X_AES_192)))
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298# define S390X_aes_256_cfb_CAPABLE (S390X_aes_256_CAPABLE && \
299 (OPENSSL_s390xcap_P.kmf[0] & \
459b15d4 300 S390X_CAPBIT(S390X_AES_256)))
dd6b2706 301# define S390X_aes_128_cfb8_CAPABLE (OPENSSL_s390xcap_P.kmf[0] & \
459b15d4 302 S390X_CAPBIT(S390X_AES_128))
dd6b2706 303# define S390X_aes_192_cfb8_CAPABLE (OPENSSL_s390xcap_P.kmf[0] & \
459b15d4 304 S390X_CAPBIT(S390X_AES_192))
dd6b2706 305# define S390X_aes_256_cfb8_CAPABLE (OPENSSL_s390xcap_P.kmf[0] & \
459b15d4 306 S390X_CAPBIT(S390X_AES_256))
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307# define S390X_aes_128_cfb1_CAPABLE 0
308# define S390X_aes_192_cfb1_CAPABLE 0
309# define S390X_aes_256_cfb1_CAPABLE 0
459b15d4 310
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311# define S390X_aes_128_ctr_CAPABLE 1 /* checked by callee */
312# define S390X_aes_192_ctr_CAPABLE 1
313# define S390X_aes_256_ctr_CAPABLE 1
459b15d4 314
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315# define S390X_aes_128_xts_CAPABLE 1 /* checked by callee */
316# define S390X_aes_256_xts_CAPABLE 1
459b15d4 317
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318# define S390X_aes_128_gcm_CAPABLE (S390X_aes_128_CAPABLE && \
319 (OPENSSL_s390xcap_P.kma[0] & \
459b15d4 320 S390X_CAPBIT(S390X_AES_128)))
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321# define S390X_aes_192_gcm_CAPABLE (S390X_aes_192_CAPABLE && \
322 (OPENSSL_s390xcap_P.kma[0] & \
459b15d4 323 S390X_CAPBIT(S390X_AES_192)))
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324# define S390X_aes_256_gcm_CAPABLE (S390X_aes_256_CAPABLE && \
325 (OPENSSL_s390xcap_P.kma[0] & \
326 S390X_CAPBIT(S390X_AES_256)))
327
328# define S390X_aes_128_ccm_CAPABLE (S390X_aes_128_CAPABLE && \
329 (OPENSSL_s390xcap_P.kmac[0] & \
330 S390X_CAPBIT(S390X_AES_128)))
331# define S390X_aes_192_ccm_CAPABLE (S390X_aes_192_CAPABLE && \
332 (OPENSSL_s390xcap_P.kmac[0] & \
333 S390X_CAPBIT(S390X_AES_192)))
334# define S390X_aes_256_ccm_CAPABLE (S390X_aes_256_CAPABLE && \
335 (OPENSSL_s390xcap_P.kmac[0] & \
459b15d4 336 S390X_CAPBIT(S390X_AES_256)))
dd6b2706 337# define S390X_CCM_AAD_FLAG 0x40
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338
339# ifndef OPENSSL_NO_OCB
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340# define S390X_aes_128_ocb_CAPABLE 0
341# define S390X_aes_192_ocb_CAPABLE 0
342# define S390X_aes_256_ocb_CAPABLE 0
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343# endif /* OPENSSL_NO_OCB */
344
345# ifndef OPENSSL_NO_SIV
346# define S390X_aes_128_siv_CAPABLE 0
347# define S390X_aes_192_siv_CAPABLE 0
348# define S390X_aes_256_siv_CAPABLE 0
349# endif /* OPENSSL_NO_SIV */
350
351/* Convert key size to function code: [16,24,32] -> [18,19,20]. */
352# define S390X_AES_FC(keylen) (S390X_AES_128 + ((((keylen) << 3) - 128) >> 6))
353# endif
354
355# if defined(HWAES_CAPABLE)
356int HWAES_set_encrypt_key(const unsigned char *userKey, const int bits,
357 AES_KEY *key);
358int HWAES_set_decrypt_key(const unsigned char *userKey, const int bits,
359 AES_KEY *key);
360void HWAES_encrypt(const unsigned char *in, unsigned char *out,
361 const AES_KEY *key);
362void HWAES_decrypt(const unsigned char *in, unsigned char *out,
363 const AES_KEY *key);
364void HWAES_cbc_encrypt(const unsigned char *in, unsigned char *out,
365 size_t length, const AES_KEY *key,
366 unsigned char *ivec, const int enc);
367void HWAES_ctr32_encrypt_blocks(const unsigned char *in, unsigned char *out,
368 size_t len, const AES_KEY *key,
369 const unsigned char ivec[16]);
370void HWAES_xts_encrypt(const unsigned char *inp, unsigned char *out,
371 size_t len, const AES_KEY *key1,
372 const AES_KEY *key2, const unsigned char iv[16]);
373void HWAES_xts_decrypt(const unsigned char *inp, unsigned char *out,
374 size_t len, const AES_KEY *key1,
375 const AES_KEY *key2, const unsigned char iv[16]);
376# ifndef OPENSSL_NO_OCB
377# ifdef HWAES_ocb_encrypt
378void HWAES_ocb_encrypt(const unsigned char *in, unsigned char *out,
379 size_t blocks, const void *key,
380 size_t start_block_num,
381 unsigned char offset_i[16],
382 const unsigned char L_[][16],
383 unsigned char checksum[16]);
384# else
385# define HWAES_ocb_encrypt ((ocb128_f)NULL)
386# endif
387# ifdef HWAES_ocb_decrypt
388void HWAES_ocb_decrypt(const unsigned char *in, unsigned char *out,
389 size_t blocks, const void *key,
390 size_t start_block_num,
391 unsigned char offset_i[16],
392 const unsigned char L_[][16],
393 unsigned char checksum[16]);
394# else
395# define HWAES_ocb_decrypt ((ocb128_f)NULL)
396# endif
397# endif /* OPENSSL_NO_OCB */
398
399# endif /* HWAES_CAPABLE */
400
401#endif /* HEADER_INTERNAL_AES_PLATFORM_H */