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4782ac80 | 1 | /* |
4c2e3da8 | 2 | * Copyright (C) Freescale Semiconductor, Inc. 2006. |
4782ac80 JZ |
3 | * Author: Jason Jin<Jason.jin@freescale.com> |
4 | * Zhang Wei<wei.zhang@freescale.com> | |
5 | * | |
6 | * See file CREDITS for list of people who contributed to this | |
7 | * project. | |
8 | * | |
9 | * This program is free software; you can redistribute it and/or | |
10 | * modify it under the terms of the GNU General Public License as | |
11 | * published by the Free Software Foundation; either version 2 of | |
12 | * the License, or (at your option) any later version. | |
13 | * | |
14 | * This program is distributed in the hope that it will be useful, | |
15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 | * GNU General Public License for more details. | |
18 | * | |
19 | * You should have received a copy of the GNU General Public License | |
20 | * along with this program; if not, write to the Free Software | |
21 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
22 | * MA 02111-1307 USA | |
23 | * | |
24 | * with the reference on libata and ahci drvier in kernel | |
25 | * | |
26 | */ | |
27 | #include <common.h> | |
28 | ||
4782ac80 JZ |
29 | #include <command.h> |
30 | #include <pci.h> | |
31 | #include <asm/processor.h> | |
32 | #include <asm/errno.h> | |
33 | #include <asm/io.h> | |
34 | #include <malloc.h> | |
35 | #include <scsi.h> | |
36 | #include <ata.h> | |
37 | #include <linux/ctype.h> | |
38 | #include <ahci.h> | |
39 | ||
766b16fe MJ |
40 | static int ata_io_flush(u8 port); |
41 | ||
4782ac80 JZ |
42 | struct ahci_probe_ent *probe_ent = NULL; |
43 | hd_driveid_t *ataid[AHCI_MAX_PORTS]; | |
44 | ||
4a7cc0f2 JL |
45 | #define writel_with_flush(a,b) do { writel(a,b); readl(b); } while (0) |
46 | ||
284231e4 | 47 | /* |
b7a21b70 HTL |
48 | * Some controllers limit number of blocks they can read/write at once. |
49 | * Contemporary SSD devices work much faster if the read/write size is aligned | |
50 | * to a power of 2. Let's set default to 128 and allowing to be overwritten if | |
51 | * needed. | |
284231e4 | 52 | */ |
b7a21b70 HTL |
53 | #ifndef MAX_SATA_BLOCKS_READ_WRITE |
54 | #define MAX_SATA_BLOCKS_READ_WRITE 0x80 | |
284231e4 | 55 | #endif |
4782ac80 | 56 | |
57847660 | 57 | /* Maximum timeouts for each event */ |
2a0c61d4 | 58 | #define WAIT_MS_SPINUP 10000 |
57847660 | 59 | #define WAIT_MS_DATAIO 5000 |
766b16fe | 60 | #define WAIT_MS_FLUSH 5000 |
57847660 WM |
61 | #define WAIT_MS_LINKUP 4 |
62 | ||
4782ac80 JZ |
63 | static inline u32 ahci_port_base(u32 base, u32 port) |
64 | { | |
65 | return base + 0x100 + (port * 0x80); | |
66 | } | |
67 | ||
68 | ||
69 | static void ahci_setup_port(struct ahci_ioports *port, unsigned long base, | |
70 | unsigned int port_idx) | |
71 | { | |
72 | base = ahci_port_base(base, port_idx); | |
73 | ||
4a7cc0f2 JL |
74 | port->cmd_addr = base; |
75 | port->scr_addr = base + PORT_SCR; | |
4782ac80 JZ |
76 | } |
77 | ||
78 | ||
79 | #define msleep(a) udelay(a * 1000) | |
4a7cc0f2 | 80 | |
90b276f6 TH |
81 | static void ahci_dcache_flush_range(unsigned begin, unsigned len) |
82 | { | |
83 | const unsigned long start = begin; | |
84 | const unsigned long end = start + len; | |
85 | ||
86 | debug("%s: flush dcache: [%#lx, %#lx)\n", __func__, start, end); | |
87 | flush_dcache_range(start, end); | |
88 | } | |
89 | ||
90 | /* | |
91 | * SATA controller DMAs to physical RAM. Ensure data from the | |
92 | * controller is invalidated from dcache; next access comes from | |
93 | * physical RAM. | |
94 | */ | |
95 | static void ahci_dcache_invalidate_range(unsigned begin, unsigned len) | |
96 | { | |
97 | const unsigned long start = begin; | |
98 | const unsigned long end = start + len; | |
99 | ||
100 | debug("%s: invalidate dcache: [%#lx, %#lx)\n", __func__, start, end); | |
101 | invalidate_dcache_range(start, end); | |
102 | } | |
103 | ||
104 | /* | |
105 | * Ensure data for SATA controller is flushed out of dcache and | |
106 | * written to physical memory. | |
107 | */ | |
108 | static void ahci_dcache_flush_sata_cmd(struct ahci_ioports *pp) | |
109 | { | |
110 | ahci_dcache_flush_range((unsigned long)pp->cmd_slot, | |
111 | AHCI_PORT_PRIV_DMA_SZ); | |
112 | } | |
113 | ||
4a7cc0f2 JL |
114 | static int waiting_for_cmd_completed(volatile u8 *offset, |
115 | int timeout_msec, | |
116 | u32 sign) | |
4782ac80 JZ |
117 | { |
118 | int i; | |
119 | u32 status; | |
4a7cc0f2 JL |
120 | |
121 | for (i = 0; ((status = readl(offset)) & sign) && i < timeout_msec; i++) | |
4782ac80 JZ |
122 | msleep(1); |
123 | ||
4a7cc0f2 | 124 | return (i < timeout_msec) ? 0 : -1; |
4782ac80 JZ |
125 | } |
126 | ||
127 | ||
128 | static int ahci_host_init(struct ahci_probe_ent *probe_ent) | |
129 | { | |
942e3143 | 130 | #ifndef CONFIG_SCSI_AHCI_PLAT |
4782ac80 | 131 | pci_dev_t pdev = probe_ent->dev; |
942e3143 RH |
132 | u16 tmp16; |
133 | unsigned short vendor; | |
134 | #endif | |
4782ac80 | 135 | volatile u8 *mmio = (volatile u8 *)probe_ent->mmio_base; |
2a0c61d4 | 136 | u32 tmp, cap_save, cmd; |
4782ac80 | 137 | int i, j; |
4a7cc0f2 | 138 | volatile u8 *port_mmio; |
4782ac80 | 139 | |
284231e4 VB |
140 | debug("ahci_host_init: start\n"); |
141 | ||
4782ac80 | 142 | cap_save = readl(mmio + HOST_CAP); |
4a7cc0f2 | 143 | cap_save &= ((1 << 28) | (1 << 17)); |
2a0c61d4 | 144 | cap_save |= (1 << 27); /* Staggered Spin-up. Not needed. */ |
4782ac80 JZ |
145 | |
146 | /* global controller reset */ | |
147 | tmp = readl(mmio + HOST_CTL); | |
148 | if ((tmp & HOST_RESET) == 0) | |
149 | writel_with_flush(tmp | HOST_RESET, mmio + HOST_CTL); | |
150 | ||
151 | /* reset must complete within 1 second, or | |
152 | * the hardware should be considered fried. | |
153 | */ | |
9a65b875 SR |
154 | i = 1000; |
155 | do { | |
156 | udelay(1000); | |
157 | tmp = readl(mmio + HOST_CTL); | |
158 | if (!i--) { | |
159 | debug("controller reset failed (0x%x)\n", tmp); | |
160 | return -1; | |
161 | } | |
162 | } while (tmp & HOST_RESET); | |
4782ac80 JZ |
163 | |
164 | writel_with_flush(HOST_AHCI_EN, mmio + HOST_CTL); | |
165 | writel(cap_save, mmio + HOST_CAP); | |
166 | writel_with_flush(0xf, mmio + HOST_PORTS_IMPL); | |
167 | ||
942e3143 | 168 | #ifndef CONFIG_SCSI_AHCI_PLAT |
4782ac80 JZ |
169 | pci_read_config_word(pdev, PCI_VENDOR_ID, &vendor); |
170 | ||
171 | if (vendor == PCI_VENDOR_ID_INTEL) { | |
172 | u16 tmp16; | |
173 | pci_read_config_word(pdev, 0x92, &tmp16); | |
174 | tmp16 |= 0xf; | |
175 | pci_write_config_word(pdev, 0x92, tmp16); | |
176 | } | |
942e3143 | 177 | #endif |
4782ac80 JZ |
178 | probe_ent->cap = readl(mmio + HOST_CAP); |
179 | probe_ent->port_map = readl(mmio + HOST_PORTS_IMPL); | |
180 | probe_ent->n_ports = (probe_ent->cap & 0x1f) + 1; | |
181 | ||
182 | debug("cap 0x%x port_map 0x%x n_ports %d\n", | |
4a7cc0f2 | 183 | probe_ent->cap, probe_ent->port_map, probe_ent->n_ports); |
4782ac80 | 184 | |
284231e4 VB |
185 | if (probe_ent->n_ports > CONFIG_SYS_SCSI_MAX_SCSI_ID) |
186 | probe_ent->n_ports = CONFIG_SYS_SCSI_MAX_SCSI_ID; | |
187 | ||
4782ac80 | 188 | for (i = 0; i < probe_ent->n_ports; i++) { |
4a7cc0f2 JL |
189 | probe_ent->port[i].port_mmio = ahci_port_base((u32) mmio, i); |
190 | port_mmio = (u8 *) probe_ent->port[i].port_mmio; | |
191 | ahci_setup_port(&probe_ent->port[i], (unsigned long)mmio, i); | |
4782ac80 JZ |
192 | |
193 | /* make sure port is not active */ | |
194 | tmp = readl(port_mmio + PORT_CMD); | |
195 | if (tmp & (PORT_CMD_LIST_ON | PORT_CMD_FIS_ON | | |
196 | PORT_CMD_FIS_RX | PORT_CMD_START)) { | |
7ba7917c | 197 | debug("Port %d is active. Deactivating.\n", i); |
4782ac80 JZ |
198 | tmp &= ~(PORT_CMD_LIST_ON | PORT_CMD_FIS_ON | |
199 | PORT_CMD_FIS_RX | PORT_CMD_START); | |
200 | writel_with_flush(tmp, port_mmio + PORT_CMD); | |
201 | ||
202 | /* spec says 500 msecs for each bit, so | |
203 | * this is slightly incorrect. | |
204 | */ | |
205 | msleep(500); | |
206 | } | |
207 | ||
2a0c61d4 MJ |
208 | /* Add the spinup command to whatever mode bits may |
209 | * already be on in the command register. | |
210 | */ | |
211 | cmd = readl(port_mmio + PORT_CMD); | |
212 | cmd |= PORT_CMD_FIS_RX; | |
213 | cmd |= PORT_CMD_SPIN_UP; | |
214 | writel_with_flush(cmd, port_mmio + PORT_CMD); | |
215 | ||
216 | /* Bring up SATA link. | |
217 | * SATA link bringup time is usually less than 1 ms; only very | |
218 | * rarely has it taken between 1-2 ms. Never seen it above 2 ms. | |
219 | */ | |
4782ac80 | 220 | j = 0; |
57847660 | 221 | while (j < WAIT_MS_LINKUP) { |
4782ac80 JZ |
222 | tmp = readl(port_mmio + PORT_SCR_STAT); |
223 | if ((tmp & 0xf) == 0x3) | |
224 | break; | |
9a65b875 | 225 | udelay(1000); |
4782ac80 JZ |
226 | j++; |
227 | } | |
2a0c61d4 MJ |
228 | if (j == WAIT_MS_LINKUP) { |
229 | printf("SATA link %d timeout.\n", i); | |
230 | continue; | |
231 | } else { | |
232 | debug("SATA link ok.\n"); | |
233 | } | |
234 | ||
235 | /* Clear error status */ | |
236 | tmp = readl(port_mmio + PORT_SCR_ERR); | |
237 | if (tmp) | |
238 | writel(tmp, port_mmio + PORT_SCR_ERR); | |
239 | ||
240 | debug("Spinning up device on SATA port %d... ", i); | |
241 | ||
242 | j = 0; | |
243 | while (j < WAIT_MS_SPINUP) { | |
244 | tmp = readl(port_mmio + PORT_TFDATA); | |
245 | if (!(tmp & (ATA_STAT_BUSY | ATA_STAT_DRQ))) | |
246 | break; | |
247 | udelay(1000); | |
248 | j++; | |
249 | } | |
250 | printf("Target spinup took %d ms.\n", j); | |
251 | if (j == WAIT_MS_SPINUP) | |
9a65b875 SR |
252 | debug("timeout.\n"); |
253 | else | |
254 | debug("ok.\n"); | |
4782ac80 JZ |
255 | |
256 | tmp = readl(port_mmio + PORT_SCR_ERR); | |
257 | debug("PORT_SCR_ERR 0x%x\n", tmp); | |
258 | writel(tmp, port_mmio + PORT_SCR_ERR); | |
259 | ||
260 | /* ack any pending irq events for this port */ | |
261 | tmp = readl(port_mmio + PORT_IRQ_STAT); | |
262 | debug("PORT_IRQ_STAT 0x%x\n", tmp); | |
263 | if (tmp) | |
264 | writel(tmp, port_mmio + PORT_IRQ_STAT); | |
265 | ||
266 | writel(1 << i, mmio + HOST_IRQ_STAT); | |
267 | ||
268 | /* set irq mask (enables interrupts) */ | |
269 | writel(DEF_PORT_IRQ, port_mmio + PORT_IRQ_MASK); | |
270 | ||
4e422bce | 271 | /* register linkup ports */ |
4782ac80 | 272 | tmp = readl(port_mmio + PORT_SCR_STAT); |
766b16fe | 273 | debug("SATA port %d status: 0x%x\n", i, tmp); |
4a7cc0f2 JL |
274 | if ((tmp & 0xf) == 0x03) |
275 | probe_ent->link_port_map |= (0x01 << i); | |
4782ac80 JZ |
276 | } |
277 | ||
278 | tmp = readl(mmio + HOST_CTL); | |
279 | debug("HOST_CTL 0x%x\n", tmp); | |
280 | writel(tmp | HOST_IRQ_EN, mmio + HOST_CTL); | |
281 | tmp = readl(mmio + HOST_CTL); | |
282 | debug("HOST_CTL 0x%x\n", tmp); | |
942e3143 | 283 | #ifndef CONFIG_SCSI_AHCI_PLAT |
4782ac80 JZ |
284 | pci_read_config_word(pdev, PCI_COMMAND, &tmp16); |
285 | tmp |= PCI_COMMAND_MASTER; | |
286 | pci_write_config_word(pdev, PCI_COMMAND, tmp16); | |
942e3143 | 287 | #endif |
4782ac80 JZ |
288 | return 0; |
289 | } | |
290 | ||
291 | ||
292 | static void ahci_print_info(struct ahci_probe_ent *probe_ent) | |
293 | { | |
942e3143 | 294 | #ifndef CONFIG_SCSI_AHCI_PLAT |
4782ac80 | 295 | pci_dev_t pdev = probe_ent->dev; |
942e3143 RH |
296 | u16 cc; |
297 | #endif | |
4a7cc0f2 | 298 | volatile u8 *mmio = (volatile u8 *)probe_ent->mmio_base; |
4e422bce | 299 | u32 vers, cap, cap2, impl, speed; |
4782ac80 | 300 | const char *speed_s; |
4782ac80 JZ |
301 | const char *scc_s; |
302 | ||
303 | vers = readl(mmio + HOST_VERSION); | |
304 | cap = probe_ent->cap; | |
4e422bce | 305 | cap2 = readl(mmio + HOST_CAP2); |
4782ac80 JZ |
306 | impl = probe_ent->port_map; |
307 | ||
308 | speed = (cap >> 20) & 0xf; | |
309 | if (speed == 1) | |
310 | speed_s = "1.5"; | |
311 | else if (speed == 2) | |
312 | speed_s = "3"; | |
4e422bce SR |
313 | else if (speed == 3) |
314 | speed_s = "6"; | |
4782ac80 JZ |
315 | else |
316 | speed_s = "?"; | |
317 | ||
942e3143 RH |
318 | #ifdef CONFIG_SCSI_AHCI_PLAT |
319 | scc_s = "SATA"; | |
320 | #else | |
4782ac80 JZ |
321 | pci_read_config_word(pdev, 0x0a, &cc); |
322 | if (cc == 0x0101) | |
323 | scc_s = "IDE"; | |
324 | else if (cc == 0x0106) | |
325 | scc_s = "SATA"; | |
326 | else if (cc == 0x0104) | |
327 | scc_s = "RAID"; | |
328 | else | |
329 | scc_s = "unknown"; | |
942e3143 | 330 | #endif |
4a7cc0f2 JL |
331 | printf("AHCI %02x%02x.%02x%02x " |
332 | "%u slots %u ports %s Gbps 0x%x impl %s mode\n", | |
333 | (vers >> 24) & 0xff, | |
334 | (vers >> 16) & 0xff, | |
335 | (vers >> 8) & 0xff, | |
336 | vers & 0xff, | |
337 | ((cap >> 8) & 0x1f) + 1, (cap & 0x1f) + 1, speed_s, impl, scc_s); | |
4782ac80 JZ |
338 | |
339 | printf("flags: " | |
4e422bce SR |
340 | "%s%s%s%s%s%s%s" |
341 | "%s%s%s%s%s%s%s" | |
342 | "%s%s%s%s%s%s\n", | |
4a7cc0f2 JL |
343 | cap & (1 << 31) ? "64bit " : "", |
344 | cap & (1 << 30) ? "ncq " : "", | |
345 | cap & (1 << 28) ? "ilck " : "", | |
346 | cap & (1 << 27) ? "stag " : "", | |
347 | cap & (1 << 26) ? "pm " : "", | |
348 | cap & (1 << 25) ? "led " : "", | |
349 | cap & (1 << 24) ? "clo " : "", | |
350 | cap & (1 << 19) ? "nz " : "", | |
351 | cap & (1 << 18) ? "only " : "", | |
352 | cap & (1 << 17) ? "pmp " : "", | |
4e422bce | 353 | cap & (1 << 16) ? "fbss " : "", |
4a7cc0f2 JL |
354 | cap & (1 << 15) ? "pio " : "", |
355 | cap & (1 << 14) ? "slum " : "", | |
4e422bce SR |
356 | cap & (1 << 13) ? "part " : "", |
357 | cap & (1 << 7) ? "ccc " : "", | |
358 | cap & (1 << 6) ? "ems " : "", | |
359 | cap & (1 << 5) ? "sxs " : "", | |
360 | cap2 & (1 << 2) ? "apst " : "", | |
361 | cap2 & (1 << 1) ? "nvmp " : "", | |
362 | cap2 & (1 << 0) ? "boh " : ""); | |
4782ac80 JZ |
363 | } |
364 | ||
942e3143 | 365 | #ifndef CONFIG_SCSI_AHCI_PLAT |
4a7cc0f2 | 366 | static int ahci_init_one(pci_dev_t pdev) |
4782ac80 | 367 | { |
63cec581 | 368 | u16 vendor; |
4782ac80 JZ |
369 | int rc; |
370 | ||
4a7cc0f2 | 371 | memset((void *)ataid, 0, sizeof(hd_driveid_t *) * AHCI_MAX_PORTS); |
4782ac80 | 372 | |
594e7983 ES |
373 | probe_ent = malloc(sizeof(struct ahci_probe_ent)); |
374 | memset(probe_ent, 0, sizeof(struct ahci_probe_ent)); | |
4782ac80 JZ |
375 | probe_ent->dev = pdev; |
376 | ||
4a7cc0f2 JL |
377 | probe_ent->host_flags = ATA_FLAG_SATA |
378 | | ATA_FLAG_NO_LEGACY | |
379 | | ATA_FLAG_MMIO | |
380 | | ATA_FLAG_PIO_DMA | |
381 | | ATA_FLAG_NO_ATAPI; | |
382 | probe_ent->pio_mask = 0x1f; | |
383 | probe_ent->udma_mask = 0x7f; /*Fixme,assume to support UDMA6 */ | |
4782ac80 | 384 | |
284231e4 VB |
385 | pci_read_config_dword(pdev, PCI_BASE_ADDRESS_5, &probe_ent->mmio_base); |
386 | debug("ahci mmio_base=0x%08x\n", probe_ent->mmio_base); | |
4782ac80 JZ |
387 | |
388 | /* Take from kernel: | |
389 | * JMicron-specific fixup: | |
390 | * make sure we're in AHCI mode | |
391 | */ | |
392 | pci_read_config_word(pdev, PCI_VENDOR_ID, &vendor); | |
4a7cc0f2 | 393 | if (vendor == 0x197b) |
4782ac80 JZ |
394 | pci_write_config_byte(pdev, 0x41, 0xa1); |
395 | ||
396 | /* initialize adapter */ | |
397 | rc = ahci_host_init(probe_ent); | |
398 | if (rc) | |
399 | goto err_out; | |
400 | ||
401 | ahci_print_info(probe_ent); | |
402 | ||
403 | return 0; | |
404 | ||
4a7cc0f2 | 405 | err_out: |
4782ac80 JZ |
406 | return rc; |
407 | } | |
942e3143 | 408 | #endif |
4782ac80 JZ |
409 | |
410 | #define MAX_DATA_BYTE_COUNT (4*1024*1024) | |
4a7cc0f2 | 411 | |
4782ac80 JZ |
412 | static int ahci_fill_sg(u8 port, unsigned char *buf, int buf_len) |
413 | { | |
4782ac80 JZ |
414 | struct ahci_ioports *pp = &(probe_ent->port[port]); |
415 | struct ahci_sg *ahci_sg = pp->cmd_tbl_sg; | |
416 | u32 sg_count; | |
417 | int i; | |
418 | ||
419 | sg_count = ((buf_len - 1) / MAX_DATA_BYTE_COUNT) + 1; | |
4a7cc0f2 | 420 | if (sg_count > AHCI_MAX_SG) { |
4782ac80 JZ |
421 | printf("Error:Too much sg!\n"); |
422 | return -1; | |
423 | } | |
424 | ||
4a7cc0f2 JL |
425 | for (i = 0; i < sg_count; i++) { |
426 | ahci_sg->addr = | |
427 | cpu_to_le32((u32) buf + i * MAX_DATA_BYTE_COUNT); | |
4782ac80 | 428 | ahci_sg->addr_hi = 0; |
4a7cc0f2 JL |
429 | ahci_sg->flags_size = cpu_to_le32(0x3fffff & |
430 | (buf_len < MAX_DATA_BYTE_COUNT | |
431 | ? (buf_len - 1) | |
432 | : (MAX_DATA_BYTE_COUNT - 1))); | |
4782ac80 JZ |
433 | ahci_sg++; |
434 | buf_len -= MAX_DATA_BYTE_COUNT; | |
435 | } | |
436 | ||
437 | return sg_count; | |
438 | } | |
439 | ||
440 | ||
441 | static void ahci_fill_cmd_slot(struct ahci_ioports *pp, u32 opts) | |
442 | { | |
443 | pp->cmd_slot->opts = cpu_to_le32(opts); | |
444 | pp->cmd_slot->status = 0; | |
445 | pp->cmd_slot->tbl_addr = cpu_to_le32(pp->cmd_tbl & 0xffffffff); | |
446 | pp->cmd_slot->tbl_addr_hi = 0; | |
447 | } | |
448 | ||
449 | ||
e81058c0 | 450 | #ifdef CONFIG_AHCI_SETFEATURES_XFER |
4782ac80 JZ |
451 | static void ahci_set_feature(u8 port) |
452 | { | |
4782ac80 | 453 | struct ahci_ioports *pp = &(probe_ent->port[port]); |
4a7cc0f2 JL |
454 | volatile u8 *port_mmio = (volatile u8 *)pp->port_mmio; |
455 | u32 cmd_fis_len = 5; /* five dwords */ | |
4782ac80 JZ |
456 | u8 fis[20]; |
457 | ||
4e422bce | 458 | /* set feature */ |
c8731115 | 459 | memset(fis, 0, sizeof(fis)); |
4782ac80 JZ |
460 | fis[0] = 0x27; |
461 | fis[1] = 1 << 7; | |
462 | fis[2] = ATA_CMD_SETF; | |
463 | fis[3] = SETFEATURES_XFER; | |
464 | fis[12] = __ilog2(probe_ent->udma_mask + 1) + 0x40 - 0x01; | |
465 | ||
c8731115 | 466 | memcpy((unsigned char *)pp->cmd_tbl, fis, sizeof(fis)); |
4782ac80 | 467 | ahci_fill_cmd_slot(pp, cmd_fis_len); |
90b276f6 | 468 | ahci_dcache_flush_sata_cmd(pp); |
4782ac80 JZ |
469 | writel(1, port_mmio + PORT_CMD_ISSUE); |
470 | readl(port_mmio + PORT_CMD_ISSUE); | |
471 | ||
57847660 WM |
472 | if (waiting_for_cmd_completed(port_mmio + PORT_CMD_ISSUE, |
473 | WAIT_MS_DATAIO, 0x1)) { | |
4e422bce | 474 | printf("set feature error on port %d!\n", port); |
4782ac80 JZ |
475 | } |
476 | } | |
e81058c0 | 477 | #endif |
4782ac80 JZ |
478 | |
479 | ||
480 | static int ahci_port_start(u8 port) | |
481 | { | |
4782ac80 | 482 | struct ahci_ioports *pp = &(probe_ent->port[port]); |
4a7cc0f2 | 483 | volatile u8 *port_mmio = (volatile u8 *)pp->port_mmio; |
4782ac80 JZ |
484 | u32 port_status; |
485 | u32 mem; | |
486 | ||
4a7cc0f2 | 487 | debug("Enter start port: %d\n", port); |
4782ac80 | 488 | port_status = readl(port_mmio + PORT_SCR_STAT); |
4a7cc0f2 JL |
489 | debug("Port %d status: %x\n", port, port_status); |
490 | if ((port_status & 0xf) != 0x03) { | |
4782ac80 JZ |
491 | printf("No Link on this port!\n"); |
492 | return -1; | |
493 | } | |
494 | ||
4a7cc0f2 | 495 | mem = (u32) malloc(AHCI_PORT_PRIV_DMA_SZ + 2048); |
4782ac80 JZ |
496 | if (!mem) { |
497 | free(pp); | |
498 | printf("No mem for table!\n"); | |
499 | return -ENOMEM; | |
500 | } | |
501 | ||
4a7cc0f2 JL |
502 | mem = (mem + 0x800) & (~0x7ff); /* Aligned to 2048-bytes */ |
503 | memset((u8 *) mem, 0, AHCI_PORT_PRIV_DMA_SZ); | |
4782ac80 | 504 | |
4782ac80 JZ |
505 | /* |
506 | * First item in chunk of DMA memory: 32-slot command table, | |
507 | * 32 bytes each in size | |
508 | */ | |
64738e8a TH |
509 | pp->cmd_slot = |
510 | (struct ahci_cmd_hdr *)(uintptr_t)virt_to_phys((void *)mem); | |
284231e4 | 511 | debug("cmd_slot = 0x%x\n", (unsigned)pp->cmd_slot); |
4782ac80 | 512 | mem += (AHCI_CMD_SLOT_SZ + 224); |
4a7cc0f2 | 513 | |
4782ac80 JZ |
514 | /* |
515 | * Second item: Received-FIS area | |
516 | */ | |
64738e8a | 517 | pp->rx_fis = virt_to_phys((void *)mem); |
4782ac80 | 518 | mem += AHCI_RX_FIS_SZ; |
4a7cc0f2 | 519 | |
4782ac80 JZ |
520 | /* |
521 | * Third item: data area for storing a single command | |
522 | * and its scatter-gather table | |
523 | */ | |
64738e8a | 524 | pp->cmd_tbl = virt_to_phys((void *)mem); |
4a7cc0f2 | 525 | debug("cmd_tbl_dma = 0x%x\n", pp->cmd_tbl); |
4782ac80 JZ |
526 | |
527 | mem += AHCI_CMD_TBL_HDR; | |
64738e8a TH |
528 | pp->cmd_tbl_sg = |
529 | (struct ahci_sg *)(uintptr_t)virt_to_phys((void *)mem); | |
4782ac80 | 530 | |
4a7cc0f2 | 531 | writel_with_flush((u32) pp->cmd_slot, port_mmio + PORT_LST_ADDR); |
4782ac80 JZ |
532 | |
533 | writel_with_flush(pp->rx_fis, port_mmio + PORT_FIS_ADDR); | |
534 | ||
535 | writel_with_flush(PORT_CMD_ICC_ACTIVE | PORT_CMD_FIS_RX | | |
4a7cc0f2 JL |
536 | PORT_CMD_POWER_ON | PORT_CMD_SPIN_UP | |
537 | PORT_CMD_START, port_mmio + PORT_CMD); | |
4782ac80 | 538 | |
4a7cc0f2 | 539 | debug("Exit start port %d\n", port); |
4782ac80 JZ |
540 | |
541 | return 0; | |
542 | } | |
543 | ||
544 | ||
b7a21b70 HTL |
545 | static int ahci_device_data_io(u8 port, u8 *fis, int fis_len, u8 *buf, |
546 | int buf_len, u8 is_write) | |
4782ac80 JZ |
547 | { |
548 | ||
4a7cc0f2 JL |
549 | struct ahci_ioports *pp = &(probe_ent->port[port]); |
550 | volatile u8 *port_mmio = (volatile u8 *)pp->port_mmio; | |
4782ac80 JZ |
551 | u32 opts; |
552 | u32 port_status; | |
553 | int sg_count; | |
554 | ||
b7a21b70 | 555 | debug("Enter %s: for port %d\n", __func__, port); |
4782ac80 | 556 | |
4a7cc0f2 | 557 | if (port > probe_ent->n_ports) { |
5a2b77f4 | 558 | printf("Invalid port number %d\n", port); |
4782ac80 JZ |
559 | return -1; |
560 | } | |
561 | ||
562 | port_status = readl(port_mmio + PORT_SCR_STAT); | |
4a7cc0f2 JL |
563 | if ((port_status & 0xf) != 0x03) { |
564 | debug("No Link on port %d!\n", port); | |
4782ac80 JZ |
565 | return -1; |
566 | } | |
567 | ||
568 | memcpy((unsigned char *)pp->cmd_tbl, fis, fis_len); | |
569 | ||
4a7cc0f2 | 570 | sg_count = ahci_fill_sg(port, buf, buf_len); |
b7a21b70 | 571 | opts = (fis_len >> 2) | (sg_count << 16) | (is_write << 6); |
4782ac80 JZ |
572 | ahci_fill_cmd_slot(pp, opts); |
573 | ||
90b276f6 TH |
574 | ahci_dcache_flush_sata_cmd(pp); |
575 | ahci_dcache_flush_range((unsigned)buf, (unsigned)buf_len); | |
576 | ||
4782ac80 JZ |
577 | writel_with_flush(1, port_mmio + PORT_CMD_ISSUE); |
578 | ||
57847660 WM |
579 | if (waiting_for_cmd_completed(port_mmio + PORT_CMD_ISSUE, |
580 | WAIT_MS_DATAIO, 0x1)) { | |
4782ac80 JZ |
581 | printf("timeout exit!\n"); |
582 | return -1; | |
583 | } | |
90b276f6 TH |
584 | |
585 | ahci_dcache_invalidate_range((unsigned)buf, (unsigned)buf_len); | |
b7a21b70 | 586 | debug("%s: %d byte transferred.\n", __func__, pp->cmd_slot->status); |
4782ac80 JZ |
587 | |
588 | return 0; | |
589 | } | |
590 | ||
591 | ||
592 | static char *ata_id_strcpy(u16 *target, u16 *src, int len) | |
593 | { | |
594 | int i; | |
4a7cc0f2 | 595 | for (i = 0; i < len / 2; i++) |
e5a6c79d | 596 | target[i] = swab16(src[i]); |
4782ac80 JZ |
597 | return (char *)target; |
598 | } | |
599 | ||
600 | ||
601 | static void dump_ataid(hd_driveid_t *ataid) | |
602 | { | |
603 | debug("(49)ataid->capability = 0x%x\n", ataid->capability); | |
604 | debug("(53)ataid->field_valid =0x%x\n", ataid->field_valid); | |
605 | debug("(63)ataid->dma_mword = 0x%x\n", ataid->dma_mword); | |
606 | debug("(64)ataid->eide_pio_modes = 0x%x\n", ataid->eide_pio_modes); | |
607 | debug("(75)ataid->queue_depth = 0x%x\n", ataid->queue_depth); | |
608 | debug("(80)ataid->major_rev_num = 0x%x\n", ataid->major_rev_num); | |
609 | debug("(81)ataid->minor_rev_num = 0x%x\n", ataid->minor_rev_num); | |
610 | debug("(82)ataid->command_set_1 = 0x%x\n", ataid->command_set_1); | |
611 | debug("(83)ataid->command_set_2 = 0x%x\n", ataid->command_set_2); | |
612 | debug("(84)ataid->cfsse = 0x%x\n", ataid->cfsse); | |
613 | debug("(85)ataid->cfs_enable_1 = 0x%x\n", ataid->cfs_enable_1); | |
614 | debug("(86)ataid->cfs_enable_2 = 0x%x\n", ataid->cfs_enable_2); | |
615 | debug("(87)ataid->csf_default = 0x%x\n", ataid->csf_default); | |
616 | debug("(88)ataid->dma_ultra = 0x%x\n", ataid->dma_ultra); | |
617 | debug("(93)ataid->hw_config = 0x%x\n", ataid->hw_config); | |
618 | } | |
619 | ||
4a7cc0f2 | 620 | |
4782ac80 JZ |
621 | /* |
622 | * SCSI INQUIRY command operation. | |
623 | */ | |
624 | static int ata_scsiop_inquiry(ccb *pccb) | |
625 | { | |
626 | u8 hdr[] = { | |
627 | 0, | |
628 | 0, | |
4a7cc0f2 | 629 | 0x5, /* claim SPC-3 version compatibility */ |
4782ac80 JZ |
630 | 2, |
631 | 95 - 4, | |
632 | }; | |
633 | u8 fis[20]; | |
634 | u8 *tmpid; | |
635 | u8 port; | |
636 | ||
637 | /* Clean ccb data buffer */ | |
638 | memset(pccb->pdata, 0, pccb->datalen); | |
639 | ||
640 | memcpy(pccb->pdata, hdr, sizeof(hdr)); | |
641 | ||
4a7cc0f2 | 642 | if (pccb->datalen <= 35) |
4782ac80 JZ |
643 | return 0; |
644 | ||
c8731115 | 645 | memset(fis, 0, sizeof(fis)); |
4782ac80 | 646 | /* Construct the FIS */ |
4a7cc0f2 JL |
647 | fis[0] = 0x27; /* Host to device FIS. */ |
648 | fis[1] = 1 << 7; /* Command FIS. */ | |
649 | fis[2] = ATA_CMD_IDENT; /* Command byte. */ | |
4782ac80 JZ |
650 | |
651 | /* Read id from sata */ | |
652 | port = pccb->target; | |
4a7cc0f2 | 653 | if (!(tmpid = malloc(sizeof(hd_driveid_t)))) |
4782ac80 JZ |
654 | return -ENOMEM; |
655 | ||
c8731115 | 656 | if (ahci_device_data_io(port, (u8 *) &fis, sizeof(fis), tmpid, |
b7a21b70 | 657 | sizeof(hd_driveid_t), 0)) { |
4782ac80 JZ |
658 | debug("scsi_ahci: SCSI inquiry command failure.\n"); |
659 | return -EIO; | |
660 | } | |
661 | ||
4a7cc0f2 | 662 | if (ataid[port]) |
4782ac80 | 663 | free(ataid[port]); |
4a7cc0f2 | 664 | ataid[port] = (hd_driveid_t *) tmpid; |
4782ac80 JZ |
665 | |
666 | memcpy(&pccb->pdata[8], "ATA ", 8); | |
4a7cc0f2 JL |
667 | ata_id_strcpy((u16 *) &pccb->pdata[16], (u16 *)ataid[port]->model, 16); |
668 | ata_id_strcpy((u16 *) &pccb->pdata[32], (u16 *)ataid[port]->fw_rev, 4); | |
4782ac80 JZ |
669 | |
670 | dump_ataid(ataid[port]); | |
671 | return 0; | |
672 | } | |
673 | ||
674 | ||
675 | /* | |
b7a21b70 | 676 | * SCSI READ10/WRITE10 command operation. |
4782ac80 | 677 | */ |
b7a21b70 | 678 | static int ata_scsiop_read_write(ccb *pccb, u8 is_write) |
4782ac80 | 679 | { |
284231e4 VB |
680 | u32 lba = 0; |
681 | u16 blocks = 0; | |
4782ac80 | 682 | u8 fis[20]; |
284231e4 VB |
683 | u8 *user_buffer = pccb->pdata; |
684 | u32 user_buffer_size = pccb->datalen; | |
4782ac80 | 685 | |
284231e4 VB |
686 | /* Retrieve the base LBA number from the ccb structure. */ |
687 | memcpy(&lba, pccb->cmd + 2, sizeof(lba)); | |
688 | lba = be32_to_cpu(lba); | |
4782ac80 | 689 | |
284231e4 VB |
690 | /* |
691 | * And the number of blocks. | |
692 | * | |
693 | * For 10-byte and 16-byte SCSI R/W commands, transfer | |
4782ac80 JZ |
694 | * length 0 means transfer 0 block of data. |
695 | * However, for ATA R/W commands, sector count 0 means | |
696 | * 256 or 65536 sectors, not 0 sectors as in SCSI. | |
697 | * | |
698 | * WARNING: one or two older ATA drives treat 0 as 0... | |
699 | */ | |
284231e4 VB |
700 | blocks = (((u16)pccb->cmd[7]) << 8) | ((u16) pccb->cmd[8]); |
701 | ||
b7a21b70 HTL |
702 | debug("scsi_ahci: %s %d blocks starting from lba 0x%x\n", |
703 | is_write ? "write" : "read", (unsigned)lba, blocks); | |
284231e4 VB |
704 | |
705 | /* Preset the FIS */ | |
c8731115 | 706 | memset(fis, 0, sizeof(fis)); |
284231e4 VB |
707 | fis[0] = 0x27; /* Host to device FIS. */ |
708 | fis[1] = 1 << 7; /* Command FIS. */ | |
b7a21b70 | 709 | /* Command byte (read/write). */ |
fe1f808c | 710 | fis[2] = is_write ? ATA_CMD_WRITE_EXT : ATA_CMD_READ_EXT; |
4782ac80 | 711 | |
284231e4 VB |
712 | while (blocks) { |
713 | u16 now_blocks; /* number of blocks per iteration */ | |
714 | u32 transfer_size; /* number of bytes per iteration */ | |
715 | ||
b7a21b70 | 716 | now_blocks = min(MAX_SATA_BLOCKS_READ_WRITE, blocks); |
284231e4 VB |
717 | |
718 | transfer_size = ATA_BLOCKSIZE * now_blocks; | |
719 | if (transfer_size > user_buffer_size) { | |
720 | printf("scsi_ahci: Error: buffer too small.\n"); | |
721 | return -EIO; | |
722 | } | |
723 | ||
fe1f808c WM |
724 | /* LBA48 SATA command but only use 32bit address range within |
725 | * that. The next smaller command range (28bit) is too small. | |
726 | */ | |
284231e4 VB |
727 | fis[4] = (lba >> 0) & 0xff; |
728 | fis[5] = (lba >> 8) & 0xff; | |
729 | fis[6] = (lba >> 16) & 0xff; | |
fe1f808c WM |
730 | fis[7] = 1 << 6; /* device reg: set LBA mode */ |
731 | fis[8] = ((lba >> 24) & 0xff); | |
732 | fis[3] = 0xe0; /* features */ | |
284231e4 VB |
733 | |
734 | /* Block (sector) count */ | |
735 | fis[12] = (now_blocks >> 0) & 0xff; | |
736 | fis[13] = (now_blocks >> 8) & 0xff; | |
737 | ||
b7a21b70 HTL |
738 | /* Read/Write from ahci */ |
739 | if (ahci_device_data_io(pccb->target, (u8 *) &fis, sizeof(fis), | |
740 | user_buffer, user_buffer_size, | |
741 | is_write)) { | |
742 | debug("scsi_ahci: SCSI %s10 command failure.\n", | |
743 | is_write ? "WRITE" : "READ"); | |
284231e4 VB |
744 | return -EIO; |
745 | } | |
766b16fe MJ |
746 | |
747 | /* If this transaction is a write, do a following flush. | |
748 | * Writes in u-boot are so rare, and the logic to know when is | |
749 | * the last write and do a flush only there is sufficiently | |
750 | * difficult. Just do a flush after every write. This incurs, | |
751 | * usually, one extra flush when the rare writes do happen. | |
752 | */ | |
753 | if (is_write) { | |
754 | if (-EIO == ata_io_flush(pccb->target)) | |
755 | return -EIO; | |
756 | } | |
284231e4 VB |
757 | user_buffer += transfer_size; |
758 | user_buffer_size -= transfer_size; | |
759 | blocks -= now_blocks; | |
760 | lba += now_blocks; | |
4782ac80 JZ |
761 | } |
762 | ||
763 | return 0; | |
764 | } | |
765 | ||
766 | ||
767 | /* | |
768 | * SCSI READ CAPACITY10 command operation. | |
769 | */ | |
770 | static int ata_scsiop_read_capacity10(ccb *pccb) | |
771 | { | |
cb6d0b72 | 772 | u32 cap; |
19d1d41e | 773 | u32 block_size; |
4782ac80 | 774 | |
4a7cc0f2 | 775 | if (!ataid[pccb->target]) { |
4782ac80 | 776 | printf("scsi_ahci: SCSI READ CAPACITY10 command failure. " |
4a7cc0f2 JL |
777 | "\tNo ATA info!\n" |
778 | "\tPlease run SCSI commmand INQUIRY firstly!\n"); | |
4782ac80 JZ |
779 | return -EPERM; |
780 | } | |
781 | ||
19d1d41e GB |
782 | cap = le32_to_cpu(ataid[pccb->target]->lba_capacity); |
783 | if (cap == 0xfffffff) { | |
784 | unsigned short *cap48 = ataid[pccb->target]->lba48_capacity; | |
785 | if (cap48[2] || cap48[3]) { | |
786 | cap = 0xffffffff; | |
787 | } else { | |
788 | cap = (le16_to_cpu(cap48[1]) << 16) | | |
789 | (le16_to_cpu(cap48[0])); | |
790 | } | |
791 | } | |
792 | ||
793 | cap = cpu_to_be32(cap); | |
cb6d0b72 | 794 | memcpy(pccb->pdata, &cap, sizeof(cap)); |
4782ac80 | 795 | |
19d1d41e GB |
796 | block_size = cpu_to_be32((u32)512); |
797 | memcpy(&pccb->pdata[4], &block_size, 4); | |
798 | ||
799 | return 0; | |
800 | } | |
801 | ||
802 | ||
803 | /* | |
804 | * SCSI READ CAPACITY16 command operation. | |
805 | */ | |
806 | static int ata_scsiop_read_capacity16(ccb *pccb) | |
807 | { | |
808 | u64 cap; | |
809 | u64 block_size; | |
810 | ||
811 | if (!ataid[pccb->target]) { | |
812 | printf("scsi_ahci: SCSI READ CAPACITY16 command failure. " | |
813 | "\tNo ATA info!\n" | |
814 | "\tPlease run SCSI commmand INQUIRY firstly!\n"); | |
815 | return -EPERM; | |
816 | } | |
817 | ||
818 | cap = le32_to_cpu(ataid[pccb->target]->lba_capacity); | |
819 | if (cap == 0xfffffff) { | |
820 | memcpy(&cap, ataid[pccb->target]->lba48_capacity, sizeof(cap)); | |
821 | cap = le64_to_cpu(cap); | |
822 | } | |
823 | ||
824 | cap = cpu_to_be64(cap); | |
825 | memcpy(pccb->pdata, &cap, sizeof(cap)); | |
826 | ||
827 | block_size = cpu_to_be64((u64)512); | |
828 | memcpy(&pccb->pdata[8], &block_size, 8); | |
4782ac80 JZ |
829 | |
830 | return 0; | |
831 | } | |
832 | ||
833 | ||
834 | /* | |
835 | * SCSI TEST UNIT READY command operation. | |
836 | */ | |
837 | static int ata_scsiop_test_unit_ready(ccb *pccb) | |
838 | { | |
839 | return (ataid[pccb->target]) ? 0 : -EPERM; | |
840 | } | |
841 | ||
4a7cc0f2 | 842 | |
4782ac80 JZ |
843 | int scsi_exec(ccb *pccb) |
844 | { | |
845 | int ret; | |
846 | ||
4a7cc0f2 | 847 | switch (pccb->cmd[0]) { |
4782ac80 | 848 | case SCSI_READ10: |
b7a21b70 HTL |
849 | ret = ata_scsiop_read_write(pccb, 0); |
850 | break; | |
851 | case SCSI_WRITE10: | |
852 | ret = ata_scsiop_read_write(pccb, 1); | |
4782ac80 | 853 | break; |
19d1d41e | 854 | case SCSI_RD_CAPAC10: |
4782ac80 JZ |
855 | ret = ata_scsiop_read_capacity10(pccb); |
856 | break; | |
19d1d41e GB |
857 | case SCSI_RD_CAPAC16: |
858 | ret = ata_scsiop_read_capacity16(pccb); | |
859 | break; | |
4782ac80 JZ |
860 | case SCSI_TST_U_RDY: |
861 | ret = ata_scsiop_test_unit_ready(pccb); | |
862 | break; | |
863 | case SCSI_INQUIRY: | |
864 | ret = ata_scsiop_inquiry(pccb); | |
865 | break; | |
866 | default: | |
867 | printf("Unsupport SCSI command 0x%02x\n", pccb->cmd[0]); | |
472d5460 | 868 | return false; |
4782ac80 JZ |
869 | } |
870 | ||
4a7cc0f2 JL |
871 | if (ret) { |
872 | debug("SCSI command 0x%02x ret errno %d\n", pccb->cmd[0], ret); | |
472d5460 | 873 | return false; |
4782ac80 | 874 | } |
472d5460 | 875 | return true; |
4782ac80 JZ |
876 | |
877 | } | |
878 | ||
879 | ||
880 | void scsi_low_level_init(int busdevfunc) | |
881 | { | |
882 | int i; | |
883 | u32 linkmap; | |
884 | ||
942e3143 | 885 | #ifndef CONFIG_SCSI_AHCI_PLAT |
4782ac80 | 886 | ahci_init_one(busdevfunc); |
942e3143 | 887 | #endif |
4782ac80 JZ |
888 | |
889 | linkmap = probe_ent->link_port_map; | |
890 | ||
6d0f6bcf | 891 | for (i = 0; i < CONFIG_SYS_SCSI_MAX_SCSI_ID; i++) { |
4a7cc0f2 JL |
892 | if (((linkmap >> i) & 0x01)) { |
893 | if (ahci_port_start((u8) i)) { | |
894 | printf("Can not start port %d\n", i); | |
4782ac80 JZ |
895 | continue; |
896 | } | |
e81058c0 | 897 | #ifdef CONFIG_AHCI_SETFEATURES_XFER |
4a7cc0f2 | 898 | ahci_set_feature((u8) i); |
e81058c0 | 899 | #endif |
4782ac80 JZ |
900 | } |
901 | } | |
902 | } | |
903 | ||
942e3143 RH |
904 | #ifdef CONFIG_SCSI_AHCI_PLAT |
905 | int ahci_init(u32 base) | |
906 | { | |
907 | int i, rc = 0; | |
908 | u32 linkmap; | |
909 | ||
910 | memset(ataid, 0, sizeof(ataid)); | |
911 | ||
912 | probe_ent = malloc(sizeof(struct ahci_probe_ent)); | |
913 | memset(probe_ent, 0, sizeof(struct ahci_probe_ent)); | |
914 | ||
915 | probe_ent->host_flags = ATA_FLAG_SATA | |
916 | | ATA_FLAG_NO_LEGACY | |
917 | | ATA_FLAG_MMIO | |
918 | | ATA_FLAG_PIO_DMA | |
919 | | ATA_FLAG_NO_ATAPI; | |
920 | probe_ent->pio_mask = 0x1f; | |
921 | probe_ent->udma_mask = 0x7f; /*Fixme,assume to support UDMA6 */ | |
922 | ||
923 | probe_ent->mmio_base = base; | |
924 | ||
925 | /* initialize adapter */ | |
926 | rc = ahci_host_init(probe_ent); | |
927 | if (rc) | |
928 | goto err_out; | |
929 | ||
930 | ahci_print_info(probe_ent); | |
931 | ||
932 | linkmap = probe_ent->link_port_map; | |
933 | ||
934 | for (i = 0; i < CONFIG_SYS_SCSI_MAX_SCSI_ID; i++) { | |
935 | if (((linkmap >> i) & 0x01)) { | |
936 | if (ahci_port_start((u8) i)) { | |
937 | printf("Can not start port %d\n", i); | |
938 | continue; | |
939 | } | |
e81058c0 | 940 | #ifdef CONFIG_AHCI_SETFEATURES_XFER |
942e3143 | 941 | ahci_set_feature((u8) i); |
e81058c0 | 942 | #endif |
942e3143 RH |
943 | } |
944 | } | |
945 | err_out: | |
946 | return rc; | |
947 | } | |
948 | #endif | |
4782ac80 | 949 | |
766b16fe MJ |
950 | /* |
951 | * In the general case of generic rotating media it makes sense to have a | |
952 | * flush capability. It probably even makes sense in the case of SSDs because | |
953 | * one cannot always know for sure what kind of internal cache/flush mechanism | |
954 | * is embodied therein. At first it was planned to invoke this after the last | |
955 | * write to disk and before rebooting. In practice, knowing, a priori, which | |
956 | * is the last write is difficult. Because writing to the disk in u-boot is | |
957 | * very rare, this flush command will be invoked after every block write. | |
958 | */ | |
959 | static int ata_io_flush(u8 port) | |
960 | { | |
961 | u8 fis[20]; | |
962 | struct ahci_ioports *pp = &(probe_ent->port[port]); | |
963 | volatile u8 *port_mmio = (volatile u8 *)pp->port_mmio; | |
964 | u32 cmd_fis_len = 5; /* five dwords */ | |
965 | ||
966 | /* Preset the FIS */ | |
967 | memset(fis, 0, 20); | |
968 | fis[0] = 0x27; /* Host to device FIS. */ | |
969 | fis[1] = 1 << 7; /* Command FIS. */ | |
fe1f808c | 970 | fis[2] = ATA_CMD_FLUSH_EXT; |
766b16fe MJ |
971 | |
972 | memcpy((unsigned char *)pp->cmd_tbl, fis, 20); | |
973 | ahci_fill_cmd_slot(pp, cmd_fis_len); | |
974 | writel_with_flush(1, port_mmio + PORT_CMD_ISSUE); | |
975 | ||
976 | if (waiting_for_cmd_completed(port_mmio + PORT_CMD_ISSUE, | |
977 | WAIT_MS_FLUSH, 0x1)) { | |
978 | debug("scsi_ahci: flush command timeout on port %d.\n", port); | |
979 | return -EIO; | |
980 | } | |
981 | ||
982 | return 0; | |
983 | } | |
984 | ||
985 | ||
4782ac80 JZ |
986 | void scsi_bus_reset(void) |
987 | { | |
4a7cc0f2 | 988 | /*Not implement*/ |
4782ac80 JZ |
989 | } |
990 | ||
991 | ||
4a7cc0f2 | 992 | void scsi_print_error(ccb * pccb) |
4782ac80 | 993 | { |
4a7cc0f2 | 994 | /*The ahci error info can be read in the ahci driver*/ |
4782ac80 | 995 | } |