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3f85ce27 WD |
1 | /* |
2 | * Copyright (c) 2004 Picture Elements, Inc. | |
3 | * Stephen Williams (XXXXXXXXXXXXXXXX) | |
4 | * | |
1a459660 | 5 | * SPDX-License-Identifier: GPL-2.0+ |
3f85ce27 | 6 | */ |
3f85ce27 WD |
7 | |
8 | /* | |
9 | * The Xilinx SystemACE chip support is activated by defining | |
6d0f6bcf | 10 | * CONFIG_SYSTEMACE to turn on support, and CONFIG_SYS_SYSTEMACE_BASE |
3f85ce27 WD |
11 | * to set the base address of the device. This code currently |
12 | * assumes that the chip is connected via a byte-wide bus. | |
13 | * | |
14 | * The CONFIG_SYSTEMACE also adds to fat support the device class | |
15 | * "ace" that allows the user to execute "fatls ace 0" and the | |
16 | * like. This works by making the systemace_get_dev function | |
17 | * available to cmd_fat.c:get_dev and filling in a block device | |
18 | * description that has all the bits needed for FAT support to | |
19 | * read sectors. | |
8f79e4c2 | 20 | * |
fe599e17 WD |
21 | * According to Xilinx technical support, before accessing the |
22 | * SystemACE CF you need to set the following control bits: | |
984618f3 GL |
23 | * FORCECFGMODE : 1 |
24 | * CFGMODE : 0 | |
25 | * CFGSTART : 0 | |
3f85ce27 WD |
26 | */ |
27 | ||
984618f3 GL |
28 | #include <common.h> |
29 | #include <command.h> | |
30 | #include <systemace.h> | |
31 | #include <part.h> | |
32 | #include <asm/io.h> | |
3f85ce27 | 33 | |
3f85ce27 WD |
34 | /* |
35 | * The ace_readw and writew functions read/write 16bit words, but the | |
36 | * offset value is the BYTE offset as most used in the Xilinx | |
6d0f6bcf | 37 | * datasheet for the SystemACE chip. The CONFIG_SYS_SYSTEMACE_BASE is defined |
3f85ce27 WD |
38 | * to be the base address for the chip, usually in the local |
39 | * peripheral bus. | |
40 | */ | |
5340a7f1 MS |
41 | |
42 | static u32 base = CONFIG_SYS_SYSTEMACE_BASE; | |
43 | static u32 width = CONFIG_SYS_SYSTEMACE_WIDTH; | |
44 | ||
45 | static void ace_writew(u16 val, unsigned off) | |
46 | { | |
47 | if (width == 8) { | |
a5bbcc3c | 48 | #if !defined(__BIG_ENDIAN) |
5340a7f1 MS |
49 | writeb(val >> 8, base + off); |
50 | writeb(val, base + off + 1); | |
a5bbcc3c | 51 | #else |
5340a7f1 MS |
52 | writeb(val, base + off); |
53 | writeb(val >> 8, base + off + 1); | |
a5bbcc3c | 54 | #endif |
7cde9f35 AB |
55 | } else |
56 | out16(base + off, val); | |
5340a7f1 MS |
57 | } |
58 | ||
59 | static u16 ace_readw(unsigned off) | |
60 | { | |
61 | if (width == 8) { | |
62 | #if !defined(__BIG_ENDIAN) | |
63 | return (readb(base + off) << 8) | readb(base + off + 1); | |
a5bbcc3c | 64 | #else |
5340a7f1 | 65 | return readb(base + off) | (readb(base + off + 1) << 8); |
a5bbcc3c | 66 | #endif |
5340a7f1 | 67 | } |
3f85ce27 | 68 | |
5340a7f1 MS |
69 | return in16(base + off); |
70 | } | |
3f85ce27 | 71 | |
4101f687 | 72 | static unsigned long systemace_read(struct blk_desc *block_dev, |
7c4213f6 SW |
73 | unsigned long start, lbaint_t blkcnt, |
74 | void *buffer); | |
3f85ce27 | 75 | |
4101f687 | 76 | static struct blk_desc systemace_dev = { 0 }; |
3f85ce27 WD |
77 | |
78 | static int get_cf_lock(void) | |
79 | { | |
984618f3 | 80 | int retry = 10; |
3f85ce27 WD |
81 | |
82 | /* CONTROLREG = LOCKREG */ | |
984618f3 GL |
83 | unsigned val = ace_readw(0x18); |
84 | val |= 0x0002; | |
85 | ace_writew((val & 0xffff), 0x18); | |
3f85ce27 WD |
86 | |
87 | /* Wait for MPULOCK in STATUSREG[15:0] */ | |
984618f3 | 88 | while (!(ace_readw(0x04) & 0x0002)) { |
3f85ce27 | 89 | |
984618f3 GL |
90 | if (retry < 0) |
91 | return -1; | |
3f85ce27 | 92 | |
984618f3 GL |
93 | udelay(100000); |
94 | retry -= 1; | |
95 | } | |
3f85ce27 | 96 | |
984618f3 | 97 | return 0; |
3f85ce27 WD |
98 | } |
99 | ||
100 | static void release_cf_lock(void) | |
101 | { | |
984618f3 GL |
102 | unsigned val = ace_readw(0x18); |
103 | val &= ~(0x0002); | |
104 | ace_writew((val & 0xffff), 0x18); | |
3f85ce27 WD |
105 | } |
106 | ||
df3fc526 | 107 | #ifdef CONFIG_PARTITIONS |
4101f687 | 108 | struct blk_desc *systemace_get_dev(int dev) |
3f85ce27 WD |
109 | { |
110 | /* The first time through this, the systemace_dev object is | |
111 | not yet initialized. In that case, fill it in. */ | |
984618f3 GL |
112 | if (systemace_dev.blksz == 0) { |
113 | systemace_dev.if_type = IF_TYPE_UNKNOWN; | |
114 | systemace_dev.dev = 0; | |
115 | systemace_dev.part_type = PART_TYPE_UNKNOWN; | |
116 | systemace_dev.type = DEV_TYPE_HARDDISK; | |
117 | systemace_dev.blksz = 512; | |
0472fbfd | 118 | systemace_dev.log2blksz = LOG2(systemace_dev.blksz); |
984618f3 GL |
119 | systemace_dev.removable = 1; |
120 | systemace_dev.block_read = systemace_read; | |
fe599e17 | 121 | |
d93e2212 | 122 | /* |
8274ec0b | 123 | * Ensure the correct bus mode (8/16 bits) gets enabled |
d93e2212 | 124 | */ |
5340a7f1 | 125 | ace_writew(width == 8 ? 0 : 0x0001, 0); |
d93e2212 | 126 | |
3e8bd469 | 127 | part_init(&systemace_dev); |
fe599e17 | 128 | |
984618f3 | 129 | } |
3f85ce27 | 130 | |
984618f3 | 131 | return &systemace_dev; |
3f85ce27 | 132 | } |
df3fc526 | 133 | #endif |
3f85ce27 WD |
134 | |
135 | /* | |
136 | * This function is called (by dereferencing the block_read pointer in | |
137 | * the dev_desc) to read blocks of data. The return value is the | |
138 | * number of blocks read. A zero return indicates an error. | |
139 | */ | |
4101f687 | 140 | static unsigned long systemace_read(struct blk_desc *block_dev, |
7c4213f6 SW |
141 | unsigned long start, lbaint_t blkcnt, |
142 | void *buffer) | |
3f85ce27 | 143 | { |
984618f3 GL |
144 | int retry; |
145 | unsigned blk_countdown; | |
eb867a76 | 146 | unsigned char *dp = buffer; |
984618f3 GL |
147 | unsigned val; |
148 | ||
149 | if (get_cf_lock() < 0) { | |
150 | unsigned status = ace_readw(0x04); | |
151 | ||
152 | /* If CFDETECT is false, card is missing. */ | |
153 | if (!(status & 0x0010)) { | |
154 | printf("** CompactFlash card not present. **\n"); | |
155 | return 0; | |
156 | } | |
157 | ||
158 | printf("**** ACE locked away from me (STATUSREG=%04x)\n", | |
159 | status); | |
160 | return 0; | |
161 | } | |
e7c85689 | 162 | #ifdef DEBUG_SYSTEMACE |
984618f3 | 163 | printf("... systemace read %lu sectors at %lu\n", blkcnt, start); |
e7c85689 WD |
164 | #endif |
165 | ||
984618f3 GL |
166 | retry = 2000; |
167 | for (;;) { | |
168 | val = ace_readw(0x04); | |
3f85ce27 | 169 | |
984618f3 GL |
170 | /* If CFDETECT is false, card is missing. */ |
171 | if (!(val & 0x0010)) { | |
172 | printf("**** ACE CompactFlash not found.\n"); | |
173 | release_cf_lock(); | |
174 | return 0; | |
175 | } | |
3f85ce27 | 176 | |
984618f3 GL |
177 | /* If RDYFORCMD, then we are ready to go. */ |
178 | if (val & 0x0100) | |
179 | break; | |
3f85ce27 | 180 | |
984618f3 GL |
181 | if (retry < 0) { |
182 | printf("**** SystemACE not ready.\n"); | |
183 | release_cf_lock(); | |
184 | return 0; | |
185 | } | |
3f85ce27 | 186 | |
984618f3 GL |
187 | udelay(1000); |
188 | retry -= 1; | |
189 | } | |
3f85ce27 | 190 | |
e7c85689 WD |
191 | /* The SystemACE can only transfer 256 sectors at a time, so |
192 | limit the current chunk of sectors. The blk_countdown | |
193 | variable is the number of sectors left to transfer. */ | |
3f85ce27 | 194 | |
984618f3 GL |
195 | blk_countdown = blkcnt; |
196 | while (blk_countdown > 0) { | |
197 | unsigned trans = blk_countdown; | |
3f85ce27 | 198 | |
984618f3 GL |
199 | if (trans > 256) |
200 | trans = 256; | |
3f85ce27 | 201 | |
e7c85689 | 202 | #ifdef DEBUG_SYSTEMACE |
984618f3 | 203 | printf("... transfer %lu sector in a chunk\n", trans); |
e7c85689 | 204 | #endif |
984618f3 GL |
205 | /* Write LBA block address */ |
206 | ace_writew((start >> 0) & 0xffff, 0x10); | |
d93e2212 | 207 | ace_writew((start >> 16) & 0x0fff, 0x12); |
984618f3 GL |
208 | |
209 | /* NOTE: in the Write Sector count below, a count of 0 | |
210 | causes a transfer of 256, so &0xff gives the right | |
211 | value for whatever transfer count we want. */ | |
212 | ||
213 | /* Write sector count | ReadMemCardData. */ | |
214 | ace_writew((trans & 0xff) | 0x0300, 0x14); | |
215 | ||
d62f64cc | 216 | /* |
32556443 MS |
217 | * For FPGA configuration via SystemACE is reset unacceptable |
218 | * CFGDONE bit in STATUSREG is not set to 1. | |
219 | */ | |
220 | #ifndef SYSTEMACE_CONFIG_FPGA | |
984618f3 GL |
221 | /* Reset the configruation controller */ |
222 | val = ace_readw(0x18); | |
223 | val |= 0x0080; | |
224 | ace_writew(val, 0x18); | |
32556443 | 225 | #endif |
984618f3 GL |
226 | |
227 | retry = trans * 16; | |
228 | while (retry > 0) { | |
229 | int idx; | |
230 | ||
231 | /* Wait for buffer to become ready. */ | |
232 | while (!(ace_readw(0x04) & 0x0020)) { | |
233 | udelay(100); | |
234 | } | |
235 | ||
236 | /* Read 16 words of 2bytes from the sector buffer. */ | |
237 | for (idx = 0; idx < 16; idx += 1) { | |
238 | unsigned short val = ace_readw(0x40); | |
239 | *dp++ = val & 0xff; | |
240 | *dp++ = (val >> 8) & 0xff; | |
241 | } | |
242 | ||
243 | retry -= 1; | |
244 | } | |
245 | ||
246 | /* Clear the configruation controller reset */ | |
247 | val = ace_readw(0x18); | |
248 | val &= ~0x0080; | |
249 | ace_writew(val, 0x18); | |
250 | ||
251 | /* Count the blocks we transfer this time. */ | |
252 | start += trans; | |
253 | blk_countdown -= trans; | |
254 | } | |
255 | ||
256 | release_cf_lock(); | |
257 | ||
258 | return blkcnt; | |
3f85ce27 | 259 | } |