projects / thirdparty / u-boot.git / blame
| Commit | Line | Data |
|---|---|---|
| 88ebf583 DN |
1 | // SPDX-License-Identifier: GPL-2.0 |
| 2 | /* | |
| 3 | * Copyright (C) 2019 Intel Corporation <www.intel.com> | |
| 4 | */ | |
| d678a59d | 5 | #include <common.h> |
| 88ebf583 DN |
6 | #include <command.h> |
| 7 | #include <dm.h> | |
| 8 | ||
| 9 | #include <asm/io.h> | |
| 10 | #include <asm/pl310.h> | |
| 11 | ||
| 12 | static void l2c310_of_parse_and_init(struct udevice *dev) | |
| 13 | { | |
| 14 | u32 tag[3] = { 0, 0, 0 }; | |
| 15 | u32 saved_reg, prefetch; | |
| a12a73b6 | 16 | struct pl310_regs *regs = dev_read_addr_ptr(dev); |
| 88ebf583 DN |
17 | |
| 18 | /* Disable the L2 Cache */ | |
| 19 | clrbits_le32(®s->pl310_ctrl, L2X0_CTRL_EN); | |
| 20 | ||
| 21 | saved_reg = readl(®s->pl310_aux_ctrl); | |
| 22 | if (!dev_read_u32(dev, "prefetch-data", &prefetch)) { | |
| 23 | if (prefetch) | |
| 24 | saved_reg |= L310_AUX_CTRL_DATA_PREFETCH_MASK; | |
| 25 | else | |
| 26 | saved_reg &= ~L310_AUX_CTRL_DATA_PREFETCH_MASK; | |
| 27 | } | |
| 28 | ||
| 29 | if (!dev_read_u32(dev, "prefetch-instr", &prefetch)) { | |
| 30 | if (prefetch) | |
| 31 | saved_reg |= L310_AUX_CTRL_INST_PREFETCH_MASK; | |
| 32 | else | |
| 33 | saved_reg &= ~L310_AUX_CTRL_INST_PREFETCH_MASK; | |
| 34 | } | |
| 35 | ||
| f62782fb LFT |
36 | if (dev_read_bool(dev, "arm,shared-override")) |
| 37 | saved_reg |= L310_SHARED_ATT_OVERRIDE_ENABLE; | |
| 88ebf583 | 38 | |
| 653f7c44 LFT |
39 | writel(saved_reg, ®s->pl310_aux_ctrl); |
| 40 | ||
| 88ebf583 DN |
41 | saved_reg = readl(®s->pl310_tag_latency_ctrl); |
| 42 | if (!dev_read_u32_array(dev, "arm,tag-latency", tag, 3)) | |
| 43 | saved_reg |= L310_LATENCY_CTRL_RD(tag[0] - 1) | | |
| 44 | L310_LATENCY_CTRL_WR(tag[1] - 1) | | |
| 45 | L310_LATENCY_CTRL_SETUP(tag[2] - 1); | |
| 46 | writel(saved_reg, ®s->pl310_tag_latency_ctrl); | |
| 47 | ||
| 48 | saved_reg = readl(®s->pl310_data_latency_ctrl); | |
| 49 | if (!dev_read_u32_array(dev, "arm,data-latency", tag, 3)) | |
| 50 | saved_reg |= L310_LATENCY_CTRL_RD(tag[0] - 1) | | |
| 51 | L310_LATENCY_CTRL_WR(tag[1] - 1) | | |
| 52 | L310_LATENCY_CTRL_SETUP(tag[2] - 1); | |
| 53 | writel(saved_reg, ®s->pl310_data_latency_ctrl); | |
| 54 | ||
| 55 | /* Enable the L2 cache */ | |
| 56 | setbits_le32(®s->pl310_ctrl, L2X0_CTRL_EN); | |
| 57 | } | |
| 58 | ||
| 59 | static int l2x0_probe(struct udevice *dev) | |
| 60 | { | |
| 61 | l2c310_of_parse_and_init(dev); | |
| 62 | ||
| 63 | return 0; | |
| 64 | } | |
| 65 | ||
| 66 | ||
| 67 | static const struct udevice_id l2x0_ids[] = { | |
| 68 | { .compatible = "arm,pl310-cache" }, | |
| 69 | {} | |
| 70 | }; | |
| 71 | ||
| 72 | U_BOOT_DRIVER(pl310_cache) = { | |
| 73 | .name = "pl310_cache", | |
| 74 | .id = UCLASS_CACHE, | |
| 75 | .of_match = l2x0_ids, | |
| 76 | .probe = l2x0_probe, | |
| 77 | .flags = DM_FLAG_PRE_RELOC, | |
| 78 | }; |