]>
Commit | Line | Data |
---|---|---|
5653fc33 | 1 | /* |
bf9e3b38 | 2 | * (C) Copyright 2002-2004 |
5653fc33 WD |
3 | * Brad Kemp, Seranoa Networks, Brad.Kemp@seranoa.com |
4 | * | |
5 | * Copyright (C) 2003 Arabella Software Ltd. | |
6 | * Yuli Barcohen <yuli@arabellasw.com> | |
7 | * Modified to work with AMD flashes | |
8 | * | |
bf9e3b38 WD |
9 | * Copyright (C) 2004 |
10 | * Ed Okerson | |
11 | * Modified to work with little-endian systems. | |
12 | * | |
5653fc33 WD |
13 | * See file CREDITS for list of people who contributed to this |
14 | * project. | |
15 | * | |
16 | * This program is free software; you can redistribute it and/or | |
17 | * modify it under the terms of the GNU General Public License as | |
18 | * published by the Free Software Foundation; either version 2 of | |
19 | * the License, or (at your option) any later version. | |
20 | * | |
21 | * This program is distributed in the hope that it will be useful, | |
22 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
23 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
24 | * GNU General Public License for more details. | |
25 | * | |
26 | * You should have received a copy of the GNU General Public License | |
27 | * along with this program; if not, write to the Free Software | |
28 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
29 | * MA 02111-1307 USA | |
30 | * | |
31 | * History | |
32 | * 01/20/2004 - combined variants of original driver. | |
bf9e3b38 WD |
33 | * 01/22/2004 - Write performance enhancements for parallel chips (Tolunay) |
34 | * 01/23/2004 - Support for x8/x16 chips (Rune Raknerud) | |
35 | * 01/27/2004 - Little endian support Ed Okerson | |
5653fc33 WD |
36 | * |
37 | * Tested Architectures | |
bf9e3b38 | 38 | * Port Width Chip Width # of banks Flash Chip Board |
2d1a537d WD |
39 | * 32 16 1 28F128J3 seranoa/eagle |
40 | * 64 16 1 28F128J3 seranoa/falcon | |
cd37d9e6 | 41 | * |
5653fc33 WD |
42 | */ |
43 | ||
44 | /* The DEBUG define must be before common to enable debugging */ | |
2d1a537d WD |
45 | /* #define DEBUG */ |
46 | ||
5653fc33 WD |
47 | #include <common.h> |
48 | #include <asm/processor.h> | |
4c0d4c3b | 49 | #include <asm/byteorder.h> |
2a8af187 | 50 | #include <environment.h> |
bf9e3b38 | 51 | #ifdef CFG_FLASH_CFI_DRIVER |
028ab6b5 | 52 | |
5653fc33 WD |
53 | /* |
54 | * This file implements a Common Flash Interface (CFI) driver for U-Boot. | |
55 | * The width of the port and the width of the chips are determined at initialization. | |
56 | * These widths are used to calculate the address for access CFI data structures. | |
57 | * It has been tested on an Intel Strataflash implementation and AMD 29F016D. | |
58 | * | |
59 | * References | |
60 | * JEDEC Standard JESD68 - Common Flash Interface (CFI) | |
61 | * JEDEC Standard JEP137-A Common Flash Interface (CFI) ID Codes | |
62 | * Intel Application Note 646 Common Flash Interface (CFI) and Command Sets | |
63 | * Intel 290667-008 3 Volt Intel StrataFlash Memory datasheet | |
64 | * | |
65 | * TODO | |
66 | * | |
67 | * Use Primary Extended Query table (PRI) and Alternate Algorithm Query | |
68 | * Table (ALT) to determine if protection is available | |
69 | * | |
70 | * Add support for other command sets Use the PRI and ALT to determine command set | |
71 | * Verify erase and program timeouts. | |
72 | */ | |
73 | ||
bf9e3b38 WD |
74 | #ifndef CFG_FLASH_BANKS_LIST |
75 | #define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE } | |
76 | #endif | |
77 | ||
5653fc33 WD |
78 | #define FLASH_CMD_CFI 0x98 |
79 | #define FLASH_CMD_READ_ID 0x90 | |
80 | #define FLASH_CMD_RESET 0xff | |
81 | #define FLASH_CMD_BLOCK_ERASE 0x20 | |
82 | #define FLASH_CMD_ERASE_CONFIRM 0xD0 | |
83 | #define FLASH_CMD_WRITE 0x40 | |
84 | #define FLASH_CMD_PROTECT 0x60 | |
85 | #define FLASH_CMD_PROTECT_SET 0x01 | |
86 | #define FLASH_CMD_PROTECT_CLEAR 0xD0 | |
87 | #define FLASH_CMD_CLEAR_STATUS 0x50 | |
bf9e3b38 WD |
88 | #define FLASH_CMD_WRITE_TO_BUFFER 0xE8 |
89 | #define FLASH_CMD_WRITE_BUFFER_CONFIRM 0xD0 | |
5653fc33 WD |
90 | |
91 | #define FLASH_STATUS_DONE 0x80 | |
92 | #define FLASH_STATUS_ESS 0x40 | |
93 | #define FLASH_STATUS_ECLBS 0x20 | |
94 | #define FLASH_STATUS_PSLBS 0x10 | |
95 | #define FLASH_STATUS_VPENS 0x08 | |
96 | #define FLASH_STATUS_PSS 0x04 | |
97 | #define FLASH_STATUS_DPS 0x02 | |
98 | #define FLASH_STATUS_R 0x01 | |
99 | #define FLASH_STATUS_PROTECT 0x01 | |
100 | ||
101 | #define AMD_CMD_RESET 0xF0 | |
102 | #define AMD_CMD_WRITE 0xA0 | |
103 | #define AMD_CMD_ERASE_START 0x80 | |
104 | #define AMD_CMD_ERASE_SECTOR 0x30 | |
855a496f WD |
105 | #define AMD_CMD_UNLOCK_START 0xAA |
106 | #define AMD_CMD_UNLOCK_ACK 0x55 | |
5653fc33 WD |
107 | |
108 | #define AMD_STATUS_TOGGLE 0x40 | |
109 | #define AMD_STATUS_ERROR 0x20 | |
855a496f WD |
110 | #define AMD_ADDR_ERASE_START 0x555 |
111 | #define AMD_ADDR_START 0x555 | |
112 | #define AMD_ADDR_ACK 0x2AA | |
5653fc33 WD |
113 | |
114 | #define FLASH_OFFSET_CFI 0x55 | |
115 | #define FLASH_OFFSET_CFI_RESP 0x10 | |
bf9e3b38 | 116 | #define FLASH_OFFSET_PRIMARY_VENDOR 0x13 |
5653fc33 | 117 | #define FLASH_OFFSET_WTOUT 0x1F |
bf9e3b38 | 118 | #define FLASH_OFFSET_WBTOUT 0x20 |
5653fc33 | 119 | #define FLASH_OFFSET_ETOUT 0x21 |
bf9e3b38 | 120 | #define FLASH_OFFSET_CETOUT 0x22 |
5653fc33 | 121 | #define FLASH_OFFSET_WMAX_TOUT 0x23 |
bf9e3b38 | 122 | #define FLASH_OFFSET_WBMAX_TOUT 0x24 |
5653fc33 | 123 | #define FLASH_OFFSET_EMAX_TOUT 0x25 |
bf9e3b38 | 124 | #define FLASH_OFFSET_CEMAX_TOUT 0x26 |
5653fc33 | 125 | #define FLASH_OFFSET_SIZE 0x27 |
bf9e3b38 WD |
126 | #define FLASH_OFFSET_INTERFACE 0x28 |
127 | #define FLASH_OFFSET_BUFFER_SIZE 0x2A | |
5653fc33 WD |
128 | #define FLASH_OFFSET_NUM_ERASE_REGIONS 0x2C |
129 | #define FLASH_OFFSET_ERASE_REGIONS 0x2D | |
130 | #define FLASH_OFFSET_PROTECT 0x02 | |
bf9e3b38 WD |
131 | #define FLASH_OFFSET_USER_PROTECTION 0x85 |
132 | #define FLASH_OFFSET_INTEL_PROTECTION 0x81 | |
5653fc33 WD |
133 | |
134 | ||
135 | #define FLASH_MAN_CFI 0x01000000 | |
136 | ||
bf9e3b38 | 137 | #define CFI_CMDSET_NONE 0 |
5653fc33 | 138 | #define CFI_CMDSET_INTEL_EXTENDED 1 |
bf9e3b38 | 139 | #define CFI_CMDSET_AMD_STANDARD 2 |
5653fc33 | 140 | #define CFI_CMDSET_INTEL_STANDARD 3 |
bf9e3b38 | 141 | #define CFI_CMDSET_AMD_EXTENDED 4 |
5653fc33 WD |
142 | #define CFI_CMDSET_MITSU_STANDARD 256 |
143 | #define CFI_CMDSET_MITSU_EXTENDED 257 | |
bf9e3b38 | 144 | #define CFI_CMDSET_SST 258 |
5653fc33 WD |
145 | |
146 | ||
f7d1572b WD |
147 | #ifdef CFG_FLASH_CFI_AMD_RESET /* needed for STM_ID_29W320DB on UC100 */ |
148 | # undef FLASH_CMD_RESET | |
149 | # define FLASH_CMD_RESET AMD_CMD_RESET /* use AMD-Reset instead */ | |
150 | #endif | |
151 | ||
152 | ||
5653fc33 WD |
153 | typedef union { |
154 | unsigned char c; | |
155 | unsigned short w; | |
156 | unsigned long l; | |
157 | unsigned long long ll; | |
158 | } cfiword_t; | |
159 | ||
160 | typedef union { | |
bf9e3b38 | 161 | volatile unsigned char *cp; |
5653fc33 | 162 | volatile unsigned short *wp; |
bf9e3b38 | 163 | volatile unsigned long *lp; |
5653fc33 WD |
164 | volatile unsigned long long *llp; |
165 | } cfiptr_t; | |
166 | ||
167 | #define NUM_ERASE_REGIONS 4 | |
168 | ||
169 | static ulong bank_base[CFG_MAX_FLASH_BANKS] = CFG_FLASH_BANKS_LIST; | |
170 | ||
bf9e3b38 | 171 | flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ |
5653fc33 WD |
172 | |
173 | /*----------------------------------------------------------------------- | |
174 | * Functions | |
175 | */ | |
176 | ||
177 | typedef unsigned long flash_sect_t; | |
178 | ||
bf9e3b38 WD |
179 | static void flash_add_byte (flash_info_t * info, cfiword_t * cword, uchar c); |
180 | static void flash_make_cmd (flash_info_t * info, uchar cmd, void *cmdbuf); | |
028ab6b5 | 181 | static void flash_write_cmd (flash_info_t * info, flash_sect_t sect, uint offset, uchar cmd); |
bf9e3b38 | 182 | static void flash_unlock_seq (flash_info_t * info, flash_sect_t sect); |
028ab6b5 WD |
183 | static int flash_isequal (flash_info_t * info, flash_sect_t sect, uint offset, uchar cmd); |
184 | static int flash_isset (flash_info_t * info, flash_sect_t sect, uint offset, uchar cmd); | |
185 | static int flash_toggle (flash_info_t * info, flash_sect_t sect, uint offset, uchar cmd); | |
bf9e3b38 | 186 | static int flash_detect_cfi (flash_info_t * info); |
5653fc33 | 187 | static ulong flash_get_size (ulong base, int banknum); |
028ab6b5 | 188 | static int flash_write_cfiword (flash_info_t * info, ulong dest, cfiword_t cword); |
bf9e3b38 WD |
189 | static int flash_full_status_check (flash_info_t * info, flash_sect_t sector, |
190 | ulong tout, char *prompt); | |
080bdb7f | 191 | #if defined(CFG_ENV_IS_IN_FLASH) || defined(CFG_ENV_ADDR_REDUND) || (CFG_MONITOR_BASE >= CFG_FLASH_BASE) |
7680c140 | 192 | static flash_info_t *flash_get_info(ulong base); |
080bdb7f | 193 | #endif |
5653fc33 | 194 | #ifdef CFG_FLASH_USE_BUFFER_WRITE |
028ab6b5 | 195 | static int flash_write_cfibuffer (flash_info_t * info, ulong dest, uchar * cp, int len); |
5653fc33 WD |
196 | #endif |
197 | ||
bf9e3b38 WD |
198 | /*----------------------------------------------------------------------- |
199 | * create an address based on the offset and the port width | |
200 | */ | |
028ab6b5 | 201 | inline uchar *flash_make_addr (flash_info_t * info, flash_sect_t sect, uint offset) |
bf9e3b38 WD |
202 | { |
203 | return ((uchar *) (info->start[sect] + (offset * info->portwidth))); | |
204 | } | |
205 | ||
5653fc33 | 206 | #ifdef DEBUG |
bf9e3b38 WD |
207 | /*----------------------------------------------------------------------- |
208 | * Debug support | |
209 | */ | |
210 | void print_longlong (char *str, unsigned long long data) | |
5653fc33 WD |
211 | { |
212 | int i; | |
213 | char *cp; | |
bf9e3b38 WD |
214 | |
215 | cp = (unsigned char *) &data; | |
216 | for (i = 0; i < 8; i++) | |
217 | sprintf (&str[i * 2], "%2.2x", *cp++); | |
218 | } | |
219 | static void flash_printqry (flash_info_t * info, flash_sect_t sect) | |
220 | { | |
221 | cfiptr_t cptr; | |
222 | int x, y; | |
223 | ||
47340a46 | 224 | for (x = 0; x < 0x40; x += 16U / info->portwidth) { |
bf9e3b38 WD |
225 | cptr.cp = |
226 | flash_make_addr (info, sect, | |
227 | x + FLASH_OFFSET_CFI_RESP); | |
228 | debug ("%p : ", cptr.cp); | |
229 | for (y = 0; y < 16; y++) { | |
230 | debug ("%2.2x ", cptr.cp[y]); | |
231 | } | |
232 | debug (" "); | |
233 | for (y = 0; y < 16; y++) { | |
234 | if (cptr.cp[y] >= 0x20 && cptr.cp[y] <= 0x7e) { | |
235 | debug ("%c", cptr.cp[y]); | |
236 | } else { | |
237 | debug ("."); | |
238 | } | |
239 | } | |
240 | debug ("\n"); | |
241 | } | |
5653fc33 WD |
242 | } |
243 | #endif | |
244 | ||
245 | ||
5653fc33 WD |
246 | /*----------------------------------------------------------------------- |
247 | * read a character at a port width address | |
248 | */ | |
bf9e3b38 | 249 | inline uchar flash_read_uchar (flash_info_t * info, uint offset) |
5653fc33 WD |
250 | { |
251 | uchar *cp; | |
bf9e3b38 WD |
252 | |
253 | cp = flash_make_addr (info, 0, offset); | |
254 | #if defined(__LITTLE_ENDIAN) | |
255 | return (cp[0]); | |
256 | #else | |
5653fc33 | 257 | return (cp[info->portwidth - 1]); |
bf9e3b38 | 258 | #endif |
5653fc33 WD |
259 | } |
260 | ||
261 | /*----------------------------------------------------------------------- | |
262 | * read a short word by swapping for ppc format. | |
263 | */ | |
bf9e3b38 | 264 | ushort flash_read_ushort (flash_info_t * info, flash_sect_t sect, uint offset) |
5653fc33 | 265 | { |
bf9e3b38 WD |
266 | uchar *addr; |
267 | ushort retval; | |
5653fc33 | 268 | |
bf9e3b38 WD |
269 | #ifdef DEBUG |
270 | int x; | |
271 | #endif | |
272 | addr = flash_make_addr (info, sect, offset); | |
5653fc33 | 273 | |
bf9e3b38 WD |
274 | #ifdef DEBUG |
275 | debug ("ushort addr is at %p info->portwidth = %d\n", addr, | |
276 | info->portwidth); | |
277 | for (x = 0; x < 2 * info->portwidth; x++) { | |
278 | debug ("addr[%x] = 0x%x\n", x, addr[x]); | |
279 | } | |
280 | #endif | |
281 | #if defined(__LITTLE_ENDIAN) | |
282 | retval = ((addr[(info->portwidth)] << 8) | addr[0]); | |
283 | #else | |
284 | retval = ((addr[(2 * info->portwidth) - 1] << 8) | | |
285 | addr[info->portwidth - 1]); | |
286 | #endif | |
287 | ||
288 | debug ("retval = 0x%x\n", retval); | |
289 | return retval; | |
5653fc33 WD |
290 | } |
291 | ||
292 | /*----------------------------------------------------------------------- | |
293 | * read a long word by picking the least significant byte of each maiximum | |
294 | * port size word. Swap for ppc format. | |
295 | */ | |
bf9e3b38 | 296 | ulong flash_read_long (flash_info_t * info, flash_sect_t sect, uint offset) |
5653fc33 | 297 | { |
bf9e3b38 WD |
298 | uchar *addr; |
299 | ulong retval; | |
300 | ||
301 | #ifdef DEBUG | |
302 | int x; | |
303 | #endif | |
304 | addr = flash_make_addr (info, sect, offset); | |
5653fc33 | 305 | |
bf9e3b38 WD |
306 | #ifdef DEBUG |
307 | debug ("long addr is at %p info->portwidth = %d\n", addr, | |
308 | info->portwidth); | |
309 | for (x = 0; x < 4 * info->portwidth; x++) { | |
310 | debug ("addr[%x] = 0x%x\n", x, addr[x]); | |
311 | } | |
312 | #endif | |
313 | #if defined(__LITTLE_ENDIAN) | |
314 | retval = (addr[0] << 16) | (addr[(info->portwidth)] << 24) | | |
028ab6b5 | 315 | (addr[(2 * info->portwidth)]) | (addr[(3 * info->portwidth)] << 8); |
bf9e3b38 WD |
316 | #else |
317 | retval = (addr[(2 * info->portwidth) - 1] << 24) | | |
318 | (addr[(info->portwidth) - 1] << 16) | | |
319 | (addr[(4 * info->portwidth) - 1] << 8) | | |
320 | addr[(3 * info->portwidth) - 1]; | |
321 | #endif | |
322 | return retval; | |
5653fc33 WD |
323 | } |
324 | ||
325 | /*----------------------------------------------------------------------- | |
326 | */ | |
327 | unsigned long flash_init (void) | |
328 | { | |
329 | unsigned long size = 0; | |
330 | int i; | |
331 | ||
332 | /* Init: no FLASHes known */ | |
bf9e3b38 | 333 | for (i = 0; i < CFG_MAX_FLASH_BANKS; ++i) { |
5653fc33 | 334 | flash_info[i].flash_id = FLASH_UNKNOWN; |
bf9e3b38 | 335 | size += flash_info[i].size = flash_get_size (bank_base[i], i); |
5653fc33 | 336 | if (flash_info[i].flash_id == FLASH_UNKNOWN) { |
028ab6b5 WD |
337 | printf ("## Unknown FLASH on Bank %d - Size = 0x%08lx = %ld MB\n", |
338 | i, flash_info[i].size, flash_info[i].size << 20); | |
5653fc33 WD |
339 | } |
340 | } | |
341 | ||
342 | /* Monitor protection ON by default */ | |
343 | #if (CFG_MONITOR_BASE >= CFG_FLASH_BASE) | |
bf9e3b38 WD |
344 | flash_protect (FLAG_PROTECT_SET, |
345 | CFG_MONITOR_BASE, | |
7680c140 WD |
346 | CFG_MONITOR_BASE + monitor_flash_len - 1, |
347 | flash_get_info(CFG_MONITOR_BASE)); | |
5653fc33 WD |
348 | #endif |
349 | ||
656658dd WD |
350 | /* Environment protection ON by default */ |
351 | #ifdef CFG_ENV_IS_IN_FLASH | |
352 | flash_protect (FLAG_PROTECT_SET, | |
353 | CFG_ENV_ADDR, | |
354 | CFG_ENV_ADDR + CFG_ENV_SECT_SIZE - 1, | |
7680c140 | 355 | flash_get_info(CFG_ENV_ADDR)); |
656658dd WD |
356 | #endif |
357 | ||
358 | /* Redundant environment protection ON by default */ | |
359 | #ifdef CFG_ENV_ADDR_REDUND | |
360 | flash_protect (FLAG_PROTECT_SET, | |
361 | CFG_ENV_ADDR_REDUND, | |
362 | CFG_ENV_ADDR_REDUND + CFG_ENV_SIZE_REDUND - 1, | |
7680c140 | 363 | flash_get_info(CFG_ENV_ADDR_REDUND)); |
656658dd | 364 | #endif |
5653fc33 WD |
365 | return (size); |
366 | } | |
367 | ||
7680c140 WD |
368 | /*----------------------------------------------------------------------- |
369 | */ | |
080bdb7f | 370 | #if defined(CFG_ENV_IS_IN_FLASH) || defined(CFG_ENV_ADDR_REDUND) || (CFG_MONITOR_BASE >= CFG_FLASH_BASE) |
7680c140 WD |
371 | static flash_info_t *flash_get_info(ulong base) |
372 | { | |
373 | int i; | |
374 | flash_info_t * info; | |
375 | ||
376 | for (i = 0; i < CFG_MAX_FLASH_BANKS; i ++) { | |
377 | info = & flash_info[i]; | |
378 | if (info->size && info->start[0] <= base && | |
379 | base <= info->start[0] + info->size - 1) | |
380 | break; | |
381 | } | |
382 | ||
383 | return i == CFG_MAX_FLASH_BANKS ? 0 : info; | |
384 | } | |
080bdb7f | 385 | #endif |
7680c140 | 386 | |
5653fc33 WD |
387 | /*----------------------------------------------------------------------- |
388 | */ | |
bf9e3b38 | 389 | int flash_erase (flash_info_t * info, int s_first, int s_last) |
5653fc33 WD |
390 | { |
391 | int rcode = 0; | |
392 | int prot; | |
393 | flash_sect_t sect; | |
394 | ||
bf9e3b38 | 395 | if (info->flash_id != FLASH_MAN_CFI) { |
4b9206ed | 396 | puts ("Can't erase unknown flash type - aborted\n"); |
5653fc33 WD |
397 | return 1; |
398 | } | |
399 | if ((s_first < 0) || (s_first > s_last)) { | |
4b9206ed | 400 | puts ("- no sectors to erase\n"); |
5653fc33 WD |
401 | return 1; |
402 | } | |
403 | ||
404 | prot = 0; | |
bf9e3b38 | 405 | for (sect = s_first; sect <= s_last; ++sect) { |
5653fc33 WD |
406 | if (info->protect[sect]) { |
407 | prot++; | |
408 | } | |
409 | } | |
410 | if (prot) { | |
bf9e3b38 | 411 | printf ("- Warning: %d protected sectors will not be erased!\n", prot); |
5653fc33 | 412 | } else { |
4b9206ed | 413 | putc ('\n'); |
5653fc33 WD |
414 | } |
415 | ||
416 | ||
bf9e3b38 | 417 | for (sect = s_first; sect <= s_last; sect++) { |
5653fc33 | 418 | if (info->protect[sect] == 0) { /* not protected */ |
bf9e3b38 | 419 | switch (info->vendor) { |
5653fc33 WD |
420 | case CFI_CMDSET_INTEL_STANDARD: |
421 | case CFI_CMDSET_INTEL_EXTENDED: | |
028ab6b5 WD |
422 | flash_write_cmd (info, sect, 0, FLASH_CMD_CLEAR_STATUS); |
423 | flash_write_cmd (info, sect, 0, FLASH_CMD_BLOCK_ERASE); | |
424 | flash_write_cmd (info, sect, 0, FLASH_CMD_ERASE_CONFIRM); | |
5653fc33 WD |
425 | break; |
426 | case CFI_CMDSET_AMD_STANDARD: | |
427 | case CFI_CMDSET_AMD_EXTENDED: | |
bf9e3b38 | 428 | flash_unlock_seq (info, sect); |
855a496f WD |
429 | flash_write_cmd (info, sect, AMD_ADDR_ERASE_START, |
430 | AMD_CMD_ERASE_START); | |
bf9e3b38 | 431 | flash_unlock_seq (info, sect); |
028ab6b5 | 432 | flash_write_cmd (info, sect, 0, AMD_CMD_ERASE_SECTOR); |
5653fc33 WD |
433 | break; |
434 | default: | |
bf9e3b38 WD |
435 | debug ("Unkown flash vendor %d\n", |
436 | info->vendor); | |
5653fc33 WD |
437 | break; |
438 | } | |
439 | ||
bf9e3b38 WD |
440 | if (flash_full_status_check |
441 | (info, sect, info->erase_blk_tout, "erase")) { | |
5653fc33 WD |
442 | rcode = 1; |
443 | } else | |
4b9206ed | 444 | putc ('.'); |
5653fc33 WD |
445 | } |
446 | } | |
4b9206ed | 447 | puts (" done\n"); |
5653fc33 WD |
448 | return rcode; |
449 | } | |
450 | ||
451 | /*----------------------------------------------------------------------- | |
452 | */ | |
bf9e3b38 | 453 | void flash_print_info (flash_info_t * info) |
5653fc33 WD |
454 | { |
455 | int i; | |
456 | ||
457 | if (info->flash_id != FLASH_MAN_CFI) { | |
4b9206ed | 458 | puts ("missing or unknown FLASH type\n"); |
5653fc33 WD |
459 | return; |
460 | } | |
461 | ||
bf9e3b38 WD |
462 | printf ("CFI conformant FLASH (%d x %d)", |
463 | (info->portwidth << 3), (info->chipwidth << 3)); | |
5653fc33 WD |
464 | printf (" Size: %ld MB in %d Sectors\n", |
465 | info->size >> 20, info->sector_count); | |
028ab6b5 WD |
466 | printf (" Erase timeout %ld ms, write timeout %ld ms, buffer write timeout %ld ms, buffer size %d\n", |
467 | info->erase_blk_tout, | |
468 | info->write_tout, | |
469 | info->buffer_write_tout, | |
470 | info->buffer_size); | |
5653fc33 | 471 | |
4b9206ed | 472 | puts (" Sector Start Addresses:"); |
bf9e3b38 | 473 | for (i = 0; i < info->sector_count; ++i) { |
5653fc33 WD |
474 | #ifdef CFG_FLASH_EMPTY_INFO |
475 | int k; | |
476 | int size; | |
477 | int erased; | |
478 | volatile unsigned long *flash; | |
479 | ||
480 | /* | |
481 | * Check if whole sector is erased | |
482 | */ | |
bf9e3b38 WD |
483 | if (i != (info->sector_count - 1)) |
484 | size = info->start[i + 1] - info->start[i]; | |
5653fc33 | 485 | else |
bf9e3b38 | 486 | size = info->start[0] + info->size - info->start[i]; |
5653fc33 | 487 | erased = 1; |
bf9e3b38 WD |
488 | flash = (volatile unsigned long *) info->start[i]; |
489 | size = size >> 2; /* divide by 4 for longword access */ | |
490 | for (k = 0; k < size; k++) { | |
491 | if (*flash++ != 0xffffffff) { | |
492 | erased = 0; | |
493 | break; | |
494 | } | |
495 | } | |
5653fc33 WD |
496 | |
497 | if ((i % 5) == 0) | |
498 | printf ("\n"); | |
499 | /* print empty and read-only info */ | |
500 | printf (" %08lX%s%s", | |
501 | info->start[i], | |
502 | erased ? " E" : " ", | |
503 | info->protect[i] ? "RO " : " "); | |
b63de2c0 | 504 | #else /* ! CFG_FLASH_EMPTY_INFO */ |
5653fc33 WD |
505 | if ((i % 5) == 0) |
506 | printf ("\n "); | |
507 | printf (" %08lX%s", | |
b63de2c0 | 508 | info->start[i], info->protect[i] ? " (RO)" : " "); |
5653fc33 WD |
509 | #endif |
510 | } | |
4b9206ed | 511 | putc ('\n'); |
5653fc33 WD |
512 | return; |
513 | } | |
514 | ||
515 | /*----------------------------------------------------------------------- | |
516 | * Copy memory to flash, returns: | |
517 | * 0 - OK | |
518 | * 1 - write timeout | |
519 | * 2 - Flash not erased | |
520 | */ | |
bf9e3b38 | 521 | int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt) |
5653fc33 WD |
522 | { |
523 | ulong wp; | |
524 | ulong cp; | |
525 | int aln; | |
526 | cfiword_t cword; | |
527 | int i, rc; | |
528 | ||
bf9e3b38 WD |
529 | #ifdef CFG_FLASH_USE_BUFFER_WRITE |
530 | int buffered_size; | |
531 | #endif | |
bf9e3b38 | 532 | /* get lower aligned address */ |
5653fc33 WD |
533 | /* get lower aligned address */ |
534 | wp = (addr & ~(info->portwidth - 1)); | |
535 | ||
536 | /* handle unaligned start */ | |
bf9e3b38 | 537 | if ((aln = addr - wp) != 0) { |
5653fc33 WD |
538 | cword.l = 0; |
539 | cp = wp; | |
bf9e3b38 WD |
540 | for (i = 0; i < aln; ++i, ++cp) |
541 | flash_add_byte (info, &cword, (*(uchar *) cp)); | |
5653fc33 | 542 | |
bf9e3b38 WD |
543 | for (; (i < info->portwidth) && (cnt > 0); i++) { |
544 | flash_add_byte (info, &cword, *src++); | |
5653fc33 WD |
545 | cnt--; |
546 | cp++; | |
547 | } | |
bf9e3b38 WD |
548 | for (; (cnt == 0) && (i < info->portwidth); ++i, ++cp) |
549 | flash_add_byte (info, &cword, (*(uchar *) cp)); | |
550 | if ((rc = flash_write_cfiword (info, wp, cword)) != 0) | |
5653fc33 WD |
551 | return rc; |
552 | wp = cp; | |
553 | } | |
554 | ||
bf9e3b38 | 555 | /* handle the aligned part */ |
5653fc33 | 556 | #ifdef CFG_FLASH_USE_BUFFER_WRITE |
bf9e3b38 WD |
557 | buffered_size = (info->portwidth / info->chipwidth); |
558 | buffered_size *= info->buffer_size; | |
559 | while (cnt >= info->portwidth) { | |
560 | i = buffered_size > cnt ? cnt : buffered_size; | |
561 | if ((rc = flash_write_cfibuffer (info, wp, src, i)) != ERR_OK) | |
5653fc33 | 562 | return rc; |
8d4ba3da | 563 | i -= i & (info->portwidth - 1); |
5653fc33 WD |
564 | wp += i; |
565 | src += i; | |
bf9e3b38 | 566 | cnt -= i; |
5653fc33 WD |
567 | } |
568 | #else | |
bf9e3b38 | 569 | while (cnt >= info->portwidth) { |
5653fc33 | 570 | cword.l = 0; |
bf9e3b38 WD |
571 | for (i = 0; i < info->portwidth; i++) { |
572 | flash_add_byte (info, &cword, *src++); | |
5653fc33 | 573 | } |
bf9e3b38 | 574 | if ((rc = flash_write_cfiword (info, wp, cword)) != 0) |
5653fc33 WD |
575 | return rc; |
576 | wp += info->portwidth; | |
577 | cnt -= info->portwidth; | |
578 | } | |
579 | #endif /* CFG_FLASH_USE_BUFFER_WRITE */ | |
580 | if (cnt == 0) { | |
581 | return (0); | |
582 | } | |
583 | ||
584 | /* | |
585 | * handle unaligned tail bytes | |
586 | */ | |
587 | cword.l = 0; | |
bf9e3b38 WD |
588 | for (i = 0, cp = wp; (i < info->portwidth) && (cnt > 0); ++i, ++cp) { |
589 | flash_add_byte (info, &cword, *src++); | |
5653fc33 WD |
590 | --cnt; |
591 | } | |
bf9e3b38 WD |
592 | for (; i < info->portwidth; ++i, ++cp) { |
593 | flash_add_byte (info, &cword, (*(uchar *) cp)); | |
5653fc33 WD |
594 | } |
595 | ||
bf9e3b38 | 596 | return flash_write_cfiword (info, wp, cword); |
5653fc33 WD |
597 | } |
598 | ||
599 | /*----------------------------------------------------------------------- | |
600 | */ | |
601 | #ifdef CFG_FLASH_PROTECTION | |
602 | ||
bf9e3b38 | 603 | int flash_real_protect (flash_info_t * info, long sector, int prot) |
5653fc33 WD |
604 | { |
605 | int retcode = 0; | |
606 | ||
bf9e3b38 WD |
607 | flash_write_cmd (info, sector, 0, FLASH_CMD_CLEAR_STATUS); |
608 | flash_write_cmd (info, sector, 0, FLASH_CMD_PROTECT); | |
609 | if (prot) | |
610 | flash_write_cmd (info, sector, 0, FLASH_CMD_PROTECT_SET); | |
5653fc33 | 611 | else |
bf9e3b38 | 612 | flash_write_cmd (info, sector, 0, FLASH_CMD_PROTECT_CLEAR); |
5653fc33 | 613 | |
bf9e3b38 WD |
614 | if ((retcode = |
615 | flash_full_status_check (info, sector, info->erase_blk_tout, | |
616 | prot ? "protect" : "unprotect")) == 0) { | |
5653fc33 WD |
617 | |
618 | info->protect[sector] = prot; | |
619 | /* Intel's unprotect unprotects all locking */ | |
bf9e3b38 | 620 | if (prot == 0) { |
5653fc33 | 621 | flash_sect_t i; |
bf9e3b38 WD |
622 | |
623 | for (i = 0; i < info->sector_count; i++) { | |
624 | if (info->protect[i]) | |
625 | flash_real_protect (info, i, 1); | |
5653fc33 WD |
626 | } |
627 | } | |
628 | } | |
5653fc33 | 629 | return retcode; |
bf9e3b38 WD |
630 | } |
631 | ||
5653fc33 WD |
632 | /*----------------------------------------------------------------------- |
633 | * flash_read_user_serial - read the OneTimeProgramming cells | |
634 | */ | |
bf9e3b38 WD |
635 | void flash_read_user_serial (flash_info_t * info, void *buffer, int offset, |
636 | int len) | |
5653fc33 | 637 | { |
bf9e3b38 WD |
638 | uchar *src; |
639 | uchar *dst; | |
5653fc33 WD |
640 | |
641 | dst = buffer; | |
bf9e3b38 WD |
642 | src = flash_make_addr (info, 0, FLASH_OFFSET_USER_PROTECTION); |
643 | flash_write_cmd (info, 0, 0, FLASH_CMD_READ_ID); | |
644 | memcpy (dst, src + offset, len); | |
db421e64 | 645 | flash_write_cmd (info, 0, 0, info->cmd_reset); |
5653fc33 | 646 | } |
bf9e3b38 | 647 | |
5653fc33 WD |
648 | /* |
649 | * flash_read_factory_serial - read the device Id from the protection area | |
650 | */ | |
bf9e3b38 WD |
651 | void flash_read_factory_serial (flash_info_t * info, void *buffer, int offset, |
652 | int len) | |
5653fc33 | 653 | { |
bf9e3b38 | 654 | uchar *src; |
cd37d9e6 | 655 | |
bf9e3b38 WD |
656 | src = flash_make_addr (info, 0, FLASH_OFFSET_INTEL_PROTECTION); |
657 | flash_write_cmd (info, 0, 0, FLASH_CMD_READ_ID); | |
658 | memcpy (buffer, src + offset, len); | |
db421e64 | 659 | flash_write_cmd (info, 0, 0, info->cmd_reset); |
5653fc33 WD |
660 | } |
661 | ||
662 | #endif /* CFG_FLASH_PROTECTION */ | |
663 | ||
bf9e3b38 WD |
664 | /* |
665 | * flash_is_busy - check to see if the flash is busy | |
666 | * This routine checks the status of the chip and returns true if the chip is busy | |
667 | */ | |
668 | static int flash_is_busy (flash_info_t * info, flash_sect_t sect) | |
5653fc33 WD |
669 | { |
670 | int retval; | |
bf9e3b38 WD |
671 | |
672 | switch (info->vendor) { | |
5653fc33 WD |
673 | case CFI_CMDSET_INTEL_STANDARD: |
674 | case CFI_CMDSET_INTEL_EXTENDED: | |
bf9e3b38 | 675 | retval = !flash_isset (info, sect, 0, FLASH_STATUS_DONE); |
5653fc33 WD |
676 | break; |
677 | case CFI_CMDSET_AMD_STANDARD: | |
678 | case CFI_CMDSET_AMD_EXTENDED: | |
bf9e3b38 | 679 | retval = flash_toggle (info, sect, 0, AMD_STATUS_TOGGLE); |
5653fc33 WD |
680 | break; |
681 | default: | |
682 | retval = 0; | |
683 | } | |
bf9e3b38 | 684 | debug ("flash_is_busy: %d\n", retval); |
5653fc33 WD |
685 | return retval; |
686 | } | |
bf9e3b38 | 687 | |
5653fc33 WD |
688 | /*----------------------------------------------------------------------- |
689 | * wait for XSR.7 to be set. Time out with an error if it does not. | |
690 | * This routine does not set the flash to read-array mode. | |
691 | */ | |
bf9e3b38 WD |
692 | static int flash_status_check (flash_info_t * info, flash_sect_t sector, |
693 | ulong tout, char *prompt) | |
5653fc33 WD |
694 | { |
695 | ulong start; | |
696 | ||
697 | /* Wait for command completion */ | |
698 | start = get_timer (0); | |
bf9e3b38 WD |
699 | while (flash_is_busy (info, sector)) { |
700 | if (get_timer (start) > info->erase_blk_tout * CFG_HZ) { | |
701 | printf ("Flash %s timeout at address %lx data %lx\n", | |
702 | prompt, info->start[sector], | |
703 | flash_read_long (info, sector, 0)); | |
704 | flash_write_cmd (info, sector, 0, info->cmd_reset); | |
5653fc33 WD |
705 | return ERR_TIMOUT; |
706 | } | |
707 | } | |
708 | return ERR_OK; | |
709 | } | |
bf9e3b38 | 710 | |
5653fc33 WD |
711 | /*----------------------------------------------------------------------- |
712 | * Wait for XSR.7 to be set, if it times out print an error, otherwise do a full status check. | |
713 | * This routine sets the flash to read-array mode. | |
714 | */ | |
bf9e3b38 WD |
715 | static int flash_full_status_check (flash_info_t * info, flash_sect_t sector, |
716 | ulong tout, char *prompt) | |
5653fc33 WD |
717 | { |
718 | int retcode; | |
bf9e3b38 WD |
719 | |
720 | retcode = flash_status_check (info, sector, tout, prompt); | |
721 | switch (info->vendor) { | |
5653fc33 WD |
722 | case CFI_CMDSET_INTEL_EXTENDED: |
723 | case CFI_CMDSET_INTEL_STANDARD: | |
bf9e3b38 WD |
724 | if ((retcode != ERR_OK) |
725 | && !flash_isequal (info, sector, 0, FLASH_STATUS_DONE)) { | |
5653fc33 | 726 | retcode = ERR_INVAL; |
bf9e3b38 WD |
727 | printf ("Flash %s error at address %lx\n", prompt, |
728 | info->start[sector]); | |
028ab6b5 | 729 | if (flash_isset (info, sector, 0, FLASH_STATUS_ECLBS | FLASH_STATUS_PSLBS)) { |
4b9206ed | 730 | puts ("Command Sequence Error.\n"); |
028ab6b5 | 731 | } else if (flash_isset (info, sector, 0, FLASH_STATUS_ECLBS)) { |
4b9206ed | 732 | puts ("Block Erase Error.\n"); |
5653fc33 | 733 | retcode = ERR_NOT_ERASED; |
028ab6b5 | 734 | } else if (flash_isset (info, sector, 0, FLASH_STATUS_PSLBS)) { |
4b9206ed | 735 | puts ("Locking Error\n"); |
5653fc33 | 736 | } |
bf9e3b38 | 737 | if (flash_isset (info, sector, 0, FLASH_STATUS_DPS)) { |
4b9206ed | 738 | puts ("Block locked.\n"); |
bf9e3b38 WD |
739 | retcode = ERR_PROTECTED; |
740 | } | |
741 | if (flash_isset (info, sector, 0, FLASH_STATUS_VPENS)) | |
4b9206ed | 742 | puts ("Vpp Low Error.\n"); |
5653fc33 | 743 | } |
db421e64 | 744 | flash_write_cmd (info, sector, 0, info->cmd_reset); |
5653fc33 WD |
745 | break; |
746 | default: | |
747 | break; | |
748 | } | |
749 | return retcode; | |
750 | } | |
bf9e3b38 | 751 | |
5653fc33 WD |
752 | /*----------------------------------------------------------------------- |
753 | */ | |
bf9e3b38 | 754 | static void flash_add_byte (flash_info_t * info, cfiword_t * cword, uchar c) |
5653fc33 | 755 | { |
4d13cbad WD |
756 | #if defined(__LITTLE_ENDIAN) |
757 | unsigned short w; | |
758 | unsigned int l; | |
759 | unsigned long long ll; | |
760 | #endif | |
761 | ||
bf9e3b38 | 762 | switch (info->portwidth) { |
5653fc33 WD |
763 | case FLASH_CFI_8BIT: |
764 | cword->c = c; | |
765 | break; | |
766 | case FLASH_CFI_16BIT: | |
4d13cbad WD |
767 | #if defined(__LITTLE_ENDIAN) |
768 | w = c; | |
769 | w <<= 8; | |
770 | cword->w = (cword->w >> 8) | w; | |
771 | #else | |
5653fc33 | 772 | cword->w = (cword->w << 8) | c; |
4d13cbad | 773 | #endif |
5653fc33 WD |
774 | break; |
775 | case FLASH_CFI_32BIT: | |
4d13cbad WD |
776 | #if defined(__LITTLE_ENDIAN) |
777 | l = c; | |
778 | l <<= 24; | |
779 | cword->l = (cword->l >> 8) | l; | |
780 | #else | |
5653fc33 | 781 | cword->l = (cword->l << 8) | c; |
4d13cbad | 782 | #endif |
5653fc33 WD |
783 | break; |
784 | case FLASH_CFI_64BIT: | |
4d13cbad WD |
785 | #if defined(__LITTLE_ENDIAN) |
786 | ll = c; | |
787 | ll <<= 56; | |
788 | cword->ll = (cword->ll >> 8) | ll; | |
789 | #else | |
5653fc33 | 790 | cword->ll = (cword->ll << 8) | c; |
4d13cbad | 791 | #endif |
5653fc33 WD |
792 | break; |
793 | } | |
794 | } | |
795 | ||
796 | ||
797 | /*----------------------------------------------------------------------- | |
798 | * make a proper sized command based on the port and chip widths | |
799 | */ | |
bf9e3b38 | 800 | static void flash_make_cmd (flash_info_t * info, uchar cmd, void *cmdbuf) |
5653fc33 WD |
801 | { |
802 | int i; | |
bf9e3b38 WD |
803 | uchar *cp = (uchar *) cmdbuf; |
804 | ||
bf9e3b38 | 805 | #if defined(__LITTLE_ENDIAN) |
dafbe379 WD |
806 | for (i = info->portwidth; i > 0; i--) |
807 | #else | |
808 | for (i = 1; i <= info->portwidth; i++) | |
bf9e3b38 | 809 | #endif |
47340a46 | 810 | *cp++ = (i & (info->chipwidth - 1)) ? '\0' : cmd; |
5653fc33 WD |
811 | } |
812 | ||
813 | /* | |
814 | * Write a proper sized command to the correct address | |
815 | */ | |
028ab6b5 | 816 | static void flash_write_cmd (flash_info_t * info, flash_sect_t sect, uint offset, uchar cmd) |
5653fc33 WD |
817 | { |
818 | ||
819 | volatile cfiptr_t addr; | |
820 | cfiword_t cword; | |
bf9e3b38 WD |
821 | |
822 | addr.cp = flash_make_addr (info, sect, offset); | |
823 | flash_make_cmd (info, cmd, &cword); | |
824 | switch (info->portwidth) { | |
5653fc33 | 825 | case FLASH_CFI_8BIT: |
bf9e3b38 WD |
826 | debug ("fwc addr %p cmd %x %x 8bit x %d bit\n", addr.cp, cmd, |
827 | cword.c, info->chipwidth << CFI_FLASH_SHIFT_WIDTH); | |
5653fc33 WD |
828 | *addr.cp = cword.c; |
829 | break; | |
830 | case FLASH_CFI_16BIT: | |
bf9e3b38 WD |
831 | debug ("fwc addr %p cmd %x %4.4x 16bit x %d bit\n", addr.wp, |
832 | cmd, cword.w, | |
5653fc33 WD |
833 | info->chipwidth << CFI_FLASH_SHIFT_WIDTH); |
834 | *addr.wp = cword.w; | |
835 | break; | |
836 | case FLASH_CFI_32BIT: | |
bf9e3b38 WD |
837 | debug ("fwc addr %p cmd %x %8.8lx 32bit x %d bit\n", addr.lp, |
838 | cmd, cword.l, | |
5653fc33 WD |
839 | info->chipwidth << CFI_FLASH_SHIFT_WIDTH); |
840 | *addr.lp = cword.l; | |
841 | break; | |
842 | case FLASH_CFI_64BIT: | |
843 | #ifdef DEBUG | |
bf9e3b38 | 844 | { |
5653fc33 | 845 | char str[20]; |
cd37d9e6 | 846 | |
bf9e3b38 WD |
847 | print_longlong (str, cword.ll); |
848 | ||
849 | debug ("fwrite addr %p cmd %x %s 64 bit x %d bit\n", | |
850 | addr.llp, cmd, str, | |
5653fc33 WD |
851 | info->chipwidth << CFI_FLASH_SHIFT_WIDTH); |
852 | } | |
853 | #endif | |
854 | *addr.llp = cword.ll; | |
855 | break; | |
856 | } | |
857 | } | |
858 | ||
bf9e3b38 | 859 | static void flash_unlock_seq (flash_info_t * info, flash_sect_t sect) |
5653fc33 | 860 | { |
855a496f WD |
861 | flash_write_cmd (info, sect, AMD_ADDR_START, AMD_CMD_UNLOCK_START); |
862 | flash_write_cmd (info, sect, AMD_ADDR_ACK, AMD_CMD_UNLOCK_ACK); | |
5653fc33 | 863 | } |
bf9e3b38 | 864 | |
5653fc33 WD |
865 | /*----------------------------------------------------------------------- |
866 | */ | |
028ab6b5 | 867 | static int flash_isequal (flash_info_t * info, flash_sect_t sect, uint offset, uchar cmd) |
5653fc33 WD |
868 | { |
869 | cfiptr_t cptr; | |
870 | cfiword_t cword; | |
871 | int retval; | |
5653fc33 | 872 | |
bf9e3b38 WD |
873 | cptr.cp = flash_make_addr (info, sect, offset); |
874 | flash_make_cmd (info, cmd, &cword); | |
875 | ||
876 | debug ("is= cmd %x(%c) addr %p ", cmd, cmd, cptr.cp); | |
877 | switch (info->portwidth) { | |
5653fc33 | 878 | case FLASH_CFI_8BIT: |
bf9e3b38 | 879 | debug ("is= %x %x\n", cptr.cp[0], cword.c); |
5653fc33 WD |
880 | retval = (cptr.cp[0] == cword.c); |
881 | break; | |
882 | case FLASH_CFI_16BIT: | |
bf9e3b38 | 883 | debug ("is= %4.4x %4.4x\n", cptr.wp[0], cword.w); |
5653fc33 WD |
884 | retval = (cptr.wp[0] == cword.w); |
885 | break; | |
886 | case FLASH_CFI_32BIT: | |
bf9e3b38 | 887 | debug ("is= %8.8lx %8.8lx\n", cptr.lp[0], cword.l); |
5653fc33 WD |
888 | retval = (cptr.lp[0] == cword.l); |
889 | break; | |
890 | case FLASH_CFI_64BIT: | |
cd37d9e6 | 891 | #ifdef DEBUG |
bf9e3b38 | 892 | { |
5653fc33 WD |
893 | char str1[20]; |
894 | char str2[20]; | |
bf9e3b38 WD |
895 | |
896 | print_longlong (str1, cptr.llp[0]); | |
897 | print_longlong (str2, cword.ll); | |
898 | debug ("is= %s %s\n", str1, str2); | |
5653fc33 WD |
899 | } |
900 | #endif | |
901 | retval = (cptr.llp[0] == cword.ll); | |
902 | break; | |
903 | default: | |
904 | retval = 0; | |
905 | break; | |
906 | } | |
907 | return retval; | |
908 | } | |
bf9e3b38 | 909 | |
5653fc33 WD |
910 | /*----------------------------------------------------------------------- |
911 | */ | |
028ab6b5 | 912 | static int flash_isset (flash_info_t * info, flash_sect_t sect, uint offset, uchar cmd) |
5653fc33 WD |
913 | { |
914 | cfiptr_t cptr; | |
915 | cfiword_t cword; | |
916 | int retval; | |
bf9e3b38 WD |
917 | |
918 | cptr.cp = flash_make_addr (info, sect, offset); | |
919 | flash_make_cmd (info, cmd, &cword); | |
920 | switch (info->portwidth) { | |
5653fc33 WD |
921 | case FLASH_CFI_8BIT: |
922 | retval = ((cptr.cp[0] & cword.c) == cword.c); | |
923 | break; | |
924 | case FLASH_CFI_16BIT: | |
925 | retval = ((cptr.wp[0] & cword.w) == cword.w); | |
926 | break; | |
927 | case FLASH_CFI_32BIT: | |
928 | retval = ((cptr.lp[0] & cword.l) == cword.l); | |
929 | break; | |
930 | case FLASH_CFI_64BIT: | |
931 | retval = ((cptr.llp[0] & cword.ll) == cword.ll); | |
bf9e3b38 | 932 | break; |
5653fc33 WD |
933 | default: |
934 | retval = 0; | |
935 | break; | |
936 | } | |
937 | return retval; | |
938 | } | |
939 | ||
940 | /*----------------------------------------------------------------------- | |
941 | */ | |
028ab6b5 | 942 | static int flash_toggle (flash_info_t * info, flash_sect_t sect, uint offset, uchar cmd) |
5653fc33 WD |
943 | { |
944 | cfiptr_t cptr; | |
945 | cfiword_t cword; | |
946 | int retval; | |
bf9e3b38 WD |
947 | |
948 | cptr.cp = flash_make_addr (info, sect, offset); | |
949 | flash_make_cmd (info, cmd, &cword); | |
950 | switch (info->portwidth) { | |
5653fc33 WD |
951 | case FLASH_CFI_8BIT: |
952 | retval = ((cptr.cp[0] & cword.c) != (cptr.cp[0] & cword.c)); | |
953 | break; | |
954 | case FLASH_CFI_16BIT: | |
955 | retval = ((cptr.wp[0] & cword.w) != (cptr.wp[0] & cword.w)); | |
956 | break; | |
957 | case FLASH_CFI_32BIT: | |
958 | retval = ((cptr.lp[0] & cword.l) != (cptr.lp[0] & cword.l)); | |
959 | break; | |
960 | case FLASH_CFI_64BIT: | |
bf9e3b38 WD |
961 | retval = ((cptr.llp[0] & cword.ll) != |
962 | (cptr.llp[0] & cword.ll)); | |
5653fc33 WD |
963 | break; |
964 | default: | |
965 | retval = 0; | |
966 | break; | |
967 | } | |
968 | return retval; | |
969 | } | |
970 | ||
971 | /*----------------------------------------------------------------------- | |
972 | * detect if flash is compatible with the Common Flash Interface (CFI) | |
973 | * http://www.jedec.org/download/search/jesd68.pdf | |
974 | * | |
975 | */ | |
bf9e3b38 | 976 | static int flash_detect_cfi (flash_info_t * info) |
5653fc33 | 977 | { |
bf9e3b38 WD |
978 | debug ("flash detect cfi\n"); |
979 | ||
980 | for (info->portwidth = FLASH_CFI_8BIT; | |
981 | info->portwidth <= FLASH_CFI_64BIT; info->portwidth <<= 1) { | |
982 | for (info->chipwidth = FLASH_CFI_BY8; | |
983 | info->chipwidth <= info->portwidth; | |
984 | info->chipwidth <<= 1) { | |
db421e64 | 985 | flash_write_cmd (info, 0, 0, info->cmd_reset); |
028ab6b5 WD |
986 | flash_write_cmd (info, 0, FLASH_OFFSET_CFI, FLASH_CMD_CFI); |
987 | if (flash_isequal (info, 0, FLASH_OFFSET_CFI_RESP, 'Q') | |
988 | && flash_isequal (info, 0, FLASH_OFFSET_CFI_RESP + 1, 'R') | |
989 | && flash_isequal (info, 0, FLASH_OFFSET_CFI_RESP + 2, 'Y')) { | |
990 | info->interface = flash_read_ushort (info, 0, FLASH_OFFSET_INTERFACE); | |
bf9e3b38 WD |
991 | debug ("device interface is %d\n", |
992 | info->interface); | |
993 | debug ("found port %d chip %d ", | |
994 | info->portwidth, info->chipwidth); | |
995 | debug ("port %d bits chip %d bits\n", | |
028ab6b5 WD |
996 | info->portwidth << CFI_FLASH_SHIFT_WIDTH, |
997 | info->chipwidth << CFI_FLASH_SHIFT_WIDTH); | |
5653fc33 WD |
998 | return 1; |
999 | } | |
1000 | } | |
1001 | } | |
bf9e3b38 | 1002 | debug ("not found\n"); |
5653fc33 WD |
1003 | return 0; |
1004 | } | |
bf9e3b38 | 1005 | |
5653fc33 WD |
1006 | /* |
1007 | * The following code cannot be run from FLASH! | |
1008 | * | |
1009 | */ | |
1010 | static ulong flash_get_size (ulong base, int banknum) | |
1011 | { | |
bf9e3b38 | 1012 | flash_info_t *info = &flash_info[banknum]; |
5653fc33 WD |
1013 | int i, j; |
1014 | flash_sect_t sect_cnt; | |
1015 | unsigned long sector; | |
1016 | unsigned long tmp; | |
1017 | int size_ratio; | |
1018 | uchar num_erase_regions; | |
bf9e3b38 WD |
1019 | int erase_region_size; |
1020 | int erase_region_count; | |
5653fc33 WD |
1021 | |
1022 | info->start[0] = base; | |
1023 | ||
bf9e3b38 | 1024 | if (flash_detect_cfi (info)) { |
028ab6b5 | 1025 | info->vendor = flash_read_ushort (info, 0, FLASH_OFFSET_PRIMARY_VENDOR); |
bf9e3b38 WD |
1026 | #ifdef DEBUG |
1027 | flash_printqry (info, 0); | |
1028 | #endif | |
1029 | switch (info->vendor) { | |
5653fc33 WD |
1030 | case CFI_CMDSET_INTEL_STANDARD: |
1031 | case CFI_CMDSET_INTEL_EXTENDED: | |
1032 | default: | |
1033 | info->cmd_reset = FLASH_CMD_RESET; | |
1034 | break; | |
1035 | case CFI_CMDSET_AMD_STANDARD: | |
1036 | case CFI_CMDSET_AMD_EXTENDED: | |
1037 | info->cmd_reset = AMD_CMD_RESET; | |
1038 | break; | |
1039 | } | |
cd37d9e6 | 1040 | |
bf9e3b38 | 1041 | debug ("manufacturer is %d\n", info->vendor); |
5653fc33 | 1042 | size_ratio = info->portwidth / info->chipwidth; |
bf9e3b38 WD |
1043 | /* if the chip is x8/x16 reduce the ratio by half */ |
1044 | if ((info->interface == FLASH_CFI_X8X16) | |
1045 | && (info->chipwidth == FLASH_CFI_BY8)) { | |
1046 | size_ratio >>= 1; | |
1047 | } | |
028ab6b5 | 1048 | num_erase_regions = flash_read_uchar (info, FLASH_OFFSET_NUM_ERASE_REGIONS); |
bf9e3b38 WD |
1049 | debug ("size_ratio %d port %d bits chip %d bits\n", |
1050 | size_ratio, info->portwidth << CFI_FLASH_SHIFT_WIDTH, | |
1051 | info->chipwidth << CFI_FLASH_SHIFT_WIDTH); | |
1052 | debug ("found %d erase regions\n", num_erase_regions); | |
5653fc33 WD |
1053 | sect_cnt = 0; |
1054 | sector = base; | |
bf9e3b38 WD |
1055 | for (i = 0; i < num_erase_regions; i++) { |
1056 | if (i > NUM_ERASE_REGIONS) { | |
028ab6b5 WD |
1057 | printf ("%d erase regions found, only %d used\n", |
1058 | num_erase_regions, NUM_ERASE_REGIONS); | |
5653fc33 WD |
1059 | break; |
1060 | } | |
bf9e3b38 WD |
1061 | tmp = flash_read_long (info, 0, |
1062 | FLASH_OFFSET_ERASE_REGIONS + | |
1063 | i * 4); | |
1064 | erase_region_size = | |
1065 | (tmp & 0xffff) ? ((tmp & 0xffff) * 256) : 128; | |
5653fc33 | 1066 | tmp >>= 16; |
bf9e3b38 | 1067 | erase_region_count = (tmp & 0xffff) + 1; |
4c0d4c3b | 1068 | debug ("erase_region_count = %d erase_region_size = %d\n", |
028ab6b5 | 1069 | erase_region_count, erase_region_size); |
bf9e3b38 | 1070 | for (j = 0; j < erase_region_count; j++) { |
5653fc33 WD |
1071 | info->start[sect_cnt] = sector; |
1072 | sector += (erase_region_size * size_ratio); | |
a1191902 WD |
1073 | |
1074 | /* | |
1075 | * Only read protection status from supported devices (intel...) | |
1076 | */ | |
1077 | switch (info->vendor) { | |
1078 | case CFI_CMDSET_INTEL_EXTENDED: | |
1079 | case CFI_CMDSET_INTEL_STANDARD: | |
1080 | info->protect[sect_cnt] = | |
1081 | flash_isset (info, sect_cnt, | |
1082 | FLASH_OFFSET_PROTECT, | |
1083 | FLASH_STATUS_PROTECT); | |
1084 | break; | |
1085 | default: | |
1086 | info->protect[sect_cnt] = 0; /* default: not protected */ | |
1087 | } | |
1088 | ||
5653fc33 WD |
1089 | sect_cnt++; |
1090 | } | |
1091 | } | |
1092 | ||
1093 | info->sector_count = sect_cnt; | |
1094 | /* multiply the size by the number of chips */ | |
028ab6b5 WD |
1095 | info->size = (1 << flash_read_uchar (info, FLASH_OFFSET_SIZE)) * size_ratio; |
1096 | info->buffer_size = (1 << flash_read_ushort (info, 0, FLASH_OFFSET_BUFFER_SIZE)); | |
bf9e3b38 | 1097 | tmp = 1 << flash_read_uchar (info, FLASH_OFFSET_ETOUT); |
028ab6b5 | 1098 | info->erase_blk_tout = (tmp * (1 << flash_read_uchar (info, FLASH_OFFSET_EMAX_TOUT))); |
bf9e3b38 | 1099 | tmp = 1 << flash_read_uchar (info, FLASH_OFFSET_WBTOUT); |
028ab6b5 | 1100 | info->buffer_write_tout = (tmp * (1 << flash_read_uchar (info, FLASH_OFFSET_WBMAX_TOUT))); |
bf9e3b38 | 1101 | tmp = 1 << flash_read_uchar (info, FLASH_OFFSET_WTOUT); |
028ab6b5 | 1102 | info->write_tout = (tmp * (1 << flash_read_uchar (info, FLASH_OFFSET_WMAX_TOUT))) / 1000; |
5653fc33 | 1103 | info->flash_id = FLASH_MAN_CFI; |
855a496f WD |
1104 | if ((info->interface == FLASH_CFI_X8X16) && (info->chipwidth == FLASH_CFI_BY8)) { |
1105 | info->portwidth >>= 1; /* XXX - Need to test on x8/x16 in parallel. */ | |
1106 | } | |
5653fc33 WD |
1107 | } |
1108 | ||
db421e64 | 1109 | flash_write_cmd (info, 0, 0, info->cmd_reset); |
bf9e3b38 | 1110 | return (info->size); |
5653fc33 WD |
1111 | } |
1112 | ||
1113 | ||
1114 | /*----------------------------------------------------------------------- | |
1115 | */ | |
bf9e3b38 WD |
1116 | static int flash_write_cfiword (flash_info_t * info, ulong dest, |
1117 | cfiword_t cword) | |
5653fc33 WD |
1118 | { |
1119 | ||
1120 | cfiptr_t ctladdr; | |
1121 | cfiptr_t cptr; | |
1122 | int flag; | |
1123 | ||
bf9e3b38 WD |
1124 | ctladdr.cp = flash_make_addr (info, 0, 0); |
1125 | cptr.cp = (uchar *) dest; | |
5653fc33 WD |
1126 | |
1127 | ||
1128 | /* Check if Flash is (sufficiently) erased */ | |
bf9e3b38 | 1129 | switch (info->portwidth) { |
5653fc33 WD |
1130 | case FLASH_CFI_8BIT: |
1131 | flag = ((cptr.cp[0] & cword.c) == cword.c); | |
1132 | break; | |
1133 | case FLASH_CFI_16BIT: | |
1134 | flag = ((cptr.wp[0] & cword.w) == cword.w); | |
1135 | break; | |
1136 | case FLASH_CFI_32BIT: | |
bf9e3b38 | 1137 | flag = ((cptr.lp[0] & cword.l) == cword.l); |
5653fc33 WD |
1138 | break; |
1139 | case FLASH_CFI_64BIT: | |
e1599e83 | 1140 | flag = ((cptr.llp[0] & cword.ll) == cword.ll); |
5653fc33 WD |
1141 | break; |
1142 | default: | |
1143 | return 2; | |
1144 | } | |
bf9e3b38 | 1145 | if (!flag) |
5653fc33 WD |
1146 | return 2; |
1147 | ||
1148 | /* Disable interrupts which might cause a timeout here */ | |
bf9e3b38 | 1149 | flag = disable_interrupts (); |
5653fc33 | 1150 | |
bf9e3b38 | 1151 | switch (info->vendor) { |
5653fc33 WD |
1152 | case CFI_CMDSET_INTEL_EXTENDED: |
1153 | case CFI_CMDSET_INTEL_STANDARD: | |
bf9e3b38 WD |
1154 | flash_write_cmd (info, 0, 0, FLASH_CMD_CLEAR_STATUS); |
1155 | flash_write_cmd (info, 0, 0, FLASH_CMD_WRITE); | |
5653fc33 WD |
1156 | break; |
1157 | case CFI_CMDSET_AMD_EXTENDED: | |
1158 | case CFI_CMDSET_AMD_STANDARD: | |
bf9e3b38 | 1159 | flash_unlock_seq (info, 0); |
855a496f | 1160 | flash_write_cmd (info, 0, AMD_ADDR_START, AMD_CMD_WRITE); |
5653fc33 WD |
1161 | break; |
1162 | } | |
1163 | ||
bf9e3b38 | 1164 | switch (info->portwidth) { |
5653fc33 WD |
1165 | case FLASH_CFI_8BIT: |
1166 | cptr.cp[0] = cword.c; | |
1167 | break; | |
1168 | case FLASH_CFI_16BIT: | |
1169 | cptr.wp[0] = cword.w; | |
1170 | break; | |
1171 | case FLASH_CFI_32BIT: | |
1172 | cptr.lp[0] = cword.l; | |
1173 | break; | |
1174 | case FLASH_CFI_64BIT: | |
1175 | cptr.llp[0] = cword.ll; | |
1176 | break; | |
1177 | } | |
1178 | ||
1179 | /* re-enable interrupts if necessary */ | |
bf9e3b38 WD |
1180 | if (flag) |
1181 | enable_interrupts (); | |
5653fc33 | 1182 | |
bf9e3b38 | 1183 | return flash_full_status_check (info, 0, info->write_tout, "write"); |
5653fc33 WD |
1184 | } |
1185 | ||
1186 | #ifdef CFG_FLASH_USE_BUFFER_WRITE | |
1187 | ||
1188 | /* loop through the sectors from the highest address | |
1189 | * when the passed address is greater or equal to the sector address | |
1190 | * we have a match | |
1191 | */ | |
bf9e3b38 | 1192 | static flash_sect_t find_sector (flash_info_t * info, ulong addr) |
5653fc33 WD |
1193 | { |
1194 | flash_sect_t sector; | |
bf9e3b38 WD |
1195 | |
1196 | for (sector = info->sector_count - 1; sector >= 0; sector--) { | |
1197 | if (addr >= info->start[sector]) | |
5653fc33 WD |
1198 | break; |
1199 | } | |
1200 | return sector; | |
1201 | } | |
1202 | ||
bf9e3b38 WD |
1203 | static int flash_write_cfibuffer (flash_info_t * info, ulong dest, uchar * cp, |
1204 | int len) | |
5653fc33 WD |
1205 | { |
1206 | flash_sect_t sector; | |
1207 | int cnt; | |
1208 | int retcode; | |
1209 | volatile cfiptr_t src; | |
1210 | volatile cfiptr_t dst; | |
855a496f WD |
1211 | /* buffered writes in the AMD chip set is not supported yet */ |
1212 | if((info->vendor == CFI_CMDSET_AMD_STANDARD) || | |
1213 | (info->vendor == CFI_CMDSET_AMD_EXTENDED)) | |
1214 | return ERR_INVAL; | |
5653fc33 WD |
1215 | |
1216 | src.cp = cp; | |
bf9e3b38 WD |
1217 | dst.cp = (uchar *) dest; |
1218 | sector = find_sector (info, dest); | |
1219 | flash_write_cmd (info, sector, 0, FLASH_CMD_CLEAR_STATUS); | |
1220 | flash_write_cmd (info, sector, 0, FLASH_CMD_WRITE_TO_BUFFER); | |
1221 | if ((retcode = | |
1222 | flash_status_check (info, sector, info->buffer_write_tout, | |
1223 | "write to buffer")) == ERR_OK) { | |
1224 | /* reduce the number of loops by the width of the port */ | |
1225 | switch (info->portwidth) { | |
5653fc33 WD |
1226 | case FLASH_CFI_8BIT: |
1227 | cnt = len; | |
1228 | break; | |
1229 | case FLASH_CFI_16BIT: | |
1230 | cnt = len >> 1; | |
1231 | break; | |
1232 | case FLASH_CFI_32BIT: | |
1233 | cnt = len >> 2; | |
1234 | break; | |
1235 | case FLASH_CFI_64BIT: | |
1236 | cnt = len >> 3; | |
1237 | break; | |
1238 | default: | |
1239 | return ERR_INVAL; | |
1240 | break; | |
1241 | } | |
bf9e3b38 WD |
1242 | flash_write_cmd (info, sector, 0, (uchar) cnt - 1); |
1243 | while (cnt-- > 0) { | |
1244 | switch (info->portwidth) { | |
5653fc33 WD |
1245 | case FLASH_CFI_8BIT: |
1246 | *dst.cp++ = *src.cp++; | |
1247 | break; | |
1248 | case FLASH_CFI_16BIT: | |
1249 | *dst.wp++ = *src.wp++; | |
1250 | break; | |
1251 | case FLASH_CFI_32BIT: | |
1252 | *dst.lp++ = *src.lp++; | |
1253 | break; | |
1254 | case FLASH_CFI_64BIT: | |
1255 | *dst.llp++ = *src.llp++; | |
1256 | break; | |
1257 | default: | |
1258 | return ERR_INVAL; | |
1259 | break; | |
1260 | } | |
1261 | } | |
bf9e3b38 WD |
1262 | flash_write_cmd (info, sector, 0, |
1263 | FLASH_CMD_WRITE_BUFFER_CONFIRM); | |
1264 | retcode = | |
1265 | flash_full_status_check (info, sector, | |
1266 | info->buffer_write_tout, | |
1267 | "buffer write"); | |
5653fc33 | 1268 | } |
bf9e3b38 | 1269 | flash_write_cmd (info, sector, 0, FLASH_CMD_CLEAR_STATUS); |
5653fc33 WD |
1270 | return retcode; |
1271 | } | |
cce625e5 | 1272 | #endif /* CFG_FLASH_USE_BUFFER_WRITE */ |
5653fc33 | 1273 | #endif /* CFG_FLASH_CFI */ |