]>
Commit | Line | Data |
---|---|---|
1d7993d1 LM |
1 | // SPDX-License-Identifier: GPL-2.0 |
2 | /* | |
3 | * Copyright (C) 2019 DENX Software Engineering | |
4 | * Lukasz Majewski, DENX Software Engineering, lukma@denx.de | |
5 | * | |
6 | * Copyright (C) 2011 Sascha Hauer, Pengutronix <s.hauer@pengutronix.de> | |
7 | * Copyright (C) 2011 Richard Zhao, Linaro <richard.zhao@linaro.org> | |
8 | * Copyright (C) 2011-2012 Mike Turquette, Linaro Ltd <mturquette@linaro.org> | |
9 | * | |
10 | * Simple multiplexer clock implementation | |
11 | */ | |
12 | ||
13 | /* | |
14 | * U-Boot CCF porting node: | |
15 | * | |
16 | * The Linux kernel - as of tag: 5.0-rc3 is using also the imx_clk_fixup_mux() | |
17 | * version of CCF mux. It is used on e.g. imx6q to provide fixes (like | |
18 | * imx_cscmr1_fixup) for broken HW. | |
19 | * | |
20 | * At least for IMX6Q (but NOT IMX6QP) it is important when we set the parent | |
21 | * clock. | |
22 | */ | |
23 | ||
560e1e00 PD |
24 | #define LOG_CATEGORY UCLASS_CLK |
25 | ||
d678a59d | 26 | #include <common.h> |
76eaa2d0 | 27 | #include <clk.h> |
1d7993d1 | 28 | #include <clk-uclass.h> |
560e1e00 | 29 | #include <log.h> |
572c446e PD |
30 | #include <malloc.h> |
31 | #include <asm/io.h> | |
1d7993d1 | 32 | #include <dm/device.h> |
560e1e00 | 33 | #include <dm/device_compat.h> |
61b29b82 | 34 | #include <dm/devres.h> |
ebd3f1f0 | 35 | #include <dm/uclass.h> |
cd93d625 | 36 | #include <linux/bitops.h> |
1d7993d1 | 37 | #include <linux/clk-provider.h> |
61b29b82 | 38 | #include <linux/err.h> |
1e94b46f | 39 | #include <linux/printk.h> |
572c446e | 40 | |
76eaa2d0 | 41 | #include "clk.h" |
1d7993d1 LM |
42 | |
43 | #define UBOOT_DM_CLK_CCF_MUX "ccf_clk_mux" | |
44 | ||
45 | int clk_mux_val_to_index(struct clk *clk, u32 *table, unsigned int flags, | |
46 | unsigned int val) | |
47 | { | |
78ce0bd3 | 48 | struct clk_mux *mux = to_clk_mux(clk); |
1d7993d1 LM |
49 | int num_parents = mux->num_parents; |
50 | ||
51 | if (table) { | |
52 | int i; | |
53 | ||
54 | for (i = 0; i < num_parents; i++) | |
55 | if (table[i] == val) | |
56 | return i; | |
57 | return -EINVAL; | |
58 | } | |
59 | ||
60 | if (val && (flags & CLK_MUX_INDEX_BIT)) | |
61 | val = ffs(val) - 1; | |
62 | ||
63 | if (val && (flags & CLK_MUX_INDEX_ONE)) | |
64 | val--; | |
65 | ||
66 | if (val >= num_parents) | |
67 | return -EINVAL; | |
68 | ||
69 | return val; | |
70 | } | |
71 | ||
4b044082 PF |
72 | unsigned int clk_mux_index_to_val(u32 *table, unsigned int flags, u8 index) |
73 | { | |
74 | unsigned int val = index; | |
75 | ||
76 | if (table) { | |
77 | val = table[index]; | |
78 | } else { | |
79 | if (flags & CLK_MUX_INDEX_BIT) | |
80 | val = 1 << index; | |
81 | ||
82 | if (flags & CLK_MUX_INDEX_ONE) | |
83 | val++; | |
84 | } | |
85 | ||
86 | return val; | |
87 | } | |
88 | ||
89 | u8 clk_mux_get_parent(struct clk *clk) | |
1d7993d1 | 90 | { |
78ce0bd3 | 91 | struct clk_mux *mux = to_clk_mux(clk); |
1d7993d1 LM |
92 | u32 val; |
93 | ||
4051c400 | 94 | #if IS_ENABLED(CONFIG_SANDBOX_CLK_CCF) |
5da0095e LM |
95 | val = mux->io_mux_val; |
96 | #else | |
97 | val = readl(mux->reg); | |
98 | #endif | |
99 | val >>= mux->shift; | |
1d7993d1 LM |
100 | val &= mux->mask; |
101 | ||
102 | return clk_mux_val_to_index(clk, mux->table, mux->flags, val); | |
103 | } | |
104 | ||
4b044082 PF |
105 | static int clk_fetch_parent_index(struct clk *clk, |
106 | struct clk *parent) | |
107 | { | |
78ce0bd3 | 108 | struct clk_mux *mux = to_clk_mux(clk); |
4b044082 PF |
109 | |
110 | int i; | |
111 | ||
112 | if (!parent) | |
113 | return -EINVAL; | |
114 | ||
115 | for (i = 0; i < mux->num_parents; i++) { | |
116 | if (!strcmp(parent->dev->name, mux->parent_names[i])) | |
117 | return i; | |
118 | } | |
119 | ||
120 | return -EINVAL; | |
121 | } | |
122 | ||
123 | static int clk_mux_set_parent(struct clk *clk, struct clk *parent) | |
124 | { | |
78ce0bd3 | 125 | struct clk_mux *mux = to_clk_mux(clk); |
4b044082 PF |
126 | int index; |
127 | u32 val; | |
128 | u32 reg; | |
129 | ||
130 | index = clk_fetch_parent_index(clk, parent); | |
131 | if (index < 0) { | |
560e1e00 | 132 | log_err("Could not fetch index\n"); |
4b044082 PF |
133 | return index; |
134 | } | |
135 | ||
136 | val = clk_mux_index_to_val(mux->table, mux->flags, index); | |
137 | ||
138 | if (mux->flags & CLK_MUX_HIWORD_MASK) { | |
139 | reg = mux->mask << (mux->shift + 16); | |
140 | } else { | |
4051c400 | 141 | #if IS_ENABLED(CONFIG_SANDBOX_CLK_CCF) |
e3b5d74c DB |
142 | reg = mux->io_mux_val; |
143 | #else | |
4b044082 | 144 | reg = readl(mux->reg); |
e3b5d74c | 145 | #endif |
4b044082 PF |
146 | reg &= ~(mux->mask << mux->shift); |
147 | } | |
148 | val = val << mux->shift; | |
149 | reg |= val; | |
4051c400 | 150 | #if IS_ENABLED(CONFIG_SANDBOX_CLK_CCF) |
e3b5d74c DB |
151 | mux->io_mux_val = reg; |
152 | #else | |
4b044082 | 153 | writel(reg, mux->reg); |
e3b5d74c | 154 | #endif |
4b044082 PF |
155 | |
156 | return 0; | |
157 | } | |
158 | ||
1d7993d1 | 159 | const struct clk_ops clk_mux_ops = { |
fa181d1a | 160 | .get_rate = clk_generic_get_rate, |
4b044082 | 161 | .set_parent = clk_mux_set_parent, |
1d7993d1 LM |
162 | }; |
163 | ||
164 | struct clk *clk_hw_register_mux_table(struct device *dev, const char *name, | |
165 | const char * const *parent_names, u8 num_parents, | |
166 | unsigned long flags, | |
167 | void __iomem *reg, u8 shift, u32 mask, | |
168 | u8 clk_mux_flags, u32 *table) | |
169 | { | |
170 | struct clk_mux *mux; | |
171 | struct clk *clk; | |
172 | u8 width = 0; | |
173 | int ret; | |
174 | ||
175 | if (clk_mux_flags & CLK_MUX_HIWORD_MASK) { | |
176 | width = fls(mask) - ffs(mask) + 1; | |
177 | if (width + shift > 16) { | |
560e1e00 | 178 | dev_err(dev, "mux value exceeds LOWORD field\n"); |
1d7993d1 LM |
179 | return ERR_PTR(-EINVAL); |
180 | } | |
181 | } | |
182 | ||
183 | /* allocate the mux */ | |
184 | mux = kzalloc(sizeof(*mux), GFP_KERNEL); | |
185 | if (!mux) | |
186 | return ERR_PTR(-ENOMEM); | |
187 | ||
1be82afa | 188 | /* U-Boot specific assignments */ |
1d7993d1 LM |
189 | mux->parent_names = parent_names; |
190 | mux->num_parents = num_parents; | |
191 | ||
192 | /* struct clk_mux assignments */ | |
193 | mux->reg = reg; | |
194 | mux->shift = shift; | |
195 | mux->mask = mask; | |
196 | mux->flags = clk_mux_flags; | |
197 | mux->table = table; | |
4051c400 | 198 | #if IS_ENABLED(CONFIG_SANDBOX_CLK_CCF) |
5da0095e LM |
199 | mux->io_mux_val = *(u32 *)reg; |
200 | #endif | |
1d7993d1 LM |
201 | |
202 | clk = &mux->clk; | |
16bdc85b | 203 | clk->flags = flags; |
1d7993d1 LM |
204 | |
205 | /* | |
206 | * Read the current mux setup - so we assign correct parent. | |
207 | * | |
208 | * Changing parent would require changing internals of udevice struct | |
40559d27 | 209 | * for the corresponding clock (to do that define .set_parent() method). |
1d7993d1 LM |
210 | */ |
211 | ret = clk_register(clk, UBOOT_DM_CLK_CCF_MUX, name, | |
212 | parent_names[clk_mux_get_parent(clk)]); | |
213 | if (ret) { | |
214 | kfree(mux); | |
215 | return ERR_PTR(ret); | |
216 | } | |
217 | ||
218 | return clk; | |
219 | } | |
220 | ||
221 | struct clk *clk_register_mux_table(struct device *dev, const char *name, | |
222 | const char * const *parent_names, u8 num_parents, | |
223 | unsigned long flags, | |
224 | void __iomem *reg, u8 shift, u32 mask, | |
225 | u8 clk_mux_flags, u32 *table) | |
226 | { | |
227 | struct clk *clk; | |
228 | ||
229 | clk = clk_hw_register_mux_table(dev, name, parent_names, num_parents, | |
230 | flags, reg, shift, mask, clk_mux_flags, | |
231 | table); | |
232 | if (IS_ERR(clk)) | |
233 | return ERR_CAST(clk); | |
234 | return clk; | |
235 | } | |
236 | ||
237 | struct clk *clk_register_mux(struct device *dev, const char *name, | |
238 | const char * const *parent_names, u8 num_parents, | |
239 | unsigned long flags, | |
240 | void __iomem *reg, u8 shift, u8 width, | |
241 | u8 clk_mux_flags) | |
242 | { | |
243 | u32 mask = BIT(width) - 1; | |
244 | ||
245 | return clk_register_mux_table(dev, name, parent_names, num_parents, | |
246 | flags, reg, shift, mask, clk_mux_flags, | |
247 | NULL); | |
248 | } | |
249 | ||
250 | U_BOOT_DRIVER(ccf_clk_mux) = { | |
251 | .name = UBOOT_DM_CLK_CCF_MUX, | |
252 | .id = UCLASS_CLK, | |
253 | .ops = &clk_mux_ops, | |
254 | .flags = DM_FLAG_PRE_RELOC, | |
255 | }; |