[thirdparty/u-boot.git] / drivers / clk / clk-xlnx-clock-wizard.c

// SPDX-License-Identifier: GPL-2.0
/*
 * Xilinx 'Clocking Wizard' driver
 *
 * Copyright (c) 2021 Macronix Inc.
 *
 * Author: Zhengxun Li <zhengxunli@mxic.com.tw>
 */

#include <common.h>
#include <clk-uclass.h>
#include <dm.h>
#include <div64.h>
#include <dm/device_compat.h>
#include <linux/iopoll.h>

#include <linux/bitfield.h>

#define SRR			0x0

#define SR			0x4
#define SR_LOCKED		BIT(0)

#define CCR(x)			(0x200 + ((x) * 4))

#define FBOUT_CFG		CCR(0)
#define FBOUT_DIV(x)		(x)
#define FBOUT_DIV_MASK		GENMASK(7, 0)
#define FBOUT_GET_DIV(x)	FIELD_GET(FBOUT_DIV_MASK, x)
#define FBOUT_MUL(x)		((x) << 8)
#define FBOUT_MUL_MASK		GENMASK(15, 8)
#define FBOUT_GET_MUL(x)	FIELD_GET(FBOUT_MUL_MASK, x)
#define FBOUT_FRAC(x)		((x) << 16)
#define FBOUT_FRAC_MASK		GENMASK(25, 16)
#define FBOUT_GET_FRAC(x)	FIELD_GET(FBOUT_FRAC_MASK, x)
#define FBOUT_FRAC_EN		BIT(26)

#define FBOUT_PHASE		CCR(1)

#define OUT_CFG(x)		CCR(2 + ((x) * 3))
#define OUT_DIV(x)		(x)
#define OUT_DIV_MASK		GENMASK(7, 0)
#define OUT_GET_DIV(x)		FIELD_GET(OUT_DIV_MASK, x)
#define OUT_FRAC(x)		((x) << 8)
#define OUT_GET_MASK		GENMASK(17, 8)
#define OUT_GET_FRAC(x)		FIELD_GET(OUT_GET_MASK, x)
#define OUT_FRAC_EN		BIT(18)

#define OUT_PHASE(x)		CCR(3 + ((x) * 3))
#define OUT_DUTY(x)		CCR(4 + ((x) * 3))

#define CTRL			CCR(23)
#define CTRL_SEN		BIT(2)
#define CTRL_SADDR		BIT(1)
#define CTRL_LOAD		BIT(0)

/**
 * struct clkwzrd - Clock wizard private data structure
 *
 * @base:		memory base
 * @vco_clk:		voltage-controlled oscillator frequency
 *
 */
struct clkwzd {
	void *base;
	u64 vco_clk;
};

struct clkwzd_plat {
	fdt_addr_t addr;
};

static int clk_wzrd_enable(struct clk *clk)
{
	struct clkwzd *priv = dev_get_priv(clk->dev);
	int ret;
	u32 val;

	ret = readl_poll_sleep_timeout(priv->base + SR, val, val & SR_LOCKED,
				       1, 100);
	if (!ret) {
		writel(CTRL_SEN | CTRL_SADDR | CTRL_LOAD, priv->base + CTRL);
		writel(CTRL_SADDR, priv->base + CTRL);
		ret = readl_poll_sleep_timeout(priv->base + SR, val,
					       val & SR_LOCKED, 1, 100);
	}

	return ret;
}

static unsigned long clk_wzrd_set_rate(struct clk *clk, ulong rate)
{
	struct clkwzd *priv = dev_get_priv(clk->dev);
	u64 div;
	u32 cfg;

	/* Get output clock divide value */
	div = DIV_ROUND_DOWN_ULL(priv->vco_clk * 1000, rate);
	if (div < 1000 || div > 255999)
		return -EINVAL;

	cfg = OUT_DIV((u32)div / 1000);

	writel(cfg, priv->base + OUT_CFG(clk->id));

	return 0;
}

static struct clk_ops clk_wzrd_ops = {
	.enable = clk_wzrd_enable,
	.set_rate = clk_wzrd_set_rate,
};

static int clk_wzrd_probe(struct udevice *dev)
{
	struct clkwzd_plat *plat = dev_get_plat(dev);
	struct clkwzd *priv = dev_get_priv(dev);
	struct clk clk_in1;
	u64 clock, vco_clk;
	u32 cfg;
	int ret;

	priv->base = (void *)plat->addr;

	ret = clk_get_by_name(dev, "clk_in1", &clk_in1);
	if (ret < 0) {
		dev_err(dev, "failed to get clock\n");
		return ret;
	}

	clock = clk_get_rate(&clk_in1);
	if (IS_ERR_VALUE(clock)) {
		dev_err(dev, "failed to get rate\n");
		return clock;
	}

	ret = clk_enable(&clk_in1);
	if (ret) {
		dev_err(dev, "failed to enable clock\n");
		return ret;
	}

	/* Read clock configuration registers */
	cfg = readl(priv->base + FBOUT_CFG);

	/* Recalculate VCO rate */
	if (cfg & FBOUT_FRAC_EN)
		vco_clk = DIV_ROUND_DOWN_ULL(clock *
					     ((FBOUT_GET_MUL(cfg) * 1000) +
					      FBOUT_GET_FRAC(cfg)),
					     1000);
	else
		vco_clk = clock * FBOUT_GET_MUL(cfg);

	priv->vco_clk = DIV_ROUND_DOWN_ULL(vco_clk, FBOUT_GET_DIV(cfg));

	return 0;
}

static int clk_wzrd_of_to_plat(struct udevice *dev)
{
	struct clkwzd_plat *plat = dev_get_plat(dev);

	plat->addr = dev_read_addr(dev);
	if (plat->addr == FDT_ADDR_T_NONE)
		return -EINVAL;

	return 0;
}

static const struct udevice_id clk_wzrd_ids[] = {
	{ .compatible = "xlnx,clocking-wizard" },
	{ /* sentinel */ }
};

U_BOOT_DRIVER(clk_wzrd) = {
	.name = "zynq-clk-wizard",
	.id = UCLASS_CLK,
	.of_match = clk_wzrd_ids,
	.ops = &clk_wzrd_ops,
	.probe = clk_wzrd_probe,
	.of_to_plat = clk_wzrd_of_to_plat,
	.priv_auto = sizeof(struct clkwzd),
	.plat_auto = sizeof(struct clkwzd_plat),
};
Commit	Line	Data
2b157d81 Z	1	// SPDX-License-Identifier: GPL-2.0
	2	/*
	3	* Xilinx 'Clocking Wizard' driver
	4	*
	5	* Copyright (c) 2021 Macronix Inc.
	6	*
	7	* Author: Zhengxun Li <zhengxunli@mxic.com.tw>
	8	*/
	9
d678a59d	10	#include <common.h>
2b157d81 Z	11	#include <clk-uclass.h>
	12	#include <dm.h>
	13	#include <div64.h>
	14	#include <dm/device_compat.h>
	15	#include <linux/iopoll.h>
	16
	17	#include <linux/bitfield.h>
	18
	19	#define SRR 0x0
	20
	21	#define SR 0x4
	22	#define SR_LOCKED BIT(0)
	23
	24	#define CCR(x) (0x200 + ((x) * 4))
	25
	26	#define FBOUT_CFG CCR(0)
	27	#define FBOUT_DIV(x) (x)
	28	#define FBOUT_DIV_MASK GENMASK(7, 0)
	29	#define FBOUT_GET_DIV(x) FIELD_GET(FBOUT_DIV_MASK, x)
	30	#define FBOUT_MUL(x) ((x) << 8)
	31	#define FBOUT_MUL_MASK GENMASK(15, 8)
	32	#define FBOUT_GET_MUL(x) FIELD_GET(FBOUT_MUL_MASK, x)
	33	#define FBOUT_FRAC(x) ((x) << 16)
	34	#define FBOUT_FRAC_MASK GENMASK(25, 16)
	35	#define FBOUT_GET_FRAC(x) FIELD_GET(FBOUT_FRAC_MASK, x)
	36	#define FBOUT_FRAC_EN BIT(26)
	37
	38	#define FBOUT_PHASE CCR(1)
	39
	40	#define OUT_CFG(x) CCR(2 + ((x) * 3))
	41	#define OUT_DIV(x) (x)
	42	#define OUT_DIV_MASK GENMASK(7, 0)
	43	#define OUT_GET_DIV(x) FIELD_GET(OUT_DIV_MASK, x)
	44	#define OUT_FRAC(x) ((x) << 8)
	45	#define OUT_GET_MASK GENMASK(17, 8)
	46	#define OUT_GET_FRAC(x) FIELD_GET(OUT_GET_MASK, x)
	47	#define OUT_FRAC_EN BIT(18)
	48
	49	#define OUT_PHASE(x) CCR(3 + ((x) * 3))
	50	#define OUT_DUTY(x) CCR(4 + ((x) * 3))
	51
	52	#define CTRL CCR(23)
	53	#define CTRL_SEN BIT(2)
	54	#define CTRL_SADDR BIT(1)
	55	#define CTRL_LOAD BIT(0)
	56
	57	/**
	58	* struct clkwzrd - Clock wizard private data structure
	59	*
	60	* @base: memory base
	61	* @vco_clk: voltage-controlled oscillator frequency
	62	*
	63	*/
	64	struct clkwzd {
	65	void *base;
	66	u64 vco_clk;
	67	};
	68
	69	struct clkwzd_plat {
	70	fdt_addr_t addr;
	71	};
	72
	73	static int clk_wzrd_enable(struct clk *clk)
	74	{
75	struct clkwzd *priv = dev_get_priv(clk->dev);
76	int ret;
77	u32 val;
78
79	ret = readl_poll_sleep_timeout(priv->base + SR, val, val & SR_LOCKED,
80	1, 100);
81	if (!ret) {
82	writel(CTRL_SEN \| CTRL_SADDR \| CTRL_LOAD, priv->base + CTRL);
83	writel(CTRL_SADDR, priv->base + CTRL);
84	ret = readl_poll_sleep_timeout(priv->base + SR, val,
85	val & SR_LOCKED, 1, 100);
86	}
87
88	return ret;
89	}
90
91	static unsigned long clk_wzrd_set_rate(struct clk *clk, ulong rate)
92	{
93	struct clkwzd *priv = dev_get_priv(clk->dev);
94	u64 div;
95	u32 cfg;
96
97	/* Get output clock divide value */
98	div = DIV_ROUND_DOWN_ULL(priv->vco_clk * 1000, rate);
99	if (div < 1000 \|\| div > 255999)
100	return -EINVAL;
101
102	cfg = OUT_DIV((u32)div / 1000);
103
104	writel(cfg, priv->base + OUT_CFG(clk->id));
105
106	return 0;
107	}
108
109	static struct clk_ops clk_wzrd_ops = {
110	.enable = clk_wzrd_enable,
111	.set_rate = clk_wzrd_set_rate,
112	};
113
114	static int clk_wzrd_probe(struct udevice *dev)
115	{
116	struct clkwzd_plat *plat = dev_get_plat(dev);
117	struct clkwzd *priv = dev_get_priv(dev);
118	struct clk clk_in1;
119	u64 clock, vco_clk;
120	u32 cfg;
121	int ret;
122
123	priv->base = (void *)plat->addr;
124
125	ret = clk_get_by_name(dev, "clk_in1", &clk_in1);
126	if (ret < 0) {
127	dev_err(dev, "failed to get clock\n");
128	return ret;
129	}
130
131	clock = clk_get_rate(&clk_in1);
132	if (IS_ERR_VALUE(clock)) {
133	dev_err(dev, "failed to get rate\n");
134	return clock;
135	}
136
137	ret = clk_enable(&clk_in1);
138	if (ret) {
139	dev_err(dev, "failed to enable clock\n");
2b157d81 Z	140	return ret;
	141	}
	142
	143	/* Read clock configuration registers */
	144	cfg = readl(priv->base + FBOUT_CFG);
	145
	146	/* Recalculate VCO rate */
	147	if (cfg & FBOUT_FRAC_EN)
	148	vco_clk = DIV_ROUND_DOWN_ULL(clock *
	149	((FBOUT_GET_MUL(cfg) * 1000) +
	150	FBOUT_GET_FRAC(cfg)),
	151	1000);
	152	else
	153	vco_clk = clock * FBOUT_GET_MUL(cfg);
	154
	155	priv->vco_clk = DIV_ROUND_DOWN_ULL(vco_clk, FBOUT_GET_DIV(cfg));
	156
	157	return 0;
	158	}
	159
	160	static int clk_wzrd_of_to_plat(struct udevice *dev)
	161	{
	162	struct clkwzd_plat *plat = dev_get_plat(dev);
	163
	164	plat->addr = dev_read_addr(dev);
	165	if (plat->addr == FDT_ADDR_T_NONE)
	166	return -EINVAL;
	167
	168	return 0;
	169	}
	170
	171	static const struct udevice_id clk_wzrd_ids[] = {
	172	{ .compatible = "xlnx,clocking-wizard" },
	173	{ /* sentinel */ }
	174	};
	175
	176	U_BOOT_DRIVER(clk_wzrd) = {
	177	.name = "zynq-clk-wizard",
	178	.id = UCLASS_CLK,
	179	.of_match = clk_wzrd_ids,
	180	.ops = &clk_wzrd_ops,
	181	.probe = clk_wzrd_probe,
	182	.of_to_plat = clk_wzrd_of_to_plat,
	183	.priv_auto = sizeof(struct clkwzd),
	184	.plat_auto = sizeof(struct clkwzd_plat),
	185	};