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Commit | Line | Data |
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e66c49fa | 1 | /* |
3bc599c9 PC |
2 | * Copyright (C) 2017, STMicroelectronics - All Rights Reserved |
3 | * Author(s): Vikas Manocha, <vikas.manocha@st.com> for STMicroelectronics. | |
e66c49fa VM |
4 | * |
5 | * SPDX-License-Identifier: GPL-2.0+ | |
6 | */ | |
3bc599c9 | 7 | |
e66c49fa | 8 | #include <common.h> |
712f99a5 VM |
9 | #include <clk-uclass.h> |
10 | #include <dm.h> | |
d0a768b1 | 11 | |
e66c49fa VM |
12 | #include <asm/io.h> |
13 | #include <asm/arch/rcc.h> | |
14 | #include <asm/arch/stm32.h> | |
15 | #include <asm/arch/stm32_periph.h> | |
d0a768b1 | 16 | #include <asm/arch/stm32_pwr.h> |
e66c49fa | 17 | |
288f17e6 PC |
18 | #include <dt-bindings/mfd/stm32f7-rcc.h> |
19 | ||
bad5188b MK |
20 | #define RCC_CR_HSION BIT(0) |
21 | #define RCC_CR_HSEON BIT(16) | |
22 | #define RCC_CR_HSERDY BIT(17) | |
23 | #define RCC_CR_HSEBYP BIT(18) | |
24 | #define RCC_CR_CSSON BIT(19) | |
25 | #define RCC_CR_PLLON BIT(24) | |
26 | #define RCC_CR_PLLRDY BIT(25) | |
ba0a3c16 | 27 | |
bad5188b MK |
28 | #define RCC_PLLCFGR_PLLM_MASK GENMASK(5, 0) |
29 | #define RCC_PLLCFGR_PLLN_MASK GENMASK(14, 6) | |
30 | #define RCC_PLLCFGR_PLLP_MASK GENMASK(17, 16) | |
31 | #define RCC_PLLCFGR_PLLQ_MASK GENMASK(27, 24) | |
32 | #define RCC_PLLCFGR_PLLSRC BIT(22) | |
33 | #define RCC_PLLCFGR_PLLM_SHIFT 0 | |
34 | #define RCC_PLLCFGR_PLLN_SHIFT 6 | |
35 | #define RCC_PLLCFGR_PLLP_SHIFT 16 | |
36 | #define RCC_PLLCFGR_PLLQ_SHIFT 24 | |
ba0a3c16 | 37 | |
bad5188b MK |
38 | #define RCC_CFGR_AHB_PSC_MASK GENMASK(7, 4) |
39 | #define RCC_CFGR_APB1_PSC_MASK GENMASK(12, 10) | |
40 | #define RCC_CFGR_APB2_PSC_MASK GENMASK(15, 13) | |
41 | #define RCC_CFGR_SW0 BIT(0) | |
42 | #define RCC_CFGR_SW1 BIT(1) | |
43 | #define RCC_CFGR_SW_MASK GENMASK(1, 0) | |
44 | #define RCC_CFGR_SW_HSI 0 | |
45 | #define RCC_CFGR_SW_HSE RCC_CFGR_SW0 | |
46 | #define RCC_CFGR_SW_PLL RCC_CFGR_SW1 | |
47 | #define RCC_CFGR_SWS0 BIT(2) | |
48 | #define RCC_CFGR_SWS1 BIT(3) | |
49 | #define RCC_CFGR_SWS_MASK GENMASK(3, 2) | |
50 | #define RCC_CFGR_SWS_HSI 0 | |
51 | #define RCC_CFGR_SWS_HSE RCC_CFGR_SWS0 | |
52 | #define RCC_CFGR_SWS_PLL RCC_CFGR_SWS1 | |
53 | #define RCC_CFGR_HPRE_SHIFT 4 | |
54 | #define RCC_CFGR_PPRE1_SHIFT 10 | |
55 | #define RCC_CFGR_PPRE2_SHIFT 13 | |
ba0a3c16 | 56 | |
ba0a3c16 TN |
57 | |
58 | struct pll_psc { | |
59 | u8 pll_m; | |
60 | u16 pll_n; | |
61 | u8 pll_p; | |
62 | u8 pll_q; | |
63 | u8 ahb_psc; | |
64 | u8 apb1_psc; | |
65 | u8 apb2_psc; | |
66 | }; | |
67 | ||
bad5188b MK |
68 | #define AHB_PSC_1 0 |
69 | #define AHB_PSC_2 0x8 | |
70 | #define AHB_PSC_4 0x9 | |
71 | #define AHB_PSC_8 0xA | |
72 | #define AHB_PSC_16 0xB | |
73 | #define AHB_PSC_64 0xC | |
74 | #define AHB_PSC_128 0xD | |
75 | #define AHB_PSC_256 0xE | |
76 | #define AHB_PSC_512 0xF | |
ba0a3c16 | 77 | |
bad5188b MK |
78 | #define APB_PSC_1 0 |
79 | #define APB_PSC_2 0x4 | |
80 | #define APB_PSC_4 0x5 | |
81 | #define APB_PSC_8 0x6 | |
82 | #define APB_PSC_16 0x7 | |
ba0a3c16 | 83 | |
f9333c93 PC |
84 | struct stm32_clk_info { |
85 | struct pll_psc sys_pll_psc; | |
86 | bool has_overdrive; | |
87 | }; | |
88 | ||
89 | struct stm32_clk_info stm32f4_clk_info = { | |
90 | /* 180 MHz */ | |
91 | .sys_pll_psc = { | |
92 | .pll_m = 8, | |
93 | .pll_n = 360, | |
94 | .pll_p = 2, | |
95 | .pll_q = 8, | |
96 | .ahb_psc = AHB_PSC_1, | |
97 | .apb1_psc = APB_PSC_4, | |
98 | .apb2_psc = APB_PSC_2, | |
99 | }, | |
100 | .has_overdrive = false, | |
101 | }; | |
102 | ||
103 | struct stm32_clk_info stm32f7_clk_info = { | |
104 | /* 200 MHz */ | |
105 | .sys_pll_psc = { | |
106 | .pll_m = 25, | |
107 | .pll_n = 400, | |
108 | .pll_p = 2, | |
109 | .pll_q = 8, | |
110 | .ahb_psc = AHB_PSC_1, | |
111 | .apb1_psc = APB_PSC_4, | |
112 | .apb2_psc = APB_PSC_2, | |
113 | }, | |
114 | .has_overdrive = true, | |
115 | }; | |
116 | ||
199a2178 PC |
117 | struct stm32_clk { |
118 | struct stm32_rcc_regs *base; | |
d0a768b1 | 119 | struct stm32_pwr_regs *pwr_regs; |
f9333c93 | 120 | struct stm32_clk_info *info; |
199a2178 PC |
121 | }; |
122 | ||
199a2178 | 123 | static int configure_clocks(struct udevice *dev) |
ba0a3c16 | 124 | { |
199a2178 PC |
125 | struct stm32_clk *priv = dev_get_priv(dev); |
126 | struct stm32_rcc_regs *regs = priv->base; | |
d0a768b1 | 127 | struct stm32_pwr_regs *pwr = priv->pwr_regs; |
f9333c93 | 128 | struct pll_psc sys_pll_psc = priv->info->sys_pll_psc; |
199a2178 | 129 | |
ba0a3c16 | 130 | /* Reset RCC configuration */ |
199a2178 PC |
131 | setbits_le32(®s->cr, RCC_CR_HSION); |
132 | writel(0, ®s->cfgr); /* Reset CFGR */ | |
133 | clrbits_le32(®s->cr, (RCC_CR_HSEON | RCC_CR_CSSON | |
ba0a3c16 | 134 | | RCC_CR_PLLON)); |
199a2178 PC |
135 | writel(0x24003010, ®s->pllcfgr); /* Reset value from RM */ |
136 | clrbits_le32(®s->cr, RCC_CR_HSEBYP); | |
137 | writel(0, ®s->cir); /* Disable all interrupts */ | |
ba0a3c16 TN |
138 | |
139 | /* Configure for HSE+PLL operation */ | |
199a2178 PC |
140 | setbits_le32(®s->cr, RCC_CR_HSEON); |
141 | while (!(readl(®s->cr) & RCC_CR_HSERDY)) | |
ba0a3c16 TN |
142 | ; |
143 | ||
199a2178 | 144 | setbits_le32(®s->cfgr, (( |
ba0a3c16 TN |
145 | sys_pll_psc.ahb_psc << RCC_CFGR_HPRE_SHIFT) |
146 | | (sys_pll_psc.apb1_psc << RCC_CFGR_PPRE1_SHIFT) | |
147 | | (sys_pll_psc.apb2_psc << RCC_CFGR_PPRE2_SHIFT))); | |
148 | ||
149 | /* Configure the main PLL */ | |
1543bf79 PC |
150 | setbits_le32(®s->pllcfgr, RCC_PLLCFGR_PLLSRC); /* pll source HSE */ |
151 | clrsetbits_le32(®s->pllcfgr, RCC_PLLCFGR_PLLM_MASK, | |
152 | sys_pll_psc.pll_m << RCC_PLLCFGR_PLLM_SHIFT); | |
153 | clrsetbits_le32(®s->pllcfgr, RCC_PLLCFGR_PLLN_MASK, | |
154 | sys_pll_psc.pll_n << RCC_PLLCFGR_PLLN_SHIFT); | |
155 | clrsetbits_le32(®s->pllcfgr, RCC_PLLCFGR_PLLP_MASK, | |
156 | ((sys_pll_psc.pll_p >> 1) - 1) << RCC_PLLCFGR_PLLP_SHIFT); | |
157 | clrsetbits_le32(®s->pllcfgr, RCC_PLLCFGR_PLLQ_MASK, | |
158 | sys_pll_psc.pll_q << RCC_PLLCFGR_PLLQ_SHIFT); | |
ba0a3c16 TN |
159 | |
160 | /* Enable the main PLL */ | |
199a2178 PC |
161 | setbits_le32(®s->cr, RCC_CR_PLLON); |
162 | while (!(readl(®s->cr) & RCC_CR_PLLRDY)) | |
ba0a3c16 TN |
163 | ; |
164 | ||
199a2178 | 165 | setbits_le32(®s->apb1enr, RCC_APB1ENR_PWREN); |
f9333c93 PC |
166 | |
167 | if (priv->info->has_overdrive) { | |
168 | /* | |
169 | * Enable high performance mode | |
170 | * System frequency up to 200 MHz | |
171 | */ | |
172 | setbits_le32(&pwr->cr1, PWR_CR1_ODEN); | |
173 | /* Infinite wait! */ | |
174 | while (!(readl(&pwr->csr1) & PWR_CSR1_ODRDY)) | |
175 | ; | |
176 | /* Enable the Over-drive switch */ | |
177 | setbits_le32(&pwr->cr1, PWR_CR1_ODSWEN); | |
178 | /* Infinite wait! */ | |
179 | while (!(readl(&pwr->csr1) & PWR_CSR1_ODSWRDY)) | |
180 | ; | |
181 | } | |
ba0a3c16 TN |
182 | |
183 | stm32_flash_latency_cfg(5); | |
199a2178 PC |
184 | clrbits_le32(®s->cfgr, (RCC_CFGR_SW0 | RCC_CFGR_SW1)); |
185 | setbits_le32(®s->cfgr, RCC_CFGR_SW_PLL); | |
ba0a3c16 | 186 | |
199a2178 | 187 | while ((readl(®s->cfgr) & RCC_CFGR_SWS_MASK) != |
ba0a3c16 TN |
188 | RCC_CFGR_SWS_PLL) |
189 | ; | |
190 | ||
191 | return 0; | |
192 | } | |
193 | ||
288f17e6 PC |
194 | static unsigned long stm32_clk_get_rate(struct clk *clk) |
195 | { | |
196 | struct stm32_clk *priv = dev_get_priv(clk->dev); | |
197 | struct stm32_rcc_regs *regs = priv->base; | |
198 | u32 sysclk = 0; | |
199 | u32 shift = 0; | |
f264e235 | 200 | u16 pllm, plln, pllp; |
288f17e6 PC |
201 | /* Prescaler table lookups for clock computation */ |
202 | u8 ahb_psc_table[16] = { | |
203 | 0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9 | |
204 | }; | |
205 | u8 apb_psc_table[8] = { | |
206 | 0, 0, 0, 0, 1, 2, 3, 4 | |
207 | }; | |
208 | ||
209 | if ((readl(®s->cfgr) & RCC_CFGR_SWS_MASK) == | |
210 | RCC_CFGR_SWS_PLL) { | |
288f17e6 PC |
211 | pllm = (readl(®s->pllcfgr) & RCC_PLLCFGR_PLLM_MASK); |
212 | plln = ((readl(®s->pllcfgr) & RCC_PLLCFGR_PLLN_MASK) | |
213 | >> RCC_PLLCFGR_PLLN_SHIFT); | |
214 | pllp = ((((readl(®s->pllcfgr) & RCC_PLLCFGR_PLLP_MASK) | |
215 | >> RCC_PLLCFGR_PLLP_SHIFT) + 1) << 1); | |
216 | sysclk = ((CONFIG_STM32_HSE_HZ / pllm) * plln) / pllp; | |
217 | } else { | |
218 | return -EINVAL; | |
219 | } | |
220 | ||
221 | switch (clk->id) { | |
222 | /* | |
223 | * AHB CLOCK: 3 x 32 bits consecutive registers are used : | |
224 | * AHB1, AHB2 and AHB3 | |
225 | */ | |
226 | case STM32F7_AHB1_CLOCK(GPIOA) ... STM32F7_AHB3_CLOCK(QSPI): | |
227 | shift = ahb_psc_table[( | |
228 | (readl(®s->cfgr) & RCC_CFGR_AHB_PSC_MASK) | |
229 | >> RCC_CFGR_HPRE_SHIFT)]; | |
230 | return sysclk >>= shift; | |
288f17e6 PC |
231 | /* APB1 CLOCK */ |
232 | case STM32F7_APB1_CLOCK(TIM2) ... STM32F7_APB1_CLOCK(UART8): | |
233 | shift = apb_psc_table[( | |
234 | (readl(®s->cfgr) & RCC_CFGR_APB1_PSC_MASK) | |
235 | >> RCC_CFGR_PPRE1_SHIFT)]; | |
236 | return sysclk >>= shift; | |
288f17e6 PC |
237 | /* APB2 CLOCK */ |
238 | case STM32F7_APB2_CLOCK(TIM1) ... STM32F7_APB2_CLOCK(LTDC): | |
239 | shift = apb_psc_table[( | |
240 | (readl(®s->cfgr) & RCC_CFGR_APB2_PSC_MASK) | |
241 | >> RCC_CFGR_PPRE2_SHIFT)]; | |
242 | return sysclk >>= shift; | |
288f17e6 | 243 | default: |
9b643e31 | 244 | pr_err("clock index %ld out of range\n", clk->id); |
288f17e6 | 245 | return -EINVAL; |
288f17e6 PC |
246 | } |
247 | } | |
248 | ||
712f99a5 VM |
249 | static int stm32_clk_enable(struct clk *clk) |
250 | { | |
199a2178 PC |
251 | struct stm32_clk *priv = dev_get_priv(clk->dev); |
252 | struct stm32_rcc_regs *regs = priv->base; | |
712f99a5 VM |
253 | u32 offset = clk->id / 32; |
254 | u32 bit_index = clk->id % 32; | |
255 | ||
256 | debug("%s: clkid = %ld, offset from AHB1ENR is %d, bit_index = %d\n", | |
257 | __func__, clk->id, offset, bit_index); | |
199a2178 | 258 | setbits_le32(®s->ahb1enr + offset, BIT(bit_index)); |
712f99a5 VM |
259 | |
260 | return 0; | |
261 | } | |
ba0a3c16 | 262 | |
e66c49fa VM |
263 | void clock_setup(int peripheral) |
264 | { | |
265 | switch (peripheral) { | |
081de09d MK |
266 | case SYSCFG_CLOCK_CFG: |
267 | setbits_le32(&STM32_RCC->apb2enr, RCC_APB2ENR_SYSCFGEN); | |
268 | break; | |
269 | case TIMER2_CLOCK_CFG: | |
270 | setbits_le32(&STM32_RCC->apb1enr, RCC_APB1ENR_TIM2EN); | |
271 | break; | |
b20b70fc MK |
272 | case STMMAC_CLOCK_CFG: |
273 | setbits_le32(&STM32_RCC->ahb1enr, RCC_AHB1ENR_ETHMAC_EN); | |
274 | setbits_le32(&STM32_RCC->ahb1enr, RCC_AHB1ENR_ETHMAC_RX_EN); | |
275 | setbits_le32(&STM32_RCC->ahb1enr, RCC_AHB1ENR_ETHMAC_TX_EN); | |
276 | break; | |
e66c49fa VM |
277 | default: |
278 | break; | |
279 | } | |
280 | } | |
712f99a5 VM |
281 | |
282 | static int stm32_clk_probe(struct udevice *dev) | |
283 | { | |
d0a768b1 PC |
284 | struct ofnode_phandle_args args; |
285 | int err; | |
286 | ||
f264e235 | 287 | debug("%s\n", __func__); |
199a2178 PC |
288 | |
289 | struct stm32_clk *priv = dev_get_priv(dev); | |
290 | fdt_addr_t addr; | |
291 | ||
f9333c93 | 292 | addr = dev_read_addr(dev); |
199a2178 PC |
293 | if (addr == FDT_ADDR_T_NONE) |
294 | return -EINVAL; | |
295 | ||
296 | priv->base = (struct stm32_rcc_regs *)addr; | |
f9333c93 PC |
297 | priv->info = (struct stm32_clk_info *)dev_get_driver_data(dev); |
298 | ||
299 | if (priv->info->has_overdrive) { | |
300 | err = dev_read_phandle_with_args(dev, "st,syscfg", NULL, 0, 0, | |
301 | &args); | |
302 | if (err) { | |
303 | debug("%s: can't find syscon device (%d)\n", __func__, | |
304 | err); | |
305 | return err; | |
306 | } | |
307 | ||
308 | priv->pwr_regs = (struct stm32_pwr_regs *)ofnode_get_addr(args.node); | |
d0a768b1 PC |
309 | } |
310 | ||
199a2178 | 311 | configure_clocks(dev); |
712f99a5 VM |
312 | |
313 | return 0; | |
314 | } | |
315 | ||
a4e0ef50 | 316 | static int stm32_clk_of_xlate(struct clk *clk, struct ofnode_phandle_args *args) |
712f99a5 VM |
317 | { |
318 | debug("%s(clk=%p)\n", __func__, clk); | |
319 | ||
320 | if (args->args_count != 2) { | |
321 | debug("Invaild args_count: %d\n", args->args_count); | |
322 | return -EINVAL; | |
323 | } | |
324 | ||
325 | if (args->args_count) | |
326 | clk->id = args->args[1]; | |
327 | else | |
328 | clk->id = 0; | |
329 | ||
330 | return 0; | |
331 | } | |
332 | ||
333 | static struct clk_ops stm32_clk_ops = { | |
334 | .of_xlate = stm32_clk_of_xlate, | |
335 | .enable = stm32_clk_enable, | |
288f17e6 | 336 | .get_rate = stm32_clk_get_rate, |
712f99a5 VM |
337 | }; |
338 | ||
339 | static const struct udevice_id stm32_clk_ids[] = { | |
f9333c93 PC |
340 | { .compatible = "st,stm32f42xx-rcc", .data = (ulong)&stm32f4_clk_info}, |
341 | { .compatible = "st,stm32f746-rcc", .data = (ulong)&stm32f7_clk_info}, | |
712f99a5 VM |
342 | {} |
343 | }; | |
344 | ||
f264e235 PC |
345 | U_BOOT_DRIVER(stm32fx_clk) = { |
346 | .name = "stm32fx_clk", | |
0cc40dfc PC |
347 | .id = UCLASS_CLK, |
348 | .of_match = stm32_clk_ids, | |
349 | .ops = &stm32_clk_ops, | |
350 | .probe = stm32_clk_probe, | |
351 | .priv_auto_alloc_size = sizeof(struct stm32_clk), | |
352 | .flags = DM_FLAG_PRE_RELOC, | |
712f99a5 | 353 | }; |