[people/ms/u-boot.git] / drivers / clk / clk_stm32f7.c

/*
 * Copyright (C) 2017, STMicroelectronics - All Rights Reserved
 * Author(s): Vikas Manocha, <vikas.manocha@st.com> for STMicroelectronics.
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#include <common.h>
#include <clk-uclass.h>
#include <dm.h>
#include <asm/io.h>
#include <asm/arch/rcc.h>
#include <asm/arch/stm32.h>
#include <asm/arch/stm32_periph.h>

#include <dt-bindings/mfd/stm32f7-rcc.h>

#define RCC_CR_HSION			BIT(0)
#define RCC_CR_HSEON			BIT(16)
#define RCC_CR_HSERDY			BIT(17)
#define RCC_CR_HSEBYP			BIT(18)
#define RCC_CR_CSSON			BIT(19)
#define RCC_CR_PLLON			BIT(24)
#define RCC_CR_PLLRDY			BIT(25)

#define RCC_PLLCFGR_PLLM_MASK		GENMASK(5, 0)
#define RCC_PLLCFGR_PLLN_MASK		GENMASK(14, 6)
#define RCC_PLLCFGR_PLLP_MASK		GENMASK(17, 16)
#define RCC_PLLCFGR_PLLQ_MASK		GENMASK(27, 24)
#define RCC_PLLCFGR_PLLSRC		BIT(22)
#define RCC_PLLCFGR_PLLM_SHIFT		0
#define RCC_PLLCFGR_PLLN_SHIFT		6
#define RCC_PLLCFGR_PLLP_SHIFT		16
#define RCC_PLLCFGR_PLLQ_SHIFT		24

#define RCC_CFGR_AHB_PSC_MASK		GENMASK(7, 4)
#define RCC_CFGR_APB1_PSC_MASK		GENMASK(12, 10)
#define RCC_CFGR_APB2_PSC_MASK		GENMASK(15, 13)
#define RCC_CFGR_SW0			BIT(0)
#define RCC_CFGR_SW1			BIT(1)
#define RCC_CFGR_SW_MASK		GENMASK(1, 0)
#define RCC_CFGR_SW_HSI			0
#define RCC_CFGR_SW_HSE			RCC_CFGR_SW0
#define RCC_CFGR_SW_PLL			RCC_CFGR_SW1
#define RCC_CFGR_SWS0			BIT(2)
#define RCC_CFGR_SWS1			BIT(3)
#define RCC_CFGR_SWS_MASK		GENMASK(3, 2)
#define RCC_CFGR_SWS_HSI		0
#define RCC_CFGR_SWS_HSE		RCC_CFGR_SWS0
#define RCC_CFGR_SWS_PLL		RCC_CFGR_SWS1
#define RCC_CFGR_HPRE_SHIFT		4
#define RCC_CFGR_PPRE1_SHIFT		10
#define RCC_CFGR_PPRE2_SHIFT		13

/*
 * Offsets of some PWR registers
 */
#define PWR_CR1_ODEN			BIT(16)
#define PWR_CR1_ODSWEN			BIT(17)
#define PWR_CSR1_ODRDY			BIT(16)
#define PWR_CSR1_ODSWRDY		BIT(17)

struct pll_psc {
	u8	pll_m;
	u16	pll_n;
	u8	pll_p;
	u8	pll_q;
	u8	ahb_psc;
	u8	apb1_psc;
	u8	apb2_psc;
};

#define AHB_PSC_1			0
#define AHB_PSC_2			0x8
#define AHB_PSC_4			0x9
#define AHB_PSC_8			0xA
#define AHB_PSC_16			0xB
#define AHB_PSC_64			0xC
#define AHB_PSC_128			0xD
#define AHB_PSC_256			0xE
#define AHB_PSC_512			0xF

#define APB_PSC_1			0
#define APB_PSC_2			0x4
#define APB_PSC_4			0x5
#define APB_PSC_8			0x6
#define APB_PSC_16			0x7

struct stm32_clk {
	struct stm32_rcc_regs *base;
};

#if !defined(CONFIG_STM32_HSE_HZ)
#error "CONFIG_STM32_HSE_HZ not defined!"
#else
#if (CONFIG_STM32_HSE_HZ == 25000000)
#if (CONFIG_SYS_CLK_FREQ == 200000000)
/* 200 MHz */
struct pll_psc sys_pll_psc = {
	.pll_m = 25,
	.pll_n = 400,
	.pll_p = 2,
	.pll_q = 8,
	.ahb_psc = AHB_PSC_1,
	.apb1_psc = APB_PSC_4,
	.apb2_psc = APB_PSC_2
};
#endif
#else
#error "No PLL/Prescaler configuration for given CONFIG_STM32_HSE_HZ exists"
#endif
#endif

static int configure_clocks(struct udevice *dev)
{
	struct stm32_clk *priv = dev_get_priv(dev);
	struct stm32_rcc_regs *regs = priv->base;

	/* Reset RCC configuration */
	setbits_le32(&regs->cr, RCC_CR_HSION);
	writel(0, &regs->cfgr); /* Reset CFGR */
	clrbits_le32(&regs->cr, (RCC_CR_HSEON | RCC_CR_CSSON
		| RCC_CR_PLLON));
	writel(0x24003010, &regs->pllcfgr); /* Reset value from RM */
	clrbits_le32(&regs->cr, RCC_CR_HSEBYP);
	writel(0, &regs->cir); /* Disable all interrupts */

	/* Configure for HSE+PLL operation */
	setbits_le32(&regs->cr, RCC_CR_HSEON);
	while (!(readl(&regs->cr) & RCC_CR_HSERDY))
		;

	setbits_le32(&regs->cfgr, ((
		sys_pll_psc.ahb_psc << RCC_CFGR_HPRE_SHIFT)
		| (sys_pll_psc.apb1_psc << RCC_CFGR_PPRE1_SHIFT)
		| (sys_pll_psc.apb2_psc << RCC_CFGR_PPRE2_SHIFT)));

	/* Configure the main PLL */
	setbits_le32(&regs->pllcfgr, RCC_PLLCFGR_PLLSRC); /* pll source HSE */
	clrsetbits_le32(&regs->pllcfgr, RCC_PLLCFGR_PLLM_MASK,
			sys_pll_psc.pll_m << RCC_PLLCFGR_PLLM_SHIFT);
	clrsetbits_le32(&regs->pllcfgr, RCC_PLLCFGR_PLLN_MASK,
			sys_pll_psc.pll_n << RCC_PLLCFGR_PLLN_SHIFT);
	clrsetbits_le32(&regs->pllcfgr, RCC_PLLCFGR_PLLP_MASK,
			((sys_pll_psc.pll_p >> 1) - 1) << RCC_PLLCFGR_PLLP_SHIFT);
	clrsetbits_le32(&regs->pllcfgr, RCC_PLLCFGR_PLLQ_MASK,
			sys_pll_psc.pll_q << RCC_PLLCFGR_PLLQ_SHIFT);

	/* Enable the main PLL */
	setbits_le32(&regs->cr, RCC_CR_PLLON);
	while (!(readl(&regs->cr) & RCC_CR_PLLRDY))
		;

	/* Enable high performance mode, System frequency up to 200 MHz */
	setbits_le32(&regs->apb1enr, RCC_APB1ENR_PWREN);
	setbits_le32(&STM32_PWR->cr1, PWR_CR1_ODEN);
	/* Infinite wait! */
	while (!(readl(&STM32_PWR->csr1) & PWR_CSR1_ODRDY))
		;
	/* Enable the Over-drive switch */
	setbits_le32(&STM32_PWR->cr1, PWR_CR1_ODSWEN);
	/* Infinite wait! */
	while (!(readl(&STM32_PWR->csr1) & PWR_CSR1_ODSWRDY))
		;

	stm32_flash_latency_cfg(5);
	clrbits_le32(&regs->cfgr, (RCC_CFGR_SW0 | RCC_CFGR_SW1));
	setbits_le32(&regs->cfgr, RCC_CFGR_SW_PLL);

	while ((readl(&regs->cfgr) & RCC_CFGR_SWS_MASK) !=
			RCC_CFGR_SWS_PLL)
		;

	return 0;
}

static unsigned long stm32_clk_get_rate(struct clk *clk)
{
	struct stm32_clk *priv = dev_get_priv(clk->dev);
	struct stm32_rcc_regs *regs = priv->base;
	u32 sysclk = 0;
	u32 shift = 0;
	/* Prescaler table lookups for clock computation */
	u8 ahb_psc_table[16] = {
		0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9
	};
	u8 apb_psc_table[8] = {
		0, 0, 0, 0, 1, 2, 3, 4
	};

	if ((readl(&regs->cfgr) & RCC_CFGR_SWS_MASK) ==
			RCC_CFGR_SWS_PLL) {
		u16 pllm, plln, pllp;
		pllm = (readl(&regs->pllcfgr) & RCC_PLLCFGR_PLLM_MASK);
		plln = ((readl(&regs->pllcfgr) & RCC_PLLCFGR_PLLN_MASK)
			>> RCC_PLLCFGR_PLLN_SHIFT);
		pllp = ((((readl(&regs->pllcfgr) & RCC_PLLCFGR_PLLP_MASK)
			>> RCC_PLLCFGR_PLLP_SHIFT) + 1) << 1);
		sysclk = ((CONFIG_STM32_HSE_HZ / pllm) * plln) / pllp;
	} else {
		return -EINVAL;
	}

	switch (clk->id) {
	/*
	 * AHB CLOCK: 3 x 32 bits consecutive registers are used :
	 * AHB1, AHB2 and AHB3
	 */
	case STM32F7_AHB1_CLOCK(GPIOA) ... STM32F7_AHB3_CLOCK(QSPI):
		shift = ahb_psc_table[(
			(readl(&regs->cfgr) & RCC_CFGR_AHB_PSC_MASK)
			>> RCC_CFGR_HPRE_SHIFT)];
		return sysclk >>= shift;
		break;
	/* APB1 CLOCK */
	case STM32F7_APB1_CLOCK(TIM2) ... STM32F7_APB1_CLOCK(UART8):
		shift = apb_psc_table[(
			(readl(&regs->cfgr) & RCC_CFGR_APB1_PSC_MASK)
			>> RCC_CFGR_PPRE1_SHIFT)];
		return sysclk >>= shift;
		break;
	/* APB2 CLOCK */
	case STM32F7_APB2_CLOCK(TIM1) ... STM32F7_APB2_CLOCK(LTDC):
		shift = apb_psc_table[(
			(readl(&regs->cfgr) & RCC_CFGR_APB2_PSC_MASK)
			>> RCC_CFGR_PPRE2_SHIFT)];
		return sysclk >>= shift;
		break;
	default:
		pr_err("clock index %ld out of range\n", clk->id);
		return -EINVAL;
		break;
	}
}

static int stm32_clk_enable(struct clk *clk)
{
	struct stm32_clk *priv = dev_get_priv(clk->dev);
	struct stm32_rcc_regs *regs = priv->base;
	u32 offset = clk->id / 32;
	u32 bit_index = clk->id % 32;

	debug("%s: clkid = %ld, offset from AHB1ENR is %d, bit_index = %d\n",
	      __func__, clk->id, offset, bit_index);
	setbits_le32(&regs->ahb1enr + offset, BIT(bit_index));

	return 0;
}

void clock_setup(int peripheral)
{
	switch (peripheral) {
	case SYSCFG_CLOCK_CFG:
		setbits_le32(&STM32_RCC->apb2enr, RCC_APB2ENR_SYSCFGEN);
		break;
	case TIMER2_CLOCK_CFG:
		setbits_le32(&STM32_RCC->apb1enr, RCC_APB1ENR_TIM2EN);
		break;
	case STMMAC_CLOCK_CFG:
		setbits_le32(&STM32_RCC->ahb1enr, RCC_AHB1ENR_ETHMAC_EN);
		setbits_le32(&STM32_RCC->ahb1enr, RCC_AHB1ENR_ETHMAC_RX_EN);
		setbits_le32(&STM32_RCC->ahb1enr, RCC_AHB1ENR_ETHMAC_TX_EN);
		break;
	default:
		break;
	}
}

static int stm32_clk_probe(struct udevice *dev)
{
	debug("%s: stm32_clk_probe\n", __func__);

	struct stm32_clk *priv = dev_get_priv(dev);
	fdt_addr_t addr;

	addr = devfdt_get_addr(dev);
	if (addr == FDT_ADDR_T_NONE)
		return -EINVAL;

	priv->base = (struct stm32_rcc_regs *)addr;

	configure_clocks(dev);

	return 0;
}

static int stm32_clk_of_xlate(struct clk *clk, struct ofnode_phandle_args *args)
{
	debug("%s(clk=%p)\n", __func__, clk);

	if (args->args_count != 2) {
		debug("Invaild args_count: %d\n", args->args_count);
		return -EINVAL;
	}

	if (args->args_count)
		clk->id = args->args[1];
	else
		clk->id = 0;

	return 0;
}

static struct clk_ops stm32_clk_ops = {
	.of_xlate	= stm32_clk_of_xlate,
	.enable		= stm32_clk_enable,
	.get_rate	= stm32_clk_get_rate,
};

static const struct udevice_id stm32_clk_ids[] = {
	{ .compatible = "st,stm32f42xx-rcc"},
	{}
};

U_BOOT_DRIVER(stm32f7_clk) = {
	.name			= "stm32f7_clk",
	.id			= UCLASS_CLK,
	.of_match		= stm32_clk_ids,
	.ops			= &stm32_clk_ops,
	.probe			= stm32_clk_probe,
	.priv_auto_alloc_size	= sizeof(struct stm32_clk),
	.flags			= DM_FLAG_PRE_RELOC,
};
Commit	Line	Data
e66c49fa	1	/*
3bc599c9 PC	2	* Copyright (C) 2017, STMicroelectronics - All Rights Reserved
3bc599c9 PC	3	* Author(s): Vikas Manocha, <vikas.manocha@st.com> for STMicroelectronics.
e66c49fa VM	4	*
	5	* SPDX-License-Identifier: GPL-2.0+
	6	*/
3bc599c9	7
e66c49fa	8	#include <common.h>
712f99a5 VM	9	#include <clk-uclass.h>
712f99a5 VM	10	#include <dm.h>
e66c49fa VM	11	#include <asm/io.h>
	12	#include <asm/arch/rcc.h>
	13	#include <asm/arch/stm32.h>
	14	#include <asm/arch/stm32_periph.h>
	15
288f17e6 PC	16	#include <dt-bindings/mfd/stm32f7-rcc.h>
288f17e6 PC	17
bad5188b MK	18	#define RCC_CR_HSION BIT(0)
	19	#define RCC_CR_HSEON BIT(16)
	20	#define RCC_CR_HSERDY BIT(17)
	21	#define RCC_CR_HSEBYP BIT(18)
	22	#define RCC_CR_CSSON BIT(19)
	23	#define RCC_CR_PLLON BIT(24)
	24	#define RCC_CR_PLLRDY BIT(25)
ba0a3c16	25
bad5188b MK	26	#define RCC_PLLCFGR_PLLM_MASK GENMASK(5, 0)
	27	#define RCC_PLLCFGR_PLLN_MASK GENMASK(14, 6)
	28	#define RCC_PLLCFGR_PLLP_MASK GENMASK(17, 16)
	29	#define RCC_PLLCFGR_PLLQ_MASK GENMASK(27, 24)
	30	#define RCC_PLLCFGR_PLLSRC BIT(22)
	31	#define RCC_PLLCFGR_PLLM_SHIFT 0
	32	#define RCC_PLLCFGR_PLLN_SHIFT 6
	33	#define RCC_PLLCFGR_PLLP_SHIFT 16
	34	#define RCC_PLLCFGR_PLLQ_SHIFT 24
ba0a3c16	35
bad5188b MK	36	#define RCC_CFGR_AHB_PSC_MASK GENMASK(7, 4)
	37	#define RCC_CFGR_APB1_PSC_MASK GENMASK(12, 10)
	38	#define RCC_CFGR_APB2_PSC_MASK GENMASK(15, 13)
	39	#define RCC_CFGR_SW0 BIT(0)
	40	#define RCC_CFGR_SW1 BIT(1)
	41	#define RCC_CFGR_SW_MASK GENMASK(1, 0)
	42	#define RCC_CFGR_SW_HSI 0
	43	#define RCC_CFGR_SW_HSE RCC_CFGR_SW0
	44	#define RCC_CFGR_SW_PLL RCC_CFGR_SW1
	45	#define RCC_CFGR_SWS0 BIT(2)
	46	#define RCC_CFGR_SWS1 BIT(3)
	47	#define RCC_CFGR_SWS_MASK GENMASK(3, 2)
	48	#define RCC_CFGR_SWS_HSI 0
	49	#define RCC_CFGR_SWS_HSE RCC_CFGR_SWS0
	50	#define RCC_CFGR_SWS_PLL RCC_CFGR_SWS1
	51	#define RCC_CFGR_HPRE_SHIFT 4
	52	#define RCC_CFGR_PPRE1_SHIFT 10
	53	#define RCC_CFGR_PPRE2_SHIFT 13
ba0a3c16 TN	54
	55	/*
	56	* Offsets of some PWR registers
	57	*/
bad5188b MK	58	#define PWR_CR1_ODEN BIT(16)
	59	#define PWR_CR1_ODSWEN BIT(17)
	60	#define PWR_CSR1_ODRDY BIT(16)
	61	#define PWR_CSR1_ODSWRDY BIT(17)
ba0a3c16 TN	62
	63	struct pll_psc {
	64	u8 pll_m;
	65	u16 pll_n;
	66	u8 pll_p;
	67	u8 pll_q;
	68	u8 ahb_psc;
	69	u8 apb1_psc;
	70	u8 apb2_psc;
	71	};
	72
bad5188b MK	73	#define AHB_PSC_1 0
	74	#define AHB_PSC_2 0x8
	75	#define AHB_PSC_4 0x9
	76	#define AHB_PSC_8 0xA
	77	#define AHB_PSC_16 0xB
	78	#define AHB_PSC_64 0xC
	79	#define AHB_PSC_128 0xD
	80	#define AHB_PSC_256 0xE
	81	#define AHB_PSC_512 0xF
ba0a3c16	82
bad5188b MK	83	#define APB_PSC_1 0
	84	#define APB_PSC_2 0x4
	85	#define APB_PSC_4 0x5
	86	#define APB_PSC_8 0x6
	87	#define APB_PSC_16 0x7
ba0a3c16	88
199a2178 PC	89	struct stm32_clk {
	90	struct stm32_rcc_regs *base;
	91	};
	92
ba0a3c16 TN	93	#if !defined(CONFIG_STM32_HSE_HZ)
	94	#error "CONFIG_STM32_HSE_HZ not defined!"
	95	#else
	96	#if (CONFIG_STM32_HSE_HZ == 25000000)
	97	#if (CONFIG_SYS_CLK_FREQ == 200000000)
	98	/* 200 MHz */
	99	struct pll_psc sys_pll_psc = {
	100	.pll_m = 25,
	101	.pll_n = 400,
	102	.pll_p = 2,
	103	.pll_q = 8,
	104	.ahb_psc = AHB_PSC_1,
	105	.apb1_psc = APB_PSC_4,
	106	.apb2_psc = APB_PSC_2
	107	};
	108	#endif
	109	#else
	110	#error "No PLL/Prescaler configuration for given CONFIG_STM32_HSE_HZ exists"
	111	#endif
	112	#endif
	113
199a2178	114	static int configure_clocks(struct udevice *dev)
ba0a3c16	115	{
199a2178 PC	116	struct stm32_clk *priv = dev_get_priv(dev);
	117	struct stm32_rcc_regs *regs = priv->base;
	118
ba0a3c16	119	/* Reset RCC configuration */
199a2178 PC	120	setbits_le32(&regs->cr, RCC_CR_HSION);
	121	writel(0, &regs->cfgr); /* Reset CFGR */
	122	clrbits_le32(&regs->cr, (RCC_CR_HSEON \| RCC_CR_CSSON
ba0a3c16	123	\| RCC_CR_PLLON));
199a2178 PC	124	writel(0x24003010, &regs->pllcfgr); /* Reset value from RM */
	125	clrbits_le32(&regs->cr, RCC_CR_HSEBYP);
	126	writel(0, &regs->cir); /* Disable all interrupts */
ba0a3c16 TN	127
ba0a3c16 TN	128	/* Configure for HSE+PLL operation */
199a2178 PC	129	setbits_le32(&regs->cr, RCC_CR_HSEON);
199a2178 PC	130	while (!(readl(&regs->cr) & RCC_CR_HSERDY))
ba0a3c16 TN	131	;
ba0a3c16 TN	132
199a2178	133	setbits_le32(&regs->cfgr, ((
ba0a3c16 TN	134	sys_pll_psc.ahb_psc << RCC_CFGR_HPRE_SHIFT)
	135	\| (sys_pll_psc.apb1_psc << RCC_CFGR_PPRE1_SHIFT)
	136	\| (sys_pll_psc.apb2_psc << RCC_CFGR_PPRE2_SHIFT)));
	137
	138	/* Configure the main PLL */
1543bf79 PC	139	setbits_le32(&regs->pllcfgr, RCC_PLLCFGR_PLLSRC); /* pll source HSE */
	140	clrsetbits_le32(&regs->pllcfgr, RCC_PLLCFGR_PLLM_MASK,
	141	sys_pll_psc.pll_m << RCC_PLLCFGR_PLLM_SHIFT);
	142	clrsetbits_le32(&regs->pllcfgr, RCC_PLLCFGR_PLLN_MASK,
	143	sys_pll_psc.pll_n << RCC_PLLCFGR_PLLN_SHIFT);
	144	clrsetbits_le32(&regs->pllcfgr, RCC_PLLCFGR_PLLP_MASK,
	145	((sys_pll_psc.pll_p >> 1) - 1) << RCC_PLLCFGR_PLLP_SHIFT);
	146	clrsetbits_le32(&regs->pllcfgr, RCC_PLLCFGR_PLLQ_MASK,
	147	sys_pll_psc.pll_q << RCC_PLLCFGR_PLLQ_SHIFT);
ba0a3c16 TN	148
ba0a3c16 TN	149	/* Enable the main PLL */
199a2178 PC	150	setbits_le32(&regs->cr, RCC_CR_PLLON);
199a2178 PC	151	while (!(readl(&regs->cr) & RCC_CR_PLLRDY))
ba0a3c16 TN	152	;
	153
	154	/* Enable high performance mode, System frequency up to 200 MHz */
199a2178	155	setbits_le32(&regs->apb1enr, RCC_APB1ENR_PWREN);
ba0a3c16 TN	156	setbits_le32(&STM32_PWR->cr1, PWR_CR1_ODEN);
	157	/* Infinite wait! */
	158	while (!(readl(&STM32_PWR->csr1) & PWR_CSR1_ODRDY))
	159	;
	160	/* Enable the Over-drive switch */
	161	setbits_le32(&STM32_PWR->cr1, PWR_CR1_ODSWEN);
	162	/* Infinite wait! */
	163	while (!(readl(&STM32_PWR->csr1) & PWR_CSR1_ODSWRDY))
	164	;
	165
	166	stm32_flash_latency_cfg(5);
199a2178 PC	167	clrbits_le32(&regs->cfgr, (RCC_CFGR_SW0 \| RCC_CFGR_SW1));
199a2178 PC	168	setbits_le32(&regs->cfgr, RCC_CFGR_SW_PLL);
ba0a3c16	169
199a2178	170	while ((readl(&regs->cfgr) & RCC_CFGR_SWS_MASK) !=
ba0a3c16 TN	171	RCC_CFGR_SWS_PLL)
	172	;
	173
	174	return 0;
	175	}
	176
288f17e6 PC	177	static unsigned long stm32_clk_get_rate(struct clk *clk)
	178	{
	179	struct stm32_clk *priv = dev_get_priv(clk->dev);
	180	struct stm32_rcc_regs *regs = priv->base;
	181	u32 sysclk = 0;
	182	u32 shift = 0;
	183	/* Prescaler table lookups for clock computation */
	184	u8 ahb_psc_table[16] = {
	185	0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9
	186	};
	187	u8 apb_psc_table[8] = {
	188	0, 0, 0, 0, 1, 2, 3, 4
	189	};
	190
	191	if ((readl(&regs->cfgr) & RCC_CFGR_SWS_MASK) ==
	192	RCC_CFGR_SWS_PLL) {
	193	u16 pllm, plln, pllp;
	194	pllm = (readl(&regs->pllcfgr) & RCC_PLLCFGR_PLLM_MASK);
	195	plln = ((readl(&regs->pllcfgr) & RCC_PLLCFGR_PLLN_MASK)
	196	>> RCC_PLLCFGR_PLLN_SHIFT);
	197	pllp = ((((readl(&regs->pllcfgr) & RCC_PLLCFGR_PLLP_MASK)
	198	>> RCC_PLLCFGR_PLLP_SHIFT) + 1) << 1);
	199	sysclk = ((CONFIG_STM32_HSE_HZ / pllm) * plln) / pllp;
	200	} else {
	201	return -EINVAL;
	202	}
	203
	204	switch (clk->id) {
	205	/*
	206	* AHB CLOCK: 3 x 32 bits consecutive registers are used :
	207	* AHB1, AHB2 and AHB3
	208	*/
	209	case STM32F7_AHB1_CLOCK(GPIOA) ... STM32F7_AHB3_CLOCK(QSPI):
	210	shift = ahb_psc_table[(
	211	(readl(&regs->cfgr) & RCC_CFGR_AHB_PSC_MASK)
	212	>> RCC_CFGR_HPRE_SHIFT)];
	213	return sysclk >>= shift;
	214	break;
	215	/* APB1 CLOCK */
	216	case STM32F7_APB1_CLOCK(TIM2) ... STM32F7_APB1_CLOCK(UART8):
	217	shift = apb_psc_table[(
	218	(readl(&regs->cfgr) & RCC_CFGR_APB1_PSC_MASK)
	219	>> RCC_CFGR_PPRE1_SHIFT)];
	220	return sysclk >>= shift;
	221	break;
	222	/* APB2 CLOCK */
	223	case STM32F7_APB2_CLOCK(TIM1) ... STM32F7_APB2_CLOCK(LTDC):
	224	shift = apb_psc_table[(
	225	(readl(&regs->cfgr) & RCC_CFGR_APB2_PSC_MASK)
	226	>> RCC_CFGR_PPRE2_SHIFT)];
	227	return sysclk >>= shift;
	228	break;
	229	default:
9b643e31	230	pr_err("clock index %ld out of range\n", clk->id);
288f17e6 PC	231	return -EINVAL;
	232	break;
	233	}
	234	}
	235
712f99a5 VM	236	static int stm32_clk_enable(struct clk *clk)
712f99a5 VM	237	{
199a2178 PC	238	struct stm32_clk *priv = dev_get_priv(clk->dev);
199a2178 PC	239	struct stm32_rcc_regs *regs = priv->base;
712f99a5 VM	240	u32 offset = clk->id / 32;
	241	u32 bit_index = clk->id % 32;
	242
	243	debug("%s: clkid = %ld, offset from AHB1ENR is %d, bit_index = %d\n",
	244	__func__, clk->id, offset, bit_index);
199a2178	245	setbits_le32(&regs->ahb1enr + offset, BIT(bit_index));
712f99a5 VM	246
	247	return 0;
	248	}
ba0a3c16	249
e66c49fa VM	250	void clock_setup(int peripheral)
	251	{
	252	switch (peripheral) {
081de09d MK	253	case SYSCFG_CLOCK_CFG:
	254	setbits_le32(&STM32_RCC->apb2enr, RCC_APB2ENR_SYSCFGEN);
	255	break;
	256	case TIMER2_CLOCK_CFG:
	257	setbits_le32(&STM32_RCC->apb1enr, RCC_APB1ENR_TIM2EN);
	258	break;
b20b70fc MK	259	case STMMAC_CLOCK_CFG:
	260	setbits_le32(&STM32_RCC->ahb1enr, RCC_AHB1ENR_ETHMAC_EN);
	261	setbits_le32(&STM32_RCC->ahb1enr, RCC_AHB1ENR_ETHMAC_RX_EN);
	262	setbits_le32(&STM32_RCC->ahb1enr, RCC_AHB1ENR_ETHMAC_TX_EN);
	263	break;
e66c49fa VM	264	default:
	265	break;
	266	}
	267	}
712f99a5 VM	268
	269	static int stm32_clk_probe(struct udevice *dev)
	270	{
	271	debug("%s: stm32_clk_probe\n", __func__);
199a2178 PC	272
	273	struct stm32_clk *priv = dev_get_priv(dev);
	274	fdt_addr_t addr;
	275
	276	addr = devfdt_get_addr(dev);
	277	if (addr == FDT_ADDR_T_NONE)
	278	return -EINVAL;
	279
	280	priv->base = (struct stm32_rcc_regs *)addr;
	281
	282	configure_clocks(dev);
712f99a5 VM	283
	284	return 0;
	285	}
	286
a4e0ef50	287	static int stm32_clk_of_xlate(struct clk clk, struct ofnode_phandle_args args)
712f99a5 VM	288	{
	289	debug("%s(clk=%p)\n", __func__, clk);
	290
	291	if (args->args_count != 2) {
	292	debug("Invaild args_count: %d\n", args->args_count);
	293	return -EINVAL;
	294	}
	295
	296	if (args->args_count)
	297	clk->id = args->args[1];
	298	else
	299	clk->id = 0;
	300
	301	return 0;
	302	}
	303
	304	static struct clk_ops stm32_clk_ops = {
	305	.of_xlate = stm32_clk_of_xlate,
	306	.enable = stm32_clk_enable,
288f17e6	307	.get_rate = stm32_clk_get_rate,
712f99a5 VM	308	};
	309
	310	static const struct udevice_id stm32_clk_ids[] = {
	311	{ .compatible = "st,stm32f42xx-rcc"},
	312	{}
	313	};
	314
	315	U_BOOT_DRIVER(stm32f7_clk) = {
0cc40dfc PC	316	.name = "stm32f7_clk",
	317	.id = UCLASS_CLK,
	318	.of_match = stm32_clk_ids,
	319	.ops = &stm32_clk_ops,
	320	.probe = stm32_clk_probe,
	321	.priv_auto_alloc_size = sizeof(struct stm32_clk),
	322	.flags = DM_FLAG_PRE_RELOC,
712f99a5	323	};