[thirdparty/u-boot.git] / drivers / clk / imx / clk-imx8mn.c

// SPDX-License-Identifier: GPL-2.0
/*
 * Copyright 2019 NXP
 * Peng Fan <peng.fan@nxp.com>
 */

#include <common.h>
#include <clk.h>
#include <clk-uclass.h>
#include <dm.h>
#include <log.h>
#include <asm/arch/clock.h>
#include <asm/arch/imx-regs.h>
#include <dt-bindings/clock/imx8mn-clock.h>

#include "clk.h"

static u32 share_count_nand;

static const char *pll_ref_sels[] = { "clock-osc-24m", "dummy", "dummy", "dummy", };
static const char *dram_pll_bypass_sels[] = {"dram_pll", "dram_pll_ref_sel", };
static const char *arm_pll_bypass_sels[] = {"arm_pll", "arm_pll_ref_sel", };
static const char *sys_pll1_bypass_sels[] = {"sys_pll1", "sys_pll1_ref_sel", };
static const char *sys_pll2_bypass_sels[] = {"sys_pll2", "sys_pll2_ref_sel", };
static const char *sys_pll3_bypass_sels[] = {"sys_pll3", "sys_pll3_ref_sel", };

static const char *imx8mn_a53_sels[] = {"clock-osc-24m", "arm_pll_out", "sys_pll2_500m", "sys_pll2_1000m",
					"sys_pll1_800m", "sys_pll1_400m", "audio_pll1_out", "sys_pll3_out", };

static const char *imx8mn_ahb_sels[] = {"clock-osc-24m", "sys_pll1_133m", "sys_pll1_800m", "sys_pll1_400m",
					"sys_pll2_125m", "sys_pll3_out", "audio_pll1_out", "video_pll_out", };

static const char *imx8mn_enet_axi_sels[] = {"clock-osc-24m", "sys_pll1_266m", "sys_pll1_800m", "sys_pll2_250m",
					     "sys_pll2_200m", "audio_pll1_out", "video_pll_out", "sys_pll3_out", };

#ifndef CONFIG_SPL_BUILD
static const char *imx8mn_enet_ref_sels[] = {"clock-osc-24m", "sys_pll2_125m", "sys_pll2_50m", "sys_pll2_100m",
					     "sys_pll1_160m", "audio_pll1_out", "video_pll_out", "clk_ext4", };

static const char *imx8mn_enet_timer_sels[] = {"clock-osc-24m", "sys_pll2_100m", "audio_pll1_out", "clk_ext1", "clk_ext2",
					       "clk_ext3", "clk_ext4", "video_pll_out", };

static const char *imx8mn_enet_phy_sels[] = {"clock-osc-24m", "sys_pll2_50m", "sys_pll2_125m", "sys_pll2_200m",
					     "sys_pll2_500m", "audio_pll1_out", "video_pll_out", "audio_pll2_out", };
#endif

static const char *imx8mn_nand_usdhc_sels[] = {"clock-osc-24m", "sys_pll1_266m", "sys_pll1_800m", "sys_pll2_200m",
					       "sys_pll1_133m", "sys_pll3_out", "sys_pll2_250m", "audio_pll1_out", };

static const char * const imx8mn_usb_bus_sels[] = {"clock-osc-24m", "sys_pll2_500m", "sys_pll1_800m",
						"sys_pll2_100m", "sys_pll2_200m", "clk_ext2",
						"clk_ext4", "audio_pll2_out", };

static const char *imx8mn_usdhc1_sels[] = {"clock-osc-24m", "sys_pll1_400m", "sys_pll1_800m", "sys_pll2_500m",
					   "sys_pll3_out", "sys_pll1_266m", "audio_pll2_out", "sys_pll1_100m", };

static const char *imx8mn_usdhc2_sels[] = {"clock-osc-24m", "sys_pll1_400m", "sys_pll1_800m", "sys_pll2_500m",
					   "sys_pll3_out", "sys_pll1_266m", "audio_pll2_out", "sys_pll1_100m", };

#if CONFIG_IS_ENABLED(DM_SPI)
static const char *imx8mn_ecspi1_sels[] = {"osc_24m", "sys_pll2_200m", "sys_pll1_40m",
					   "sys_pll1_160m", "sys_pll1_800m", "sys_pll3_out",
					   "sys_pll2_250m", "audio_pll2_out", };

static const char *imx8mn_ecspi2_sels[] = {"osc_24m", "sys_pll2_200m", "sys_pll1_40m",
					   "sys_pll1_160m", "sys_pll1_800m", "sys_pll3_out",
					   "sys_pll2_250m", "audio_pll2_out", };

static const char *imx8mn_ecspi3_sels[] = {"osc_24m", "sys_pll2_200m", "sys_pll1_40m",
					   "sys_pll1_160m", "sys_pll1_800m", "sys_pll3_out",
					   "sys_pll2_250m", "audio_pll2_out", };
#endif

static const char *imx8mn_i2c1_sels[] = {"clock-osc-24m", "sys_pll1_160m", "sys_pll2_50m", "sys_pll3_out", "audio_pll1_out",
					 "video_pll_out", "audio_pll2_out", "sys_pll1_133m", };

static const char *imx8mn_i2c2_sels[] = {"clock-osc-24m", "sys_pll1_160m", "sys_pll2_50m", "sys_pll3_out", "audio_pll1_out",
					 "video_pll_out", "audio_pll2_out", "sys_pll1_133m", };

static const char *imx8mn_i2c3_sels[] = {"clock-osc-24m", "sys_pll1_160m", "sys_pll2_50m", "sys_pll3_out", "audio_pll1_out",
					 "video_pll_out", "audio_pll2_out", "sys_pll1_133m", };

static const char *imx8mn_i2c4_sels[] = {"clock-osc-24m", "sys_pll1_160m", "sys_pll2_50m", "sys_pll3_out", "audio_pll1_out",
					 "video_pll_out", "audio_pll2_out", "sys_pll1_133m", };

#ifndef CONFIG_SPL_BUILD
static const char *imx8mn_pwm1_sels[] = {"clock-osc-24m", "sys_pll2_100m", "sys_pll1_160m", "sys_pll1_40m",
					 "sys_pll3_out", "clk_ext1", "sys_pll1_80m", "video_pll_out", };

static const char *imx8mn_pwm2_sels[] = {"clock-osc-24m", "sys_pll2_100m", "sys_pll1_160m", "sys_pll1_40m",
					 "sys_pll3_out", "clk_ext1", "sys_pll1_80m", "video_pll_out", };

static const char *imx8mn_pwm3_sels[] = {"clock-osc-24m", "sys_pll2_100m", "sys_pll1_160m", "sys_pll1_40m",
					 "sys_pll3_out", "clk_ext2", "sys_pll1_80m", "video_pll_out", };

static const char *imx8mn_pwm4_sels[] = {"clock-osc-24m", "sys_pll2_100m", "sys_pll1_160m", "sys_pll1_40m",
					 "sys_pll3_out", "clk_ext2", "sys_pll1_80m", "video_pll_out", };
#endif

static const char *imx8mn_wdog_sels[] = {"clock-osc-24m", "sys_pll1_133m", "sys_pll1_160m", "m7_alt_pll",
					 "sys_pll2_125m", "sys_pll3_out", "sys_pll1_80m", "sys_pll2_166m", };

static const char *imx8mn_usdhc3_sels[] = {"clock-osc-24m", "sys_pll1_400m", "sys_pll1_800m", "sys_pll2_500m",
					   "sys_pll3_out", "sys_pll1_266m", "audio_pll2_clk", "sys_pll1_100m", };

static const char *imx8mn_qspi_sels[] = {"clock-osc-24m", "sys_pll1_400m", "sys_pll2_333m", "sys_pll2_500m",
					   "audio_pll2_out", "sys_pll1_266m", "sys_pll3_out", "sys_pll1_100m", };

static const char * const imx8mn_nand_sels[] = {"osc_24m", "sys_pll2_500m", "audio_pll1_out",
						"sys_pll1_400m", "audio_pll2_out", "sys_pll3_out",
						"sys_pll2_250m", "video_pll_out", };

static const char * const imx8mn_usb_core_sels[] = {"clock-osc-24m", "sys_pll1_100m", "sys_pll1_40m",
						"sys_pll2_100m", "sys_pll2_200m", "clk_ext2",
						"clk_ext3", "audio_pll2_out", };

static const char * const imx8mn_usb_phy_sels[] = {"clock-osc-24m", "sys_pll1_100m", "sys_pll1_40m",
						"sys_pll2_100m", "sys_pll2_200m", "clk_ext2",
						"clk_ext3", "audio_pll2_out", };

static int imx8mn_clk_probe(struct udevice *dev)
{
	void __iomem *base;

	base = (void *)ANATOP_BASE_ADDR;

	clk_dm(IMX8MN_DRAM_PLL_REF_SEL,
	       imx_clk_mux("dram_pll_ref_sel", base + 0x50, 0, 2,
			   pll_ref_sels, ARRAY_SIZE(pll_ref_sels)));
	clk_dm(IMX8MN_ARM_PLL_REF_SEL,
	       imx_clk_mux("arm_pll_ref_sel", base + 0x84, 0, 2,
			   pll_ref_sels, ARRAY_SIZE(pll_ref_sels)));
	clk_dm(IMX8MN_SYS_PLL1_REF_SEL,
	       imx_clk_mux("sys_pll1_ref_sel", base + 0x94, 0, 2,
			   pll_ref_sels, ARRAY_SIZE(pll_ref_sels)));
	clk_dm(IMX8MN_SYS_PLL2_REF_SEL,
	       imx_clk_mux("sys_pll2_ref_sel", base + 0x104, 0, 2,
			   pll_ref_sels, ARRAY_SIZE(pll_ref_sels)));
	clk_dm(IMX8MN_SYS_PLL3_REF_SEL,
	       imx_clk_mux("sys_pll3_ref_sel", base + 0x114, 0, 2,
			   pll_ref_sels, ARRAY_SIZE(pll_ref_sels)));

	clk_dm(IMX8MN_DRAM_PLL,
	       imx_clk_pll14xx("dram_pll", "dram_pll_ref_sel",
			       base + 0x50, &imx_1443x_dram_pll));
	clk_dm(IMX8MN_ARM_PLL,
	       imx_clk_pll14xx("arm_pll", "arm_pll_ref_sel",
			       base + 0x84, &imx_1416x_pll));
	clk_dm(IMX8MN_SYS_PLL1,
	       imx_clk_pll14xx("sys_pll1", "sys_pll1_ref_sel",
			       base + 0x94, &imx_1416x_pll));
	clk_dm(IMX8MN_SYS_PLL2,
	       imx_clk_pll14xx("sys_pll2", "sys_pll2_ref_sel",
			       base + 0x104, &imx_1416x_pll));
	clk_dm(IMX8MN_SYS_PLL3,
	       imx_clk_pll14xx("sys_pll3", "sys_pll3_ref_sel",
			       base + 0x114, &imx_1416x_pll));

	/* PLL bypass out */
	clk_dm(IMX8MN_DRAM_PLL_BYPASS,
	       imx_clk_mux_flags("dram_pll_bypass", base + 0x50, 4, 1,
				 dram_pll_bypass_sels,
				 ARRAY_SIZE(dram_pll_bypass_sels),
				 CLK_SET_RATE_PARENT));
	clk_dm(IMX8MN_ARM_PLL_BYPASS,
	       imx_clk_mux_flags("arm_pll_bypass", base + 0x84, 4, 1,
				 arm_pll_bypass_sels,
				 ARRAY_SIZE(arm_pll_bypass_sels),
				 CLK_SET_RATE_PARENT));
	clk_dm(IMX8MN_SYS_PLL1_BYPASS,
	       imx_clk_mux_flags("sys_pll1_bypass", base + 0x94, 4, 1,
				 sys_pll1_bypass_sels,
				 ARRAY_SIZE(sys_pll1_bypass_sels),
				 CLK_SET_RATE_PARENT));
	clk_dm(IMX8MN_SYS_PLL2_BYPASS,
	       imx_clk_mux_flags("sys_pll2_bypass", base + 0x104, 4, 1,
				 sys_pll2_bypass_sels,
				 ARRAY_SIZE(sys_pll2_bypass_sels),
				 CLK_SET_RATE_PARENT));
	clk_dm(IMX8MN_SYS_PLL3_BYPASS,
	       imx_clk_mux_flags("sys_pll3_bypass", base + 0x114, 4, 1,
				 sys_pll3_bypass_sels,
				 ARRAY_SIZE(sys_pll3_bypass_sels),
				 CLK_SET_RATE_PARENT));

	/* PLL out gate */
	clk_dm(IMX8MN_DRAM_PLL_OUT,
	       imx_clk_gate("dram_pll_out", "dram_pll_bypass",
			    base + 0x50, 13));
	clk_dm(IMX8MN_ARM_PLL_OUT,
	       imx_clk_gate("arm_pll_out", "arm_pll_bypass",
			    base + 0x84, 11));
	clk_dm(IMX8MN_SYS_PLL1_OUT,
	       imx_clk_gate("sys_pll1_out", "sys_pll1_bypass",
			    base + 0x94, 11));
	clk_dm(IMX8MN_SYS_PLL2_OUT,
	       imx_clk_gate("sys_pll2_out", "sys_pll2_bypass",
			    base + 0x104, 11));
	clk_dm(IMX8MN_SYS_PLL3_OUT,
	       imx_clk_gate("sys_pll3_out", "sys_pll3_bypass",
			    base + 0x114, 11));

	/* SYS PLL fixed output */
	clk_dm(IMX8MN_SYS_PLL1_40M,
	       imx_clk_fixed_factor("sys_pll1_40m", "sys_pll1_out", 1, 20));
	clk_dm(IMX8MN_SYS_PLL1_80M,
	       imx_clk_fixed_factor("sys_pll1_80m", "sys_pll1_out", 1, 10));
	clk_dm(IMX8MN_SYS_PLL1_100M,
	       imx_clk_fixed_factor("sys_pll1_100m", "sys_pll1_out", 1, 8));
	clk_dm(IMX8MN_SYS_PLL1_133M,
	       imx_clk_fixed_factor("sys_pll1_133m", "sys_pll1_out", 1, 6));
	clk_dm(IMX8MN_SYS_PLL1_160M,
	       imx_clk_fixed_factor("sys_pll1_160m", "sys_pll1_out", 1, 5));
	clk_dm(IMX8MN_SYS_PLL1_200M,
	       imx_clk_fixed_factor("sys_pll1_200m", "sys_pll1_out", 1, 4));
	clk_dm(IMX8MN_SYS_PLL1_266M,
	       imx_clk_fixed_factor("sys_pll1_266m", "sys_pll1_out", 1, 3));
	clk_dm(IMX8MN_SYS_PLL1_400M,
	       imx_clk_fixed_factor("sys_pll1_400m", "sys_pll1_out", 1, 2));
	clk_dm(IMX8MN_SYS_PLL1_800M,
	       imx_clk_fixed_factor("sys_pll1_800m", "sys_pll1_out", 1, 1));

	clk_dm(IMX8MN_SYS_PLL2_50M,
	       imx_clk_fixed_factor("sys_pll2_50m", "sys_pll2_out", 1, 20));
	clk_dm(IMX8MN_SYS_PLL2_100M,
	       imx_clk_fixed_factor("sys_pll2_100m", "sys_pll2_out", 1, 10));
	clk_dm(IMX8MN_SYS_PLL2_125M,
	       imx_clk_fixed_factor("sys_pll2_125m", "sys_pll2_out", 1, 8));
	clk_dm(IMX8MN_SYS_PLL2_166M,
	       imx_clk_fixed_factor("sys_pll2_166m", "sys_pll2_out", 1, 6));
	clk_dm(IMX8MN_SYS_PLL2_200M,
	       imx_clk_fixed_factor("sys_pll2_200m", "sys_pll2_out", 1, 5));
	clk_dm(IMX8MN_SYS_PLL2_250M,
	       imx_clk_fixed_factor("sys_pll2_250m", "sys_pll2_out", 1, 4));
	clk_dm(IMX8MN_SYS_PLL2_333M,
	       imx_clk_fixed_factor("sys_pll2_333m", "sys_pll2_out", 1, 3));
	clk_dm(IMX8MN_SYS_PLL2_500M,
	       imx_clk_fixed_factor("sys_pll2_500m", "sys_pll2_out", 1, 2));
	clk_dm(IMX8MN_SYS_PLL2_1000M,
	       imx_clk_fixed_factor("sys_pll2_1000m", "sys_pll2_out", 1, 1));

	base = dev_read_addr_ptr(dev);
	if (!base)
		return -EINVAL;

	clk_dm(IMX8MN_CLK_A53_SRC,
	       imx_clk_mux2("arm_a53_src", base + 0x8000, 24, 3,
			    imx8mn_a53_sels, ARRAY_SIZE(imx8mn_a53_sels)));
	clk_dm(IMX8MN_CLK_A53_CG,
	       imx_clk_gate3("arm_a53_cg", "arm_a53_src", base + 0x8000, 28));
	clk_dm(IMX8MN_CLK_A53_DIV,
	       imx_clk_divider2("arm_a53_div", "arm_a53_cg",
				base + 0x8000, 0, 3));

	clk_dm(IMX8MN_CLK_AHB,
	       imx8m_clk_composite_critical("ahb", imx8mn_ahb_sels,
					    base + 0x9000));
	clk_dm(IMX8MN_CLK_IPG_ROOT,
	       imx_clk_divider2("ipg_root", "ahb", base + 0x9080, 0, 1));

	clk_dm(IMX8MN_CLK_ENET_AXI,
	       imx8m_clk_composite("enet_axi", imx8mn_enet_axi_sels,
				   base + 0x8880));
	clk_dm(IMX8MN_CLK_NAND_USDHC_BUS,
	       imx8m_clk_composite_critical("nand_usdhc_bus",
					    imx8mn_nand_usdhc_sels,
					    base + 0x8900));
	clk_dm(IMX8MN_CLK_USB_BUS,
		imx8m_clk_composite("usb_bus", imx8mn_usb_bus_sels, base + 0x8b80));

	/* IP */
	clk_dm(IMX8MN_CLK_USDHC1,
	       imx8m_clk_composite("usdhc1", imx8mn_usdhc1_sels,
				   base + 0xac00));
	clk_dm(IMX8MN_CLK_USDHC2,
	       imx8m_clk_composite("usdhc2", imx8mn_usdhc2_sels,
				   base + 0xac80));
	clk_dm(IMX8MN_CLK_I2C1,
	       imx8m_clk_composite("i2c1", imx8mn_i2c1_sels, base + 0xad00));
	clk_dm(IMX8MN_CLK_I2C2,
	       imx8m_clk_composite("i2c2", imx8mn_i2c2_sels, base + 0xad80));
	clk_dm(IMX8MN_CLK_I2C3,
	       imx8m_clk_composite("i2c3", imx8mn_i2c3_sels, base + 0xae00));
	clk_dm(IMX8MN_CLK_I2C4,
	       imx8m_clk_composite("i2c4", imx8mn_i2c4_sels, base + 0xae80));
	clk_dm(IMX8MN_CLK_WDOG,
	       imx8m_clk_composite("wdog", imx8mn_wdog_sels, base + 0xb900));
	clk_dm(IMX8MN_CLK_USDHC3,
	       imx8m_clk_composite("usdhc3", imx8mn_usdhc3_sels,
				   base + 0xbc80));
	clk_dm(IMX8MN_CLK_NAND,
	       imx8m_clk_composite("nand", imx8mn_nand_sels, base + 0xab00));
	clk_dm(IMX8MN_CLK_QSPI,
	       imx8m_clk_composite("qspi", imx8mn_qspi_sels, base + 0xab80));
	clk_dm(IMX8MN_CLK_USB_CORE_REF,
		imx8m_clk_composite("usb_core_ref", imx8mn_usb_core_sels, base + 0xb100));
	clk_dm(IMX8MN_CLK_USB_PHY_REF,
		imx8m_clk_composite("usb_phy_ref", imx8mn_usb_phy_sels, base + 0xb180));

	clk_dm(IMX8MN_CLK_I2C1_ROOT,
	       imx_clk_gate4("i2c1_root_clk", "i2c1", base + 0x4170, 0));
	clk_dm(IMX8MN_CLK_I2C2_ROOT,
	       imx_clk_gate4("i2c2_root_clk", "i2c2", base + 0x4180, 0));
	clk_dm(IMX8MN_CLK_I2C3_ROOT,
	       imx_clk_gate4("i2c3_root_clk", "i2c3", base + 0x4190, 0));
	clk_dm(IMX8MN_CLK_I2C4_ROOT,
	       imx_clk_gate4("i2c4_root_clk", "i2c4", base + 0x41a0, 0));
	clk_dm(IMX8MN_CLK_OCOTP_ROOT,
	       imx_clk_gate4("ocotp_root_clk", "ipg_root", base + 0x4220, 0));
	clk_dm(IMX8MN_CLK_USDHC1_ROOT,
	       imx_clk_gate4("usdhc1_root_clk", "usdhc1", base + 0x4510, 0));
	clk_dm(IMX8MN_CLK_USDHC2_ROOT,
	       imx_clk_gate4("usdhc2_root_clk", "usdhc2", base + 0x4520, 0));
	clk_dm(IMX8MN_CLK_WDOG1_ROOT,
	       imx_clk_gate4("wdog1_root_clk", "wdog", base + 0x4530, 0));
	clk_dm(IMX8MN_CLK_WDOG2_ROOT,
	       imx_clk_gate4("wdog2_root_clk", "wdog", base + 0x4540, 0));
	clk_dm(IMX8MN_CLK_WDOG3_ROOT,
	       imx_clk_gate4("wdog3_root_clk", "wdog", base + 0x4550, 0));
	clk_dm(IMX8MN_CLK_USDHC3_ROOT,
	       imx_clk_gate4("usdhc3_root_clk", "usdhc3", base + 0x45e0, 0));
	clk_dm(IMX8MN_CLK_QSPI_ROOT,
	       imx_clk_gate4("qspi_root_clk", "qspi", base + 0x42f0, 0));
	clk_dm(IMX8MN_CLK_NAND_ROOT,
	       imx_clk_gate2_shared2("nand_root_clk", "nand", base + 0x4300, 0, &share_count_nand));
	clk_dm(IMX8MN_CLK_NAND_USDHC_BUS_RAWNAND_CLK,
	       imx_clk_gate2_shared2("nand_usdhc_rawnand_clk",
				     "nand_usdhc_bus", base + 0x4300, 0,
				     &share_count_nand));
	clk_dm(IMX8MN_CLK_USB1_CTRL_ROOT,
		imx_clk_gate4("usb1_ctrl_root_clk", "usb_bus", base + 0x44d0, 0));

	/* clks not needed in SPL stage */
#ifndef CONFIG_SPL_BUILD
	clk_dm(IMX8MN_CLK_ENET_REF,
	       imx8m_clk_composite("enet_ref", imx8mn_enet_ref_sels,
	       base + 0xa980));
	clk_dm(IMX8MN_CLK_ENET_TIMER,
	       imx8m_clk_composite("enet_timer", imx8mn_enet_timer_sels,
	       base + 0xaa00));
	clk_dm(IMX8MN_CLK_ENET_PHY_REF,
	       imx8m_clk_composite("enet_phy", imx8mn_enet_phy_sels,
	       base + 0xaa80));
	clk_dm(IMX8MN_CLK_ENET1_ROOT,
	       imx_clk_gate4("enet1_root_clk", "enet_axi",
	       base + 0x40a0, 0));
	clk_dm(IMX8MN_CLK_PWM1,
	       imx8m_clk_composite("pwm1", imx8mn_pwm1_sels, base + 0xb380));
	clk_dm(IMX8MN_CLK_PWM2,
	       imx8m_clk_composite("pwm2", imx8mn_pwm2_sels, base + 0xb400));
	clk_dm(IMX8MN_CLK_PWM3,
	       imx8m_clk_composite("pwm3", imx8mn_pwm3_sels, base + 0xb480));
	clk_dm(IMX8MN_CLK_PWM4,
	       imx8m_clk_composite("pwm4", imx8mn_pwm4_sels, base + 0xb500));
	clk_dm(IMX8MN_CLK_PWM1_ROOT,
	       imx_clk_gate4("pwm1_root_clk", "pwm1", base + 0x4280, 0));
	clk_dm(IMX8MN_CLK_PWM2_ROOT,
	       imx_clk_gate4("pwm2_root_clk", "pwm2", base + 0x4290, 0));
	clk_dm(IMX8MN_CLK_PWM3_ROOT,
	       imx_clk_gate4("pwm3_root_clk", "pwm3", base + 0x42a0, 0));
	clk_dm(IMX8MN_CLK_PWM4_ROOT,
	       imx_clk_gate4("pwm4_root_clk", "pwm4", base + 0x42b0, 0));
#endif

#if CONFIG_IS_ENABLED(DM_SPI)
	clk_dm(IMX8MN_CLK_ECSPI1,
	       imx8m_clk_composite("ecspi1", imx8mn_ecspi1_sels, base + 0xb280));
	clk_dm(IMX8MN_CLK_ECSPI2,
	       imx8m_clk_composite("ecspi2", imx8mn_ecspi2_sels, base + 0xb300));
	clk_dm(IMX8MN_CLK_ECSPI3,
	       imx8m_clk_composite("ecspi3", imx8mn_ecspi3_sels, base + 0xc180));
	clk_dm(IMX8MN_CLK_ECSPI1_ROOT,
	       imx_clk_gate4("ecspi1_root_clk", "ecspi1", base + 0x4070, 0));
	clk_dm(IMX8MN_CLK_ECSPI2_ROOT,
	       imx_clk_gate4("ecspi2_root_clk", "ecspi2", base + 0x4080, 0));
	clk_dm(IMX8MN_CLK_ECSPI3_ROOT,
	       imx_clk_gate4("ecspi3_root_clk", "ecspi3", base + 0x4090, 0));
#endif

	return 0;
}

static const struct udevice_id imx8mn_clk_ids[] = {
	{ .compatible = "fsl,imx8mn-ccm" },
	{ },
};

U_BOOT_DRIVER(imx8mn_clk) = {
	.name = "clk_imx8mn",
	.id = UCLASS_CLK,
	.of_match = imx8mn_clk_ids,
	.ops = &ccf_clk_ops,
	.probe = imx8mn_clk_probe,
	.flags = DM_FLAG_PRE_RELOC,
};
Commit	Line	Data
a3aff5e5 PF	1	// SPDX-License-Identifier: GPL-2.0
	2	/*
	3	* Copyright 2019 NXP
	4	* Peng Fan <peng.fan@nxp.com>
	5	*/
	6
d678a59d	7	#include <common.h>
a3aff5e5 PF	8	#include <clk.h>
	9	#include <clk-uclass.h>
	10	#include <dm.h>
f7ae49fc	11	#include <log.h>
a3aff5e5 PF	12	#include <asm/arch/clock.h>
	13	#include <asm/arch/imx-regs.h>
	14	#include <dt-bindings/clock/imx8mn-clock.h>
	15
	16	#include "clk.h"
	17
710c4ffb MT	18	static u32 share_count_nand;
710c4ffb MT	19
a3aff5e5 PF	20	static const char *pll_ref_sels[] = { "clock-osc-24m", "dummy", "dummy", "dummy", };
	21	static const char *dram_pll_bypass_sels[] = {"dram_pll", "dram_pll_ref_sel", };
	22	static const char *arm_pll_bypass_sels[] = {"arm_pll", "arm_pll_ref_sel", };
	23	static const char *sys_pll1_bypass_sels[] = {"sys_pll1", "sys_pll1_ref_sel", };
	24	static const char *sys_pll2_bypass_sels[] = {"sys_pll2", "sys_pll2_ref_sel", };
	25	static const char *sys_pll3_bypass_sels[] = {"sys_pll3", "sys_pll3_ref_sel", };
	26
	27	static const char *imx8mn_a53_sels[] = {"clock-osc-24m", "arm_pll_out", "sys_pll2_500m", "sys_pll2_1000m",
	28	"sys_pll1_800m", "sys_pll1_400m", "audio_pll1_out", "sys_pll3_out", };
	29
	30	static const char *imx8mn_ahb_sels[] = {"clock-osc-24m", "sys_pll1_133m", "sys_pll1_800m", "sys_pll1_400m",
e02bf587	31	"sys_pll2_125m", "sys_pll3_out", "audio_pll1_out", "video_pll_out", };
a3aff5e5 PF	32
a3aff5e5 PF	33	static const char *imx8mn_enet_axi_sels[] = {"clock-osc-24m", "sys_pll1_266m", "sys_pll1_800m", "sys_pll2_250m",
e02bf587	34	"sys_pll2_200m", "audio_pll1_out", "video_pll_out", "sys_pll3_out", };
a3aff5e5	35
ee1f8b22 YL	36	#ifndef CONFIG_SPL_BUILD
ee1f8b22 YL	37	static const char *imx8mn_enet_ref_sels[] = {"clock-osc-24m", "sys_pll2_125m", "sys_pll2_50m", "sys_pll2_100m",
e02bf587	38	"sys_pll1_160m", "audio_pll1_out", "video_pll_out", "clk_ext4", };
ee1f8b22 YL	39
ee1f8b22 YL	40	static const char *imx8mn_enet_timer_sels[] = {"clock-osc-24m", "sys_pll2_100m", "audio_pll1_out", "clk_ext1", "clk_ext2",
e02bf587	41	"clk_ext3", "clk_ext4", "video_pll_out", };
ee1f8b22 YL	42
ee1f8b22 YL	43	static const char *imx8mn_enet_phy_sels[] = {"clock-osc-24m", "sys_pll2_50m", "sys_pll2_125m", "sys_pll2_200m",
4a18d230	44	"sys_pll2_500m", "audio_pll1_out", "video_pll_out", "audio_pll2_out", };
ee1f8b22 YL	45	#endif
ee1f8b22 YL	46
a3aff5e5 PF	47	static const char *imx8mn_nand_usdhc_sels[] = {"clock-osc-24m", "sys_pll1_266m", "sys_pll1_800m", "sys_pll2_200m",
	48	"sys_pll1_133m", "sys_pll3_out", "sys_pll2_250m", "audio_pll1_out", };
	49
4b6548d1 YL	50	static const char * const imx8mn_usb_bus_sels[] = {"clock-osc-24m", "sys_pll2_500m", "sys_pll1_800m",
	51	"sys_pll2_100m", "sys_pll2_200m", "clk_ext2",
	52	"clk_ext4", "audio_pll2_out", };
	53
a3aff5e5 PF	54	static const char *imx8mn_usdhc1_sels[] = {"clock-osc-24m", "sys_pll1_400m", "sys_pll1_800m", "sys_pll2_500m",
	55	"sys_pll3_out", "sys_pll1_266m", "audio_pll2_out", "sys_pll1_100m", };
	56
	57	static const char *imx8mn_usdhc2_sels[] = {"clock-osc-24m", "sys_pll1_400m", "sys_pll1_800m", "sys_pll2_500m",
	58	"sys_pll3_out", "sys_pll1_266m", "audio_pll2_out", "sys_pll1_100m", };
	59
85b1c119 MV	60	#if CONFIG_IS_ENABLED(DM_SPI)
	61	static const char *imx8mn_ecspi1_sels[] = {"osc_24m", "sys_pll2_200m", "sys_pll1_40m",
	62	"sys_pll1_160m", "sys_pll1_800m", "sys_pll3_out",
	63	"sys_pll2_250m", "audio_pll2_out", };
	64
	65	static const char *imx8mn_ecspi2_sels[] = {"osc_24m", "sys_pll2_200m", "sys_pll1_40m",
	66	"sys_pll1_160m", "sys_pll1_800m", "sys_pll3_out",
	67	"sys_pll2_250m", "audio_pll2_out", };
	68
	69	static const char *imx8mn_ecspi3_sels[] = {"osc_24m", "sys_pll2_200m", "sys_pll1_40m",
	70	"sys_pll1_160m", "sys_pll1_800m", "sys_pll3_out",
	71	"sys_pll2_250m", "audio_pll2_out", };
	72	#endif
	73
a3aff5e5	74	static const char *imx8mn_i2c1_sels[] = {"clock-osc-24m", "sys_pll1_160m", "sys_pll2_50m", "sys_pll3_out", "audio_pll1_out",
e02bf587	75	"video_pll_out", "audio_pll2_out", "sys_pll1_133m", };
a3aff5e5 PF	76
a3aff5e5 PF	77	static const char *imx8mn_i2c2_sels[] = {"clock-osc-24m", "sys_pll1_160m", "sys_pll2_50m", "sys_pll3_out", "audio_pll1_out",
e02bf587	78	"video_pll_out", "audio_pll2_out", "sys_pll1_133m", };
a3aff5e5 PF	79
a3aff5e5 PF	80	static const char *imx8mn_i2c3_sels[] = {"clock-osc-24m", "sys_pll1_160m", "sys_pll2_50m", "sys_pll3_out", "audio_pll1_out",
e02bf587	81	"video_pll_out", "audio_pll2_out", "sys_pll1_133m", };
a3aff5e5 PF	82
a3aff5e5 PF	83	static const char *imx8mn_i2c4_sels[] = {"clock-osc-24m", "sys_pll1_160m", "sys_pll2_50m", "sys_pll3_out", "audio_pll1_out",
e02bf587	84	"video_pll_out", "audio_pll2_out", "sys_pll1_133m", };
a3aff5e5	85
cb1d68b1 NH	86	#ifndef CONFIG_SPL_BUILD
	87	static const char *imx8mn_pwm1_sels[] = {"clock-osc-24m", "sys_pll2_100m", "sys_pll1_160m", "sys_pll1_40m",
	88	"sys_pll3_out", "clk_ext1", "sys_pll1_80m", "video_pll_out", };
	89
	90	static const char *imx8mn_pwm2_sels[] = {"clock-osc-24m", "sys_pll2_100m", "sys_pll1_160m", "sys_pll1_40m",
	91	"sys_pll3_out", "clk_ext1", "sys_pll1_80m", "video_pll_out", };
	92
	93	static const char *imx8mn_pwm3_sels[] = {"clock-osc-24m", "sys_pll2_100m", "sys_pll1_160m", "sys_pll1_40m",
	94	"sys_pll3_out", "clk_ext2", "sys_pll1_80m", "video_pll_out", };
	95
	96	static const char *imx8mn_pwm4_sels[] = {"clock-osc-24m", "sys_pll2_100m", "sys_pll1_160m", "sys_pll1_40m",
	97	"sys_pll3_out", "clk_ext2", "sys_pll1_80m", "video_pll_out", };
	98	#endif
	99
d0cc6a6c	100	static const char *imx8mn_wdog_sels[] = {"clock-osc-24m", "sys_pll1_133m", "sys_pll1_160m", "m7_alt_pll",
a3aff5e5 PF	101	"sys_pll2_125m", "sys_pll3_out", "sys_pll1_80m", "sys_pll2_166m", };
	102
	103	static const char *imx8mn_usdhc3_sels[] = {"clock-osc-24m", "sys_pll1_400m", "sys_pll1_800m", "sys_pll2_500m",
	104	"sys_pll3_out", "sys_pll1_266m", "audio_pll2_clk", "sys_pll1_100m", };
	105
ee1f8b22 YL	106	static const char *imx8mn_qspi_sels[] = {"clock-osc-24m", "sys_pll1_400m", "sys_pll2_333m", "sys_pll2_500m",
	107	"audio_pll2_out", "sys_pll1_266m", "sys_pll3_out", "sys_pll1_100m", };
	108
710c4ffb MT	109	static const char * const imx8mn_nand_sels[] = {"osc_24m", "sys_pll2_500m", "audio_pll1_out",
710c4ffb MT	110	"sys_pll1_400m", "audio_pll2_out", "sys_pll3_out",
e02bf587	111	"sys_pll2_250m", "video_pll_out", };
710c4ffb	112
4b6548d1 YL	113	static const char * const imx8mn_usb_core_sels[] = {"clock-osc-24m", "sys_pll1_100m", "sys_pll1_40m",
	114	"sys_pll2_100m", "sys_pll2_200m", "clk_ext2",
	115	"clk_ext3", "audio_pll2_out", };
	116
	117	static const char * const imx8mn_usb_phy_sels[] = {"clock-osc-24m", "sys_pll1_100m", "sys_pll1_40m",
	118	"sys_pll2_100m", "sys_pll2_200m", "clk_ext2",
	119	"clk_ext3", "audio_pll2_out", };
	120
a3aff5e5 PF	121	static int imx8mn_clk_probe(struct udevice *dev)
	122	{
	123	void __iomem *base;
	124
	125	base = (void *)ANATOP_BASE_ADDR;
	126
	127	clk_dm(IMX8MN_DRAM_PLL_REF_SEL,
	128	imx_clk_mux("dram_pll_ref_sel", base + 0x50, 0, 2,
	129	pll_ref_sels, ARRAY_SIZE(pll_ref_sels)));
	130	clk_dm(IMX8MN_ARM_PLL_REF_SEL,
	131	imx_clk_mux("arm_pll_ref_sel", base + 0x84, 0, 2,
	132	pll_ref_sels, ARRAY_SIZE(pll_ref_sels)));
	133	clk_dm(IMX8MN_SYS_PLL1_REF_SEL,
	134	imx_clk_mux("sys_pll1_ref_sel", base + 0x94, 0, 2,
	135	pll_ref_sels, ARRAY_SIZE(pll_ref_sels)));
	136	clk_dm(IMX8MN_SYS_PLL2_REF_SEL,
	137	imx_clk_mux("sys_pll2_ref_sel", base + 0x104, 0, 2,
	138	pll_ref_sels, ARRAY_SIZE(pll_ref_sels)));
	139	clk_dm(IMX8MN_SYS_PLL3_REF_SEL,
	140	imx_clk_mux("sys_pll3_ref_sel", base + 0x114, 0, 2,
	141	pll_ref_sels, ARRAY_SIZE(pll_ref_sels)));
	142
	143	clk_dm(IMX8MN_DRAM_PLL,
	144	imx_clk_pll14xx("dram_pll", "dram_pll_ref_sel",
129f5102	145	base + 0x50, &imx_1443x_dram_pll));
a3aff5e5 PF	146	clk_dm(IMX8MN_ARM_PLL,
a3aff5e5 PF	147	imx_clk_pll14xx("arm_pll", "arm_pll_ref_sel",
129f5102	148	base + 0x84, &imx_1416x_pll));
a3aff5e5 PF	149	clk_dm(IMX8MN_SYS_PLL1,
a3aff5e5 PF	150	imx_clk_pll14xx("sys_pll1", "sys_pll1_ref_sel",
129f5102	151	base + 0x94, &imx_1416x_pll));
a3aff5e5 PF	152	clk_dm(IMX8MN_SYS_PLL2,
a3aff5e5 PF	153	imx_clk_pll14xx("sys_pll2", "sys_pll2_ref_sel",
129f5102	154	base + 0x104, &imx_1416x_pll));
a3aff5e5 PF	155	clk_dm(IMX8MN_SYS_PLL3,
a3aff5e5 PF	156	imx_clk_pll14xx("sys_pll3", "sys_pll3_ref_sel",
129f5102	157	base + 0x114, &imx_1416x_pll));
a3aff5e5 PF	158
	159	/* PLL bypass out */
	160	clk_dm(IMX8MN_DRAM_PLL_BYPASS,
	161	imx_clk_mux_flags("dram_pll_bypass", base + 0x50, 4, 1,
	162	dram_pll_bypass_sels,
	163	ARRAY_SIZE(dram_pll_bypass_sels),
	164	CLK_SET_RATE_PARENT));
	165	clk_dm(IMX8MN_ARM_PLL_BYPASS,
	166	imx_clk_mux_flags("arm_pll_bypass", base + 0x84, 4, 1,
	167	arm_pll_bypass_sels,
	168	ARRAY_SIZE(arm_pll_bypass_sels),
	169	CLK_SET_RATE_PARENT));
	170	clk_dm(IMX8MN_SYS_PLL1_BYPASS,
	171	imx_clk_mux_flags("sys_pll1_bypass", base + 0x94, 4, 1,
	172	sys_pll1_bypass_sels,
	173	ARRAY_SIZE(sys_pll1_bypass_sels),
	174	CLK_SET_RATE_PARENT));
	175	clk_dm(IMX8MN_SYS_PLL2_BYPASS,
	176	imx_clk_mux_flags("sys_pll2_bypass", base + 0x104, 4, 1,
	177	sys_pll2_bypass_sels,
	178	ARRAY_SIZE(sys_pll2_bypass_sels),
	179	CLK_SET_RATE_PARENT));
	180	clk_dm(IMX8MN_SYS_PLL3_BYPASS,
	181	imx_clk_mux_flags("sys_pll3_bypass", base + 0x114, 4, 1,
	182	sys_pll3_bypass_sels,
	183	ARRAY_SIZE(sys_pll3_bypass_sels),
	184	CLK_SET_RATE_PARENT));
	185
	186	/* PLL out gate */
	187	clk_dm(IMX8MN_DRAM_PLL_OUT,
	188	imx_clk_gate("dram_pll_out", "dram_pll_bypass",
	189	base + 0x50, 13));
	190	clk_dm(IMX8MN_ARM_PLL_OUT,
	191	imx_clk_gate("arm_pll_out", "arm_pll_bypass",
	192	base + 0x84, 11));
	193	clk_dm(IMX8MN_SYS_PLL1_OUT,
	194	imx_clk_gate("sys_pll1_out", "sys_pll1_bypass",
	195	base + 0x94, 11));
	196	clk_dm(IMX8MN_SYS_PLL2_OUT,
	197	imx_clk_gate("sys_pll2_out", "sys_pll2_bypass",
	198	base + 0x104, 11));
	199	clk_dm(IMX8MN_SYS_PLL3_OUT,
	200	imx_clk_gate("sys_pll3_out", "sys_pll3_bypass",
	201	base + 0x114, 11));
	202
	203	/* SYS PLL fixed output */
	204	clk_dm(IMX8MN_SYS_PLL1_40M,
	205	imx_clk_fixed_factor("sys_pll1_40m", "sys_pll1_out", 1, 20));
	206	clk_dm(IMX8MN_SYS_PLL1_80M,
	207	imx_clk_fixed_factor("sys_pll1_80m", "sys_pll1_out", 1, 10));
	208	clk_dm(IMX8MN_SYS_PLL1_100M,
	209	imx_clk_fixed_factor("sys_pll1_100m", "sys_pll1_out", 1, 8));
	210	clk_dm(IMX8MN_SYS_PLL1_133M,
	211	imx_clk_fixed_factor("sys_pll1_133m", "sys_pll1_out", 1, 6));
	212	clk_dm(IMX8MN_SYS_PLL1_160M,
	213	imx_clk_fixed_factor("sys_pll1_160m", "sys_pll1_out", 1, 5));
	214	clk_dm(IMX8MN_SYS_PLL1_200M,
	215	imx_clk_fixed_factor("sys_pll1_200m", "sys_pll1_out", 1, 4));
	216	clk_dm(IMX8MN_SYS_PLL1_266M,
	217	imx_clk_fixed_factor("sys_pll1_266m", "sys_pll1_out", 1, 3));
	218	clk_dm(IMX8MN_SYS_PLL1_400M,
	219	imx_clk_fixed_factor("sys_pll1_400m", "sys_pll1_out", 1, 2));
	220	clk_dm(IMX8MN_SYS_PLL1_800M,
	221	imx_clk_fixed_factor("sys_pll1_800m", "sys_pll1_out", 1, 1));
222
223	clk_dm(IMX8MN_SYS_PLL2_50M,
224	imx_clk_fixed_factor("sys_pll2_50m", "sys_pll2_out", 1, 20));
225	clk_dm(IMX8MN_SYS_PLL2_100M,
226	imx_clk_fixed_factor("sys_pll2_100m", "sys_pll2_out", 1, 10));
227	clk_dm(IMX8MN_SYS_PLL2_125M,
228	imx_clk_fixed_factor("sys_pll2_125m", "sys_pll2_out", 1, 8));
229	clk_dm(IMX8MN_SYS_PLL2_166M,
230	imx_clk_fixed_factor("sys_pll2_166m", "sys_pll2_out", 1, 6));
231	clk_dm(IMX8MN_SYS_PLL2_200M,
232	imx_clk_fixed_factor("sys_pll2_200m", "sys_pll2_out", 1, 5));
233	clk_dm(IMX8MN_SYS_PLL2_250M,
234	imx_clk_fixed_factor("sys_pll2_250m", "sys_pll2_out", 1, 4));
235	clk_dm(IMX8MN_SYS_PLL2_333M,
236	imx_clk_fixed_factor("sys_pll2_333m", "sys_pll2_out", 1, 3));
237	clk_dm(IMX8MN_SYS_PLL2_500M,
238	imx_clk_fixed_factor("sys_pll2_500m", "sys_pll2_out", 1, 2));
239	clk_dm(IMX8MN_SYS_PLL2_1000M,
240	imx_clk_fixed_factor("sys_pll2_1000m", "sys_pll2_out", 1, 1));
241
242	base = dev_read_addr_ptr(dev);
90cbfa50	243	if (!base)
a3aff5e5 PF	244	return -EINVAL;
	245
	246	clk_dm(IMX8MN_CLK_A53_SRC,
	247	imx_clk_mux2("arm_a53_src", base + 0x8000, 24, 3,
	248	imx8mn_a53_sels, ARRAY_SIZE(imx8mn_a53_sels)));
	249	clk_dm(IMX8MN_CLK_A53_CG,
	250	imx_clk_gate3("arm_a53_cg", "arm_a53_src", base + 0x8000, 28));
	251	clk_dm(IMX8MN_CLK_A53_DIV,
	252	imx_clk_divider2("arm_a53_div", "arm_a53_cg",
	253	base + 0x8000, 0, 3));
	254
	255	clk_dm(IMX8MN_CLK_AHB,
	256	imx8m_clk_composite_critical("ahb", imx8mn_ahb_sels,
	257	base + 0x9000));
	258	clk_dm(IMX8MN_CLK_IPG_ROOT,
	259	imx_clk_divider2("ipg_root", "ahb", base + 0x9080, 0, 1));
	260
	261	clk_dm(IMX8MN_CLK_ENET_AXI,
	262	imx8m_clk_composite("enet_axi", imx8mn_enet_axi_sels,
	263	base + 0x8880));
	264	clk_dm(IMX8MN_CLK_NAND_USDHC_BUS,
	265	imx8m_clk_composite_critical("nand_usdhc_bus",
	266	imx8mn_nand_usdhc_sels,
	267	base + 0x8900));
4b6548d1 YL	268	clk_dm(IMX8MN_CLK_USB_BUS,
4b6548d1 YL	269	imx8m_clk_composite("usb_bus", imx8mn_usb_bus_sels, base + 0x8b80));
a3aff5e5 PF	270
	271	/* IP */
	272	clk_dm(IMX8MN_CLK_USDHC1,
	273	imx8m_clk_composite("usdhc1", imx8mn_usdhc1_sels,
	274	base + 0xac00));
	275	clk_dm(IMX8MN_CLK_USDHC2,
	276	imx8m_clk_composite("usdhc2", imx8mn_usdhc2_sels,
	277	base + 0xac80));
	278	clk_dm(IMX8MN_CLK_I2C1,
	279	imx8m_clk_composite("i2c1", imx8mn_i2c1_sels, base + 0xad00));
	280	clk_dm(IMX8MN_CLK_I2C2,
	281	imx8m_clk_composite("i2c2", imx8mn_i2c2_sels, base + 0xad80));
	282	clk_dm(IMX8MN_CLK_I2C3,
	283	imx8m_clk_composite("i2c3", imx8mn_i2c3_sels, base + 0xae00));
	284	clk_dm(IMX8MN_CLK_I2C4,
	285	imx8m_clk_composite("i2c4", imx8mn_i2c4_sels, base + 0xae80));
	286	clk_dm(IMX8MN_CLK_WDOG,
	287	imx8m_clk_composite("wdog", imx8mn_wdog_sels, base + 0xb900));
	288	clk_dm(IMX8MN_CLK_USDHC3,
	289	imx8m_clk_composite("usdhc3", imx8mn_usdhc3_sels,
	290	base + 0xbc80));
710c4ffb MT	291	clk_dm(IMX8MN_CLK_NAND,
710c4ffb MT	292	imx8m_clk_composite("nand", imx8mn_nand_sels, base + 0xab00));
ee1f8b22 YL	293	clk_dm(IMX8MN_CLK_QSPI,
ee1f8b22 YL	294	imx8m_clk_composite("qspi", imx8mn_qspi_sels, base + 0xab80));
4b6548d1 YL	295	clk_dm(IMX8MN_CLK_USB_CORE_REF,
	296	imx8m_clk_composite("usb_core_ref", imx8mn_usb_core_sels, base + 0xb100));
	297	clk_dm(IMX8MN_CLK_USB_PHY_REF,
	298	imx8m_clk_composite("usb_phy_ref", imx8mn_usb_phy_sels, base + 0xb180));
a3aff5e5 PF	299
	300	clk_dm(IMX8MN_CLK_I2C1_ROOT,
	301	imx_clk_gate4("i2c1_root_clk", "i2c1", base + 0x4170, 0));
	302	clk_dm(IMX8MN_CLK_I2C2_ROOT,
	303	imx_clk_gate4("i2c2_root_clk", "i2c2", base + 0x4180, 0));
	304	clk_dm(IMX8MN_CLK_I2C3_ROOT,
	305	imx_clk_gate4("i2c3_root_clk", "i2c3", base + 0x4190, 0));
	306	clk_dm(IMX8MN_CLK_I2C4_ROOT,
	307	imx_clk_gate4("i2c4_root_clk", "i2c4", base + 0x41a0, 0));
	308	clk_dm(IMX8MN_CLK_OCOTP_ROOT,
	309	imx_clk_gate4("ocotp_root_clk", "ipg_root", base + 0x4220, 0));
	310	clk_dm(IMX8MN_CLK_USDHC1_ROOT,
	311	imx_clk_gate4("usdhc1_root_clk", "usdhc1", base + 0x4510, 0));
	312	clk_dm(IMX8MN_CLK_USDHC2_ROOT,
	313	imx_clk_gate4("usdhc2_root_clk", "usdhc2", base + 0x4520, 0));
	314	clk_dm(IMX8MN_CLK_WDOG1_ROOT,
	315	imx_clk_gate4("wdog1_root_clk", "wdog", base + 0x4530, 0));
	316	clk_dm(IMX8MN_CLK_WDOG2_ROOT,
	317	imx_clk_gate4("wdog2_root_clk", "wdog", base + 0x4540, 0));
	318	clk_dm(IMX8MN_CLK_WDOG3_ROOT,
	319	imx_clk_gate4("wdog3_root_clk", "wdog", base + 0x4550, 0));
	320	clk_dm(IMX8MN_CLK_USDHC3_ROOT,
	321	imx_clk_gate4("usdhc3_root_clk", "usdhc3", base + 0x45e0, 0));
ee1f8b22 YL	322	clk_dm(IMX8MN_CLK_QSPI_ROOT,
ee1f8b22 YL	323	imx_clk_gate4("qspi_root_clk", "qspi", base + 0x42f0, 0));
710c4ffb MT	324	clk_dm(IMX8MN_CLK_NAND_ROOT,
	325	imx_clk_gate2_shared2("nand_root_clk", "nand", base + 0x4300, 0, &share_count_nand));
	326	clk_dm(IMX8MN_CLK_NAND_USDHC_BUS_RAWNAND_CLK,
	327	imx_clk_gate2_shared2("nand_usdhc_rawnand_clk",
	328	"nand_usdhc_bus", base + 0x4300, 0,
	329	&share_count_nand));
4b6548d1 YL	330	clk_dm(IMX8MN_CLK_USB1_CTRL_ROOT,
4b6548d1 YL	331	imx_clk_gate4("usb1_ctrl_root_clk", "usb_bus", base + 0x44d0, 0));
ee1f8b22 YL	332
	333	/* clks not needed in SPL stage */
	334	#ifndef CONFIG_SPL_BUILD
	335	clk_dm(IMX8MN_CLK_ENET_REF,
	336	imx8m_clk_composite("enet_ref", imx8mn_enet_ref_sels,
	337	base + 0xa980));
	338	clk_dm(IMX8MN_CLK_ENET_TIMER,
	339	imx8m_clk_composite("enet_timer", imx8mn_enet_timer_sels,
	340	base + 0xaa00));
	341	clk_dm(IMX8MN_CLK_ENET_PHY_REF,
	342	imx8m_clk_composite("enet_phy", imx8mn_enet_phy_sels,
	343	base + 0xaa80));
	344	clk_dm(IMX8MN_CLK_ENET1_ROOT,
	345	imx_clk_gate4("enet1_root_clk", "enet_axi",
	346	base + 0x40a0, 0));
cb1d68b1 NH	347	clk_dm(IMX8MN_CLK_PWM1,
	348	imx8m_clk_composite("pwm1", imx8mn_pwm1_sels, base + 0xb380));
	349	clk_dm(IMX8MN_CLK_PWM2,
	350	imx8m_clk_composite("pwm2", imx8mn_pwm2_sels, base + 0xb400));
	351	clk_dm(IMX8MN_CLK_PWM3,
	352	imx8m_clk_composite("pwm3", imx8mn_pwm3_sels, base + 0xb480));
	353	clk_dm(IMX8MN_CLK_PWM4,
	354	imx8m_clk_composite("pwm4", imx8mn_pwm4_sels, base + 0xb500));
	355	clk_dm(IMX8MN_CLK_PWM1_ROOT,
	356	imx_clk_gate4("pwm1_root_clk", "pwm1", base + 0x4280, 0));
	357	clk_dm(IMX8MN_CLK_PWM2_ROOT,
	358	imx_clk_gate4("pwm2_root_clk", "pwm2", base + 0x4290, 0));
	359	clk_dm(IMX8MN_CLK_PWM3_ROOT,
	360	imx_clk_gate4("pwm3_root_clk", "pwm3", base + 0x42a0, 0));
	361	clk_dm(IMX8MN_CLK_PWM4_ROOT,
	362	imx_clk_gate4("pwm4_root_clk", "pwm4", base + 0x42b0, 0));
ee1f8b22	363	#endif
a3aff5e5	364
85b1c119 MV	365	#if CONFIG_IS_ENABLED(DM_SPI)
	366	clk_dm(IMX8MN_CLK_ECSPI1,
	367	imx8m_clk_composite("ecspi1", imx8mn_ecspi1_sels, base + 0xb280));
	368	clk_dm(IMX8MN_CLK_ECSPI2,
	369	imx8m_clk_composite("ecspi2", imx8mn_ecspi2_sels, base + 0xb300));
	370	clk_dm(IMX8MN_CLK_ECSPI3,
	371	imx8m_clk_composite("ecspi3", imx8mn_ecspi3_sels, base + 0xc180));
	372	clk_dm(IMX8MN_CLK_ECSPI1_ROOT,
	373	imx_clk_gate4("ecspi1_root_clk", "ecspi1", base + 0x4070, 0));
	374	clk_dm(IMX8MN_CLK_ECSPI2_ROOT,
	375	imx_clk_gate4("ecspi2_root_clk", "ecspi2", base + 0x4080, 0));
	376	clk_dm(IMX8MN_CLK_ECSPI3_ROOT,
	377	imx_clk_gate4("ecspi3_root_clk", "ecspi3", base + 0x4090, 0));
	378	#endif
	379
a3aff5e5 PF	380	return 0;
	381	}
	382
	383	static const struct udevice_id imx8mn_clk_ids[] = {
	384	{ .compatible = "fsl,imx8mn-ccm" },
	385	{ },
	386	};
	387
	388	U_BOOT_DRIVER(imx8mn_clk) = {
	389	.name = "clk_imx8mn",
	390	.id = UCLASS_CLK,
	391	.of_match = imx8mn_clk_ids,
682e73d2	392	.ops = &ccf_clk_ops,
a3aff5e5 PF	393	.probe = imx8mn_clk_probe,
	394	.flags = DM_FLAG_PRE_RELOC,
	395	};