[thirdparty/u-boot.git] / drivers / clk / qcom / clock-ipq4019.c

// SPDX-License-Identifier: GPL-2.0+
/*
 * Clock drivers for Qualcomm IPQ40xx
 *
 * Copyright (c) 2020 Sartura Ltd.
 *
 * Author: Robert Marko <robert.marko@sartura.hr>
 *
 */

#include <clk-uclass.h>
#include <common.h>
#include <dm.h>
#include <errno.h>
#include <dt-bindings/clock/qcom,gcc-ipq4019.h>

#include "clock-qcom.h"

static ulong ipq4019_clk_set_rate(struct clk *clk, ulong rate)
{
	switch (clk->id) {
	case GCC_BLSP1_UART1_APPS_CLK: /*UART1*/
		/* This clock is already initialized by SBL1 */
		return 1843200;
	default:
		return -EINVAL;
	}
}

static int ipq4019_clk_enable(struct clk *clk)
{
	switch (clk->id) {
	case GCC_BLSP1_QUP1_SPI_APPS_CLK: /*SPI1*/
		/* This clock is already initialized by SBL1 */
		return 0;
	case GCC_PRNG_AHB_CLK: /*PRNG*/
		/* This clock is already initialized by SBL1 */
		return 0;
	case GCC_USB3_MASTER_CLK:
	case GCC_USB3_SLEEP_CLK:
	case GCC_USB3_MOCK_UTMI_CLK:
	case GCC_USB2_MASTER_CLK:
	case GCC_USB2_SLEEP_CLK:
	case GCC_USB2_MOCK_UTMI_CLK:
		/* These clocks is already initialized by SBL1 */
		return 0;
	default:
		return -EINVAL;
	}
}

static const struct qcom_reset_map gcc_ipq4019_resets[] = {
	[WIFI0_CPU_INIT_RESET] = { 0x1f008, 5 },
	[WIFI0_RADIO_SRIF_RESET] = { 0x1f008, 4 },
	[WIFI0_RADIO_WARM_RESET] = { 0x1f008, 3 },
	[WIFI0_RADIO_COLD_RESET] = { 0x1f008, 2 },
	[WIFI0_CORE_WARM_RESET] = { 0x1f008, 1 },
	[WIFI0_CORE_COLD_RESET] = { 0x1f008, 0 },
	[WIFI1_CPU_INIT_RESET] = { 0x20008, 5 },
	[WIFI1_RADIO_SRIF_RESET] = { 0x20008, 4 },
	[WIFI1_RADIO_WARM_RESET] = { 0x20008, 3 },
	[WIFI1_RADIO_COLD_RESET] = { 0x20008, 2 },
	[WIFI1_CORE_WARM_RESET] = { 0x20008, 1 },
	[WIFI1_CORE_COLD_RESET] = { 0x20008, 0 },
	[USB3_UNIPHY_PHY_ARES] = { 0x1e038, 5 },
	[USB3_HSPHY_POR_ARES] = { 0x1e038, 4 },
	[USB3_HSPHY_S_ARES] = { 0x1e038, 2 },
	[USB2_HSPHY_POR_ARES] = { 0x1e01c, 4 },
	[USB2_HSPHY_S_ARES] = { 0x1e01c, 2 },
	[PCIE_PHY_AHB_ARES] = { 0x1d010, 11 },
	[PCIE_AHB_ARES] = { 0x1d010, 10 },
	[PCIE_PWR_ARES] = { 0x1d010, 9 },
	[PCIE_PIPE_STICKY_ARES] = { 0x1d010, 8 },
	[PCIE_AXI_M_STICKY_ARES] = { 0x1d010, 7 },
	[PCIE_PHY_ARES] = { 0x1d010, 6 },
	[PCIE_PARF_XPU_ARES] = { 0x1d010, 5 },
	[PCIE_AXI_S_XPU_ARES] = { 0x1d010, 4 },
	[PCIE_AXI_M_VMIDMT_ARES] = { 0x1d010, 3 },
	[PCIE_PIPE_ARES] = { 0x1d010, 2 },
	[PCIE_AXI_S_ARES] = { 0x1d010, 1 },
	[PCIE_AXI_M_ARES] = { 0x1d010, 0 },
	[ESS_RESET] = { 0x12008, 0},
	[GCC_BLSP1_BCR] = {0x01000, 0},
	[GCC_BLSP1_QUP1_BCR] = {0x02000, 0},
	[GCC_BLSP1_UART1_BCR] = {0x02038, 0},
	[GCC_BLSP1_QUP2_BCR] = {0x03008, 0},
	[GCC_BLSP1_UART2_BCR] = {0x03028, 0},
	[GCC_BIMC_BCR] = {0x04000, 0},
	[GCC_TLMM_BCR] = {0x05000, 0},
	[GCC_IMEM_BCR] = {0x0E000, 0},
	[GCC_ESS_BCR] = {0x12008, 0},
	[GCC_PRNG_BCR] = {0x13000, 0},
	[GCC_BOOT_ROM_BCR] = {0x13008, 0},
	[GCC_CRYPTO_BCR] = {0x16000, 0},
	[GCC_SDCC1_BCR] = {0x18000, 0},
	[GCC_SEC_CTRL_BCR] = {0x1A000, 0},
	[GCC_AUDIO_BCR] = {0x1B008, 0},
	[GCC_QPIC_BCR] = {0x1C000, 0},
	[GCC_PCIE_BCR] = {0x1D000, 0},
	[GCC_USB2_BCR] = {0x1E008, 0},
	[GCC_USB2_PHY_BCR] = {0x1E018, 0},
	[GCC_USB3_BCR] = {0x1E024, 0},
	[GCC_USB3_PHY_BCR] = {0x1E034, 0},
	[GCC_SYSTEM_NOC_BCR] = {0x21000, 0},
	[GCC_PCNOC_BCR] = {0x2102C, 0},
	[GCC_DCD_BCR] = {0x21038, 0},
	[GCC_SNOC_BUS_TIMEOUT0_BCR] = {0x21064, 0},
	[GCC_SNOC_BUS_TIMEOUT1_BCR] = {0x2106C, 0},
	[GCC_SNOC_BUS_TIMEOUT2_BCR] = {0x21074, 0},
	[GCC_SNOC_BUS_TIMEOUT3_BCR] = {0x2107C, 0},
	[GCC_PCNOC_BUS_TIMEOUT0_BCR] = {0x21084, 0},
	[GCC_PCNOC_BUS_TIMEOUT1_BCR] = {0x2108C, 0},
	[GCC_PCNOC_BUS_TIMEOUT2_BCR] = {0x21094, 0},
	[GCC_PCNOC_BUS_TIMEOUT3_BCR] = {0x2109C, 0},
	[GCC_PCNOC_BUS_TIMEOUT4_BCR] = {0x210A4, 0},
	[GCC_PCNOC_BUS_TIMEOUT5_BCR] = {0x210AC, 0},
	[GCC_PCNOC_BUS_TIMEOUT6_BCR] = {0x210B4, 0},
	[GCC_PCNOC_BUS_TIMEOUT7_BCR] = {0x210BC, 0},
	[GCC_PCNOC_BUS_TIMEOUT8_BCR] = {0x210C4, 0},
	[GCC_PCNOC_BUS_TIMEOUT9_BCR] = {0x210CC, 0},
	[GCC_TCSR_BCR] = {0x22000, 0},
	[GCC_MPM_BCR] = {0x24000, 0},
	[GCC_SPDM_BCR] = {0x25000, 0},
};

static struct msm_clk_data ipq4019_clk_data = {
	.enable = ipq4019_clk_enable,
	.set_rate = ipq4019_clk_set_rate,
	.resets = gcc_ipq4019_resets,
	.num_resets = ARRAY_SIZE(gcc_ipq4019_resets),
};

static const struct udevice_id gcc_ipq4019_of_match[] = {
	{
		.compatible = "qcom,gcc-ipq4019",
		.data = (ulong)&ipq4019_clk_data,
	},
	{ }
};

U_BOOT_DRIVER(gcc_ipq4019) = {
	.name		= "gcc_ipq4019",
	.id		= UCLASS_NOP,
	.of_match	= gcc_ipq4019_of_match,
	.bind		= qcom_cc_bind,
	.flags		= DM_FLAG_PRE_RELOC,
};
Commit	Line	Data
e479a7d5 RM	1	// SPDX-License-Identifier: GPL-2.0+
	2	/*
	3	* Clock drivers for Qualcomm IPQ40xx
	4	*
96d60366	5	* Copyright (c) 2020 Sartura Ltd.
e479a7d5 RM	6	*
	7	* Author: Robert Marko <robert.marko@sartura.hr>
	8	*
	9	*/
	10
e479a7d5	11	#include <clk-uclass.h>
d678a59d	12	#include <common.h>
e479a7d5 RM	13	#include <dm.h>
e479a7d5 RM	14	#include <errno.h>
3ead6616	15	#include <dt-bindings/clock/qcom,gcc-ipq4019.h>
5ae15415	16
fac2121a	17	#include "clock-qcom.h"
e479a7d5	18
37ea1343	19	static ulong ipq4019_clk_set_rate(struct clk *clk, ulong rate)
e479a7d5 RM	20	{
e479a7d5 RM	21	switch (clk->id) {
5ae15415	22	case GCC_BLSP1_UART1_APPS_CLK: /UART1/
e479a7d5	23	/* This clock is already initialized by SBL1 */
99e79174	24	return 1843200;
e479a7d5	25	default:
20476b51	26	return -EINVAL;
e479a7d5 RM	27	}
	28	}
	29
37ea1343	30	static int ipq4019_clk_enable(struct clk *clk)
96d60366 RM	31	{
	32	switch (clk->id) {
	33	case GCC_BLSP1_QUP1_SPI_APPS_CLK: /SPI1/
	34	/* This clock is already initialized by SBL1 */
	35	return 0;
cfec8d36 RM	36	case GCC_PRNG_AHB_CLK: /PRNG/
	37	/* This clock is already initialized by SBL1 */
	38	return 0;
a282ada1 RM	39	case GCC_USB3_MASTER_CLK:
	40	case GCC_USB3_SLEEP_CLK:
	41	case GCC_USB3_MOCK_UTMI_CLK:
	42	case GCC_USB2_MASTER_CLK:
	43	case GCC_USB2_SLEEP_CLK:
	44	case GCC_USB2_MOCK_UTMI_CLK:
	45	/* These clocks is already initialized by SBL1 */
	46	return 0;
96d60366	47	default:
20476b51	48	return -EINVAL;
96d60366 RM	49	}
	50	}
	51
3ead6616 KD	52	static const struct qcom_reset_map gcc_ipq4019_resets[] = {
	53	[WIFI0_CPU_INIT_RESET] = { 0x1f008, 5 },
	54	[WIFI0_RADIO_SRIF_RESET] = { 0x1f008, 4 },
	55	[WIFI0_RADIO_WARM_RESET] = { 0x1f008, 3 },
	56	[WIFI0_RADIO_COLD_RESET] = { 0x1f008, 2 },
	57	[WIFI0_CORE_WARM_RESET] = { 0x1f008, 1 },
	58	[WIFI0_CORE_COLD_RESET] = { 0x1f008, 0 },
	59	[WIFI1_CPU_INIT_RESET] = { 0x20008, 5 },
	60	[WIFI1_RADIO_SRIF_RESET] = { 0x20008, 4 },
	61	[WIFI1_RADIO_WARM_RESET] = { 0x20008, 3 },
	62	[WIFI1_RADIO_COLD_RESET] = { 0x20008, 2 },
	63	[WIFI1_CORE_WARM_RESET] = { 0x20008, 1 },
	64	[WIFI1_CORE_COLD_RESET] = { 0x20008, 0 },
	65	[USB3_UNIPHY_PHY_ARES] = { 0x1e038, 5 },
	66	[USB3_HSPHY_POR_ARES] = { 0x1e038, 4 },
	67	[USB3_HSPHY_S_ARES] = { 0x1e038, 2 },
	68	[USB2_HSPHY_POR_ARES] = { 0x1e01c, 4 },
	69	[USB2_HSPHY_S_ARES] = { 0x1e01c, 2 },
	70	[PCIE_PHY_AHB_ARES] = { 0x1d010, 11 },
	71	[PCIE_AHB_ARES] = { 0x1d010, 10 },
	72	[PCIE_PWR_ARES] = { 0x1d010, 9 },
	73	[PCIE_PIPE_STICKY_ARES] = { 0x1d010, 8 },
	74	[PCIE_AXI_M_STICKY_ARES] = { 0x1d010, 7 },
	75	[PCIE_PHY_ARES] = { 0x1d010, 6 },
	76	[PCIE_PARF_XPU_ARES] = { 0x1d010, 5 },
	77	[PCIE_AXI_S_XPU_ARES] = { 0x1d010, 4 },
	78	[PCIE_AXI_M_VMIDMT_ARES] = { 0x1d010, 3 },
	79	[PCIE_PIPE_ARES] = { 0x1d010, 2 },
	80	[PCIE_AXI_S_ARES] = { 0x1d010, 1 },
	81	[PCIE_AXI_M_ARES] = { 0x1d010, 0 },
	82	[ESS_RESET] = { 0x12008, 0},
	83	[GCC_BLSP1_BCR] = {0x01000, 0},
	84	[GCC_BLSP1_QUP1_BCR] = {0x02000, 0},
	85	[GCC_BLSP1_UART1_BCR] = {0x02038, 0},
	86	[GCC_BLSP1_QUP2_BCR] = {0x03008, 0},
	87	[GCC_BLSP1_UART2_BCR] = {0x03028, 0},
	88	[GCC_BIMC_BCR] = {0x04000, 0},
	89	[GCC_TLMM_BCR] = {0x05000, 0},
	90	[GCC_IMEM_BCR] = {0x0E000, 0},
	91	[GCC_ESS_BCR] = {0x12008, 0},
	92	[GCC_PRNG_BCR] = {0x13000, 0},
	93	[GCC_BOOT_ROM_BCR] = {0x13008, 0},
	94	[GCC_CRYPTO_BCR] = {0x16000, 0},
	95	[GCC_SDCC1_BCR] = {0x18000, 0},
	96	[GCC_SEC_CTRL_BCR] = {0x1A000, 0},
	97	[GCC_AUDIO_BCR] = {0x1B008, 0},
	98	[GCC_QPIC_BCR] = {0x1C000, 0},
	99	[GCC_PCIE_BCR] = {0x1D000, 0},
	100	[GCC_USB2_BCR] = {0x1E008, 0},
	101	[GCC_USB2_PHY_BCR] = {0x1E018, 0},
	102	[GCC_USB3_BCR] = {0x1E024, 0},
	103	[GCC_USB3_PHY_BCR] = {0x1E034, 0},
	104	[GCC_SYSTEM_NOC_BCR] = {0x21000, 0},
	105	[GCC_PCNOC_BCR] = {0x2102C, 0},
	106	[GCC_DCD_BCR] = {0x21038, 0},
	107	[GCC_SNOC_BUS_TIMEOUT0_BCR] = {0x21064, 0},
	108	[GCC_SNOC_BUS_TIMEOUT1_BCR] = {0x2106C, 0},
	109	[GCC_SNOC_BUS_TIMEOUT2_BCR] = {0x21074, 0},
	110	[GCC_SNOC_BUS_TIMEOUT3_BCR] = {0x2107C, 0},
	111	[GCC_PCNOC_BUS_TIMEOUT0_BCR] = {0x21084, 0},
	112	[GCC_PCNOC_BUS_TIMEOUT1_BCR] = {0x2108C, 0},
	113	[GCC_PCNOC_BUS_TIMEOUT2_BCR] = {0x21094, 0},
	114	[GCC_PCNOC_BUS_TIMEOUT3_BCR] = {0x2109C, 0},
	115	[GCC_PCNOC_BUS_TIMEOUT4_BCR] = {0x210A4, 0},
116	[GCC_PCNOC_BUS_TIMEOUT5_BCR] = {0x210AC, 0},
117	[GCC_PCNOC_BUS_TIMEOUT6_BCR] = {0x210B4, 0},
118	[GCC_PCNOC_BUS_TIMEOUT7_BCR] = {0x210BC, 0},
119	[GCC_PCNOC_BUS_TIMEOUT8_BCR] = {0x210C4, 0},
120	[GCC_PCNOC_BUS_TIMEOUT9_BCR] = {0x210CC, 0},
121	[GCC_TCSR_BCR] = {0x22000, 0},
122	[GCC_MPM_BCR] = {0x24000, 0},
123	[GCC_SPDM_BCR] = {0x25000, 0},
124	};
125
37ea1343 CC	126	static struct msm_clk_data ipq4019_clk_data = {
	127	.enable = ipq4019_clk_enable,
	128	.set_rate = ipq4019_clk_set_rate,
3ead6616 KD	129	.resets = gcc_ipq4019_resets,
	130	.num_resets = ARRAY_SIZE(gcc_ipq4019_resets),
	131	};
	132
	133	static const struct udevice_id gcc_ipq4019_of_match[] = {
	134	{
	135	.compatible = "qcom,gcc-ipq4019",
37ea1343	136	.data = (ulong)&ipq4019_clk_data,
3ead6616 KD	137	},
	138	{ }
	139	};
	140
	141	U_BOOT_DRIVER(gcc_ipq4019) = {
	142	.name = "gcc_ipq4019",
	143	.id = UCLASS_NOP,
	144	.of_match = gcc_ipq4019_of_match,
	145	.bind = qcom_cc_bind,
	146	.flags = DM_FLAG_PRE_RELOC,
	147	};