[people/ms/u-boot.git] / drivers / clk / renesas / clk-rcar-gen3.c

/*
 * Renesas RCar Gen3 CPG MSSR driver
 *
 * Copyright (C) 2017 Marek Vasut <marek.vasut@gmail.com>
 *
 * Based on the following driver from Linux kernel:
 * r8a7796 Clock Pulse Generator / Module Standby and Software Reset
 *
 * Copyright (C) 2016 Glider bvba
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#include <common.h>
#include <clk-uclass.h>
#include <dm.h>
#include <errno.h>
#include <wait_bit.h>
#include <asm/io.h>

#include <dt-bindings/clock/renesas-cpg-mssr.h>

#include "renesas-cpg-mssr.h"

#define CPG_RST_MODEMR		0x0060

#define CPG_PLL0CR		0x00d8
#define CPG_PLL2CR		0x002c
#define CPG_PLL4CR		0x01f4

#define CPG_RPC_PREDIV_MASK	0x3
#define CPG_RPC_PREDIV_OFFSET	3
#define CPG_RPC_POSTDIV_MASK	0x7
#define CPG_RPC_POSTDIV_OFFSET	0

/*
 * Module Standby and Software Reset register offets.
 *
 * If the registers exist, these are valid for SH-Mobile, R-Mobile,
 * R-Car Gen2, R-Car Gen3, and RZ/G1.
 * These are NOT valid for R-Car Gen1 and RZ/A1!
 */

/*
 * Module Stop Status Register offsets
 */

static const u16 mstpsr[] = {
	0x030, 0x038, 0x040, 0x048, 0x04C, 0x03C, 0x1C0, 0x1C4,
	0x9A0, 0x9A4, 0x9A8, 0x9AC,
};

#define	MSTPSR(i)	mstpsr[i]


/*
 * System Module Stop Control Register offsets
 */

static const u16 smstpcr[] = {
	0x130, 0x134, 0x138, 0x13C, 0x140, 0x144, 0x148, 0x14C,
	0x990, 0x994, 0x998, 0x99C,
};

#define	SMSTPCR(i)	smstpcr[i]


/* Realtime Module Stop Control Register offsets */
#define RMSTPCR(i)	(smstpcr[i] - 0x20)

/* Modem Module Stop Control Register offsets (r8a73a4) */
#define MMSTPCR(i)	(smstpcr[i] + 0x20)

/* Software Reset Clearing Register offsets */
#define	SRSTCLR(i)	(0x940 + (i) * 4)

/*
 * SDn Clock
 */
#define CPG_SD_STP_HCK		BIT(9)
#define CPG_SD_STP_CK		BIT(8)

#define CPG_SD_STP_MASK		(CPG_SD_STP_HCK | CPG_SD_STP_CK)
#define CPG_SD_FC_MASK		(0x7 << 2 | 0x3 << 0)

#define CPG_SD_DIV_TABLE_DATA(stp_hck, stp_ck, sd_srcfc, sd_fc, sd_div) \
{ \
	.val = ((stp_hck) ? CPG_SD_STP_HCK : 0) | \
	       ((stp_ck) ? CPG_SD_STP_CK : 0) | \
	       ((sd_srcfc) << 2) | \
	       ((sd_fc) << 0), \
	.div = (sd_div), \
}

struct sd_div_table {
	u32 val;
	unsigned int div;
};

/* SDn divider
 *                     sd_srcfc   sd_fc   div
 * stp_hck   stp_ck    (div)      (div)     = sd_srcfc x sd_fc
 *-------------------------------------------------------------------
 *  0         0         0 (1)      1 (4)      4
 *  0         0         1 (2)      1 (4)      8
 *  1         0         2 (4)      1 (4)     16
 *  1         0         3 (8)      1 (4)     32
 *  1         0         4 (16)     1 (4)     64
 *  0         0         0 (1)      0 (2)      2
 *  0         0         1 (2)      0 (2)      4
 *  1         0         2 (4)      0 (2)      8
 *  1         0         3 (8)      0 (2)     16
 *  1         0         4 (16)     0 (2)     32
 */
static const struct sd_div_table cpg_sd_div_table[] = {
/*	CPG_SD_DIV_TABLE_DATA(stp_hck,  stp_ck,   sd_srcfc,   sd_fc,  sd_div) */
	CPG_SD_DIV_TABLE_DATA(0,        0,        0,          1,        4),
	CPG_SD_DIV_TABLE_DATA(0,        0,        1,          1,        8),
	CPG_SD_DIV_TABLE_DATA(1,        0,        2,          1,       16),
	CPG_SD_DIV_TABLE_DATA(1,        0,        3,          1,       32),
	CPG_SD_DIV_TABLE_DATA(1,        0,        4,          1,       64),
	CPG_SD_DIV_TABLE_DATA(0,        0,        0,          0,        2),
	CPG_SD_DIV_TABLE_DATA(0,        0,        1,          0,        4),
	CPG_SD_DIV_TABLE_DATA(1,        0,        2,          0,        8),
	CPG_SD_DIV_TABLE_DATA(1,        0,        3,          0,       16),
	CPG_SD_DIV_TABLE_DATA(1,        0,        4,          0,       32),
};

static bool gen3_clk_is_mod(struct clk *clk)
{
	return (clk->id >> 16) == CPG_MOD;
}

static int gen3_clk_get_mod(struct clk *clk, const struct mssr_mod_clk **mssr)
{
	struct gen3_clk_priv *priv = dev_get_priv(clk->dev);
	struct cpg_mssr_info *info = priv->info;
	const unsigned long clkid = clk->id & 0xffff;
	int i;

	if (!gen3_clk_is_mod(clk))
		return -EINVAL;

	for (i = 0; i < info->mod_clk_size; i++) {
		if (info->mod_clk[i].id !=
		    (info->mod_clk_base + MOD_CLK_PACK(clkid)))
			continue;

		*mssr = &info->mod_clk[i];
		return 0;
	}

	return -ENODEV;
}

static int gen3_clk_get_core(struct clk *clk, const struct cpg_core_clk **core)
{
	struct gen3_clk_priv *priv = dev_get_priv(clk->dev);
	struct cpg_mssr_info *info = priv->info;
	const unsigned long clkid = clk->id & 0xffff;
	int i;

	if (gen3_clk_is_mod(clk))
		return -EINVAL;

	for (i = 0; i < info->core_clk_size; i++) {
		if (info->core_clk[i].id != clkid)
			continue;

		*core = &info->core_clk[i];
		return 0;
	}

	return -ENODEV;
}

static int gen3_clk_get_parent(struct clk *clk, struct clk *parent)
{
	const struct cpg_core_clk *core;
	const struct mssr_mod_clk *mssr;
	int ret;

	if (gen3_clk_is_mod(clk)) {
		ret = gen3_clk_get_mod(clk, &mssr);
		if (ret)
			return ret;

		parent->id = mssr->parent;
	} else {
		ret = gen3_clk_get_core(clk, &core);
		if (ret)
			return ret;

		if (core->type == CLK_TYPE_IN)
			parent->id = ~0;	/* Top-level clock */
		else
			parent->id = core->parent;
	}

	parent->dev = clk->dev;

	return 0;
}

static int gen3_clk_setup_sdif_div(struct clk *clk)
{
	struct gen3_clk_priv *priv = dev_get_priv(clk->dev);
	const struct cpg_core_clk *core;
	struct clk parent;
	int ret;

	ret = gen3_clk_get_parent(clk, &parent);
	if (ret) {
		printf("%s[%i] parent fail, ret=%i\n", __func__, __LINE__, ret);
		return ret;
	}

	if (gen3_clk_is_mod(&parent))
		return 0;

	ret = gen3_clk_get_core(&parent, &core);
	if (ret)
		return ret;

	if (core->type != CLK_TYPE_GEN3_SD)
		return 0;

	debug("%s[%i] SDIF offset=%x\n", __func__, __LINE__, core->offset);

	writel(1, priv->base + core->offset);

	return 0;
}

static int gen3_clk_endisable(struct clk *clk, bool enable)
{
	struct gen3_clk_priv *priv = dev_get_priv(clk->dev);
	const unsigned long clkid = clk->id & 0xffff;
	const unsigned int reg = clkid / 100;
	const unsigned int bit = clkid % 100;
	const u32 bitmask = BIT(bit);
	int ret;

	if (!gen3_clk_is_mod(clk))
		return -EINVAL;

	debug("%s[%i] MSTP %lu=%02u/%02u %s\n", __func__, __LINE__,
	      clkid, reg, bit, enable ? "ON" : "OFF");

	if (enable) {
		ret = gen3_clk_setup_sdif_div(clk);
		if (ret)
			return ret;
		clrbits_le32(priv->base + SMSTPCR(reg), bitmask);
		return wait_for_bit("MSTP", priv->base + MSTPSR(reg),
				    bitmask, 0, 100, 0);
	} else {
		setbits_le32(priv->base + SMSTPCR(reg), bitmask);
		return 0;
	}
}

static int gen3_clk_enable(struct clk *clk)
{
	return gen3_clk_endisable(clk, true);
}

static int gen3_clk_disable(struct clk *clk)
{
	return gen3_clk_endisable(clk, false);
}

static ulong gen3_clk_get_rate(struct clk *clk)
{
	struct gen3_clk_priv *priv = dev_get_priv(clk->dev);
	struct cpg_mssr_info *info = priv->info;
	struct clk parent;
	const struct cpg_core_clk *core;
	const struct rcar_gen3_cpg_pll_config *pll_config =
					priv->cpg_pll_config;
	u32 value, mult, prediv, postdiv, rate = 0;
	int i, ret;

	debug("%s[%i] Clock: id=%lu\n", __func__, __LINE__, clk->id);

	ret = gen3_clk_get_parent(clk, &parent);
	if (ret) {
		printf("%s[%i] parent fail, ret=%i\n", __func__, __LINE__, ret);
		return ret;
	}

	if (gen3_clk_is_mod(clk)) {
		rate = gen3_clk_get_rate(&parent);
		debug("%s[%i] MOD clk: parent=%lu => rate=%u\n",
		      __func__, __LINE__, parent.id, rate);
		return rate;
	}

	ret = gen3_clk_get_core(clk, &core);
	if (ret)
		return ret;

	switch (core->type) {
	case CLK_TYPE_IN:
		if (core->id == info->clk_extal_id) {
			rate = clk_get_rate(&priv->clk_extal);
			debug("%s[%i] EXTAL clk: rate=%u\n",
			      __func__, __LINE__, rate);
			return rate;
		}

		if (core->id == info->clk_extalr_id) {
			rate = clk_get_rate(&priv->clk_extalr);
			debug("%s[%i] EXTALR clk: rate=%u\n",
			      __func__, __LINE__, rate);
			return rate;
		}

		return -EINVAL;

	case CLK_TYPE_GEN3_MAIN:
		rate = gen3_clk_get_rate(&parent) / pll_config->extal_div;
		debug("%s[%i] MAIN clk: parent=%i extal_div=%i => rate=%u\n",
		      __func__, __LINE__,
		      core->parent, pll_config->extal_div, rate);
		return rate;

	case CLK_TYPE_GEN3_PLL0:
		value = readl(priv->base + CPG_PLL0CR);
		mult = (((value >> 24) & 0x7f) + 1) * 2;
		rate = gen3_clk_get_rate(&parent) * mult;
		debug("%s[%i] PLL0 clk: parent=%i mult=%u => rate=%u\n",
		      __func__, __LINE__, core->parent, mult, rate);
		return rate;

	case CLK_TYPE_GEN3_PLL1:
		rate = gen3_clk_get_rate(&parent) * pll_config->pll1_mult;
		debug("%s[%i] PLL1 clk: parent=%i mul=%i => rate=%u\n",
		      __func__, __LINE__,
		      core->parent, pll_config->pll1_mult, rate);
		return rate;

	case CLK_TYPE_GEN3_PLL2:
		value = readl(priv->base + CPG_PLL2CR);
		mult = (((value >> 24) & 0x7f) + 1) * 2;
		rate = gen3_clk_get_rate(&parent) * mult;
		debug("%s[%i] PLL2 clk: parent=%i mult=%u => rate=%u\n",
		      __func__, __LINE__, core->parent, mult, rate);
		return rate;

	case CLK_TYPE_GEN3_PLL3:
		rate = gen3_clk_get_rate(&parent) * pll_config->pll3_mult;
		debug("%s[%i] PLL3 clk: parent=%i mul=%i => rate=%u\n",
		      __func__, __LINE__,
		      core->parent, pll_config->pll3_mult, rate);
		return rate;

	case CLK_TYPE_GEN3_PLL4:
		value = readl(priv->base + CPG_PLL4CR);
		mult = (((value >> 24) & 0x7f) + 1) * 2;
		rate = gen3_clk_get_rate(&parent) * mult;
		debug("%s[%i] PLL4 clk: parent=%i mult=%u => rate=%u\n",
		      __func__, __LINE__, core->parent, mult, rate);
		return rate;

	case CLK_TYPE_FF:
	case CLK_TYPE_GEN3_PE:		/* FIXME */
		rate = (gen3_clk_get_rate(&parent) * core->mult) / core->div;
		debug("%s[%i] FIXED clk: parent=%i div=%i mul=%i => rate=%u\n",
		      __func__, __LINE__,
		      core->parent, core->mult, core->div, rate);
		return rate;

	case CLK_TYPE_GEN3_SD:		/* FIXME */
		value = readl(priv->base + core->offset);
		value &= CPG_SD_STP_MASK | CPG_SD_FC_MASK;

		for (i = 0; i < ARRAY_SIZE(cpg_sd_div_table); i++) {
			if (cpg_sd_div_table[i].val != value)
				continue;

			rate = gen3_clk_get_rate(&parent) /
			       cpg_sd_div_table[i].div;
			debug("%s[%i] SD clk: parent=%i div=%i => rate=%u\n",
			      __func__, __LINE__,
			      core->parent, cpg_sd_div_table[i].div, rate);

			return rate;
		}

		return -EINVAL;

	case CLK_TYPE_GEN3_RPC:
		rate = gen3_clk_get_rate(&parent);

		value = readl(priv->base + core->offset);

		prediv = (value >> CPG_RPC_PREDIV_OFFSET) &
			 CPG_RPC_PREDIV_MASK;
		if (prediv == 2)
			rate /= 5;
		else if (prediv == 3)
			rate /= 6;
		else
			return -EINVAL;

		postdiv = (value >> CPG_RPC_POSTDIV_OFFSET) &
			  CPG_RPC_POSTDIV_MASK;
		rate /= postdiv + 1;

		debug("%s[%i] RPC clk: parent=%i prediv=%i postdiv=%i => rate=%u\n",
		      __func__, __LINE__,
		      core->parent, prediv, postdiv, rate);

		return -EINVAL;

	}

	printf("%s[%i] unknown fail\n", __func__, __LINE__);

	return -ENOENT;
}

static ulong gen3_clk_set_rate(struct clk *clk, ulong rate)
{
	return gen3_clk_get_rate(clk);
}

static int gen3_clk_of_xlate(struct clk *clk, struct ofnode_phandle_args *args)
{
	if (args->args_count != 2) {
		debug("Invaild args_count: %d\n", args->args_count);
		return -EINVAL;
	}

	clk->id = (args->args[0] << 16) | args->args[1];

	return 0;
}

const struct clk_ops gen3_clk_ops = {
	.enable		= gen3_clk_enable,
	.disable	= gen3_clk_disable,
	.get_rate	= gen3_clk_get_rate,
	.set_rate	= gen3_clk_set_rate,
	.of_xlate	= gen3_clk_of_xlate,
};

int gen3_clk_probe(struct udevice *dev)
{
	struct gen3_clk_priv *priv = dev_get_priv(dev);
	struct cpg_mssr_info *info =
		(struct cpg_mssr_info *)dev_get_driver_data(dev);
	fdt_addr_t rst_base;
	u32 cpg_mode;
	int ret;

	priv->base = (struct gen3_base *)devfdt_get_addr(dev);
	if (!priv->base)
		return -EINVAL;

	priv->info = info;
	ret = fdt_node_offset_by_compatible(gd->fdt_blob, -1, info->reset_node);
	if (ret < 0)
		return ret;

	rst_base = fdtdec_get_addr(gd->fdt_blob, ret, "reg");
	if (rst_base == FDT_ADDR_T_NONE)
		return -EINVAL;

	cpg_mode = readl(rst_base + CPG_RST_MODEMR);

	priv->cpg_pll_config =
		(struct rcar_gen3_cpg_pll_config *)info->get_pll_config(cpg_mode);
	if (!priv->cpg_pll_config->extal_div)
		return -EINVAL;

	ret = clk_get_by_name(dev, "extal", &priv->clk_extal);
	if (ret < 0)
		return ret;

	if (info->extalr_node) {
		ret = clk_get_by_name(dev, info->extalr_node, &priv->clk_extalr);
		if (ret < 0)
			return ret;
	}

	return 0;
}

int gen3_clk_remove(struct udevice *dev)
{
	struct gen3_clk_priv *priv = dev_get_priv(dev);
	struct cpg_mssr_info *info = priv->info;
	unsigned int i;

	/* Stop TMU0 */
	clrbits_le32(TMU_BASE + TSTR0, TSTR0_STR0);

	/* Stop module clock */
	for (i = 0; i < info->mstp_table_size; i++) {
		clrsetbits_le32(priv->base + SMSTPCR(i),
				info->mstp_table[i].dis,
				info->mstp_table[i].en);
		clrsetbits_le32(priv->base + RMSTPCR(i),
				info->mstp_table[i].dis, 0x0);
	}

	return 0;
}
Commit	Line	Data
36c2ee4c	1	/*
7691ff2a	2	* Renesas RCar Gen3 CPG MSSR driver
36c2ee4c MV	3	*
	4	* Copyright (C) 2017 Marek Vasut <marek.vasut@gmail.com>
	5	*
	6	* Based on the following driver from Linux kernel:
	7	* r8a7796 Clock Pulse Generator / Module Standby and Software Reset
	8	*
	9	* Copyright (C) 2016 Glider bvba
	10	*
	11	* SPDX-License-Identifier: GPL-2.0+
	12	*/
	13
	14	#include <common.h>
	15	#include <clk-uclass.h>
	16	#include <dm.h>
	17	#include <errno.h>
	18	#include <wait_bit.h>
	19	#include <asm/io.h>
	20
f77b5a4c MV	21	#include <dt-bindings/clock/renesas-cpg-mssr.h>
	22
	23	#include "renesas-cpg-mssr.h"
36c2ee4c MV	24
	25	#define CPG_RST_MODEMR 0x0060
	26
	27	#define CPG_PLL0CR 0x00d8
	28	#define CPG_PLL2CR 0x002c
	29	#define CPG_PLL4CR 0x01f4
	30
849ab0a6 MV	31	#define CPG_RPC_PREDIV_MASK 0x3
	32	#define CPG_RPC_PREDIV_OFFSET 3
	33	#define CPG_RPC_POSTDIV_MASK 0x7
	34	#define CPG_RPC_POSTDIV_OFFSET 0
	35
36c2ee4c MV	36	/*
	37	* Module Standby and Software Reset register offets.
	38	*
	39	* If the registers exist, these are valid for SH-Mobile, R-Mobile,
	40	* R-Car Gen2, R-Car Gen3, and RZ/G1.
	41	* These are NOT valid for R-Car Gen1 and RZ/A1!
	42	*/
	43
	44	/*
	45	* Module Stop Status Register offsets
	46	*/
	47
	48	static const u16 mstpsr[] = {
	49	0x030, 0x038, 0x040, 0x048, 0x04C, 0x03C, 0x1C0, 0x1C4,
	50	0x9A0, 0x9A4, 0x9A8, 0x9AC,
	51	};
	52
	53	#define MSTPSR(i) mstpsr[i]
	54
	55
	56	/*
	57	* System Module Stop Control Register offsets
	58	*/
	59
	60	static const u16 smstpcr[] = {
	61	0x130, 0x134, 0x138, 0x13C, 0x140, 0x144, 0x148, 0x14C,
	62	0x990, 0x994, 0x998, 0x99C,
	63	};
	64
	65	#define SMSTPCR(i) smstpcr[i]
	66
	67
	68	/* Realtime Module Stop Control Register offsets */
	69	#define RMSTPCR(i) (smstpcr[i] - 0x20)
	70
	71	/* Modem Module Stop Control Register offsets (r8a73a4) */
	72	#define MMSTPCR(i) (smstpcr[i] + 0x20)
	73
	74	/* Software Reset Clearing Register offsets */
	75	#define SRSTCLR(i) (0x940 + (i) * 4)
	76
36c2ee4c MV	77	/*
	78	* SDn Clock
	79	*/
	80	#define CPG_SD_STP_HCK BIT(9)
	81	#define CPG_SD_STP_CK BIT(8)
	82
	83	#define CPG_SD_STP_MASK (CPG_SD_STP_HCK \| CPG_SD_STP_CK)
	84	#define CPG_SD_FC_MASK (0x7 << 2 \| 0x3 << 0)
	85
	86	#define CPG_SD_DIV_TABLE_DATA(stp_hck, stp_ck, sd_srcfc, sd_fc, sd_div) \
	87	{ \
	88	.val = ((stp_hck) ? CPG_SD_STP_HCK : 0) \| \
	89	((stp_ck) ? CPG_SD_STP_CK : 0) \| \
	90	((sd_srcfc) << 2) \| \
	91	((sd_fc) << 0), \
	92	.div = (sd_div), \
	93	}
	94
	95	struct sd_div_table {
	96	u32 val;
	97	unsigned int div;
	98	};
	99
	100	/* SDn divider
	101	* sd_srcfc sd_fc div
	102	* stp_hck stp_ck (div) (div) = sd_srcfc x sd_fc
	103	*-------------------------------------------------------------------
	104	* 0 0 0 (1) 1 (4) 4
	105	* 0 0 1 (2) 1 (4) 8
	106	* 1 0 2 (4) 1 (4) 16
	107	* 1 0 3 (8) 1 (4) 32
	108	* 1 0 4 (16) 1 (4) 64
	109	* 0 0 0 (1) 0 (2) 2
	110	* 0 0 1 (2) 0 (2) 4
	111	* 1 0 2 (4) 0 (2) 8
	112	* 1 0 3 (8) 0 (2) 16
	113	* 1 0 4 (16) 0 (2) 32
	114	*/
	115	static const struct sd_div_table cpg_sd_div_table[] = {
	116	/* CPG_SD_DIV_TABLE_DATA(stp_hck, stp_ck, sd_srcfc, sd_fc, sd_div) */
	117	CPG_SD_DIV_TABLE_DATA(0, 0, 0, 1, 4),
	118	CPG_SD_DIV_TABLE_DATA(0, 0, 1, 1, 8),
	119	CPG_SD_DIV_TABLE_DATA(1, 0, 2, 1, 16),
	120	CPG_SD_DIV_TABLE_DATA(1, 0, 3, 1, 32),
	121	CPG_SD_DIV_TABLE_DATA(1, 0, 4, 1, 64),
	122	CPG_SD_DIV_TABLE_DATA(0, 0, 0, 0, 2),
	123	CPG_SD_DIV_TABLE_DATA(0, 0, 1, 0, 4),
	124	CPG_SD_DIV_TABLE_DATA(1, 0, 2, 0, 8),
	125	CPG_SD_DIV_TABLE_DATA(1, 0, 3, 0, 16),
	126	CPG_SD_DIV_TABLE_DATA(1, 0, 4, 0, 32),
	127	};
	128
	129	static bool gen3_clk_is_mod(struct clk *clk)
	130	{
	131	return (clk->id >> 16) == CPG_MOD;
	132	}
	133
	134	static int gen3_clk_get_mod(struct clk clk, const struct mssr_mod_clk *mssr)
	135	{
	136	struct gen3_clk_priv *priv = dev_get_priv(clk->dev);
f77b5a4c	137	struct cpg_mssr_info *info = priv->info;
36c2ee4c MV	138	const unsigned long clkid = clk->id & 0xffff;
	139	int i;
	140
	141	if (!gen3_clk_is_mod(clk))
	142	return -EINVAL;
	143
f77b5a4c	144	for (i = 0; i < info->mod_clk_size; i++) {
f11c9679 MV	145	if (info->mod_clk[i].id !=
f11c9679 MV	146	(info->mod_clk_base + MOD_CLK_PACK(clkid)))
36c2ee4c MV	147	continue;
36c2ee4c MV	148
f77b5a4c	149	*mssr = &info->mod_clk[i];
36c2ee4c MV	150	return 0;
	151	}
	152
	153	return -ENODEV;
	154	}
	155
	156	static int gen3_clk_get_core(struct clk clk, const struct cpg_core_clk *core)
	157	{
fd8692b8	158	struct gen3_clk_priv *priv = dev_get_priv(clk->dev);
f77b5a4c	159	struct cpg_mssr_info *info = priv->info;
36c2ee4c MV	160	const unsigned long clkid = clk->id & 0xffff;
	161	int i;
	162
	163	if (gen3_clk_is_mod(clk))
	164	return -EINVAL;
	165
f77b5a4c MV	166	for (i = 0; i < info->core_clk_size; i++) {
f77b5a4c MV	167	if (info->core_clk[i].id != clkid)
36c2ee4c MV	168	continue;
36c2ee4c MV	169
f77b5a4c	170	*core = &info->core_clk[i];
36c2ee4c MV	171	return 0;
	172	}
	173
	174	return -ENODEV;
	175	}
	176
	177	static int gen3_clk_get_parent(struct clk clk, struct clk parent)
	178	{
	179	const struct cpg_core_clk *core;
	180	const struct mssr_mod_clk *mssr;
	181	int ret;
	182
	183	if (gen3_clk_is_mod(clk)) {
	184	ret = gen3_clk_get_mod(clk, &mssr);
	185	if (ret)
	186	return ret;
	187
	188	parent->id = mssr->parent;
	189	} else {
	190	ret = gen3_clk_get_core(clk, &core);
	191	if (ret)
	192	return ret;
	193
	194	if (core->type == CLK_TYPE_IN)
	195	parent->id = ~0; /* Top-level clock */
	196	else
	197	parent->id = core->parent;
	198	}
	199
	200	parent->dev = clk->dev;
	201
	202	return 0;
	203	}
	204
4b20eef3 MV	205	static int gen3_clk_setup_sdif_div(struct clk *clk)
	206	{
	207	struct gen3_clk_priv *priv = dev_get_priv(clk->dev);
	208	const struct cpg_core_clk *core;
	209	struct clk parent;
	210	int ret;
	211
	212	ret = gen3_clk_get_parent(clk, &parent);
	213	if (ret) {
	214	printf("%s[%i] parent fail, ret=%i\n", __func__, __LINE__, ret);
	215	return ret;
	216	}
	217
	218	if (gen3_clk_is_mod(&parent))
	219	return 0;
	220
	221	ret = gen3_clk_get_core(&parent, &core);
	222	if (ret)
	223	return ret;
	224
	225	if (core->type != CLK_TYPE_GEN3_SD)
	226	return 0;
	227
	228	debug("%s[%i] SDIF offset=%x\n", __func__, __LINE__, core->offset);
	229
	230	writel(1, priv->base + core->offset);
	231
	232	return 0;
	233	}
	234
36c2ee4c MV	235	static int gen3_clk_endisable(struct clk *clk, bool enable)
	236	{
	237	struct gen3_clk_priv *priv = dev_get_priv(clk->dev);
	238	const unsigned long clkid = clk->id & 0xffff;
	239	const unsigned int reg = clkid / 100;
	240	const unsigned int bit = clkid % 100;
	241	const u32 bitmask = BIT(bit);
4b20eef3	242	int ret;
36c2ee4c MV	243
	244	if (!gen3_clk_is_mod(clk))
	245	return -EINVAL;
	246
	247	debug("%s[%i] MSTP %lu=%02u/%02u %s\n", __func__, __LINE__,
	248	clkid, reg, bit, enable ? "ON" : "OFF");
	249
	250	if (enable) {
4b20eef3 MV	251	ret = gen3_clk_setup_sdif_div(clk);
	252	if (ret)
	253	return ret;
36c2ee4c MV	254	clrbits_le32(priv->base + SMSTPCR(reg), bitmask);
	255	return wait_for_bit("MSTP", priv->base + MSTPSR(reg),
	256	bitmask, 0, 100, 0);
	257	} else {
	258	setbits_le32(priv->base + SMSTPCR(reg), bitmask);
	259	return 0;
	260	}
	261	}
	262
	263	static int gen3_clk_enable(struct clk *clk)
	264	{
	265	return gen3_clk_endisable(clk, true);
	266	}
	267
	268	static int gen3_clk_disable(struct clk *clk)
	269	{
	270	return gen3_clk_endisable(clk, false);
	271	}
	272
	273	static ulong gen3_clk_get_rate(struct clk *clk)
	274	{
	275	struct gen3_clk_priv *priv = dev_get_priv(clk->dev);
f11c9679	276	struct cpg_mssr_info *info = priv->info;
36c2ee4c MV	277	struct clk parent;
	278	const struct cpg_core_clk *core;
	279	const struct rcar_gen3_cpg_pll_config *pll_config =
	280	priv->cpg_pll_config;
849ab0a6	281	u32 value, mult, prediv, postdiv, rate = 0;
36c2ee4c MV	282	int i, ret;
	283
	284	debug("%s[%i] Clock: id=%lu\n", __func__, __LINE__, clk->id);
	285
	286	ret = gen3_clk_get_parent(clk, &parent);
	287	if (ret) {
	288	printf("%s[%i] parent fail, ret=%i\n", __func__, __LINE__, ret);
	289	return ret;
	290	}
	291
	292	if (gen3_clk_is_mod(clk)) {
	293	rate = gen3_clk_get_rate(&parent);
	294	debug("%s[%i] MOD clk: parent=%lu => rate=%u\n",
	295	__func__, __LINE__, parent.id, rate);
	296	return rate;
	297	}
	298
	299	ret = gen3_clk_get_core(clk, &core);
	300	if (ret)
	301	return ret;
	302
	303	switch (core->type) {
	304	case CLK_TYPE_IN:
f11c9679	305	if (core->id == info->clk_extal_id) {
36c2ee4c MV	306	rate = clk_get_rate(&priv->clk_extal);
	307	debug("%s[%i] EXTAL clk: rate=%u\n",
	308	__func__, __LINE__, rate);
	309	return rate;
	310	}
	311
f11c9679	312	if (core->id == info->clk_extalr_id) {
36c2ee4c MV	313	rate = clk_get_rate(&priv->clk_extalr);
	314	debug("%s[%i] EXTALR clk: rate=%u\n",
	315	__func__, __LINE__, rate);
	316	return rate;
	317	}
	318
	319	return -EINVAL;
	320
	321	case CLK_TYPE_GEN3_MAIN:
	322	rate = gen3_clk_get_rate(&parent) / pll_config->extal_div;
	323	debug("%s[%i] MAIN clk: parent=%i extal_div=%i => rate=%u\n",
	324	__func__, __LINE__,
	325	core->parent, pll_config->extal_div, rate);
	326	return rate;
	327
	328	case CLK_TYPE_GEN3_PLL0:
	329	value = readl(priv->base + CPG_PLL0CR);
	330	mult = (((value >> 24) & 0x7f) + 1) * 2;
	331	rate = gen3_clk_get_rate(&parent) * mult;
	332	debug("%s[%i] PLL0 clk: parent=%i mult=%u => rate=%u\n",
	333	__func__, __LINE__, core->parent, mult, rate);
	334	return rate;
	335
	336	case CLK_TYPE_GEN3_PLL1:
	337	rate = gen3_clk_get_rate(&parent) * pll_config->pll1_mult;
	338	debug("%s[%i] PLL1 clk: parent=%i mul=%i => rate=%u\n",
	339	__func__, __LINE__,
	340	core->parent, pll_config->pll1_mult, rate);
	341	return rate;
	342
	343	case CLK_TYPE_GEN3_PLL2:
	344	value = readl(priv->base + CPG_PLL2CR);
	345	mult = (((value >> 24) & 0x7f) + 1) * 2;
	346	rate = gen3_clk_get_rate(&parent) * mult;
	347	debug("%s[%i] PLL2 clk: parent=%i mult=%u => rate=%u\n",
	348	__func__, __LINE__, core->parent, mult, rate);
	349	return rate;
	350
	351	case CLK_TYPE_GEN3_PLL3:
	352	rate = gen3_clk_get_rate(&parent) * pll_config->pll3_mult;
	353	debug("%s[%i] PLL3 clk: parent=%i mul=%i => rate=%u\n",
	354	__func__, __LINE__,
	355	core->parent, pll_config->pll3_mult, rate);
	356	return rate;
	357
	358	case CLK_TYPE_GEN3_PLL4:
	359	value = readl(priv->base + CPG_PLL4CR);
	360	mult = (((value >> 24) & 0x7f) + 1) * 2;
	361	rate = gen3_clk_get_rate(&parent) * mult;
	362	debug("%s[%i] PLL4 clk: parent=%i mult=%u => rate=%u\n",
	363	__func__, __LINE__, core->parent, mult, rate);
	364	return rate;
	365
	366	case CLK_TYPE_FF:
2c150950	367	case CLK_TYPE_GEN3_PE: /* FIXME */
36c2ee4c MV	368	rate = (gen3_clk_get_rate(&parent) * core->mult) / core->div;
	369	debug("%s[%i] FIXED clk: parent=%i div=%i mul=%i => rate=%u\n",
	370	__func__, __LINE__,
	371	core->parent, core->mult, core->div, rate);
	372	return rate;
	373
	374	case CLK_TYPE_GEN3_SD: /* FIXME */
	375	value = readl(priv->base + core->offset);
	376	value &= CPG_SD_STP_MASK \| CPG_SD_FC_MASK;
	377
	378	for (i = 0; i < ARRAY_SIZE(cpg_sd_div_table); i++) {
	379	if (cpg_sd_div_table[i].val != value)
	380	continue;
	381
	382	rate = gen3_clk_get_rate(&parent) /
	383	cpg_sd_div_table[i].div;
	384	debug("%s[%i] SD clk: parent=%i div=%i => rate=%u\n",
	385	__func__, __LINE__,
	386	core->parent, cpg_sd_div_table[i].div, rate);
	387
	388	return rate;
	389	}
	390
	391	return -EINVAL;
849ab0a6 MV	392
	393	case CLK_TYPE_GEN3_RPC:
	394	rate = gen3_clk_get_rate(&parent);
	395
	396	value = readl(priv->base + core->offset);
	397
	398	prediv = (value >> CPG_RPC_PREDIV_OFFSET) &
	399	CPG_RPC_PREDIV_MASK;
	400	if (prediv == 2)
	401	rate /= 5;
	402	else if (prediv == 3)
	403	rate /= 6;
	404	else
	405	return -EINVAL;
	406
	407	postdiv = (value >> CPG_RPC_POSTDIV_OFFSET) &
	408	CPG_RPC_POSTDIV_MASK;
	409	rate /= postdiv + 1;
	410
	411	debug("%s[%i] RPC clk: parent=%i prediv=%i postdiv=%i => rate=%u\n",
	412	__func__, __LINE__,
	413	core->parent, prediv, postdiv, rate);
	414
	415	return -EINVAL;
	416
36c2ee4c MV	417	}
	418
	419	printf("%s[%i] unknown fail\n", __func__, __LINE__);
	420
	421	return -ENOENT;
	422	}
	423
	424	static ulong gen3_clk_set_rate(struct clk *clk, ulong rate)
	425	{
	426	return gen3_clk_get_rate(clk);
	427	}
	428
	429	static int gen3_clk_of_xlate(struct clk clk, struct ofnode_phandle_args args)
	430	{
	431	if (args->args_count != 2) {
	432	debug("Invaild args_count: %d\n", args->args_count);
	433	return -EINVAL;
	434	}
	435
	436	clk->id = (args->args[0] << 16) \| args->args[1];
	437
	438	return 0;
	439	}
	440
f77b5a4c	441	const struct clk_ops gen3_clk_ops = {
36c2ee4c MV	442	.enable = gen3_clk_enable,
	443	.disable = gen3_clk_disable,
	444	.get_rate = gen3_clk_get_rate,
	445	.set_rate = gen3_clk_set_rate,
	446	.of_xlate = gen3_clk_of_xlate,
	447	};
	448
f77b5a4c	449	int gen3_clk_probe(struct udevice *dev)
36c2ee4c MV	450	{
36c2ee4c MV	451	struct gen3_clk_priv *priv = dev_get_priv(dev);
f77b5a4c MV	452	struct cpg_mssr_info *info =
f77b5a4c MV	453	(struct cpg_mssr_info *)dev_get_driver_data(dev);
36c2ee4c MV	454	fdt_addr_t rst_base;
	455	u32 cpg_mode;
	456	int ret;
	457
	458	priv->base = (struct gen3_base *)devfdt_get_addr(dev);
	459	if (!priv->base)
	460	return -EINVAL;
	461
f77b5a4c MV	462	priv->info = info;
	463	ret = fdt_node_offset_by_compatible(gd->fdt_blob, -1, info->reset_node);
	464	if (ret < 0)
	465	return ret;
36c2ee4c MV	466
	467	rst_base = fdtdec_get_addr(gd->fdt_blob, ret, "reg");
	468	if (rst_base == FDT_ADDR_T_NONE)
	469	return -EINVAL;
	470
	471	cpg_mode = readl(rst_base + CPG_RST_MODEMR);
	472
7c885563 MV	473	priv->cpg_pll_config =
7c885563 MV	474	(struct rcar_gen3_cpg_pll_config *)info->get_pll_config(cpg_mode);
36c2ee4c MV	475	if (!priv->cpg_pll_config->extal_div)
	476	return -EINVAL;
	477
	478	ret = clk_get_by_name(dev, "extal", &priv->clk_extal);
	479	if (ret < 0)
	480	return ret;
	481
f77b5a4c MV	482	if (info->extalr_node) {
f77b5a4c MV	483	ret = clk_get_by_name(dev, info->extalr_node, &priv->clk_extalr);
2c150950 MV	484	if (ret < 0)
	485	return ret;
	486	}
36c2ee4c MV	487
	488	return 0;
	489	}
	490
f77b5a4c	491	int gen3_clk_remove(struct udevice *dev)
18cac5af MV	492	{
18cac5af MV	493	struct gen3_clk_priv *priv = dev_get_priv(dev);
f77b5a4c MV	494	struct cpg_mssr_info *info = priv->info;
f77b5a4c MV	495	unsigned int i;
18cac5af MV	496
	497	/* Stop TMU0 */
	498	clrbits_le32(TMU_BASE + TSTR0, TSTR0_STR0);
	499
	500	/* Stop module clock */
f77b5a4c MV	501	for (i = 0; i < info->mstp_table_size; i++) {
	502	clrsetbits_le32(priv->base + SMSTPCR(i),
	503	info->mstp_table[i].dis,
	504	info->mstp_table[i].en);
	505	clrsetbits_le32(priv->base + RMSTPCR(i),
	506	info->mstp_table[i].dis, 0x0);
18cac5af MV	507	}
	508
	509	return 0;
	510	}