[people/ms/u-boot.git] / drivers / clk / renesas / clk-rcar-gen3.c

/*
 * Renesas RCar Gen3 CPG MSSR driver
 *
 * Copyright (C) 2017 Marek Vasut <marek.vasut@gmail.com>
 *
 * Based on the following driver from Linux kernel:
 * r8a7796 Clock Pulse Generator / Module Standby and Software Reset
 *
 * Copyright (C) 2016 Glider bvba
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#include <common.h>
#include <clk-uclass.h>
#include <dm.h>
#include <errno.h>
#include <wait_bit.h>
#include <asm/io.h>

#include <dt-bindings/clock/renesas-cpg-mssr.h>

#include "renesas-cpg-mssr.h"
#include "rcar-gen3-cpg.h"

#define CPG_RST_MODEMR		0x0060

#define CPG_PLL0CR		0x00d8
#define CPG_PLL2CR		0x002c
#define CPG_PLL4CR		0x01f4

#define CPG_RPC_PREDIV_MASK	0x3
#define CPG_RPC_PREDIV_OFFSET	3
#define CPG_RPC_POSTDIV_MASK	0x7
#define CPG_RPC_POSTDIV_OFFSET	0

/*
 * SDn Clock
 */
#define CPG_SD_STP_HCK		BIT(9)
#define CPG_SD_STP_CK		BIT(8)

#define CPG_SD_STP_MASK		(CPG_SD_STP_HCK | CPG_SD_STP_CK)
#define CPG_SD_FC_MASK		(0x7 << 2 | 0x3 << 0)

#define CPG_SD_DIV_TABLE_DATA(stp_hck, stp_ck, sd_srcfc, sd_fc, sd_div) \
{ \
	.val = ((stp_hck) ? CPG_SD_STP_HCK : 0) | \
	       ((stp_ck) ? CPG_SD_STP_CK : 0) | \
	       ((sd_srcfc) << 2) | \
	       ((sd_fc) << 0), \
	.div = (sd_div), \
}

struct sd_div_table {
	u32 val;
	unsigned int div;
};

/* SDn divider
 *                     sd_srcfc   sd_fc   div
 * stp_hck   stp_ck    (div)      (div)     = sd_srcfc x sd_fc
 *-------------------------------------------------------------------
 *  0         0         0 (1)      1 (4)      4
 *  0         0         1 (2)      1 (4)      8
 *  1         0         2 (4)      1 (4)     16
 *  1         0         3 (8)      1 (4)     32
 *  1         0         4 (16)     1 (4)     64
 *  0         0         0 (1)      0 (2)      2
 *  0         0         1 (2)      0 (2)      4
 *  1         0         2 (4)      0 (2)      8
 *  1         0         3 (8)      0 (2)     16
 *  1         0         4 (16)     0 (2)     32
 */
static const struct sd_div_table cpg_sd_div_table[] = {
/*	CPG_SD_DIV_TABLE_DATA(stp_hck,  stp_ck,   sd_srcfc,   sd_fc,  sd_div) */
	CPG_SD_DIV_TABLE_DATA(0,        0,        0,          1,        4),
	CPG_SD_DIV_TABLE_DATA(0,        0,        1,          1,        8),
	CPG_SD_DIV_TABLE_DATA(1,        0,        2,          1,       16),
	CPG_SD_DIV_TABLE_DATA(1,        0,        3,          1,       32),
	CPG_SD_DIV_TABLE_DATA(1,        0,        4,          1,       64),
	CPG_SD_DIV_TABLE_DATA(0,        0,        0,          0,        2),
	CPG_SD_DIV_TABLE_DATA(0,        0,        1,          0,        4),
	CPG_SD_DIV_TABLE_DATA(1,        0,        2,          0,        8),
	CPG_SD_DIV_TABLE_DATA(1,        0,        3,          0,       16),
	CPG_SD_DIV_TABLE_DATA(1,        0,        4,          0,       32),
};

static int gen3_clk_setup_sdif_div(struct clk *clk)
{
	struct gen3_clk_priv *priv = dev_get_priv(clk->dev);
	struct cpg_mssr_info *info = priv->info;
	const struct cpg_core_clk *core;
	struct clk parent;
	int ret;

	ret = renesas_clk_get_parent(clk, info, &parent);
	if (ret) {
		printf("%s[%i] parent fail, ret=%i\n", __func__, __LINE__, ret);
		return ret;
	}

	if (renesas_clk_is_mod(&parent))
		return 0;

	ret = renesas_clk_get_core(&parent, info, &core);
	if (ret)
		return ret;

	if (core->type != CLK_TYPE_GEN3_SD)
		return 0;

	debug("%s[%i] SDIF offset=%x\n", __func__, __LINE__, core->offset);

	writel(1, priv->base + core->offset);

	return 0;
}

static int gen3_clk_enable(struct clk *clk)
{
	struct gen3_clk_priv *priv = dev_get_priv(clk->dev);
	int ret = gen3_clk_setup_sdif_div(clk);

	if (ret)
		return ret;

	return renesas_clk_endisable(clk, priv->base, true);
}

static int gen3_clk_disable(struct clk *clk)
{
	struct gen3_clk_priv *priv = dev_get_priv(clk->dev);

	return renesas_clk_endisable(clk, priv->base, false);
}

static ulong gen3_clk_get_rate(struct clk *clk)
{
	struct gen3_clk_priv *priv = dev_get_priv(clk->dev);
	struct cpg_mssr_info *info = priv->info;
	struct clk parent;
	const struct cpg_core_clk *core;
	const struct rcar_gen3_cpg_pll_config *pll_config =
					priv->cpg_pll_config;
	u32 value, mult, prediv, postdiv, rate = 0;
	int i, ret;

	debug("%s[%i] Clock: id=%lu\n", __func__, __LINE__, clk->id);

	ret = renesas_clk_get_parent(clk, info, &parent);
	if (ret) {
		printf("%s[%i] parent fail, ret=%i\n", __func__, __LINE__, ret);
		return ret;
	}

	if (renesas_clk_is_mod(clk)) {
		rate = gen3_clk_get_rate(&parent);
		debug("%s[%i] MOD clk: parent=%lu => rate=%u\n",
		      __func__, __LINE__, parent.id, rate);
		return rate;
	}

	ret = renesas_clk_get_core(clk, info, &core);
	if (ret)
		return ret;

	switch (core->type) {
	case CLK_TYPE_IN:
		if (core->id == info->clk_extal_id) {
			rate = clk_get_rate(&priv->clk_extal);
			debug("%s[%i] EXTAL clk: rate=%u\n",
			      __func__, __LINE__, rate);
			return rate;
		}

		if (core->id == info->clk_extalr_id) {
			rate = clk_get_rate(&priv->clk_extalr);
			debug("%s[%i] EXTALR clk: rate=%u\n",
			      __func__, __LINE__, rate);
			return rate;
		}

		return -EINVAL;

	case CLK_TYPE_GEN3_MAIN:
		rate = gen3_clk_get_rate(&parent) / pll_config->extal_div;
		debug("%s[%i] MAIN clk: parent=%i extal_div=%i => rate=%u\n",
		      __func__, __LINE__,
		      core->parent, pll_config->extal_div, rate);
		return rate;

	case CLK_TYPE_GEN3_PLL0:
		value = readl(priv->base + CPG_PLL0CR);
		mult = (((value >> 24) & 0x7f) + 1) * 2;
		rate = gen3_clk_get_rate(&parent) * mult;
		debug("%s[%i] PLL0 clk: parent=%i mult=%u => rate=%u\n",
		      __func__, __LINE__, core->parent, mult, rate);
		return rate;

	case CLK_TYPE_GEN3_PLL1:
		rate = gen3_clk_get_rate(&parent) * pll_config->pll1_mult;
		debug("%s[%i] PLL1 clk: parent=%i mul=%i => rate=%u\n",
		      __func__, __LINE__,
		      core->parent, pll_config->pll1_mult, rate);
		return rate;

	case CLK_TYPE_GEN3_PLL2:
		value = readl(priv->base + CPG_PLL2CR);
		mult = (((value >> 24) & 0x7f) + 1) * 2;
		rate = gen3_clk_get_rate(&parent) * mult;
		debug("%s[%i] PLL2 clk: parent=%i mult=%u => rate=%u\n",
		      __func__, __LINE__, core->parent, mult, rate);
		return rate;

	case CLK_TYPE_GEN3_PLL3:
		rate = gen3_clk_get_rate(&parent) * pll_config->pll3_mult;
		debug("%s[%i] PLL3 clk: parent=%i mul=%i => rate=%u\n",
		      __func__, __LINE__,
		      core->parent, pll_config->pll3_mult, rate);
		return rate;

	case CLK_TYPE_GEN3_PLL4:
		value = readl(priv->base + CPG_PLL4CR);
		mult = (((value >> 24) & 0x7f) + 1) * 2;
		rate = gen3_clk_get_rate(&parent) * mult;
		debug("%s[%i] PLL4 clk: parent=%i mult=%u => rate=%u\n",
		      __func__, __LINE__, core->parent, mult, rate);
		return rate;

	case CLK_TYPE_FF:
	case CLK_TYPE_GEN3_PE:		/* FIXME */
		rate = (gen3_clk_get_rate(&parent) * core->mult) / core->div;
		debug("%s[%i] FIXED clk: parent=%i div=%i mul=%i => rate=%u\n",
		      __func__, __LINE__,
		      core->parent, core->mult, core->div, rate);
		return rate;

	case CLK_TYPE_GEN3_SD:		/* FIXME */
		value = readl(priv->base + core->offset);
		value &= CPG_SD_STP_MASK | CPG_SD_FC_MASK;

		for (i = 0; i < ARRAY_SIZE(cpg_sd_div_table); i++) {
			if (cpg_sd_div_table[i].val != value)
				continue;

			rate = gen3_clk_get_rate(&parent) /
			       cpg_sd_div_table[i].div;
			debug("%s[%i] SD clk: parent=%i div=%i => rate=%u\n",
			      __func__, __LINE__,
			      core->parent, cpg_sd_div_table[i].div, rate);

			return rate;
		}

		return -EINVAL;

	case CLK_TYPE_GEN3_RPC:
		rate = gen3_clk_get_rate(&parent);

		value = readl(priv->base + core->offset);

		prediv = (value >> CPG_RPC_PREDIV_OFFSET) &
			 CPG_RPC_PREDIV_MASK;
		if (prediv == 2)
			rate /= 5;
		else if (prediv == 3)
			rate /= 6;
		else
			return -EINVAL;

		postdiv = (value >> CPG_RPC_POSTDIV_OFFSET) &
			  CPG_RPC_POSTDIV_MASK;
		rate /= postdiv + 1;

		debug("%s[%i] RPC clk: parent=%i prediv=%i postdiv=%i => rate=%u\n",
		      __func__, __LINE__,
		      core->parent, prediv, postdiv, rate);

		return -EINVAL;

	}

	printf("%s[%i] unknown fail\n", __func__, __LINE__);

	return -ENOENT;
}

static ulong gen3_clk_set_rate(struct clk *clk, ulong rate)
{
	/* Force correct SD-IF divider configuration if applicable */
	gen3_clk_setup_sdif_div(clk);
	return gen3_clk_get_rate(clk);
}

static int gen3_clk_of_xlate(struct clk *clk, struct ofnode_phandle_args *args)
{
	if (args->args_count != 2) {
		debug("Invaild args_count: %d\n", args->args_count);
		return -EINVAL;
	}

	clk->id = (args->args[0] << 16) | args->args[1];

	return 0;
}

const struct clk_ops gen3_clk_ops = {
	.enable		= gen3_clk_enable,
	.disable	= gen3_clk_disable,
	.get_rate	= gen3_clk_get_rate,
	.set_rate	= gen3_clk_set_rate,
	.of_xlate	= gen3_clk_of_xlate,
};

int gen3_clk_probe(struct udevice *dev)
{
	struct gen3_clk_priv *priv = dev_get_priv(dev);
	struct cpg_mssr_info *info =
		(struct cpg_mssr_info *)dev_get_driver_data(dev);
	fdt_addr_t rst_base;
	u32 cpg_mode;
	int ret;

	priv->base = (struct gen3_base *)devfdt_get_addr(dev);
	if (!priv->base)
		return -EINVAL;

	priv->info = info;
	ret = fdt_node_offset_by_compatible(gd->fdt_blob, -1, info->reset_node);
	if (ret < 0)
		return ret;

	rst_base = fdtdec_get_addr(gd->fdt_blob, ret, "reg");
	if (rst_base == FDT_ADDR_T_NONE)
		return -EINVAL;

	cpg_mode = readl(rst_base + CPG_RST_MODEMR);

	priv->cpg_pll_config =
		(struct rcar_gen3_cpg_pll_config *)info->get_pll_config(cpg_mode);
	if (!priv->cpg_pll_config->extal_div)
		return -EINVAL;

	ret = clk_get_by_name(dev, "extal", &priv->clk_extal);
	if (ret < 0)
		return ret;

	if (info->extalr_node) {
		ret = clk_get_by_name(dev, info->extalr_node, &priv->clk_extalr);
		if (ret < 0)
			return ret;
	}

	return 0;
}

int gen3_clk_remove(struct udevice *dev)
{
	struct gen3_clk_priv *priv = dev_get_priv(dev);

	return renesas_clk_remove(priv->base, priv->info);
}
Commit	Line	Data
36c2ee4c	1	/*
7691ff2a	2	* Renesas RCar Gen3 CPG MSSR driver
36c2ee4c MV	3	*
	4	* Copyright (C) 2017 Marek Vasut <marek.vasut@gmail.com>
	5	*
	6	* Based on the following driver from Linux kernel:
	7	* r8a7796 Clock Pulse Generator / Module Standby and Software Reset
	8	*
	9	* Copyright (C) 2016 Glider bvba
	10	*
	11	* SPDX-License-Identifier: GPL-2.0+
	12	*/
	13
	14	#include <common.h>
	15	#include <clk-uclass.h>
	16	#include <dm.h>
	17	#include <errno.h>
	18	#include <wait_bit.h>
	19	#include <asm/io.h>
	20
f77b5a4c MV	21	#include <dt-bindings/clock/renesas-cpg-mssr.h>
	22
	23	#include "renesas-cpg-mssr.h"
d2628671	24	#include "rcar-gen3-cpg.h"
36c2ee4c MV	25
	26	#define CPG_RST_MODEMR 0x0060
	27
	28	#define CPG_PLL0CR 0x00d8
	29	#define CPG_PLL2CR 0x002c
	30	#define CPG_PLL4CR 0x01f4
	31
849ab0a6 MV	32	#define CPG_RPC_PREDIV_MASK 0x3
	33	#define CPG_RPC_PREDIV_OFFSET 3
	34	#define CPG_RPC_POSTDIV_MASK 0x7
	35	#define CPG_RPC_POSTDIV_OFFSET 0
	36
36c2ee4c MV	37	/*
	38	* SDn Clock
	39	*/
	40	#define CPG_SD_STP_HCK BIT(9)
	41	#define CPG_SD_STP_CK BIT(8)
	42
	43	#define CPG_SD_STP_MASK (CPG_SD_STP_HCK \| CPG_SD_STP_CK)
	44	#define CPG_SD_FC_MASK (0x7 << 2 \| 0x3 << 0)
	45
	46	#define CPG_SD_DIV_TABLE_DATA(stp_hck, stp_ck, sd_srcfc, sd_fc, sd_div) \
	47	{ \
	48	.val = ((stp_hck) ? CPG_SD_STP_HCK : 0) \| \
	49	((stp_ck) ? CPG_SD_STP_CK : 0) \| \
	50	((sd_srcfc) << 2) \| \
	51	((sd_fc) << 0), \
	52	.div = (sd_div), \
	53	}
	54
	55	struct sd_div_table {
	56	u32 val;
	57	unsigned int div;
	58	};
	59
	60	/* SDn divider
	61	* sd_srcfc sd_fc div
	62	* stp_hck stp_ck (div) (div) = sd_srcfc x sd_fc
	63	*-------------------------------------------------------------------
	64	* 0 0 0 (1) 1 (4) 4
	65	* 0 0 1 (2) 1 (4) 8
	66	* 1 0 2 (4) 1 (4) 16
	67	* 1 0 3 (8) 1 (4) 32
	68	* 1 0 4 (16) 1 (4) 64
	69	* 0 0 0 (1) 0 (2) 2
	70	* 0 0 1 (2) 0 (2) 4
	71	* 1 0 2 (4) 0 (2) 8
	72	* 1 0 3 (8) 0 (2) 16
	73	* 1 0 4 (16) 0 (2) 32
	74	*/
	75	static const struct sd_div_table cpg_sd_div_table[] = {
	76	/* CPG_SD_DIV_TABLE_DATA(stp_hck, stp_ck, sd_srcfc, sd_fc, sd_div) */
	77	CPG_SD_DIV_TABLE_DATA(0, 0, 0, 1, 4),
	78	CPG_SD_DIV_TABLE_DATA(0, 0, 1, 1, 8),
	79	CPG_SD_DIV_TABLE_DATA(1, 0, 2, 1, 16),
	80	CPG_SD_DIV_TABLE_DATA(1, 0, 3, 1, 32),
	81	CPG_SD_DIV_TABLE_DATA(1, 0, 4, 1, 64),
	82	CPG_SD_DIV_TABLE_DATA(0, 0, 0, 0, 2),
	83	CPG_SD_DIV_TABLE_DATA(0, 0, 1, 0, 4),
	84	CPG_SD_DIV_TABLE_DATA(1, 0, 2, 0, 8),
	85	CPG_SD_DIV_TABLE_DATA(1, 0, 3, 0, 16),
	86	CPG_SD_DIV_TABLE_DATA(1, 0, 4, 0, 32),
	87	};
	88
4b20eef3 MV	89	static int gen3_clk_setup_sdif_div(struct clk *clk)
	90	{
	91	struct gen3_clk_priv *priv = dev_get_priv(clk->dev);
d2628671	92	struct cpg_mssr_info *info = priv->info;
4b20eef3 MV	93	const struct cpg_core_clk *core;
	94	struct clk parent;
	95	int ret;
	96
d2628671	97	ret = renesas_clk_get_parent(clk, info, &parent);
4b20eef3 MV	98	if (ret) {
	99	printf("%s[%i] parent fail, ret=%i\n", __func__, __LINE__, ret);
	100	return ret;
	101	}
	102
d2628671	103	if (renesas_clk_is_mod(&parent))
4b20eef3 MV	104	return 0;
4b20eef3 MV	105
d2628671	106	ret = renesas_clk_get_core(&parent, info, &core);
4b20eef3 MV	107	if (ret)
	108	return ret;
	109
	110	if (core->type != CLK_TYPE_GEN3_SD)
	111	return 0;
	112
	113	debug("%s[%i] SDIF offset=%x\n", __func__, __LINE__, core->offset);
	114
	115	writel(1, priv->base + core->offset);
	116
	117	return 0;
	118	}
	119
d2628671	120	static int gen3_clk_enable(struct clk *clk)
36c2ee4c MV	121	{
36c2ee4c MV	122	struct gen3_clk_priv *priv = dev_get_priv(clk->dev);
d2628671	123	int ret = gen3_clk_setup_sdif_div(clk);
36c2ee4c	124
d2628671 MV	125	if (ret)
d2628671 MV	126	return ret;
36c2ee4c	127
d2628671	128	return renesas_clk_endisable(clk, priv->base, true);
36c2ee4c MV	129	}
	130
	131	static int gen3_clk_disable(struct clk *clk)
	132	{
d2628671 MV	133	struct gen3_clk_priv *priv = dev_get_priv(clk->dev);
	134
	135	return renesas_clk_endisable(clk, priv->base, false);
36c2ee4c MV	136	}
	137
	138	static ulong gen3_clk_get_rate(struct clk *clk)
	139	{
	140	struct gen3_clk_priv *priv = dev_get_priv(clk->dev);
f11c9679	141	struct cpg_mssr_info *info = priv->info;
36c2ee4c MV	142	struct clk parent;
	143	const struct cpg_core_clk *core;
	144	const struct rcar_gen3_cpg_pll_config *pll_config =
	145	priv->cpg_pll_config;
849ab0a6	146	u32 value, mult, prediv, postdiv, rate = 0;
36c2ee4c MV	147	int i, ret;
	148
	149	debug("%s[%i] Clock: id=%lu\n", __func__, __LINE__, clk->id);
	150
d2628671	151	ret = renesas_clk_get_parent(clk, info, &parent);
36c2ee4c MV	152	if (ret) {
	153	printf("%s[%i] parent fail, ret=%i\n", __func__, __LINE__, ret);
	154	return ret;
	155	}
	156
d2628671	157	if (renesas_clk_is_mod(clk)) {
36c2ee4c MV	158	rate = gen3_clk_get_rate(&parent);
	159	debug("%s[%i] MOD clk: parent=%lu => rate=%u\n",
	160	__func__, __LINE__, parent.id, rate);
	161	return rate;
	162	}
	163
d2628671	164	ret = renesas_clk_get_core(clk, info, &core);
36c2ee4c MV	165	if (ret)
	166	return ret;
	167
	168	switch (core->type) {
	169	case CLK_TYPE_IN:
f11c9679	170	if (core->id == info->clk_extal_id) {
36c2ee4c MV	171	rate = clk_get_rate(&priv->clk_extal);
	172	debug("%s[%i] EXTAL clk: rate=%u\n",
	173	__func__, __LINE__, rate);
	174	return rate;
	175	}
	176
f11c9679	177	if (core->id == info->clk_extalr_id) {
36c2ee4c MV	178	rate = clk_get_rate(&priv->clk_extalr);
	179	debug("%s[%i] EXTALR clk: rate=%u\n",
	180	__func__, __LINE__, rate);
	181	return rate;
	182	}
	183
	184	return -EINVAL;
	185
	186	case CLK_TYPE_GEN3_MAIN:
	187	rate = gen3_clk_get_rate(&parent) / pll_config->extal_div;
	188	debug("%s[%i] MAIN clk: parent=%i extal_div=%i => rate=%u\n",
	189	__func__, __LINE__,
	190	core->parent, pll_config->extal_div, rate);
	191	return rate;
	192
	193	case CLK_TYPE_GEN3_PLL0:
	194	value = readl(priv->base + CPG_PLL0CR);
	195	mult = (((value >> 24) & 0x7f) + 1) * 2;
	196	rate = gen3_clk_get_rate(&parent) * mult;
	197	debug("%s[%i] PLL0 clk: parent=%i mult=%u => rate=%u\n",
	198	__func__, __LINE__, core->parent, mult, rate);
	199	return rate;
	200
	201	case CLK_TYPE_GEN3_PLL1:
	202	rate = gen3_clk_get_rate(&parent) * pll_config->pll1_mult;
	203	debug("%s[%i] PLL1 clk: parent=%i mul=%i => rate=%u\n",
	204	__func__, __LINE__,
	205	core->parent, pll_config->pll1_mult, rate);
	206	return rate;
	207
	208	case CLK_TYPE_GEN3_PLL2:
	209	value = readl(priv->base + CPG_PLL2CR);
	210	mult = (((value >> 24) & 0x7f) + 1) * 2;
	211	rate = gen3_clk_get_rate(&parent) * mult;
	212	debug("%s[%i] PLL2 clk: parent=%i mult=%u => rate=%u\n",
	213	__func__, __LINE__, core->parent, mult, rate);
	214	return rate;
	215
	216	case CLK_TYPE_GEN3_PLL3:
	217	rate = gen3_clk_get_rate(&parent) * pll_config->pll3_mult;
	218	debug("%s[%i] PLL3 clk: parent=%i mul=%i => rate=%u\n",
	219	__func__, __LINE__,
	220	core->parent, pll_config->pll3_mult, rate);
	221	return rate;
	222
	223	case CLK_TYPE_GEN3_PLL4:
	224	value = readl(priv->base + CPG_PLL4CR);
	225	mult = (((value >> 24) & 0x7f) + 1) * 2;
	226	rate = gen3_clk_get_rate(&parent) * mult;
	227	debug("%s[%i] PLL4 clk: parent=%i mult=%u => rate=%u\n",
	228	__func__, __LINE__, core->parent, mult, rate);
	229	return rate;
	230
	231	case CLK_TYPE_FF:
2c150950	232	case CLK_TYPE_GEN3_PE: /* FIXME */
36c2ee4c MV	233	rate = (gen3_clk_get_rate(&parent) * core->mult) / core->div;
	234	debug("%s[%i] FIXED clk: parent=%i div=%i mul=%i => rate=%u\n",
	235	__func__, __LINE__,
	236	core->parent, core->mult, core->div, rate);
	237	return rate;
	238
	239	case CLK_TYPE_GEN3_SD: /* FIXME */
	240	value = readl(priv->base + core->offset);
	241	value &= CPG_SD_STP_MASK \| CPG_SD_FC_MASK;
	242
	243	for (i = 0; i < ARRAY_SIZE(cpg_sd_div_table); i++) {
	244	if (cpg_sd_div_table[i].val != value)
	245	continue;
	246
	247	rate = gen3_clk_get_rate(&parent) /
	248	cpg_sd_div_table[i].div;
	249	debug("%s[%i] SD clk: parent=%i div=%i => rate=%u\n",
	250	__func__, __LINE__,
	251	core->parent, cpg_sd_div_table[i].div, rate);
	252
	253	return rate;
	254	}
	255
	256	return -EINVAL;
849ab0a6 MV	257
	258	case CLK_TYPE_GEN3_RPC:
	259	rate = gen3_clk_get_rate(&parent);
	260
	261	value = readl(priv->base + core->offset);
	262
	263	prediv = (value >> CPG_RPC_PREDIV_OFFSET) &
	264	CPG_RPC_PREDIV_MASK;
	265	if (prediv == 2)
	266	rate /= 5;
	267	else if (prediv == 3)
	268	rate /= 6;
	269	else
	270	return -EINVAL;
	271
	272	postdiv = (value >> CPG_RPC_POSTDIV_OFFSET) &
	273	CPG_RPC_POSTDIV_MASK;
	274	rate /= postdiv + 1;
	275
	276	debug("%s[%i] RPC clk: parent=%i prediv=%i postdiv=%i => rate=%u\n",
	277	__func__, __LINE__,
	278	core->parent, prediv, postdiv, rate);
	279
	280	return -EINVAL;
	281
36c2ee4c MV	282	}
	283
	284	printf("%s[%i] unknown fail\n", __func__, __LINE__);
	285
	286	return -ENOENT;
	287	}
	288
	289	static ulong gen3_clk_set_rate(struct clk *clk, ulong rate)
	290	{
fd5577ce MV	291	/* Force correct SD-IF divider configuration if applicable */
fd5577ce MV	292	gen3_clk_setup_sdif_div(clk);
36c2ee4c MV	293	return gen3_clk_get_rate(clk);
	294	}
	295
	296	static int gen3_clk_of_xlate(struct clk clk, struct ofnode_phandle_args args)
	297	{
	298	if (args->args_count != 2) {
	299	debug("Invaild args_count: %d\n", args->args_count);
	300	return -EINVAL;
	301	}
	302
	303	clk->id = (args->args[0] << 16) \| args->args[1];
	304
	305	return 0;
	306	}
	307
f77b5a4c	308	const struct clk_ops gen3_clk_ops = {
36c2ee4c MV	309	.enable = gen3_clk_enable,
	310	.disable = gen3_clk_disable,
	311	.get_rate = gen3_clk_get_rate,
	312	.set_rate = gen3_clk_set_rate,
	313	.of_xlate = gen3_clk_of_xlate,
	314	};
	315
f77b5a4c	316	int gen3_clk_probe(struct udevice *dev)
36c2ee4c MV	317	{
36c2ee4c MV	318	struct gen3_clk_priv *priv = dev_get_priv(dev);
f77b5a4c MV	319	struct cpg_mssr_info *info =
f77b5a4c MV	320	(struct cpg_mssr_info *)dev_get_driver_data(dev);
36c2ee4c MV	321	fdt_addr_t rst_base;
	322	u32 cpg_mode;
	323	int ret;
	324
	325	priv->base = (struct gen3_base *)devfdt_get_addr(dev);
	326	if (!priv->base)
	327	return -EINVAL;
	328
f77b5a4c MV	329	priv->info = info;
	330	ret = fdt_node_offset_by_compatible(gd->fdt_blob, -1, info->reset_node);
	331	if (ret < 0)
	332	return ret;
36c2ee4c MV	333
	334	rst_base = fdtdec_get_addr(gd->fdt_blob, ret, "reg");
	335	if (rst_base == FDT_ADDR_T_NONE)
	336	return -EINVAL;
	337
	338	cpg_mode = readl(rst_base + CPG_RST_MODEMR);
	339
7c885563 MV	340	priv->cpg_pll_config =
7c885563 MV	341	(struct rcar_gen3_cpg_pll_config *)info->get_pll_config(cpg_mode);
36c2ee4c MV	342	if (!priv->cpg_pll_config->extal_div)
	343	return -EINVAL;
	344
	345	ret = clk_get_by_name(dev, "extal", &priv->clk_extal);
	346	if (ret < 0)
	347	return ret;
	348
f77b5a4c MV	349	if (info->extalr_node) {
f77b5a4c MV	350	ret = clk_get_by_name(dev, info->extalr_node, &priv->clk_extalr);
2c150950 MV	351	if (ret < 0)
	352	return ret;
	353	}
36c2ee4c MV	354
	355	return 0;
	356	}
	357
f77b5a4c	358	int gen3_clk_remove(struct udevice *dev)
18cac5af MV	359	{
18cac5af MV	360	struct gen3_clk_priv *priv = dev_get_priv(dev);
18cac5af	361
d2628671	362	return renesas_clk_remove(priv->base, priv->info);
18cac5af	363	}