[thirdparty/u-boot.git] / drivers / clk / rockchip / clk_rk3188.c

// SPDX-License-Identifier: GPL-2.0
/*
 * (C) Copyright 2015 Google, Inc
 * (C) Copyright 2016 Heiko Stuebner <heiko@sntech.de>
 */

#include <common.h>
#include <clk-uclass.h>
#include <dm.h>
#include <dt-structs.h>
#include <errno.h>
#include <log.h>
#include <malloc.h>
#include <mapmem.h>
#include <syscon.h>
#include <asm/arch-rockchip/clock.h>
#include <asm/arch-rockchip/cru_rk3188.h>
#include <asm/arch-rockchip/grf_rk3188.h>
#include <asm/arch-rockchip/hardware.h>
#include <dt-bindings/clock/rk3188-cru.h>
#include <dm/device-internal.h>
#include <dm/lists.h>
#include <dm/uclass-internal.h>
#include <linux/delay.h>
#include <linux/err.h>
#include <linux/log2.h>
#include <linux/stringify.h>

enum rk3188_clk_type {
	RK3188_CRU,
	RK3188A_CRU,
};

struct rk3188_clk_plat {
#if CONFIG_IS_ENABLED(OF_PLATDATA)
	struct dtd_rockchip_rk3188_cru dtd;
#endif
};

struct pll_div {
	u32 nr;
	u32 nf;
	u32 no;
};

enum {
	VCO_MAX_HZ	= 2200U * 1000000,
	VCO_MIN_HZ	= 440 * 1000000,
	OUTPUT_MAX_HZ	= 2200U * 1000000,
	OUTPUT_MIN_HZ	= 30 * 1000000,
	FREF_MAX_HZ	= 2200U * 1000000,
	FREF_MIN_HZ	= 30 * 1000,
};

enum {
	/* PLL CON0 */
	PLL_OD_MASK		= 0x0f,

	/* PLL CON1 */
	PLL_NF_MASK		= 0x1fff,

	/* PLL CON2 */
	PLL_BWADJ_MASK		= 0x0fff,

	/* PLL CON3 */
	PLL_RESET_SHIFT		= 5,

	/* GRF_SOC_STATUS0 */
	SOCSTS_DPLL_LOCK	= 1 << 5,
	SOCSTS_APLL_LOCK	= 1 << 6,
	SOCSTS_CPLL_LOCK	= 1 << 7,
	SOCSTS_GPLL_LOCK	= 1 << 8,
};

#define DIV_TO_RATE(input_rate, div)	((input_rate) / ((div) + 1))

#define PLL_DIVISORS(hz, _nr, _no) {\
	.nr = _nr, .nf = (u32)((u64)hz * _nr * _no / OSC_HZ), .no = _no};\
	_Static_assert(((u64)hz * _nr * _no / OSC_HZ) * OSC_HZ /\
		       (_nr * _no) == hz, #hz "Hz cannot be hit with PLL "\
		       "divisors on line " __stringify(__LINE__));

/* Keep divisors as low as possible to reduce jitter and power usage */
#ifdef CONFIG_SPL_BUILD
static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 2, 2);
static const struct pll_div cpll_init_cfg = PLL_DIVISORS(CPLL_HZ, 1, 2);
#endif

static int rkclk_set_pll(struct rk3188_cru *cru, enum rk_clk_id clk_id,
			 const struct pll_div *div, bool has_bwadj)
{
	int pll_id = rk_pll_id(clk_id);
	struct rk3188_pll *pll = &cru->pll[pll_id];
	/* All PLLs have same VCO and output frequency range restrictions. */
	uint vco_hz = OSC_HZ / 1000 * div->nf / div->nr * 1000;
	uint output_hz = vco_hz / div->no;

	debug("PLL at %x: nf=%d, nr=%d, no=%d, vco=%u Hz, output=%u Hz\n",
	      (uint)pll, div->nf, div->nr, div->no, vco_hz, output_hz);
	assert(vco_hz >= VCO_MIN_HZ && vco_hz <= VCO_MAX_HZ &&
	       output_hz >= OUTPUT_MIN_HZ && output_hz <= OUTPUT_MAX_HZ &&
	       (div->no == 1 || !(div->no % 2)));

	/* enter reset */
	rk_setreg(&pll->con3, 1 << PLL_RESET_SHIFT);

	rk_clrsetreg(&pll->con0,
		     CLKR_MASK << CLKR_SHIFT | PLL_OD_MASK,
		     ((div->nr - 1) << CLKR_SHIFT) | (div->no - 1));
	rk_clrsetreg(&pll->con1, CLKF_MASK, div->nf - 1);

	if (has_bwadj)
		rk_clrsetreg(&pll->con2, PLL_BWADJ_MASK, (div->nf >> 1) - 1);

	udelay(10);

	/* return from reset */
	rk_clrreg(&pll->con3, 1 << PLL_RESET_SHIFT);

	return 0;
}

static int rkclk_configure_ddr(struct rk3188_cru *cru, struct rk3188_grf *grf,
			       unsigned int hz, bool has_bwadj)
{
	static const struct pll_div dpll_cfg[] = {
		{.nf = 75, .nr = 1, .no = 6},
		{.nf = 400, .nr = 9, .no = 2},
		{.nf = 500, .nr = 9, .no = 2},
		{.nf = 100, .nr = 3, .no = 1},
	};
	int cfg;

	switch (hz) {
	case 300000000:
		cfg = 0;
		break;
	case 533000000:	/* actually 533.3P MHz */
		cfg = 1;
		break;
	case 666000000:	/* actually 666.6P MHz */
		cfg = 2;
		break;
	case 800000000:
		cfg = 3;
		break;
	default:
		debug("Unsupported SDRAM frequency");
		return -EINVAL;
	}

	/* pll enter slow-mode */
	rk_clrsetreg(&cru->cru_mode_con, DPLL_MODE_MASK << DPLL_MODE_SHIFT,
		     DPLL_MODE_SLOW << DPLL_MODE_SHIFT);

	rkclk_set_pll(cru, CLK_DDR, &dpll_cfg[cfg], has_bwadj);

	/* wait for pll lock */
	while (!(readl(&grf->soc_status0) & SOCSTS_DPLL_LOCK))
		udelay(1);

	/* PLL enter normal-mode */
	rk_clrsetreg(&cru->cru_mode_con, DPLL_MODE_MASK << DPLL_MODE_SHIFT,
		     DPLL_MODE_NORMAL << DPLL_MODE_SHIFT);

	return 0;
}

static int rkclk_configure_cpu(struct rk3188_cru *cru, struct rk3188_grf *grf,
			      unsigned int hz, bool has_bwadj)
{
	static const struct pll_div apll_cfg[] = {
		{.nf = 50, .nr = 1, .no = 2},
		{.nf = 67, .nr = 1, .no = 1},
	};
	int div_core_peri, div_aclk_core, cfg;

	/*
	 * We support two possible frequencies, the safe 600MHz
	 * which will work with default pmic settings and will
	 * be set in SPL to get away from the 24MHz default and
	 * the maximum of 1.6Ghz, which boards can set if they
	 * were able to get pmic support for it.
	 */
	switch (hz) {
	case APLL_SAFE_HZ:
		cfg = 0;
		div_core_peri = 1;
		div_aclk_core = 3;
		break;
	case APLL_HZ:
		cfg = 1;
		div_core_peri = 2;
		div_aclk_core = 3;
		break;
	default:
		debug("Unsupported ARMCLK frequency");
		return -EINVAL;
	}

	/* pll enter slow-mode */
	rk_clrsetreg(&cru->cru_mode_con, APLL_MODE_MASK << APLL_MODE_SHIFT,
		     APLL_MODE_SLOW << APLL_MODE_SHIFT);

	rkclk_set_pll(cru, CLK_ARM, &apll_cfg[cfg], has_bwadj);

	/* waiting for pll lock */
	while (!(readl(&grf->soc_status0) & SOCSTS_APLL_LOCK))
		udelay(1);

	/* Set divider for peripherals attached to the cpu core. */
	rk_clrsetreg(&cru->cru_clksel_con[0],
		CORE_PERI_DIV_MASK << CORE_PERI_DIV_SHIFT,
		div_core_peri << CORE_PERI_DIV_SHIFT);

	/* set up dependent divisor for aclk_core */
	rk_clrsetreg(&cru->cru_clksel_con[1],
		CORE_ACLK_DIV_MASK << CORE_ACLK_DIV_SHIFT,
		div_aclk_core << CORE_ACLK_DIV_SHIFT);

	/* PLL enter normal-mode */
	rk_clrsetreg(&cru->cru_mode_con, APLL_MODE_MASK << APLL_MODE_SHIFT,
		     APLL_MODE_NORMAL << APLL_MODE_SHIFT);

	return hz;
}

/* Get pll rate by id */
static uint32_t rkclk_pll_get_rate(struct rk3188_cru *cru,
				   enum rk_clk_id clk_id)
{
	uint32_t nr, no, nf;
	uint32_t con;
	int pll_id = rk_pll_id(clk_id);
	struct rk3188_pll *pll = &cru->pll[pll_id];
	static u8 clk_shift[CLK_COUNT] = {
		0xff, APLL_MODE_SHIFT, DPLL_MODE_SHIFT, CPLL_MODE_SHIFT,
		GPLL_MODE_SHIFT
	};
	uint shift;

	con = readl(&cru->cru_mode_con);
	shift = clk_shift[clk_id];
	switch ((con >> shift) & APLL_MODE_MASK) {
	case APLL_MODE_SLOW:
		return OSC_HZ;
	case APLL_MODE_NORMAL:
		/* normal mode */
		con = readl(&pll->con0);
		no = ((con >> CLKOD_SHIFT) & CLKOD_MASK) + 1;
		nr = ((con >> CLKR_SHIFT) & CLKR_MASK) + 1;
		con = readl(&pll->con1);
		nf = ((con >> CLKF_SHIFT) & CLKF_MASK) + 1;

		return (24 * nf / (nr * no)) * 1000000;
	case APLL_MODE_DEEP:
	default:
		return 32768;
	}
}

static ulong rockchip_mmc_get_clk(struct rk3188_cru *cru, uint gclk_rate,
				  int periph)
{
	uint div;
	u32 con;

	switch (periph) {
	case HCLK_EMMC:
	case SCLK_EMMC:
		con = readl(&cru->cru_clksel_con[12]);
		div = (con >> EMMC_DIV_SHIFT) & EMMC_DIV_MASK;
		break;
	case HCLK_SDMMC:
	case SCLK_SDMMC:
		con = readl(&cru->cru_clksel_con[11]);
		div = (con >> MMC0_DIV_SHIFT) & MMC0_DIV_MASK;
		break;
	case HCLK_SDIO:
	case SCLK_SDIO:
		con = readl(&cru->cru_clksel_con[12]);
		div = (con >> SDIO_DIV_SHIFT) & SDIO_DIV_MASK;
		break;
	default:
		return -EINVAL;
	}

	return DIV_TO_RATE(gclk_rate, div) / 2;
}

static ulong rockchip_mmc_set_clk(struct rk3188_cru *cru, uint gclk_rate,
				  int  periph, uint freq)
{
	int src_clk_div;

	debug("%s: gclk_rate=%u\n", __func__, gclk_rate);
	/* mmc clock defaulg div 2 internal, need provide double in cru */
	src_clk_div = DIV_ROUND_UP(gclk_rate / 2, freq) - 1;
	assert(src_clk_div <= 0x3f);

	switch (periph) {
	case HCLK_EMMC:
	case SCLK_EMMC:
		rk_clrsetreg(&cru->cru_clksel_con[12],
			     EMMC_DIV_MASK << EMMC_DIV_SHIFT,
			     src_clk_div << EMMC_DIV_SHIFT);
		break;
	case HCLK_SDMMC:
	case SCLK_SDMMC:
		rk_clrsetreg(&cru->cru_clksel_con[11],
			     MMC0_DIV_MASK << MMC0_DIV_SHIFT,
			     src_clk_div << MMC0_DIV_SHIFT);
		break;
	case HCLK_SDIO:
	case SCLK_SDIO:
		rk_clrsetreg(&cru->cru_clksel_con[12],
			     SDIO_DIV_MASK << SDIO_DIV_SHIFT,
			     src_clk_div << SDIO_DIV_SHIFT);
		break;
	default:
		return -EINVAL;
	}

	return rockchip_mmc_get_clk(cru, gclk_rate, periph);
}

static ulong rockchip_spi_get_clk(struct rk3188_cru *cru, uint gclk_rate,
				  int periph)
{
	uint div;
	u32 con;

	switch (periph) {
	case SCLK_SPI0:
		con = readl(&cru->cru_clksel_con[25]);
		div = (con >> SPI0_DIV_SHIFT) & SPI0_DIV_MASK;
		break;
	case SCLK_SPI1:
		con = readl(&cru->cru_clksel_con[25]);
		div = (con >> SPI1_DIV_SHIFT) & SPI1_DIV_MASK;
		break;
	default:
		return -EINVAL;
	}

	return DIV_TO_RATE(gclk_rate, div);
}

static ulong rockchip_spi_set_clk(struct rk3188_cru *cru, uint gclk_rate,
				  int periph, uint freq)
{
	int src_clk_div = DIV_ROUND_UP(gclk_rate, freq) - 1;

	assert(src_clk_div < 128);
	switch (periph) {
	case SCLK_SPI0:
		assert(src_clk_div <= SPI0_DIV_MASK);
		rk_clrsetreg(&cru->cru_clksel_con[25],
			     SPI0_DIV_MASK << SPI0_DIV_SHIFT,
			     src_clk_div << SPI0_DIV_SHIFT);
		break;
	case SCLK_SPI1:
		assert(src_clk_div <= SPI1_DIV_MASK);
		rk_clrsetreg(&cru->cru_clksel_con[25],
			     SPI1_DIV_MASK << SPI1_DIV_SHIFT,
			     src_clk_div << SPI1_DIV_SHIFT);
		break;
	default:
		return -EINVAL;
	}

	return rockchip_spi_get_clk(cru, gclk_rate, periph);
}

#ifdef CONFIG_SPL_BUILD
static void rkclk_init(struct rk3188_cru *cru, struct rk3188_grf *grf,
		       bool has_bwadj)
{
	u32 aclk_div, hclk_div, pclk_div, h2p_div;

	/* pll enter slow-mode */
	rk_clrsetreg(&cru->cru_mode_con,
		     GPLL_MODE_MASK << GPLL_MODE_SHIFT |
		     CPLL_MODE_MASK << CPLL_MODE_SHIFT,
		     GPLL_MODE_SLOW << GPLL_MODE_SHIFT |
		     CPLL_MODE_SLOW << CPLL_MODE_SHIFT);

	/* init pll */
	rkclk_set_pll(cru, CLK_GENERAL, &gpll_init_cfg, has_bwadj);
	rkclk_set_pll(cru, CLK_CODEC, &cpll_init_cfg, has_bwadj);

	/* waiting for pll lock */
	while ((readl(&grf->soc_status0) &
			(SOCSTS_CPLL_LOCK | SOCSTS_GPLL_LOCK)) !=
			(SOCSTS_CPLL_LOCK | SOCSTS_GPLL_LOCK))
		udelay(1);

	/*
	 * cpu clock pll source selection and
	 * reparent aclk_cpu_pre from apll to gpll
	 * set up dependent divisors for PCLK/HCLK and ACLK clocks.
	 */
	aclk_div = DIV_ROUND_UP(GPLL_HZ, CPU_ACLK_HZ) - 1;
	assert((aclk_div + 1) * CPU_ACLK_HZ == GPLL_HZ && aclk_div <= 0x1f);

	rk_clrsetreg(&cru->cru_clksel_con[0],
		     CPU_ACLK_PLL_MASK << CPU_ACLK_PLL_SHIFT |
		     A9_CPU_DIV_MASK << A9_CPU_DIV_SHIFT,
		     CPU_ACLK_PLL_SELECT_GPLL << CPU_ACLK_PLL_SHIFT |
		     aclk_div << A9_CPU_DIV_SHIFT);

	hclk_div = ilog2(CPU_ACLK_HZ / CPU_HCLK_HZ);
	assert((1 << hclk_div) * CPU_HCLK_HZ == CPU_ACLK_HZ && hclk_div < 0x3);
	pclk_div = ilog2(CPU_ACLK_HZ / CPU_PCLK_HZ);
	assert((1 << pclk_div) * CPU_PCLK_HZ == CPU_ACLK_HZ && pclk_div < 0x4);
	h2p_div = ilog2(CPU_HCLK_HZ / CPU_H2P_HZ);
	assert((1 << h2p_div) * CPU_H2P_HZ == CPU_HCLK_HZ && pclk_div < 0x3);

	rk_clrsetreg(&cru->cru_clksel_con[1],
		     AHB2APB_DIV_MASK << AHB2APB_DIV_SHIFT |
		     CPU_PCLK_DIV_MASK << CPU_PCLK_DIV_SHIFT |
		     CPU_HCLK_DIV_MASK << CPU_HCLK_DIV_SHIFT,
		     h2p_div << AHB2APB_DIV_SHIFT |
		     pclk_div << CPU_PCLK_DIV_SHIFT |
		     hclk_div << CPU_HCLK_DIV_SHIFT);

	/*
	 * peri clock pll source selection and
	 * set up dependent divisors for PCLK/HCLK and ACLK clocks.
	 */
	aclk_div = GPLL_HZ / PERI_ACLK_HZ - 1;
	assert((aclk_div + 1) * PERI_ACLK_HZ == GPLL_HZ && aclk_div < 0x1f);

	hclk_div = ilog2(PERI_ACLK_HZ / PERI_HCLK_HZ);
	assert((1 << hclk_div) * PERI_HCLK_HZ ==
		PERI_ACLK_HZ && (hclk_div < 0x4));

	pclk_div = ilog2(PERI_ACLK_HZ / PERI_PCLK_HZ);
	assert((1 << pclk_div) * PERI_PCLK_HZ ==
		PERI_ACLK_HZ && (pclk_div < 0x4));

	rk_clrsetreg(&cru->cru_clksel_con[10],
		     PERI_PCLK_DIV_MASK << PERI_PCLK_DIV_SHIFT |
		     PERI_HCLK_DIV_MASK << PERI_HCLK_DIV_SHIFT |
		     PERI_ACLK_DIV_MASK << PERI_ACLK_DIV_SHIFT,
		     PERI_SEL_GPLL << PERI_SEL_PLL_SHIFT |
		     pclk_div << PERI_PCLK_DIV_SHIFT |
		     hclk_div << PERI_HCLK_DIV_SHIFT |
		     aclk_div << PERI_ACLK_DIV_SHIFT);

	/* PLL enter normal-mode */
	rk_clrsetreg(&cru->cru_mode_con,
		     GPLL_MODE_MASK << GPLL_MODE_SHIFT |
		     CPLL_MODE_MASK << CPLL_MODE_SHIFT,
		     GPLL_MODE_NORMAL << GPLL_MODE_SHIFT |
		     CPLL_MODE_NORMAL << CPLL_MODE_SHIFT);

	rockchip_mmc_set_clk(cru, PERI_HCLK_HZ, HCLK_SDMMC, 16000000);
}
#endif

static ulong rk3188_clk_get_rate(struct clk *clk)
{
	struct rk3188_clk_priv *priv = dev_get_priv(clk->dev);
	ulong new_rate, gclk_rate;

	gclk_rate = rkclk_pll_get_rate(priv->cru, CLK_GENERAL);
	switch (clk->id) {
	case 1 ... 4:
		new_rate = rkclk_pll_get_rate(priv->cru, clk->id);
		break;
	case HCLK_EMMC:
	case HCLK_SDMMC:
	case HCLK_SDIO:
	case SCLK_EMMC:
	case SCLK_SDMMC:
	case SCLK_SDIO:
		new_rate = rockchip_mmc_get_clk(priv->cru, PERI_HCLK_HZ,
						clk->id);
		break;
	case SCLK_SPI0:
	case SCLK_SPI1:
		new_rate = rockchip_spi_get_clk(priv->cru, PERI_PCLK_HZ,
						clk->id);
		break;
	case PCLK_I2C0:
	case PCLK_I2C1:
	case PCLK_I2C2:
	case PCLK_I2C3:
	case PCLK_I2C4:
		return gclk_rate;
	default:
		return -ENOENT;
	}

	return new_rate;
}

static ulong rk3188_clk_set_rate(struct clk *clk, ulong rate)
{
	struct rk3188_clk_priv *priv = dev_get_priv(clk->dev);
	struct rk3188_cru *cru = priv->cru;
	ulong new_rate;

	switch (clk->id) {
	case PLL_APLL:
		new_rate = rkclk_configure_cpu(priv->cru, priv->grf, rate,
					       priv->has_bwadj);
		break;
	case CLK_DDR:
		new_rate = rkclk_configure_ddr(priv->cru, priv->grf, rate,
					       priv->has_bwadj);
		break;
	case HCLK_EMMC:
	case HCLK_SDMMC:
	case HCLK_SDIO:
	case SCLK_EMMC:
	case SCLK_SDMMC:
	case SCLK_SDIO:
		new_rate = rockchip_mmc_set_clk(cru, PERI_HCLK_HZ,
						clk->id, rate);
		break;
	case SCLK_SPI0:
	case SCLK_SPI1:
		new_rate = rockchip_spi_set_clk(cru, PERI_PCLK_HZ,
						clk->id, rate);
		break;
	default:
		return -ENOENT;
	}

	return new_rate;
}

static struct clk_ops rk3188_clk_ops = {
	.get_rate	= rk3188_clk_get_rate,
	.set_rate	= rk3188_clk_set_rate,
};

static int rk3188_clk_of_to_plat(struct udevice *dev)
{
	if (CONFIG_IS_ENABLED(OF_REAL)) {
		struct rk3188_clk_priv *priv = dev_get_priv(dev);

		priv->cru = dev_read_addr_ptr(dev);
	}

	return 0;
}

static int rk3188_clk_probe(struct udevice *dev)
{
	struct rk3188_clk_priv *priv = dev_get_priv(dev);
	enum rk3188_clk_type type = dev_get_driver_data(dev);

	priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
	if (IS_ERR(priv->grf))
		return PTR_ERR(priv->grf);
	priv->has_bwadj = (type == RK3188A_CRU) ? 1 : 0;

#ifdef CONFIG_SPL_BUILD
#if CONFIG_IS_ENABLED(OF_PLATDATA)
	struct rk3188_clk_plat *plat = dev_get_plat(dev);

	priv->cru = map_sysmem(plat->dtd.reg[0], plat->dtd.reg[1]);
#endif

	rkclk_init(priv->cru, priv->grf, priv->has_bwadj);

	/* Init CPU frequency */
	rkclk_configure_cpu(priv->cru, priv->grf, APLL_SAFE_HZ,
			    priv->has_bwadj);
#endif

	return 0;
}

static int rk3188_clk_bind(struct udevice *dev)
{
	int ret;
	struct udevice *sys_child;
	struct sysreset_reg *priv;

	/* The reset driver does not have a device node, so bind it here */
	ret = device_bind_driver(dev, "rockchip_sysreset", "sysreset",
				 &sys_child);
	if (ret) {
		debug("Warning: No sysreset driver: ret=%d\n", ret);
	} else {
		priv = malloc(sizeof(struct sysreset_reg));
		priv->glb_srst_fst_value = offsetof(struct rk3188_cru,
						    cru_glb_srst_fst_value);
		priv->glb_srst_snd_value = offsetof(struct rk3188_cru,
						    cru_glb_srst_snd_value);
		dev_set_priv(sys_child, priv);
	}

#if CONFIG_IS_ENABLED(RESET_ROCKCHIP)
	ret = offsetof(struct rk3188_cru, cru_softrst_con[0]);
	ret = rockchip_reset_bind(dev, ret, 9);
	if (ret)
		debug("Warning: software reset driver bind failed\n");
#endif

	return 0;
}

static const struct udevice_id rk3188_clk_ids[] = {
	{ .compatible = "rockchip,rk3188-cru", .data = RK3188_CRU },
	{ .compatible = "rockchip,rk3188a-cru", .data = RK3188A_CRU },
	{ }
};

U_BOOT_DRIVER(rockchip_rk3188_cru) = {
	.name			= "rockchip_rk3188_cru",
	.id			= UCLASS_CLK,
	.of_match		= rk3188_clk_ids,
	.priv_auto	= sizeof(struct rk3188_clk_priv),
	.plat_auto	= sizeof(struct rk3188_clk_plat),
	.ops			= &rk3188_clk_ops,
	.bind			= rk3188_clk_bind,
	.of_to_plat	= rk3188_clk_of_to_plat,
	.probe			= rk3188_clk_probe,
};
Commit	Line	Data
83d290c5	1	// SPDX-License-Identifier: GPL-2.0
dcdd3278 HS	2	/*
	3	* (C) Copyright 2015 Google, Inc
	4	* (C) Copyright 2016 Heiko Stuebner <heiko@sntech.de>
dcdd3278 HS	5	*/
dcdd3278 HS	6
d678a59d	7	#include <common.h>
dcdd3278 HS	8	#include <clk-uclass.h>
	9	#include <dm.h>
	10	#include <dt-structs.h>
	11	#include <errno.h>
f7ae49fc	12	#include <log.h>
336d4615	13	#include <malloc.h>
dcdd3278 HS	14	#include <mapmem.h>
dcdd3278 HS	15	#include <syscon.h>
15f09a1a KY	16	#include <asm/arch-rockchip/clock.h>
	17	#include <asm/arch-rockchip/cru_rk3188.h>
	18	#include <asm/arch-rockchip/grf_rk3188.h>
	19	#include <asm/arch-rockchip/hardware.h>
dcdd3278 HS	20	#include <dt-bindings/clock/rk3188-cru.h>
	21	#include <dm/device-internal.h>
	22	#include <dm/lists.h>
	23	#include <dm/uclass-internal.h>
c05ed00a	24	#include <linux/delay.h>
61b29b82	25	#include <linux/err.h>
dcdd3278	26	#include <linux/log2.h>
1af3c7f4	27	#include <linux/stringify.h>
dcdd3278	28
dcdd3278 HS	29	enum rk3188_clk_type {
	30	RK3188_CRU,
	31	RK3188A_CRU,
	32	};
	33
	34	struct rk3188_clk_plat {
	35	#if CONFIG_IS_ENABLED(OF_PLATDATA)
	36	struct dtd_rockchip_rk3188_cru dtd;
	37	#endif
	38	};
	39
	40	struct pll_div {
	41	u32 nr;
	42	u32 nf;
	43	u32 no;
	44	};
	45
	46	enum {
	47	VCO_MAX_HZ = 2200U * 1000000,
	48	VCO_MIN_HZ = 440 * 1000000,
	49	OUTPUT_MAX_HZ = 2200U * 1000000,
	50	OUTPUT_MIN_HZ = 30 * 1000000,
	51	FREF_MAX_HZ = 2200U * 1000000,
	52	FREF_MIN_HZ = 30 * 1000,
	53	};
	54
	55	enum {
	56	/* PLL CON0 */
	57	PLL_OD_MASK = 0x0f,
	58
	59	/* PLL CON1 */
	60	PLL_NF_MASK = 0x1fff,
	61
	62	/* PLL CON2 */
	63	PLL_BWADJ_MASK = 0x0fff,
	64
	65	/* PLL CON3 */
	66	PLL_RESET_SHIFT = 5,
	67
	68	/* GRF_SOC_STATUS0 */
	69	SOCSTS_DPLL_LOCK = 1 << 5,
	70	SOCSTS_APLL_LOCK = 1 << 6,
	71	SOCSTS_CPLL_LOCK = 1 << 7,
	72	SOCSTS_GPLL_LOCK = 1 << 8,
	73	};
	74
dcdd3278 HS	75	#define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1))
	76
	77	#define PLL_DIVISORS(hz, _nr, _no) {\
	78	.nr = _nr, .nf = (u32)((u64)hz * _nr * _no / OSC_HZ), .no = _no};\
	79	_Static_assert(((u64)hz * _nr * _no / OSC_HZ) * OSC_HZ /\
	80	(_nr * _no) == hz, #hz "Hz cannot be hit with PLL "\
	81	"divisors on line " __stringify(__LINE__));
	82
	83	/* Keep divisors as low as possible to reduce jitter and power usage */
	84	#ifdef CONFIG_SPL_BUILD
	85	static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 2, 2);
	86	static const struct pll_div cpll_init_cfg = PLL_DIVISORS(CPLL_HZ, 1, 2);
	87	#endif
	88
	89	static int rkclk_set_pll(struct rk3188_cru *cru, enum rk_clk_id clk_id,
	90	const struct pll_div *div, bool has_bwadj)
	91	{
	92	int pll_id = rk_pll_id(clk_id);
	93	struct rk3188_pll *pll = &cru->pll[pll_id];
	94	/* All PLLs have same VCO and output frequency range restrictions. */
	95	uint vco_hz = OSC_HZ / 1000 * div->nf / div->nr * 1000;
	96	uint output_hz = vco_hz / div->no;
	97
	98	debug("PLL at %x: nf=%d, nr=%d, no=%d, vco=%u Hz, output=%u Hz\n",
	99	(uint)pll, div->nf, div->nr, div->no, vco_hz, output_hz);
	100	assert(vco_hz >= VCO_MIN_HZ && vco_hz <= VCO_MAX_HZ &&
	101	output_hz >= OUTPUT_MIN_HZ && output_hz <= OUTPUT_MAX_HZ &&
	102	(div->no == 1 \|\| !(div->no % 2)));
	103
	104	/* enter reset */
	105	rk_setreg(&pll->con3, 1 << PLL_RESET_SHIFT);
	106
	107	rk_clrsetreg(&pll->con0,
	108	CLKR_MASK << CLKR_SHIFT \| PLL_OD_MASK,
	109	((div->nr - 1) << CLKR_SHIFT) \| (div->no - 1));
	110	rk_clrsetreg(&pll->con1, CLKF_MASK, div->nf - 1);
	111
	112	if (has_bwadj)
	113	rk_clrsetreg(&pll->con2, PLL_BWADJ_MASK, (div->nf >> 1) - 1);
	114
	115	udelay(10);
	116
	117	/* return from reset */
	118	rk_clrreg(&pll->con3, 1 << PLL_RESET_SHIFT);
	119
	120	return 0;
	121	}
	122
	123	static int rkclk_configure_ddr(struct rk3188_cru cru, struct rk3188_grf grf,
	124	unsigned int hz, bool has_bwadj)
	125	{
	126	static const struct pll_div dpll_cfg[] = {
6b0c26fa	127	{.nf = 75, .nr = 1, .no = 6},
dcdd3278 HS	128	{.nf = 400, .nr = 9, .no = 2},
	129	{.nf = 500, .nr = 9, .no = 2},
	130	{.nf = 100, .nr = 3, .no = 1},
	131	};
	132	int cfg;
	133
	134	switch (hz) {
	135	case 300000000:
	136	cfg = 0;
	137	break;
	138	case 533000000: /* actually 533.3P MHz */
	139	cfg = 1;
	140	break;
	141	case 666000000: /* actually 666.6P MHz */
	142	cfg = 2;
	143	break;
	144	case 800000000:
	145	cfg = 3;
	146	break;
	147	default:
	148	debug("Unsupported SDRAM frequency");
	149	return -EINVAL;
	150	}
	151
	152	/* pll enter slow-mode */
	153	rk_clrsetreg(&cru->cru_mode_con, DPLL_MODE_MASK << DPLL_MODE_SHIFT,
	154	DPLL_MODE_SLOW << DPLL_MODE_SHIFT);
	155
	156	rkclk_set_pll(cru, CLK_DDR, &dpll_cfg[cfg], has_bwadj);
	157
	158	/* wait for pll lock */
	159	while (!(readl(&grf->soc_status0) & SOCSTS_DPLL_LOCK))
	160	udelay(1);
	161
	162	/* PLL enter normal-mode */
	163	rk_clrsetreg(&cru->cru_mode_con, DPLL_MODE_MASK << DPLL_MODE_SHIFT,
	164	DPLL_MODE_NORMAL << DPLL_MODE_SHIFT);
	165
	166	return 0;
	167	}
	168
f7853570 HS	169	static int rkclk_configure_cpu(struct rk3188_cru cru, struct rk3188_grf grf,
	170	unsigned int hz, bool has_bwadj)
	171	{
	172	static const struct pll_div apll_cfg[] = {
	173	{.nf = 50, .nr = 1, .no = 2},
	174	{.nf = 67, .nr = 1, .no = 1},
	175	};
	176	int div_core_peri, div_aclk_core, cfg;
	177
	178	/*
	179	* We support two possible frequencies, the safe 600MHz
	180	* which will work with default pmic settings and will
	181	* be set in SPL to get away from the 24MHz default and
	182	* the maximum of 1.6Ghz, which boards can set if they
	183	* were able to get pmic support for it.
	184	*/
	185	switch (hz) {
	186	case APLL_SAFE_HZ:
	187	cfg = 0;
	188	div_core_peri = 1;
	189	div_aclk_core = 3;
	190	break;
	191	case APLL_HZ:
	192	cfg = 1;
	193	div_core_peri = 2;
	194	div_aclk_core = 3;
	195	break;
	196	default:
	197	debug("Unsupported ARMCLK frequency");
	198	return -EINVAL;
	199	}
	200
	201	/* pll enter slow-mode */
	202	rk_clrsetreg(&cru->cru_mode_con, APLL_MODE_MASK << APLL_MODE_SHIFT,
	203	APLL_MODE_SLOW << APLL_MODE_SHIFT);
	204
	205	rkclk_set_pll(cru, CLK_ARM, &apll_cfg[cfg], has_bwadj);
	206
	207	/* waiting for pll lock */
	208	while (!(readl(&grf->soc_status0) & SOCSTS_APLL_LOCK))
	209	udelay(1);
	210
	211	/* Set divider for peripherals attached to the cpu core. */
	212	rk_clrsetreg(&cru->cru_clksel_con[0],
	213	CORE_PERI_DIV_MASK << CORE_PERI_DIV_SHIFT,
	214	div_core_peri << CORE_PERI_DIV_SHIFT);
	215
	216	/* set up dependent divisor for aclk_core */
	217	rk_clrsetreg(&cru->cru_clksel_con[1],
	218	CORE_ACLK_DIV_MASK << CORE_ACLK_DIV_SHIFT,
	219	div_aclk_core << CORE_ACLK_DIV_SHIFT);
	220
	221	/* PLL enter normal-mode */
	222	rk_clrsetreg(&cru->cru_mode_con, APLL_MODE_MASK << APLL_MODE_SHIFT,
	223	APLL_MODE_NORMAL << APLL_MODE_SHIFT);
	224
	225	return hz;
	226	}
	227
dcdd3278 HS	228	/* Get pll rate by id */
	229	static uint32_t rkclk_pll_get_rate(struct rk3188_cru *cru,
	230	enum rk_clk_id clk_id)
	231	{
	232	uint32_t nr, no, nf;
	233	uint32_t con;
	234	int pll_id = rk_pll_id(clk_id);
	235	struct rk3188_pll *pll = &cru->pll[pll_id];
	236	static u8 clk_shift[CLK_COUNT] = {
	237	0xff, APLL_MODE_SHIFT, DPLL_MODE_SHIFT, CPLL_MODE_SHIFT,
	238	GPLL_MODE_SHIFT
	239	};
	240	uint shift;
	241
	242	con = readl(&cru->cru_mode_con);
	243	shift = clk_shift[clk_id];
	244	switch ((con >> shift) & APLL_MODE_MASK) {
	245	case APLL_MODE_SLOW:
	246	return OSC_HZ;
	247	case APLL_MODE_NORMAL:
	248	/* normal mode */
	249	con = readl(&pll->con0);
	250	no = ((con >> CLKOD_SHIFT) & CLKOD_MASK) + 1;
	251	nr = ((con >> CLKR_SHIFT) & CLKR_MASK) + 1;
	252	con = readl(&pll->con1);
	253	nf = ((con >> CLKF_SHIFT) & CLKF_MASK) + 1;
	254
	255	return (24 * nf / (nr * no)) * 1000000;
	256	case APLL_MODE_DEEP:
	257	default:
	258	return 32768;
	259	}
	260	}
	261
	262	static ulong rockchip_mmc_get_clk(struct rk3188_cru *cru, uint gclk_rate,
	263	int periph)
	264	{
	265	uint div;
	266	u32 con;
	267
	268	switch (periph) {
	269	case HCLK_EMMC:
7a25a63c	270	case SCLK_EMMC:
dcdd3278 HS	271	con = readl(&cru->cru_clksel_con[12]);
	272	div = (con >> EMMC_DIV_SHIFT) & EMMC_DIV_MASK;
	273	break;
	274	case HCLK_SDMMC:
7a25a63c	275	case SCLK_SDMMC:
dcdd3278 HS	276	con = readl(&cru->cru_clksel_con[11]);
	277	div = (con >> MMC0_DIV_SHIFT) & MMC0_DIV_MASK;
	278	break;
	279	case HCLK_SDIO:
7a25a63c	280	case SCLK_SDIO:
dcdd3278 HS	281	con = readl(&cru->cru_clksel_con[12]);
	282	div = (con >> SDIO_DIV_SHIFT) & SDIO_DIV_MASK;
	283	break;
	284	default:
	285	return -EINVAL;
	286	}
	287
3a94d75d	288	return DIV_TO_RATE(gclk_rate, div) / 2;
dcdd3278 HS	289	}
	290
	291	static ulong rockchip_mmc_set_clk(struct rk3188_cru *cru, uint gclk_rate,
	292	int periph, uint freq)
	293	{
	294	int src_clk_div;
	295
	296	debug("%s: gclk_rate=%u\n", __func__, gclk_rate);
3a94d75d	297	/* mmc clock defaulg div 2 internal, need provide double in cru */
217273cd	298	src_clk_div = DIV_ROUND_UP(gclk_rate / 2, freq) - 1;
dcdd3278 HS	299	assert(src_clk_div <= 0x3f);
	300
	301	switch (periph) {
	302	case HCLK_EMMC:
7a25a63c	303	case SCLK_EMMC:
dcdd3278 HS	304	rk_clrsetreg(&cru->cru_clksel_con[12],
	305	EMMC_DIV_MASK << EMMC_DIV_SHIFT,
	306	src_clk_div << EMMC_DIV_SHIFT);
	307	break;
	308	case HCLK_SDMMC:
7a25a63c	309	case SCLK_SDMMC:
dcdd3278 HS	310	rk_clrsetreg(&cru->cru_clksel_con[11],
	311	MMC0_DIV_MASK << MMC0_DIV_SHIFT,
	312	src_clk_div << MMC0_DIV_SHIFT);
	313	break;
	314	case HCLK_SDIO:
7a25a63c	315	case SCLK_SDIO:
dcdd3278 HS	316	rk_clrsetreg(&cru->cru_clksel_con[12],
	317	SDIO_DIV_MASK << SDIO_DIV_SHIFT,
	318	src_clk_div << SDIO_DIV_SHIFT);
	319	break;
	320	default:
	321	return -EINVAL;
	322	}
	323
	324	return rockchip_mmc_get_clk(cru, gclk_rate, periph);
	325	}
	326
	327	static ulong rockchip_spi_get_clk(struct rk3188_cru *cru, uint gclk_rate,
	328	int periph)
	329	{
	330	uint div;
	331	u32 con;
	332
	333	switch (periph) {
	334	case SCLK_SPI0:
	335	con = readl(&cru->cru_clksel_con[25]);
	336	div = (con >> SPI0_DIV_SHIFT) & SPI0_DIV_MASK;
	337	break;
	338	case SCLK_SPI1:
	339	con = readl(&cru->cru_clksel_con[25]);
	340	div = (con >> SPI1_DIV_SHIFT) & SPI1_DIV_MASK;
	341	break;
	342	default:
	343	return -EINVAL;
	344	}
	345
	346	return DIV_TO_RATE(gclk_rate, div);
	347	}
	348
	349	static ulong rockchip_spi_set_clk(struct rk3188_cru *cru, uint gclk_rate,
	350	int periph, uint freq)
	351	{
217273cd	352	int src_clk_div = DIV_ROUND_UP(gclk_rate, freq) - 1;
dcdd3278	353
217273cd	354	assert(src_clk_div < 128);
dcdd3278 HS	355	switch (periph) {
	356	case SCLK_SPI0:
	357	assert(src_clk_div <= SPI0_DIV_MASK);
	358	rk_clrsetreg(&cru->cru_clksel_con[25],
	359	SPI0_DIV_MASK << SPI0_DIV_SHIFT,
	360	src_clk_div << SPI0_DIV_SHIFT);
	361	break;
	362	case SCLK_SPI1:
	363	assert(src_clk_div <= SPI1_DIV_MASK);
	364	rk_clrsetreg(&cru->cru_clksel_con[25],
	365	SPI1_DIV_MASK << SPI1_DIV_SHIFT,
	366	src_clk_div << SPI1_DIV_SHIFT);
	367	break;
	368	default:
	369	return -EINVAL;
	370	}
	371
	372	return rockchip_spi_get_clk(cru, gclk_rate, periph);
	373	}
	374
	375	#ifdef CONFIG_SPL_BUILD
	376	static void rkclk_init(struct rk3188_cru cru, struct rk3188_grf grf,
	377	bool has_bwadj)
	378	{
	379	u32 aclk_div, hclk_div, pclk_div, h2p_div;
	380
	381	/* pll enter slow-mode */
	382	rk_clrsetreg(&cru->cru_mode_con,
	383	GPLL_MODE_MASK << GPLL_MODE_SHIFT \|
	384	CPLL_MODE_MASK << CPLL_MODE_SHIFT,
	385	GPLL_MODE_SLOW << GPLL_MODE_SHIFT \|
	386	CPLL_MODE_SLOW << CPLL_MODE_SHIFT);
	387
	388	/* init pll */
	389	rkclk_set_pll(cru, CLK_GENERAL, &gpll_init_cfg, has_bwadj);
	390	rkclk_set_pll(cru, CLK_CODEC, &cpll_init_cfg, has_bwadj);
	391
	392	/* waiting for pll lock */
	393	while ((readl(&grf->soc_status0) &
	394	(SOCSTS_CPLL_LOCK \| SOCSTS_GPLL_LOCK)) !=
	395	(SOCSTS_CPLL_LOCK \| SOCSTS_GPLL_LOCK))
	396	udelay(1);
	397
	398	/*
	399	* cpu clock pll source selection and
	400	* reparent aclk_cpu_pre from apll to gpll
	401	* set up dependent divisors for PCLK/HCLK and ACLK clocks.
	402	*/
217273cd KY	403	aclk_div = DIV_ROUND_UP(GPLL_HZ, CPU_ACLK_HZ) - 1;
217273cd KY	404	assert((aclk_div + 1) * CPU_ACLK_HZ == GPLL_HZ && aclk_div <= 0x1f);
dcdd3278 HS	405
	406	rk_clrsetreg(&cru->cru_clksel_con[0],
	407	CPU_ACLK_PLL_MASK << CPU_ACLK_PLL_SHIFT \|
	408	A9_CPU_DIV_MASK << A9_CPU_DIV_SHIFT,
	409	CPU_ACLK_PLL_SELECT_GPLL << CPU_ACLK_PLL_SHIFT \|
	410	aclk_div << A9_CPU_DIV_SHIFT);
	411
	412	hclk_div = ilog2(CPU_ACLK_HZ / CPU_HCLK_HZ);
	413	assert((1 << hclk_div) * CPU_HCLK_HZ == CPU_ACLK_HZ && hclk_div < 0x3);
	414	pclk_div = ilog2(CPU_ACLK_HZ / CPU_PCLK_HZ);
	415	assert((1 << pclk_div) * CPU_PCLK_HZ == CPU_ACLK_HZ && pclk_div < 0x4);
	416	h2p_div = ilog2(CPU_HCLK_HZ / CPU_H2P_HZ);
	417	assert((1 << h2p_div) * CPU_H2P_HZ == CPU_HCLK_HZ && pclk_div < 0x3);
	418
	419	rk_clrsetreg(&cru->cru_clksel_con[1],
	420	AHB2APB_DIV_MASK << AHB2APB_DIV_SHIFT \|
	421	CPU_PCLK_DIV_MASK << CPU_PCLK_DIV_SHIFT \|
	422	CPU_HCLK_DIV_MASK << CPU_HCLK_DIV_SHIFT,
	423	h2p_div << AHB2APB_DIV_SHIFT \|
	424	pclk_div << CPU_PCLK_DIV_SHIFT \|
	425	hclk_div << CPU_HCLK_DIV_SHIFT);
	426
	427	/*
	428	* peri clock pll source selection and
	429	* set up dependent divisors for PCLK/HCLK and ACLK clocks.
	430	*/
	431	aclk_div = GPLL_HZ / PERI_ACLK_HZ - 1;
	432	assert((aclk_div + 1) * PERI_ACLK_HZ == GPLL_HZ && aclk_div < 0x1f);
	433
	434	hclk_div = ilog2(PERI_ACLK_HZ / PERI_HCLK_HZ);
	435	assert((1 << hclk_div) * PERI_HCLK_HZ ==
	436	PERI_ACLK_HZ && (hclk_div < 0x4));
	437
	438	pclk_div = ilog2(PERI_ACLK_HZ / PERI_PCLK_HZ);
	439	assert((1 << pclk_div) * PERI_PCLK_HZ ==
	440	PERI_ACLK_HZ && (pclk_div < 0x4));
	441
	442	rk_clrsetreg(&cru->cru_clksel_con[10],
	443	PERI_PCLK_DIV_MASK << PERI_PCLK_DIV_SHIFT \|
	444	PERI_HCLK_DIV_MASK << PERI_HCLK_DIV_SHIFT \|
	445	PERI_ACLK_DIV_MASK << PERI_ACLK_DIV_SHIFT,
	446	PERI_SEL_GPLL << PERI_SEL_PLL_SHIFT \|
	447	pclk_div << PERI_PCLK_DIV_SHIFT \|
	448	hclk_div << PERI_HCLK_DIV_SHIFT \|
	449	aclk_div << PERI_ACLK_DIV_SHIFT);
	450
	451	/* PLL enter normal-mode */
	452	rk_clrsetreg(&cru->cru_mode_con,
	453	GPLL_MODE_MASK << GPLL_MODE_SHIFT \|
	454	CPLL_MODE_MASK << CPLL_MODE_SHIFT,
	455	GPLL_MODE_NORMAL << GPLL_MODE_SHIFT \|
	456	CPLL_MODE_NORMAL << CPLL_MODE_SHIFT);
	457
	458	rockchip_mmc_set_clk(cru, PERI_HCLK_HZ, HCLK_SDMMC, 16000000);
	459	}
	460	#endif
	461
	462	static ulong rk3188_clk_get_rate(struct clk *clk)
	463	{
	464	struct rk3188_clk_priv *priv = dev_get_priv(clk->dev);
	465	ulong new_rate, gclk_rate;
	466
	467	gclk_rate = rkclk_pll_get_rate(priv->cru, CLK_GENERAL);
	468	switch (clk->id) {
469	case 1 ... 4:
470	new_rate = rkclk_pll_get_rate(priv->cru, clk->id);
471	break;
472	case HCLK_EMMC:
473	case HCLK_SDMMC:
474	case HCLK_SDIO:
7a25a63c XZ	475	case SCLK_EMMC:
	476	case SCLK_SDMMC:
	477	case SCLK_SDIO:
dcdd3278 HS	478	new_rate = rockchip_mmc_get_clk(priv->cru, PERI_HCLK_HZ,
	479	clk->id);
	480	break;
	481	case SCLK_SPI0:
	482	case SCLK_SPI1:
	483	new_rate = rockchip_spi_get_clk(priv->cru, PERI_PCLK_HZ,
	484	clk->id);
	485	break;
	486	case PCLK_I2C0:
	487	case PCLK_I2C1:
	488	case PCLK_I2C2:
	489	case PCLK_I2C3:
	490	case PCLK_I2C4:
	491	return gclk_rate;
	492	default:
	493	return -ENOENT;
	494	}
	495
	496	return new_rate;
	497	}
	498
	499	static ulong rk3188_clk_set_rate(struct clk *clk, ulong rate)
	500	{
	501	struct rk3188_clk_priv *priv = dev_get_priv(clk->dev);
	502	struct rk3188_cru *cru = priv->cru;
	503	ulong new_rate;
	504
	505	switch (clk->id) {
f7853570 HS	506	case PLL_APLL:
	507	new_rate = rkclk_configure_cpu(priv->cru, priv->grf, rate,
	508	priv->has_bwadj);
	509	break;
dcdd3278 HS	510	case CLK_DDR:
	511	new_rate = rkclk_configure_ddr(priv->cru, priv->grf, rate,
	512	priv->has_bwadj);
	513	break;
	514	case HCLK_EMMC:
	515	case HCLK_SDMMC:
	516	case HCLK_SDIO:
7a25a63c XZ	517	case SCLK_EMMC:
	518	case SCLK_SDMMC:
	519	case SCLK_SDIO:
dcdd3278 HS	520	new_rate = rockchip_mmc_set_clk(cru, PERI_HCLK_HZ,
	521	clk->id, rate);
	522	break;
	523	case SCLK_SPI0:
	524	case SCLK_SPI1:
	525	new_rate = rockchip_spi_set_clk(cru, PERI_PCLK_HZ,
	526	clk->id, rate);
	527	break;
	528	default:
	529	return -ENOENT;
	530	}
	531
	532	return new_rate;
	533	}
	534
	535	static struct clk_ops rk3188_clk_ops = {
	536	.get_rate = rk3188_clk_get_rate,
	537	.set_rate = rk3188_clk_set_rate,
	538	};
	539
d1998a9f	540	static int rk3188_clk_of_to_plat(struct udevice *dev)
dcdd3278	541	{
dcfc42b1 SG	542	if (CONFIG_IS_ENABLED(OF_REAL)) {
dcfc42b1 SG	543	struct rk3188_clk_priv *priv = dev_get_priv(dev);
dcdd3278	544
dcfc42b1 SG	545	priv->cru = dev_read_addr_ptr(dev);
dcfc42b1 SG	546	}
dcdd3278 HS	547
	548	return 0;
	549	}
	550
	551	static int rk3188_clk_probe(struct udevice *dev)
	552	{
	553	struct rk3188_clk_priv *priv = dev_get_priv(dev);
	554	enum rk3188_clk_type type = dev_get_driver_data(dev);
	555
	556	priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
	557	if (IS_ERR(priv->grf))
	558	return PTR_ERR(priv->grf);
	559	priv->has_bwadj = (type == RK3188A_CRU) ? 1 : 0;
	560
	561	#ifdef CONFIG_SPL_BUILD
	562	#if CONFIG_IS_ENABLED(OF_PLATDATA)
c69cda25	563	struct rk3188_clk_plat *plat = dev_get_plat(dev);
dcdd3278 HS	564
	565	priv->cru = map_sysmem(plat->dtd.reg[0], plat->dtd.reg[1]);
	566	#endif
	567
	568	rkclk_init(priv->cru, priv->grf, priv->has_bwadj);
84a6a27a KY	569
84a6a27a KY	570	/* Init CPU frequency */
5e15dcb4 AK	571	rkclk_configure_cpu(priv->cru, priv->grf, APLL_SAFE_HZ,
5e15dcb4 AK	572	priv->has_bwadj);
dcdd3278 HS	573	#endif
	574
	575	return 0;
	576	}
	577
	578	static int rk3188_clk_bind(struct udevice *dev)
	579	{
	580	int ret;
f24e36da KY	581	struct udevice *sys_child;
f24e36da KY	582	struct sysreset_reg *priv;
dcdd3278 HS	583
dcdd3278 HS	584	/* The reset driver does not have a device node, so bind it here */
f24e36da KY	585	ret = device_bind_driver(dev, "rockchip_sysreset", "sysreset",
	586	&sys_child);
	587	if (ret) {
	588	debug("Warning: No sysreset driver: ret=%d\n", ret);
	589	} else {
	590	priv = malloc(sizeof(struct sysreset_reg));
	591	priv->glb_srst_fst_value = offsetof(struct rk3188_cru,
	592	cru_glb_srst_fst_value);
	593	priv->glb_srst_snd_value = offsetof(struct rk3188_cru,
	594	cru_glb_srst_snd_value);
0fd3d911	595	dev_set_priv(sys_child, priv);
f24e36da	596	}
dcdd3278	597
a5ada25e	598	#if CONFIG_IS_ENABLED(RESET_ROCKCHIP)
538f67c3 EZ	599	ret = offsetof(struct rk3188_cru, cru_softrst_con[0]);
	600	ret = rockchip_reset_bind(dev, ret, 9);
	601	if (ret)
30850b69	602	debug("Warning: software reset driver bind failed\n");
538f67c3 EZ	603	#endif
538f67c3 EZ	604
dcdd3278 HS	605	return 0;
	606	}
	607
	608	static const struct udevice_id rk3188_clk_ids[] = {
	609	{ .compatible = "rockchip,rk3188-cru", .data = RK3188_CRU },
	610	{ .compatible = "rockchip,rk3188a-cru", .data = RK3188A_CRU },
	611	{ }
	612	};
	613
	614	U_BOOT_DRIVER(rockchip_rk3188_cru) = {
	615	.name = "rockchip_rk3188_cru",
	616	.id = UCLASS_CLK,
	617	.of_match = rk3188_clk_ids,
41575d8e	618	.priv_auto = sizeof(struct rk3188_clk_priv),
caa4daa2	619	.plat_auto = sizeof(struct rk3188_clk_plat),
dcdd3278 HS	620	.ops = &rk3188_clk_ops,
dcdd3278 HS	621	.bind = rk3188_clk_bind,
d1998a9f	622	.of_to_plat = rk3188_clk_of_to_plat,
dcdd3278 HS	623	.probe = rk3188_clk_probe,
dcdd3278 HS	624	};