[thirdparty/u-boot.git] / drivers / clk / sunxi / clk_a23.c

// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Copyright (C) 2018 Amarula Solutions B.V.
 * Author: Jagan Teki <jagan@amarulasolutions.com>
 */

#include <common.h>
#include <clk-uclass.h>
#include <dm.h>
#include <errno.h>
#include <clk/sunxi.h>
#include <dt-bindings/clock/sun8i-a23-a33-ccu.h>
#include <dt-bindings/reset/sun8i-a23-a33-ccu.h>
#include <linux/bitops.h>

static struct ccu_clk_gate a23_gates[] = {
	[CLK_BUS_MMC0]		= GATE(0x060, BIT(8)),
	[CLK_BUS_MMC1]		= GATE(0x060, BIT(9)),
	[CLK_BUS_MMC2]		= GATE(0x060, BIT(10)),
	[CLK_BUS_NAND]		= GATE(0x060, BIT(13)),
	[CLK_BUS_SPI0]		= GATE(0x060, BIT(20)),
	[CLK_BUS_SPI1]		= GATE(0x060, BIT(21)),
	[CLK_BUS_OTG]		= GATE(0x060, BIT(24)),
	[CLK_BUS_EHCI]		= GATE(0x060, BIT(26)),
	[CLK_BUS_OHCI]		= GATE(0x060, BIT(29)),

	[CLK_BUS_PIO]		= GATE(0x068, BIT(5)),

	[CLK_BUS_I2C0]		= GATE(0x06c, BIT(0)),
	[CLK_BUS_I2C1]		= GATE(0x06c, BIT(1)),
	[CLK_BUS_I2C2]		= GATE(0x06c, BIT(2)),
	[CLK_BUS_UART0]		= GATE(0x06c, BIT(16)),
	[CLK_BUS_UART1]		= GATE(0x06c, BIT(17)),
	[CLK_BUS_UART2]		= GATE(0x06c, BIT(18)),
	[CLK_BUS_UART3]		= GATE(0x06c, BIT(19)),
	[CLK_BUS_UART4]		= GATE(0x06c, BIT(20)),

	[CLK_NAND]		= GATE(0x080, BIT(31)),
	[CLK_SPI0]		= GATE(0x0a0, BIT(31)),
	[CLK_SPI1]		= GATE(0x0a4, BIT(31)),

	[CLK_USB_PHY0]		= GATE(0x0cc, BIT(8)),
	[CLK_USB_PHY1]		= GATE(0x0cc, BIT(9)),
	[CLK_USB_HSIC]		= GATE(0x0cc, BIT(10)),
	[CLK_USB_HSIC_12M]	= GATE(0x0cc, BIT(11)),
	[CLK_USB_OHCI]		= GATE(0x0cc, BIT(16)),
};

static struct ccu_reset a23_resets[] = {
	[RST_USB_PHY0]		= RESET(0x0cc, BIT(0)),
	[RST_USB_PHY1]		= RESET(0x0cc, BIT(1)),
	[RST_USB_HSIC]		= RESET(0x0cc, BIT(2)),

	[RST_BUS_MMC0]		= RESET(0x2c0, BIT(8)),
	[RST_BUS_MMC1]		= RESET(0x2c0, BIT(9)),
	[RST_BUS_MMC2]		= RESET(0x2c0, BIT(10)),
	[RST_BUS_NAND]		= RESET(0x2c0, BIT(13)),
	[RST_BUS_SPI0]		= RESET(0x2c0, BIT(20)),
	[RST_BUS_SPI1]		= RESET(0x2c0, BIT(21)),
	[RST_BUS_OTG]		= RESET(0x2c0, BIT(24)),
	[RST_BUS_EHCI]		= RESET(0x2c0, BIT(26)),
	[RST_BUS_OHCI]		= RESET(0x2c0, BIT(29)),

	[RST_BUS_I2C0]		= RESET(0x2d8, BIT(0)),
	[RST_BUS_I2C1]		= RESET(0x2d8, BIT(1)),
	[RST_BUS_I2C2]		= RESET(0x2d8, BIT(2)),
	[RST_BUS_UART0]		= RESET(0x2d8, BIT(16)),
	[RST_BUS_UART1]		= RESET(0x2d8, BIT(17)),
	[RST_BUS_UART2]		= RESET(0x2d8, BIT(18)),
	[RST_BUS_UART3]		= RESET(0x2d8, BIT(19)),
	[RST_BUS_UART4]		= RESET(0x2d8, BIT(20)),
};

const struct ccu_desc a23_ccu_desc = {
	.gates = a23_gates,
	.resets = a23_resets,
	.num_gates = ARRAY_SIZE(a23_gates),
	.num_resets = ARRAY_SIZE(a23_resets),
};
Commit	Line	Data
3ab02936 JT	1	// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
	2	/*
	3	* Copyright (C) 2018 Amarula Solutions B.V.
	4	* Author: Jagan Teki <jagan@amarulasolutions.com>
	5	*/
	6
d678a59d	7	#include <common.h>
3ab02936 JT	8	#include <clk-uclass.h>
	9	#include <dm.h>
	10	#include <errno.h>
21d314a6	11	#include <clk/sunxi.h>
3ab02936 JT	12	#include <dt-bindings/clock/sun8i-a23-a33-ccu.h>
3ab02936 JT	13	#include <dt-bindings/reset/sun8i-a23-a33-ccu.h>
cd93d625	14	#include <linux/bitops.h>
3ab02936 JT	15
3ab02936 JT	16	static struct ccu_clk_gate a23_gates[] = {
bb3e5aa2 AP	17	[CLK_BUS_MMC0] = GATE(0x060, BIT(8)),
	18	[CLK_BUS_MMC1] = GATE(0x060, BIT(9)),
	19	[CLK_BUS_MMC2] = GATE(0x060, BIT(10)),
59c1ddd2	20	[CLK_BUS_NAND] = GATE(0x060, BIT(13)),
82111469 JT	21	[CLK_BUS_SPI0] = GATE(0x060, BIT(20)),
82111469 JT	22	[CLK_BUS_SPI1] = GATE(0x060, BIT(21)),
3ab02936 JT	23	[CLK_BUS_OTG] = GATE(0x060, BIT(24)),
	24	[CLK_BUS_EHCI] = GATE(0x060, BIT(26)),
	25	[CLK_BUS_OHCI] = GATE(0x060, BIT(29)),
	26
444ab356 AP	27	[CLK_BUS_PIO] = GATE(0x068, BIT(5)),
444ab356 AP	28
c61897bf SH	29	[CLK_BUS_I2C0] = GATE(0x06c, BIT(0)),
	30	[CLK_BUS_I2C1] = GATE(0x06c, BIT(1)),
	31	[CLK_BUS_I2C2] = GATE(0x06c, BIT(2)),
4acc7119 JT	32	[CLK_BUS_UART0] = GATE(0x06c, BIT(16)),
	33	[CLK_BUS_UART1] = GATE(0x06c, BIT(17)),
	34	[CLK_BUS_UART2] = GATE(0x06c, BIT(18)),
	35	[CLK_BUS_UART3] = GATE(0x06c, BIT(19)),
	36	[CLK_BUS_UART4] = GATE(0x06c, BIT(20)),
	37
59c1ddd2	38	[CLK_NAND] = GATE(0x080, BIT(31)),
82111469 JT	39	[CLK_SPI0] = GATE(0x0a0, BIT(31)),
	40	[CLK_SPI1] = GATE(0x0a4, BIT(31)),
	41
3ab02936 JT	42	[CLK_USB_PHY0] = GATE(0x0cc, BIT(8)),
	43	[CLK_USB_PHY1] = GATE(0x0cc, BIT(9)),
	44	[CLK_USB_HSIC] = GATE(0x0cc, BIT(10)),
	45	[CLK_USB_HSIC_12M] = GATE(0x0cc, BIT(11)),
	46	[CLK_USB_OHCI] = GATE(0x0cc, BIT(16)),
	47	};
	48
	49	static struct ccu_reset a23_resets[] = {
	50	[RST_USB_PHY0] = RESET(0x0cc, BIT(0)),
	51	[RST_USB_PHY1] = RESET(0x0cc, BIT(1)),
	52	[RST_USB_HSIC] = RESET(0x0cc, BIT(2)),
	53
bb3e5aa2 AP	54	[RST_BUS_MMC0] = RESET(0x2c0, BIT(8)),
	55	[RST_BUS_MMC1] = RESET(0x2c0, BIT(9)),
	56	[RST_BUS_MMC2] = RESET(0x2c0, BIT(10)),
59c1ddd2	57	[RST_BUS_NAND] = RESET(0x2c0, BIT(13)),
82111469 JT	58	[RST_BUS_SPI0] = RESET(0x2c0, BIT(20)),
82111469 JT	59	[RST_BUS_SPI1] = RESET(0x2c0, BIT(21)),
3ab02936 JT	60	[RST_BUS_OTG] = RESET(0x2c0, BIT(24)),
	61	[RST_BUS_EHCI] = RESET(0x2c0, BIT(26)),
	62	[RST_BUS_OHCI] = RESET(0x2c0, BIT(29)),
8606f960	63
c61897bf SH	64	[RST_BUS_I2C0] = RESET(0x2d8, BIT(0)),
	65	[RST_BUS_I2C1] = RESET(0x2d8, BIT(1)),
	66	[RST_BUS_I2C2] = RESET(0x2d8, BIT(2)),
8606f960 JT	67	[RST_BUS_UART0] = RESET(0x2d8, BIT(16)),
	68	[RST_BUS_UART1] = RESET(0x2d8, BIT(17)),
	69	[RST_BUS_UART2] = RESET(0x2d8, BIT(18)),
	70	[RST_BUS_UART3] = RESET(0x2d8, BIT(19)),
	71	[RST_BUS_UART4] = RESET(0x2d8, BIT(20)),
3ab02936 JT	72	};
3ab02936 JT	73
46fa23f9	74	const struct ccu_desc a23_ccu_desc = {
3ab02936 JT	75	.gates = a23_gates,
3ab02936 JT	76	.resets = a23_resets,
49b2b0a2 SH	77	.num_gates = ARRAY_SIZE(a23_gates),
49b2b0a2 SH	78	.num_resets = ARRAY_SIZE(a23_resets),
3ab02936	79	};