[thirdparty/u-boot.git] / drivers / clk / sunxi / clk_a80.c

// SPDX-License-Identifier: GPL-2.0+
/*
 * Copyright (C) 2018 Amarula Solutions.
 * Author: Jagan Teki <jagan@amarulasolutions.com>
 */

#include <common.h>
#include <clk-uclass.h>
#include <dm.h>
#include <errno.h>
#include <clk/sunxi.h>
#include <dt-bindings/clock/sun9i-a80-ccu.h>
#include <dt-bindings/reset/sun9i-a80-ccu.h>
#include <linux/bitops.h>

static const struct ccu_clk_gate a80_gates[] = {
	[CLK_NAND0_0]		= GATE(0x400, BIT(31)),
	[CLK_NAND0_1]		= GATE(0x404, BIT(31)),
	[CLK_NAND1_0]		= GATE(0x408, BIT(31)),
	[CLK_NAND1_1]		= GATE(0x40c, BIT(31)),
	[CLK_SPI0]		= GATE(0x430, BIT(31)),
	[CLK_SPI1]		= GATE(0x434, BIT(31)),
	[CLK_SPI2]		= GATE(0x438, BIT(31)),
	[CLK_SPI3]		= GATE(0x43c, BIT(31)),

	[CLK_BUS_MMC]		= GATE(0x580, BIT(8)),
	[CLK_BUS_NAND0]		= GATE(0x580, BIT(13)),
	[CLK_BUS_NAND1]		= GATE(0x580, BIT(12)),
	[CLK_BUS_SPI0]		= GATE(0x580, BIT(20)),
	[CLK_BUS_SPI1]		= GATE(0x580, BIT(21)),
	[CLK_BUS_SPI2]		= GATE(0x580, BIT(22)),
	[CLK_BUS_SPI3]		= GATE(0x580, BIT(23)),

	[CLK_BUS_PIO]           = GATE(0x590, BIT(5)),

	[CLK_BUS_I2C0]		= GATE(0x594, BIT(0)),
	[CLK_BUS_I2C1]		= GATE(0x594, BIT(1)),
	[CLK_BUS_I2C2]		= GATE(0x594, BIT(2)),
	[CLK_BUS_I2C3]		= GATE(0x594, BIT(3)),
	[CLK_BUS_I2C4]		= GATE(0x594, BIT(4)),
	[CLK_BUS_UART0]		= GATE(0x594, BIT(16)),
	[CLK_BUS_UART1]		= GATE(0x594, BIT(17)),
	[CLK_BUS_UART2]		= GATE(0x594, BIT(18)),
	[CLK_BUS_UART3]		= GATE(0x594, BIT(19)),
	[CLK_BUS_UART4]		= GATE(0x594, BIT(20)),
	[CLK_BUS_UART5]		= GATE(0x594, BIT(21)),
};

static const struct ccu_reset a80_resets[] = {
	[RST_BUS_MMC]		= RESET(0x5a0, BIT(8)),
	[RST_BUS_NAND0]		= RESET(0x5a0, BIT(13)),
	[RST_BUS_NAND1]		= RESET(0x5a0, BIT(12)),
	[RST_BUS_SPI0]		= RESET(0x5a0, BIT(20)),
	[RST_BUS_SPI1]		= RESET(0x5a0, BIT(21)),
	[RST_BUS_SPI2]		= RESET(0x5a0, BIT(22)),
	[RST_BUS_SPI3]		= RESET(0x5a0, BIT(23)),

	[RST_BUS_I2C0]		= RESET(0x5b4, BIT(0)),
	[RST_BUS_I2C1]		= RESET(0x5b4, BIT(1)),
	[RST_BUS_I2C2]		= RESET(0x5b4, BIT(2)),
	[RST_BUS_I2C3]		= RESET(0x5b4, BIT(3)),
	[RST_BUS_I2C4]		= RESET(0x5b4, BIT(4)),
	[RST_BUS_UART0]		= RESET(0x5b4, BIT(16)),
	[RST_BUS_UART1]		= RESET(0x5b4, BIT(17)),
	[RST_BUS_UART2]		= RESET(0x5b4, BIT(18)),
	[RST_BUS_UART3]		= RESET(0x5b4, BIT(19)),
	[RST_BUS_UART4]		= RESET(0x5b4, BIT(20)),
	[RST_BUS_UART5]		= RESET(0x5b4, BIT(21)),
};

static const struct ccu_clk_gate a80_mmc_gates[] = {
	[0]			= GATE(0x0, BIT(16)),
	[1]			= GATE(0x4, BIT(16)),
	[2]			= GATE(0x8, BIT(16)),
	[3]			= GATE(0xc, BIT(16)),
};

static const struct ccu_reset a80_mmc_resets[] = {
	[0]			= GATE(0x0, BIT(18)),
	[1]			= GATE(0x4, BIT(18)),
	[2]			= GATE(0x8, BIT(18)),
	[3]			= GATE(0xc, BIT(18)),
};

const struct ccu_desc a80_ccu_desc = {
	.gates = a80_gates,
	.resets = a80_resets,
	.num_gates = ARRAY_SIZE(a80_gates),
	.num_resets = ARRAY_SIZE(a80_resets),
};

const struct ccu_desc a80_mmc_clk_desc = {
	.gates = a80_mmc_gates,
	.resets = a80_mmc_resets,
	.num_gates = ARRAY_SIZE(a80_mmc_gates),
	.num_resets = ARRAY_SIZE(a80_mmc_resets),
};
Commit	Line	Data
6901aab8 JT	1	// SPDX-License-Identifier: GPL-2.0+
	2	/*
	3	* Copyright (C) 2018 Amarula Solutions.
	4	* Author: Jagan Teki <jagan@amarulasolutions.com>
	5	*/
	6
d678a59d	7	#include <common.h>
6901aab8 JT	8	#include <clk-uclass.h>
	9	#include <dm.h>
	10	#include <errno.h>
21d314a6	11	#include <clk/sunxi.h>
6901aab8 JT	12	#include <dt-bindings/clock/sun9i-a80-ccu.h>
6901aab8 JT	13	#include <dt-bindings/reset/sun9i-a80-ccu.h>
cd93d625	14	#include <linux/bitops.h>
6901aab8 JT	15
6901aab8 JT	16	static const struct ccu_clk_gate a80_gates[] = {
59c1ddd2 SH	17	[CLK_NAND0_0] = GATE(0x400, BIT(31)),
	18	[CLK_NAND0_1] = GATE(0x404, BIT(31)),
	19	[CLK_NAND1_0] = GATE(0x408, BIT(31)),
	20	[CLK_NAND1_1] = GATE(0x40c, BIT(31)),
82111469 JT	21	[CLK_SPI0] = GATE(0x430, BIT(31)),
	22	[CLK_SPI1] = GATE(0x434, BIT(31)),
	23	[CLK_SPI2] = GATE(0x438, BIT(31)),
	24	[CLK_SPI3] = GATE(0x43c, BIT(31)),
	25
bb3e5aa2	26	[CLK_BUS_MMC] = GATE(0x580, BIT(8)),
59c1ddd2 SH	27	[CLK_BUS_NAND0] = GATE(0x580, BIT(13)),
59c1ddd2 SH	28	[CLK_BUS_NAND1] = GATE(0x580, BIT(12)),
82111469 JT	29	[CLK_BUS_SPI0] = GATE(0x580, BIT(20)),
	30	[CLK_BUS_SPI1] = GATE(0x580, BIT(21)),
	31	[CLK_BUS_SPI2] = GATE(0x580, BIT(22)),
	32	[CLK_BUS_SPI3] = GATE(0x580, BIT(23)),
bb3e5aa2	33
444ab356 AP	34	[CLK_BUS_PIO] = GATE(0x590, BIT(5)),
444ab356 AP	35
c61897bf SH	36	[CLK_BUS_I2C0] = GATE(0x594, BIT(0)),
	37	[CLK_BUS_I2C1] = GATE(0x594, BIT(1)),
	38	[CLK_BUS_I2C2] = GATE(0x594, BIT(2)),
	39	[CLK_BUS_I2C3] = GATE(0x594, BIT(3)),
	40	[CLK_BUS_I2C4] = GATE(0x594, BIT(4)),
6901aab8 JT	41	[CLK_BUS_UART0] = GATE(0x594, BIT(16)),
	42	[CLK_BUS_UART1] = GATE(0x594, BIT(17)),
	43	[CLK_BUS_UART2] = GATE(0x594, BIT(18)),
	44	[CLK_BUS_UART3] = GATE(0x594, BIT(19)),
	45	[CLK_BUS_UART4] = GATE(0x594, BIT(20)),
	46	[CLK_BUS_UART5] = GATE(0x594, BIT(21)),
	47	};
	48
	49	static const struct ccu_reset a80_resets[] = {
bb3e5aa2	50	[RST_BUS_MMC] = RESET(0x5a0, BIT(8)),
59c1ddd2 SH	51	[RST_BUS_NAND0] = RESET(0x5a0, BIT(13)),
59c1ddd2 SH	52	[RST_BUS_NAND1] = RESET(0x5a0, BIT(12)),
82111469 JT	53	[RST_BUS_SPI0] = RESET(0x5a0, BIT(20)),
	54	[RST_BUS_SPI1] = RESET(0x5a0, BIT(21)),
	55	[RST_BUS_SPI2] = RESET(0x5a0, BIT(22)),
	56	[RST_BUS_SPI3] = RESET(0x5a0, BIT(23)),
bb3e5aa2	57
c61897bf SH	58	[RST_BUS_I2C0] = RESET(0x5b4, BIT(0)),
	59	[RST_BUS_I2C1] = RESET(0x5b4, BIT(1)),
	60	[RST_BUS_I2C2] = RESET(0x5b4, BIT(2)),
	61	[RST_BUS_I2C3] = RESET(0x5b4, BIT(3)),
	62	[RST_BUS_I2C4] = RESET(0x5b4, BIT(4)),
6901aab8 JT	63	[RST_BUS_UART0] = RESET(0x5b4, BIT(16)),
	64	[RST_BUS_UART1] = RESET(0x5b4, BIT(17)),
	65	[RST_BUS_UART2] = RESET(0x5b4, BIT(18)),
	66	[RST_BUS_UART3] = RESET(0x5b4, BIT(19)),
	67	[RST_BUS_UART4] = RESET(0x5b4, BIT(20)),
	68	[RST_BUS_UART5] = RESET(0x5b4, BIT(21)),
	69	};
	70
e0c7ce7e AP	71	static const struct ccu_clk_gate a80_mmc_gates[] = {
	72	[0] = GATE(0x0, BIT(16)),
	73	[1] = GATE(0x4, BIT(16)),
	74	[2] = GATE(0x8, BIT(16)),
	75	[3] = GATE(0xc, BIT(16)),
	76	};
	77
	78	static const struct ccu_reset a80_mmc_resets[] = {
	79	[0] = GATE(0x0, BIT(18)),
	80	[1] = GATE(0x4, BIT(18)),
	81	[2] = GATE(0x8, BIT(18)),
	82	[3] = GATE(0xc, BIT(18)),
	83	};
	84
46fa23f9	85	const struct ccu_desc a80_ccu_desc = {
6901aab8 JT	86	.gates = a80_gates,
6901aab8 JT	87	.resets = a80_resets,
49b2b0a2 SH	88	.num_gates = ARRAY_SIZE(a80_gates),
49b2b0a2 SH	89	.num_resets = ARRAY_SIZE(a80_resets),
6901aab8 JT	90	};
6901aab8 JT	91
46fa23f9	92	const struct ccu_desc a80_mmc_clk_desc = {
e0c7ce7e AP	93	.gates = a80_mmc_gates,
e0c7ce7e AP	94	.resets = a80_mmc_resets,
49b2b0a2 SH	95	.num_gates = ARRAY_SIZE(a80_mmc_gates),
49b2b0a2 SH	96	.num_resets = ARRAY_SIZE(a80_mmc_resets),
e0c7ce7e	97	};