projects / thirdparty / u-boot.git / blame
| Commit | Line | Data |
|---|---|---|
| b9a91b98 SH |
1 | // SPDX-License-Identifier: (GPL-2.0+ OR MIT) |
| 2 | /* | |
| 3 | * Copyright (C) 2021 Samuel Holland <samuel@sholland.org> | |
| 4 | */ | |
| 5 | ||
| d678a59d | 6 | #include <common.h> |
| b9a91b98 SH |
7 | #include <clk-uclass.h> |
| 8 | #include <dm.h> | |
| 9 | #include <errno.h> | |
| 10 | #include <clk/sunxi.h> | |
| 11 | #include <dt-bindings/clock/sun20i-d1-ccu.h> | |
| 12 | #include <dt-bindings/reset/sun20i-d1-ccu.h> | |
| 13 | #include <linux/bitops.h> | |
| 14 | ||
| 15 | static struct ccu_clk_gate d1_gates[] = { | |
| 16 | [CLK_APB0] = GATE_DUMMY, | |
| 17 | ||
| 18 | [CLK_BUS_MMC0] = GATE(0x84c, BIT(0)), | |
| 19 | [CLK_BUS_MMC1] = GATE(0x84c, BIT(1)), | |
| 20 | [CLK_BUS_MMC2] = GATE(0x84c, BIT(2)), | |
| 21 | [CLK_BUS_UART0] = GATE(0x90c, BIT(0)), | |
| 22 | [CLK_BUS_UART1] = GATE(0x90c, BIT(1)), | |
| 23 | [CLK_BUS_UART2] = GATE(0x90c, BIT(2)), | |
| 24 | [CLK_BUS_UART3] = GATE(0x90c, BIT(3)), | |
| 25 | [CLK_BUS_UART4] = GATE(0x90c, BIT(4)), | |
| 26 | [CLK_BUS_UART5] = GATE(0x90c, BIT(5)), | |
| 27 | [CLK_BUS_I2C0] = GATE(0x91c, BIT(0)), | |
| 28 | [CLK_BUS_I2C1] = GATE(0x91c, BIT(1)), | |
| 29 | [CLK_BUS_I2C2] = GATE(0x91c, BIT(2)), | |
| 30 | [CLK_BUS_I2C3] = GATE(0x91c, BIT(3)), | |
| 31 | [CLK_SPI0] = GATE(0x940, BIT(31)), | |
| 32 | [CLK_SPI1] = GATE(0x944, BIT(31)), | |
| 33 | [CLK_BUS_SPI0] = GATE(0x96c, BIT(0)), | |
| 34 | [CLK_BUS_SPI1] = GATE(0x96c, BIT(1)), | |
| 35 | ||
| 36 | [CLK_BUS_EMAC] = GATE(0x97c, BIT(0)), | |
| 37 | ||
| 38 | [CLK_USB_OHCI0] = GATE(0xa70, BIT(31)), | |
| 39 | [CLK_USB_OHCI1] = GATE(0xa74, BIT(31)), | |
| 40 | [CLK_BUS_OHCI0] = GATE(0xa8c, BIT(0)), | |
| 41 | [CLK_BUS_OHCI1] = GATE(0xa8c, BIT(1)), | |
| 42 | [CLK_BUS_EHCI0] = GATE(0xa8c, BIT(4)), | |
| 43 | [CLK_BUS_EHCI1] = GATE(0xa8c, BIT(5)), | |
| 44 | [CLK_BUS_OTG] = GATE(0xa8c, BIT(8)), | |
| 45 | [CLK_BUS_LRADC] = GATE(0xa9c, BIT(0)), | |
| 46 | ||
| 47 | [CLK_RISCV] = GATE(0xd04, BIT(31)), | |
| 48 | }; | |
| 49 | ||
| 50 | static struct ccu_reset d1_resets[] = { | |
| 51 | [RST_BUS_MMC0] = RESET(0x84c, BIT(16)), | |
| 52 | [RST_BUS_MMC1] = RESET(0x84c, BIT(17)), | |
| 53 | [RST_BUS_MMC2] = RESET(0x84c, BIT(18)), | |
| 54 | [RST_BUS_UART0] = RESET(0x90c, BIT(16)), | |
| 55 | [RST_BUS_UART1] = RESET(0x90c, BIT(17)), | |
| 56 | [RST_BUS_UART2] = RESET(0x90c, BIT(18)), | |
| 57 | [RST_BUS_UART3] = RESET(0x90c, BIT(19)), | |
| 58 | [RST_BUS_UART4] = RESET(0x90c, BIT(20)), | |
| 59 | [RST_BUS_UART5] = RESET(0x90c, BIT(21)), | |
| 60 | [RST_BUS_I2C0] = RESET(0x91c, BIT(16)), | |
| 61 | [RST_BUS_I2C1] = RESET(0x91c, BIT(17)), | |
| 62 | [RST_BUS_I2C2] = RESET(0x91c, BIT(18)), | |
| 63 | [RST_BUS_I2C3] = RESET(0x91c, BIT(19)), | |
| 64 | [RST_BUS_SPI0] = RESET(0x96c, BIT(16)), | |
| 65 | [RST_BUS_SPI1] = RESET(0x96c, BIT(17)), | |
| 66 | ||
| 67 | [RST_BUS_EMAC] = RESET(0x97c, BIT(16)), | |
| 68 | ||
| 69 | [RST_USB_PHY0] = RESET(0xa70, BIT(30)), | |
| 70 | [RST_USB_PHY1] = RESET(0xa74, BIT(30)), | |
| 71 | [RST_BUS_OHCI0] = RESET(0xa8c, BIT(16)), | |
| 72 | [RST_BUS_OHCI1] = RESET(0xa8c, BIT(17)), | |
| 73 | [RST_BUS_EHCI0] = RESET(0xa8c, BIT(20)), | |
| 74 | [RST_BUS_EHCI1] = RESET(0xa8c, BIT(21)), | |
| 75 | [RST_BUS_OTG] = RESET(0xa8c, BIT(24)), | |
| 76 | [RST_BUS_LRADC] = RESET(0xa9c, BIT(16)), | |
| 77 | }; | |
| 78 | ||
| 79 | const struct ccu_desc d1_ccu_desc = { | |
| 80 | .gates = d1_gates, | |
| 81 | .resets = d1_resets, | |
| 82 | .num_gates = ARRAY_SIZE(d1_gates), | |
| 83 | .num_resets = ARRAY_SIZE(d1_resets), | |
| 84 | }; |