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833508c0 BM |
1 | // SPDX-License-Identifier: GPL-2.0+ |
2 | /* | |
3 | * Copyright (C) 2018, Bin Meng <bmeng.cn@gmail.com> | |
62771862 | 4 | * Copyright (C) 2020, Sean Anderson <seanga2@gmail.com> |
833508c0 BM |
5 | */ |
6 | ||
ab24017a | 7 | #include <clk.h> |
833508c0 BM |
8 | #include <cpu.h> |
9 | #include <dm.h> | |
10 | #include <errno.h> | |
f7ae49fc | 11 | #include <log.h> |
401d1c4f | 12 | #include <asm/global_data.h> |
545e0e42 | 13 | #include <asm/sbi.h> |
833508c0 BM |
14 | #include <dm/device-internal.h> |
15 | #include <dm/lists.h> | |
cd93d625 | 16 | #include <linux/bitops.h> |
ab24017a | 17 | #include <linux/err.h> |
833508c0 | 18 | |
007056f4 AP |
19 | DECLARE_GLOBAL_DATA_PTR; |
20 | ||
961420fa | 21 | static int riscv_cpu_get_desc(const struct udevice *dev, char *buf, int size) |
833508c0 | 22 | { |
b90edde7 | 23 | const char *cpu; |
833508c0 | 24 | |
b90edde7 | 25 | cpu = dev_read_string(dev, "compatible"); |
9578e745 | 26 | if (!cpu || size < (strlen(cpu) + 1)) |
833508c0 BM |
27 | return -ENOSPC; |
28 | ||
b90edde7 | 29 | strcpy(buf, cpu); |
833508c0 BM |
30 | |
31 | return 0; | |
32 | } | |
33 | ||
961420fa | 34 | static int riscv_cpu_get_info(const struct udevice *dev, struct cpu_info *info) |
833508c0 | 35 | { |
ab24017a SA |
36 | int ret; |
37 | struct clk clk; | |
833508c0 | 38 | const char *mmu; |
add0dc1f SSK |
39 | u32 i_cache_size; |
40 | u32 d_cache_size; | |
833508c0 | 41 | |
ab24017a | 42 | /* First try getting the frequency from the assigned clock */ |
961420fa | 43 | ret = clk_get_by_index((struct udevice *)dev, 0, &clk); |
ab24017a SA |
44 | if (!ret) { |
45 | ret = clk_get_rate(&clk); | |
46 | if (!IS_ERR_VALUE(ret)) | |
47 | info->cpu_freq = ret; | |
ab24017a SA |
48 | } |
49 | ||
50 | if (!info->cpu_freq) | |
51 | dev_read_u32(dev, "clock-frequency", (u32 *)&info->cpu_freq); | |
833508c0 BM |
52 | |
53 | mmu = dev_read_string(dev, "mmu-type"); | |
b6b233dd | 54 | if (mmu) |
833508c0 BM |
55 | info->features |= BIT(CPU_FEAT_MMU); |
56 | ||
add0dc1f SSK |
57 | /* check if I cache is present */ |
58 | ret = dev_read_u32(dev, "i-cache-size", &i_cache_size); | |
59 | if (ret) | |
60 | /* if not found check if d-cache is present */ | |
61 | ret = dev_read_u32(dev, "d-cache-size", &d_cache_size); | |
62 | ||
63 | /* if either I or D cache is present set L1 cache feature */ | |
64 | if (!ret) | |
65 | info->features |= BIT(CPU_FEAT_L1_CACHE); | |
66 | ||
833508c0 BM |
67 | return 0; |
68 | } | |
69 | ||
961420fa | 70 | static int riscv_cpu_get_count(const struct udevice *dev) |
833508c0 BM |
71 | { |
72 | ofnode node; | |
73 | int num = 0; | |
74 | ||
75 | ofnode_for_each_subnode(node, dev_ofnode(dev->parent)) { | |
76 | const char *device_type; | |
77 | ||
4dfea4b5 | 78 | /* skip if hart is marked as not available in the device tree */ |
89090661 | 79 | if (!ofnode_is_enabled(node)) |
4dfea4b5 BM |
80 | continue; |
81 | ||
833508c0 BM |
82 | device_type = ofnode_read_string(node, "device_type"); |
83 | if (!device_type) | |
84 | continue; | |
85 | if (strcmp(device_type, "cpu") == 0) | |
86 | num++; | |
87 | } | |
88 | ||
89 | return num; | |
90 | } | |
91 | ||
92 | static int riscv_cpu_bind(struct udevice *dev) | |
93 | { | |
8a8d24bd | 94 | struct cpu_plat *plat = dev_get_parent_plat(dev); |
833508c0 BM |
95 | struct driver *drv; |
96 | int ret; | |
545e0e42 | 97 | long mvendorid; |
833508c0 BM |
98 | |
99 | /* save the hart id */ | |
100 | plat->cpu_id = dev_read_addr(dev); | |
545e0e42 | 101 | /* provide data for SMBIOS */ |
1b6228f2 HS |
102 | if (IS_ENABLED(CONFIG_64BIT)) |
103 | plat->family = 0x201; | |
104 | else | |
105 | plat->family = 0x200; | |
545e0e42 HS |
106 | if (CONFIG_IS_ENABLED(RISCV_SMODE)) { |
107 | /* | |
108 | * For RISC-V CPUs the SMBIOS Processor ID field contains | |
109 | * the Machine Vendor ID from CSR mvendorid. | |
110 | */ | |
111 | ret = sbi_get_mvendorid(&mvendorid); | |
112 | if (!ret) | |
113 | plat->id[0] = mvendorid; | |
114 | } | |
833508c0 BM |
115 | /* first examine the property in current cpu node */ |
116 | ret = dev_read_u32(dev, "timebase-frequency", &plat->timebase_freq); | |
117 | /* if not found, then look at the parent /cpus node */ | |
118 | if (ret) | |
119 | dev_read_u32(dev->parent, "timebase-frequency", | |
120 | &plat->timebase_freq); | |
121 | ||
122 | /* | |
007056f4 | 123 | * Bind riscv-timer driver on boot hart. |
833508c0 BM |
124 | * |
125 | * We only instantiate one timer device which is enough for U-Boot. | |
126 | * Pass the "timebase-frequency" value as the driver data for the | |
127 | * timer device. | |
128 | * | |
129 | * Return value is not checked since it's possible that the timer | |
130 | * driver is not included. | |
131 | */ | |
007056f4 | 132 | if (plat->cpu_id == gd->arch.boot_hart && plat->timebase_freq) { |
833508c0 BM |
133 | drv = lists_driver_lookup_name("riscv_timer"); |
134 | if (!drv) { | |
135 | debug("Cannot find the timer driver, not included?\n"); | |
136 | return 0; | |
137 | } | |
138 | ||
139 | device_bind_with_driver_data(dev, drv, "riscv_timer", | |
140 | plat->timebase_freq, ofnode_null(), | |
141 | NULL); | |
142 | } | |
143 | ||
144 | return 0; | |
145 | } | |
146 | ||
62771862 SA |
147 | static int riscv_cpu_probe(struct udevice *dev) |
148 | { | |
149 | int ret = 0; | |
150 | struct clk clk; | |
151 | ||
152 | /* Get a clock if it exists */ | |
153 | ret = clk_get_by_index(dev, 0, &clk); | |
154 | if (ret) | |
155 | return 0; | |
156 | ||
157 | ret = clk_enable(&clk); | |
62771862 SA |
158 | if (ret == -ENOSYS || ret == -ENOTSUPP) |
159 | return 0; | |
160 | else | |
161 | return ret; | |
162 | } | |
163 | ||
833508c0 BM |
164 | static const struct cpu_ops riscv_cpu_ops = { |
165 | .get_desc = riscv_cpu_get_desc, | |
166 | .get_info = riscv_cpu_get_info, | |
167 | .get_count = riscv_cpu_get_count, | |
168 | }; | |
169 | ||
170 | static const struct udevice_id riscv_cpu_ids[] = { | |
171 | { .compatible = "riscv" }, | |
172 | { } | |
173 | }; | |
174 | ||
175 | U_BOOT_DRIVER(riscv_cpu) = { | |
176 | .name = "riscv_cpu", | |
177 | .id = UCLASS_CPU, | |
178 | .of_match = riscv_cpu_ids, | |
179 | .bind = riscv_cpu_bind, | |
62771862 | 180 | .probe = riscv_cpu_probe, |
833508c0 BM |
181 | .ops = &riscv_cpu_ops, |
182 | .flags = DM_FLAG_PRE_RELOC, | |
183 | }; |