[thirdparty/u-boot.git] / drivers / ddr / fsl / ddr1_dimm_params.c

// SPDX-License-Identifier: GPL-2.0
/*
 * Copyright 2008 Freescale Semiconductor, Inc.
 */

#include <common.h>
#include <fsl_ddr_sdram.h>
#include <log.h>
#include <asm/bitops.h>

#include <fsl_ddr.h>

/*
 * Calculate the Density of each Physical Rank.
 * Returned size is in bytes.
 *
 * Study these table from Byte 31 of JEDEC SPD Spec.
 *
 *		DDR I	DDR II
 *	Bit	Size	Size
 *	---	-----	------
 *	7 high	512MB	512MB
 *	6	256MB	256MB
 *	5	128MB	128MB
 *	4	 64MB	 16GB
 *	3	 32MB	  8GB
 *	2	 16MB	  4GB
 *	1	  2GB	  2GB
 *	0 low	  1GB	  1GB
 *
 * Reorder Table to be linear by stripping the bottom
 * 2 or 5 bits off and shifting them up to the top.
 */

static unsigned long long
compute_ranksize(unsigned int mem_type, unsigned char row_dens)
{
	unsigned long long bsize;

	/* Bottom 2 bits up to the top. */
	bsize = ((row_dens >> 2) | ((row_dens & 3) << 6));
	bsize <<= 24ULL;
	debug("DDR: DDR I rank density = 0x%16llx\n", bsize);

	return bsize;
}

/*
 * Convert a two-nibble BCD value into a cycle time.
 * While the spec calls for nano-seconds, picos are returned.
 *
 * This implements the tables for bytes 9, 23 and 25 for both
 * DDR I and II.  No allowance for distinguishing the invalid
 * fields absent for DDR I yet present in DDR II is made.
 * (That is, cycle times of .25, .33, .66 and .75 ns are
 * allowed for both DDR II and I.)
 */
static unsigned int
convert_bcd_tenths_to_cycle_time_ps(unsigned int spd_val)
{
	/* Table look up the lower nibble, allow DDR I & II. */
	unsigned int tenths_ps[16] = {
		0,
		100,
		200,
		300,
		400,
		500,
		600,
		700,
		800,
		900,
		250,	/* This and the next 3 entries valid ... */
		330,	/* ...  only for tCK calculations. */
		660,
		750,
		0,	/* undefined */
		0	/* undefined */
	};

	unsigned int whole_ns = (spd_val & 0xF0) >> 4;
	unsigned int tenth_ns = spd_val & 0x0F;
	unsigned int ps = whole_ns * 1000 + tenths_ps[tenth_ns];

	return ps;
}

static unsigned int
convert_bcd_hundredths_to_cycle_time_ps(unsigned int spd_val)
{
	unsigned int tenth_ns = (spd_val & 0xF0) >> 4;
	unsigned int hundredth_ns = spd_val & 0x0F;
	unsigned int ps = tenth_ns * 100 + hundredth_ns * 10;

	return ps;
}

static unsigned int byte40_table_ps[8] = {
	0,
	250,
	330,
	500,
	660,
	750,
	0,	/* supposed to be RFC, but not sure what that means */
	0	/* Undefined */
};

static unsigned int
compute_trfc_ps_from_spd(unsigned char trctrfc_ext, unsigned char trfc)
{
	return ((trctrfc_ext & 0x1) * 256 + trfc) * 1000
		+ byte40_table_ps[(trctrfc_ext >> 1) & 0x7];
}

static unsigned int
compute_trc_ps_from_spd(unsigned char trctrfc_ext, unsigned char trc)
{
	return trc * 1000 + byte40_table_ps[(trctrfc_ext >> 4) & 0x7];
}

/*
 * tCKmax from DDR I SPD Byte 43
 *
 * Bits 7:2 == whole ns
 * Bits 1:0 == quarter ns
 *    00    == 0.00 ns
 *    01    == 0.25 ns
 *    10    == 0.50 ns
 *    11    == 0.75 ns
 *
 * Returns picoseconds.
 */
static unsigned int
compute_tckmax_from_spd_ps(unsigned int byte43)
{
	return (byte43 >> 2) * 1000 + (byte43 & 0x3) * 250;
}

/*
 * Determine Refresh Rate.  Ignore self refresh bit on DDR I.
 * Table from SPD Spec, Byte 12, converted to picoseconds and
 * filled in with "default" normal values.
 */
static unsigned int
determine_refresh_rate_ps(const unsigned int spd_refresh)
{
	unsigned int refresh_time_ps[8] = {
		15625000,	/* 0 Normal    1.00x */
		3900000,	/* 1 Reduced    .25x */
		7800000,	/* 2 Extended   .50x */
		31300000,	/* 3 Extended  2.00x */
		62500000,	/* 4 Extended  4.00x */
		125000000,	/* 5 Extended  8.00x */
		15625000,	/* 6 Normal    1.00x  filler */
		15625000,	/* 7 Normal    1.00x  filler */
	};

	return refresh_time_ps[spd_refresh & 0x7];
}

/*
 * The purpose of this function is to compute a suitable
 * CAS latency given the DRAM clock period.  The SPD only
 * defines at most 3 CAS latencies.  Typically the slower in
 * frequency the DIMM runs at, the shorter its CAS latency can be.
 * If the DIMM is operating at a sufficiently low frequency,
 * it may be able to run at a CAS latency shorter than the
 * shortest SPD-defined CAS latency.
 *
 * If a CAS latency is not found, 0 is returned.
 *
 * Do this by finding in the standard speed bin table the longest
 * tCKmin that doesn't exceed the value of mclk_ps (tCK).
 *
 * An assumption made is that the SDRAM device allows the
 * CL to be programmed for a value that is lower than those
 * advertised by the SPD.  This is not always the case,
 * as those modes not defined in the SPD are optional.
 *
 * CAS latency de-rating based upon values JEDEC Standard No. 79-E
 * Table 11.
 *
 * ordinal 2, ddr1_speed_bins[1] contains tCK for CL=2
 */
				  /*   CL2.0 CL2.5 CL3.0  */
unsigned short ddr1_speed_bins[] = {0, 7500, 6000, 5000 };

unsigned int
compute_derated_DDR1_CAS_latency(unsigned int mclk_ps)
{
	const unsigned int num_speed_bins = ARRAY_SIZE(ddr1_speed_bins);
	unsigned int lowest_tCKmin_found = 0;
	unsigned int lowest_tCKmin_CL = 0;
	unsigned int i;

	debug("mclk_ps = %u\n", mclk_ps);

	for (i = 0; i < num_speed_bins; i++) {
		unsigned int x = ddr1_speed_bins[i];
		debug("i=%u, x = %u, lowest_tCKmin_found = %u\n",
		      i, x, lowest_tCKmin_found);
		if (x && lowest_tCKmin_found <= x && x <= mclk_ps) {
			lowest_tCKmin_found = x;
			lowest_tCKmin_CL = i + 1;
		}
	}

	debug("lowest_tCKmin_CL = %u\n", lowest_tCKmin_CL);

	return lowest_tCKmin_CL;
}

/*
 * ddr_compute_dimm_parameters for DDR1 SPD
 *
 * Compute DIMM parameters based upon the SPD information in spd.
 * Writes the results to the dimm_params_t structure pointed by pdimm.
 *
 * FIXME: use #define for the retvals
 */
unsigned int ddr_compute_dimm_parameters(const unsigned int ctrl_num,
					 const ddr1_spd_eeprom_t *spd,
					 dimm_params_t *pdimm,
					 unsigned int dimm_number)
{
	unsigned int retval;

	if (spd->mem_type) {
		if (spd->mem_type != SPD_MEMTYPE_DDR) {
			printf("DIMM %u: is not a DDR1 SPD.\n", dimm_number);
			return 1;
		}
	} else {
		memset(pdimm, 0, sizeof(dimm_params_t));
		return 1;
	}

	retval = ddr1_spd_check(spd);
	if (retval) {
		printf("DIMM %u: failed checksum\n", dimm_number);
		return 2;
	}

	/*
	 * The part name in ASCII in the SPD EEPROM is not null terminated.
	 * Guarantee null termination here by presetting all bytes to 0
	 * and copying the part name in ASCII from the SPD onto it
	 */
	memset(pdimm->mpart, 0, sizeof(pdimm->mpart));
	memcpy(pdimm->mpart, spd->mpart, sizeof(pdimm->mpart) - 1);

	/* DIMM organization parameters */
	pdimm->n_ranks = spd->nrows;
	pdimm->rank_density = compute_ranksize(spd->mem_type, spd->bank_dens);
	pdimm->capacity = pdimm->n_ranks * pdimm->rank_density;
	pdimm->data_width = spd->dataw_lsb;
	pdimm->primary_sdram_width = spd->primw;
	pdimm->ec_sdram_width = spd->ecw;

	/*
	 * FIXME: Need to determine registered_dimm status.
	 *     1 == register buffered
	 *     0 == unbuffered
	 */
	pdimm->registered_dimm = 0;	/* unbuffered */

	/* SDRAM device parameters */
	pdimm->n_row_addr = spd->nrow_addr;
	pdimm->n_col_addr = spd->ncol_addr;
	pdimm->n_banks_per_sdram_device = spd->nbanks;
	pdimm->edc_config = spd->config;
	pdimm->burst_lengths_bitmask = spd->burstl;

	/*
	 * Calculate the Maximum Data Rate based on the Minimum Cycle time.
	 * The SPD clk_cycle field (tCKmin) is measured in tenths of
	 * nanoseconds and represented as BCD.
	 */
	pdimm->tckmin_x_ps
		= convert_bcd_tenths_to_cycle_time_ps(spd->clk_cycle);
	pdimm->tckmin_x_minus_1_ps
		= convert_bcd_tenths_to_cycle_time_ps(spd->clk_cycle2);
	pdimm->tckmin_x_minus_2_ps
		= convert_bcd_tenths_to_cycle_time_ps(spd->clk_cycle3);

	pdimm->tckmax_ps = compute_tckmax_from_spd_ps(spd->tckmax);

	/*
	 * Compute CAS latencies defined by SPD
	 * The SPD caslat_x should have at least 1 and at most 3 bits set.
	 *
	 * If cas_lat after masking is 0, the __ilog2 function returns
	 * 255 into the variable.   This behavior is abused once.
	 */
	pdimm->caslat_x  = __ilog2(spd->cas_lat);
	pdimm->caslat_x_minus_1 = __ilog2(spd->cas_lat
					  & ~(1 << pdimm->caslat_x));
	pdimm->caslat_x_minus_2 = __ilog2(spd->cas_lat
					  & ~(1 << pdimm->caslat_x)
					  & ~(1 << pdimm->caslat_x_minus_1));

	/* Compute CAS latencies below that defined by SPD */
	pdimm->caslat_lowest_derated = compute_derated_DDR1_CAS_latency(
					get_memory_clk_period_ps(ctrl_num));

	/* Compute timing parameters */
	pdimm->trcd_ps = spd->trcd * 250;
	pdimm->trp_ps = spd->trp * 250;
	pdimm->tras_ps = spd->tras * 1000;

	pdimm->twr_ps = mclk_to_picos(ctrl_num, 3);
	pdimm->twtr_ps = mclk_to_picos(ctrl_num, 1);
	pdimm->trfc_ps = compute_trfc_ps_from_spd(0, spd->trfc);

	pdimm->trrd_ps = spd->trrd * 250;
	pdimm->trc_ps = compute_trc_ps_from_spd(0, spd->trc);

	pdimm->refresh_rate_ps = determine_refresh_rate_ps(spd->refresh);

	pdimm->tis_ps = convert_bcd_hundredths_to_cycle_time_ps(spd->ca_setup);
	pdimm->tih_ps = convert_bcd_hundredths_to_cycle_time_ps(spd->ca_hold);
	pdimm->tds_ps
		= convert_bcd_hundredths_to_cycle_time_ps(spd->data_setup);
	pdimm->tdh_ps
		= convert_bcd_hundredths_to_cycle_time_ps(spd->data_hold);

	pdimm->trtp_ps = mclk_to_picos(ctrl_num, 2);	/* By the book. */
	pdimm->tdqsq_max_ps = spd->tdqsq * 10;
	pdimm->tqhs_ps = spd->tqhs * 10;

	return 0;
}
Commit	Line	Data
83d290c5	1	// SPDX-License-Identifier: GPL-2.0
05c05a23 KG	2	/*
05c05a23 KG	3	* Copyright 2008 Freescale Semiconductor, Inc.
05c05a23 KG	4	*/
05c05a23 KG	5
d678a59d	6	#include <common.h>
5614e71b	7	#include <fsl_ddr_sdram.h>
f7ae49fc	8	#include <log.h>
cd93d625	9	#include <asm/bitops.h>
05c05a23	10
5614e71b	11	#include <fsl_ddr.h>
05c05a23 KG	12
	13	/*
	14	* Calculate the Density of each Physical Rank.
	15	* Returned size is in bytes.
	16	*
	17	* Study these table from Byte 31 of JEDEC SPD Spec.
	18	*
	19	* DDR I DDR II
	20	* Bit Size Size
	21	* --- ----- ------
	22	* 7 high 512MB 512MB
	23	* 6 256MB 256MB
	24	* 5 128MB 128MB
	25	* 4 64MB 16GB
	26	* 3 32MB 8GB
	27	* 2 16MB 4GB
	28	* 1 2GB 2GB
	29	* 0 low 1GB 1GB
	30	*
	31	* Reorder Table to be linear by stripping the bottom
	32	* 2 or 5 bits off and shifting them up to the top.
	33	*/
	34
e7563aff	35	static unsigned long long
05c05a23 KG	36	compute_ranksize(unsigned int mem_type, unsigned char row_dens)
05c05a23 KG	37	{
e7563aff	38	unsigned long long bsize;
05c05a23 KG	39
	40	/* Bottom 2 bits up to the top. */
	41	bsize = ((row_dens >> 2) \| ((row_dens & 3) << 6));
	42	bsize <<= 24ULL;
cd84b1fa	43	debug("DDR: DDR I rank density = 0x%16llx\n", bsize);
05c05a23 KG	44
	45	return bsize;
	46	}
	47
	48	/*
	49	* Convert a two-nibble BCD value into a cycle time.
	50	* While the spec calls for nano-seconds, picos are returned.
	51	*
	52	* This implements the tables for bytes 9, 23 and 25 for both
	53	* DDR I and II. No allowance for distinguishing the invalid
	54	* fields absent for DDR I yet present in DDR II is made.
	55	* (That is, cycle times of .25, .33, .66 and .75 ns are
	56	* allowed for both DDR II and I.)
	57	*/
	58	static unsigned int
	59	convert_bcd_tenths_to_cycle_time_ps(unsigned int spd_val)
	60	{
	61	/* Table look up the lower nibble, allow DDR I & II. */
	62	unsigned int tenths_ps[16] = {
	63	0,
	64	100,
	65	200,
	66	300,
	67	400,
	68	500,
	69	600,
	70	700,
	71	800,
	72	900,
	73	250, /* This and the next 3 entries valid ... */
	74	330, /* ... only for tCK calculations. */
	75	660,
	76	750,
	77	0, /* undefined */
	78	0 /* undefined */
	79	};
	80
	81	unsigned int whole_ns = (spd_val & 0xF0) >> 4;
	82	unsigned int tenth_ns = spd_val & 0x0F;
	83	unsigned int ps = whole_ns * 1000 + tenths_ps[tenth_ns];
	84
	85	return ps;
	86	}
	87
	88	static unsigned int
	89	convert_bcd_hundredths_to_cycle_time_ps(unsigned int spd_val)
	90	{
	91	unsigned int tenth_ns = (spd_val & 0xF0) >> 4;
	92	unsigned int hundredth_ns = spd_val & 0x0F;
	93	unsigned int ps = tenth_ns * 100 + hundredth_ns * 10;
	94
	95	return ps;
	96	}
	97
	98	static unsigned int byte40_table_ps[8] = {
	99	0,
	100	250,
	101	330,
	102	500,
	103	660,
	104	750,
	105	0, /* supposed to be RFC, but not sure what that means */
	106	0 /* Undefined */
	107	};
108
109	static unsigned int
110	compute_trfc_ps_from_spd(unsigned char trctrfc_ext, unsigned char trfc)
111	{
a4ca3799	112	return ((trctrfc_ext & 0x1) * 256 + trfc) * 1000
05c05a23	113	+ byte40_table_ps[(trctrfc_ext >> 1) & 0x7];
05c05a23 KG	114	}
	115
	116	static unsigned int
	117	compute_trc_ps_from_spd(unsigned char trctrfc_ext, unsigned char trc)
	118	{
a4ca3799	119	return trc * 1000 + byte40_table_ps[(trctrfc_ext >> 4) & 0x7];
05c05a23 KG	120	}
	121
	122	/*
	123	* tCKmax from DDR I SPD Byte 43
	124	*
	125	* Bits 7:2 == whole ns
	126	* Bits 1:0 == quarter ns
	127	* 00 == 0.00 ns
	128	* 01 == 0.25 ns
	129	* 10 == 0.50 ns
	130	* 11 == 0.75 ns
	131	*
	132	* Returns picoseconds.
	133	*/
	134	static unsigned int
	135	compute_tckmax_from_spd_ps(unsigned int byte43)
	136	{
	137	return (byte43 >> 2) * 1000 + (byte43 & 0x3) * 250;
	138	}
	139
	140	/*
	141	* Determine Refresh Rate. Ignore self refresh bit on DDR I.
	142	* Table from SPD Spec, Byte 12, converted to picoseconds and
	143	* filled in with "default" normal values.
	144	*/
	145	static unsigned int
	146	determine_refresh_rate_ps(const unsigned int spd_refresh)
	147	{
	148	unsigned int refresh_time_ps[8] = {
	149	15625000, /* 0 Normal 1.00x */
	150	3900000, /* 1 Reduced .25x */
	151	7800000, /* 2 Extended .50x */
	152	31300000, /* 3 Extended 2.00x */
	153	62500000, /* 4 Extended 4.00x */
	154	125000000, /* 5 Extended 8.00x */
	155	15625000, /* 6 Normal 1.00x filler */
	156	15625000, /* 7 Normal 1.00x filler */
	157	};
	158
	159	return refresh_time_ps[spd_refresh & 0x7];
	160	}
	161
	162	/*
	163	* The purpose of this function is to compute a suitable
	164	* CAS latency given the DRAM clock period. The SPD only
	165	* defines at most 3 CAS latencies. Typically the slower in
	166	* frequency the DIMM runs at, the shorter its CAS latency can be.
	167	* If the DIMM is operating at a sufficiently low frequency,
	168	* it may be able to run at a CAS latency shorter than the
	169	* shortest SPD-defined CAS latency.
	170	*
	171	* If a CAS latency is not found, 0 is returned.
	172	*
	173	* Do this by finding in the standard speed bin table the longest
	174	* tCKmin that doesn't exceed the value of mclk_ps (tCK).
	175	*
	176	* An assumption made is that the SDRAM device allows the
	177	* CL to be programmed for a value that is lower than those
	178	* advertised by the SPD. This is not always the case,
	179	* as those modes not defined in the SPD are optional.
	180	*
	181	* CAS latency de-rating based upon values JEDEC Standard No. 79-E
	182	* Table 11.
	183	*
184	* ordinal 2, ddr1_speed_bins[1] contains tCK for CL=2
185	*/
186	/* CL2.0 CL2.5 CL3.0 */
187	unsigned short ddr1_speed_bins[] = {0, 7500, 6000, 5000 };
188
189	unsigned int
190	compute_derated_DDR1_CAS_latency(unsigned int mclk_ps)
191	{
192	const unsigned int num_speed_bins = ARRAY_SIZE(ddr1_speed_bins);
193	unsigned int lowest_tCKmin_found = 0;
194	unsigned int lowest_tCKmin_CL = 0;
195	unsigned int i;
196
197	debug("mclk_ps = %u\n", mclk_ps);
198
199	for (i = 0; i < num_speed_bins; i++) {
200	unsigned int x = ddr1_speed_bins[i];
201	debug("i=%u, x = %u, lowest_tCKmin_found = %u\n",
202	i, x, lowest_tCKmin_found);
203	if (x && lowest_tCKmin_found <= x && x <= mclk_ps) {
204	lowest_tCKmin_found = x;
205	lowest_tCKmin_CL = i + 1;
206	}
207	}
208
209	debug("lowest_tCKmin_CL = %u\n", lowest_tCKmin_CL);
210
211	return lowest_tCKmin_CL;
212	}
213
214	/*
215	* ddr_compute_dimm_parameters for DDR1 SPD
216	*
217	* Compute DIMM parameters based upon the SPD information in spd.
218	* Writes the results to the dimm_params_t structure pointed by pdimm.
219	*
220	* FIXME: use #define for the retvals
221	*/
03e664d8 YS	222	unsigned int ddr_compute_dimm_parameters(const unsigned int ctrl_num,
	223	const ddr1_spd_eeprom_t *spd,
	224	dimm_params_t *pdimm,
	225	unsigned int dimm_number)
05c05a23 KG	226	{
	227	unsigned int retval;
	228
	229	if (spd->mem_type) {
	230	if (spd->mem_type != SPD_MEMTYPE_DDR) {
	231	printf("DIMM %u: is not a DDR1 SPD.\n", dimm_number);
	232	return 1;
	233	}
	234	} else {
	235	memset(pdimm, 0, sizeof(dimm_params_t));
	236	return 1;
	237	}
	238
	239	retval = ddr1_spd_check(spd);
	240	if (retval) {
	241	printf("DIMM %u: failed checksum\n", dimm_number);
	242	return 2;
	243	}
	244
	245	/*
	246	* The part name in ASCII in the SPD EEPROM is not null terminated.
	247	* Guarantee null termination here by presetting all bytes to 0
	248	* and copying the part name in ASCII from the SPD onto it
	249	*/
	250	memset(pdimm->mpart, 0, sizeof(pdimm->mpart));
	251	memcpy(pdimm->mpart, spd->mpart, sizeof(pdimm->mpart) - 1);
	252
	253	/* DIMM organization parameters */
	254	pdimm->n_ranks = spd->nrows;
	255	pdimm->rank_density = compute_ranksize(spd->mem_type, spd->bank_dens);
	256	pdimm->capacity = pdimm->n_ranks * pdimm->rank_density;
	257	pdimm->data_width = spd->dataw_lsb;
	258	pdimm->primary_sdram_width = spd->primw;
	259	pdimm->ec_sdram_width = spd->ecw;
	260
	261	/*
	262	* FIXME: Need to determine registered_dimm status.
	263	* 1 == register buffered
	264	* 0 == unbuffered
	265	*/
	266	pdimm->registered_dimm = 0; /* unbuffered */
	267
	268	/* SDRAM device parameters */
	269	pdimm->n_row_addr = spd->nrow_addr;
	270	pdimm->n_col_addr = spd->ncol_addr;
	271	pdimm->n_banks_per_sdram_device = spd->nbanks;
	272	pdimm->edc_config = spd->config;
	273	pdimm->burst_lengths_bitmask = spd->burstl;
05c05a23 KG	274
	275	/*
	276	* Calculate the Maximum Data Rate based on the Minimum Cycle time.
	277	* The SPD clk_cycle field (tCKmin) is measured in tenths of
	278	* nanoseconds and represented as BCD.
	279	*/
0dd38a35	280	pdimm->tckmin_x_ps
05c05a23	281	= convert_bcd_tenths_to_cycle_time_ps(spd->clk_cycle);
0dd38a35	282	pdimm->tckmin_x_minus_1_ps
05c05a23	283	= convert_bcd_tenths_to_cycle_time_ps(spd->clk_cycle2);
0dd38a35	284	pdimm->tckmin_x_minus_2_ps
05c05a23 KG	285	= convert_bcd_tenths_to_cycle_time_ps(spd->clk_cycle3);
05c05a23 KG	286
0dd38a35	287	pdimm->tckmax_ps = compute_tckmax_from_spd_ps(spd->tckmax);
05c05a23 KG	288
	289	/*
	290	* Compute CAS latencies defined by SPD
0dd38a35	291	* The SPD caslat_x should have at least 1 and at most 3 bits set.
05c05a23 KG	292	*
	293	* If cas_lat after masking is 0, the __ilog2 function returns
	294	* 255 into the variable. This behavior is abused once.
	295	*/
0dd38a35 PJ	296	pdimm->caslat_x = __ilog2(spd->cas_lat);
	297	pdimm->caslat_x_minus_1 = __ilog2(spd->cas_lat
	298	& ~(1 << pdimm->caslat_x));
	299	pdimm->caslat_x_minus_2 = __ilog2(spd->cas_lat
	300	& ~(1 << pdimm->caslat_x)
	301	& ~(1 << pdimm->caslat_x_minus_1));
05c05a23 KG	302
05c05a23 KG	303	/* Compute CAS latencies below that defined by SPD */
03e664d8 YS	304	pdimm->caslat_lowest_derated = compute_derated_DDR1_CAS_latency(
03e664d8 YS	305	get_memory_clk_period_ps(ctrl_num));
05c05a23 KG	306
05c05a23 KG	307	/* Compute timing parameters */
0dd38a35 PJ	308	pdimm->trcd_ps = spd->trcd * 250;
	309	pdimm->trp_ps = spd->trp * 250;
	310	pdimm->tras_ps = spd->tras * 1000;
05c05a23	311
03e664d8 YS	312	pdimm->twr_ps = mclk_to_picos(ctrl_num, 3);
03e664d8 YS	313	pdimm->twtr_ps = mclk_to_picos(ctrl_num, 1);
0dd38a35	314	pdimm->trfc_ps = compute_trfc_ps_from_spd(0, spd->trfc);
05c05a23	315
0dd38a35 PJ	316	pdimm->trrd_ps = spd->trrd * 250;
0dd38a35 PJ	317	pdimm->trc_ps = compute_trc_ps_from_spd(0, spd->trc);
05c05a23 KG	318
	319	pdimm->refresh_rate_ps = determine_refresh_rate_ps(spd->refresh);
	320
0dd38a35 PJ	321	pdimm->tis_ps = convert_bcd_hundredths_to_cycle_time_ps(spd->ca_setup);
	322	pdimm->tih_ps = convert_bcd_hundredths_to_cycle_time_ps(spd->ca_hold);
	323	pdimm->tds_ps
05c05a23	324	= convert_bcd_hundredths_to_cycle_time_ps(spd->data_setup);
0dd38a35	325	pdimm->tdh_ps
05c05a23 KG	326	= convert_bcd_hundredths_to_cycle_time_ps(spd->data_hold);
05c05a23 KG	327
03e664d8	328	pdimm->trtp_ps = mclk_to_picos(ctrl_num, 2); /* By the book. */
0dd38a35 PJ	329	pdimm->tdqsq_max_ps = spd->tdqsq * 10;
0dd38a35 PJ	330	pdimm->tqhs_ps = spd->tqhs * 10;
05c05a23 KG	331
	332	return 0;
	333	}