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* Patches by Xianghua Xiao, 15 Oct 2003:
[people/ms/u-boot.git] / drivers / eepro100.c
CommitLineData
1df49e27
WD		 1/*
2 * (C) Copyright 2002
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24#include <common.h>
25#include <malloc.h>
26#include <net.h>
27#include <asm/io.h>
28#include <pci.h>
29
30#undef DEBUG
31
32#if (CONFIG_COMMANDS & CFG_CMD_NET) && defined(CONFIG_NET_MULTI) && \
33 defined(CONFIG_EEPRO100)
34
35 /* Ethernet chip registers.
36 */
37#define SCBStatus 0 /* Rx/Command Unit Status *Word* */
38#define SCBIntAckByte 1 /* Rx/Command Unit STAT/ACK byte */
39#define SCBCmd 2 /* Rx/Command Unit Command *Word* */
40#define SCBIntrCtlByte 3 /* Rx/Command Unit Intr.Control Byte */
41#define SCBPointer 4 /* General purpose pointer. */
42#define SCBPort 8 /* Misc. commands and operands. */
43#define SCBflash 12 /* Flash memory control. */
44#define SCBeeprom 14 /* EEPROM memory control. */
45#define SCBCtrlMDI 16 /* MDI interface control. */
46#define SCBEarlyRx 20 /* Early receive byte count. */
47#define SCBGenControl 28 /* 82559 General Control Register */
48#define SCBGenStatus 29 /* 82559 General Status register */
49
50 /* 82559 SCB status word defnitions
51 */
52#define SCB_STATUS_CX 0x8000 /* CU finished command (transmit) */
53#define SCB_STATUS_FR 0x4000 /* frame received */
54#define SCB_STATUS_CNA 0x2000 /* CU left active state */
55#define SCB_STATUS_RNR 0x1000 /* receiver left ready state */
56#define SCB_STATUS_MDI 0x0800 /* MDI read/write cycle done */
57#define SCB_STATUS_SWI 0x0400 /* software generated interrupt */
58#define SCB_STATUS_FCP 0x0100 /* flow control pause interrupt */
59
60#define SCB_INTACK_MASK 0xFD00 /* all the above */
61
62#define SCB_INTACK_TX (SCB_STATUS_CX | SCB_STATUS_CNA)
63#define SCB_INTACK_RX (SCB_STATUS_FR | SCB_STATUS_RNR)
64
65 /* System control block commands
66 */
67/* CU Commands */
68#define CU_NOP 0x0000
69#define CU_START 0x0010
70#define CU_RESUME 0x0020
71#define CU_STATSADDR 0x0040 /* Load Dump Statistics ctrs addr */
72#define CU_SHOWSTATS 0x0050 /* Dump statistics counters. */
73#define CU_ADDR_LOAD 0x0060 /* Base address to add to CU commands */
74#define CU_DUMPSTATS 0x0070 /* Dump then reset stats counters. */
75
76/* RUC Commands */
77#define RUC_NOP 0x0000
78#define RUC_START 0x0001
79#define RUC_RESUME 0x0002
80#define RUC_ABORT 0x0004
81#define RUC_ADDR_LOAD 0x0006 /* (seems not to clear on acceptance) */
82#define RUC_RESUMENR 0x0007
83
84#define CU_CMD_MASK 0x00f0
85#define RU_CMD_MASK 0x0007
86
87#define SCB_M 0x0100 /* 0 = enable interrupt, 1 = disable */
88#define SCB_SWI 0x0200 /* 1 - cause device to interrupt */
89
90#define CU_STATUS_MASK 0x00C0
91#define RU_STATUS_MASK 0x003C
92
93#define RU_STATUS_IDLE (0<<2)
94#define RU_STATUS_SUS (1<<2)
95#define RU_STATUS_NORES (2<<2)
96#define RU_STATUS_READY (4<<2)
97#define RU_STATUS_NO_RBDS_SUS ((1<<2)|(8<<2))
98#define RU_STATUS_NO_RBDS_NORES ((2<<2)|(8<<2))
99#define RU_STATUS_NO_RBDS_READY ((4<<2)|(8<<2))
100
101 /* 82559 Port interface commands.
102 */
103#define I82559_RESET 0x00000000 /* Software reset */
104#define I82559_SELFTEST 0x00000001 /* 82559 Selftest command */
105#define I82559_SELECTIVE_RESET 0x00000002
106#define I82559_DUMP 0x00000003
107#define I82559_DUMP_WAKEUP 0x00000007
108
109 /* 82559 Eeprom interface.
110 */
111#define EE_SHIFT_CLK 0x01 /* EEPROM shift clock. */
112#define EE_CS 0x02 /* EEPROM chip select. */
113#define EE_DATA_WRITE 0x04 /* EEPROM chip data in. */
114#define EE_WRITE_0 0x01
115#define EE_WRITE_1 0x05
116#define EE_DATA_READ 0x08 /* EEPROM chip data out. */
117#define EE_ENB (0x4800 | EE_CS)
118#define EE_CMD_BITS 3
119#define EE_DATA_BITS 16
120
121 /* The EEPROM commands include the alway-set leading bit.
122 */
123#define EE_EWENB_CMD (4 << addr_len)
124#define EE_WRITE_CMD (5 << addr_len)
125#define EE_READ_CMD (6 << addr_len)
126#define EE_ERASE_CMD (7 << addr_len)
127
128 /* Receive frame descriptors.
129 */
130struct RxFD {
131 volatile u16 status;
132 volatile u16 control;
133 volatile u32 link; /* struct RxFD * */
134 volatile u32 rx_buf_addr; /* void * */
135 volatile u32 count;
136
137 volatile u8 data[PKTSIZE_ALIGN];
138};
139
140#define RFD_STATUS_C 0x8000 /* completion of received frame */
141#define RFD_STATUS_OK 0x2000 /* frame received with no errors */
142
143#define RFD_CONTROL_EL 0x8000 /* 1=last RFD in RFA */
144#define RFD_CONTROL_S 0x4000 /* 1=suspend RU after receiving frame */
145#define RFD_CONTROL_H 0x0010 /* 1=RFD is a header RFD */
146#define RFD_CONTROL_SF 0x0008 /* 0=simplified, 1=flexible mode */
147
148#define RFD_COUNT_MASK 0x3fff
149#define RFD_COUNT_F 0x4000
150#define RFD_COUNT_EOF 0x8000
151
152#define RFD_RX_CRC 0x0800 /* crc error */
153#define RFD_RX_ALIGNMENT 0x0400 /* alignment error */
154#define RFD_RX_RESOURCE 0x0200 /* out of space, no resources */
155#define RFD_RX_DMA_OVER 0x0100 /* DMA overrun */
156#define RFD_RX_SHORT 0x0080 /* short frame error */
157#define RFD_RX_LENGTH 0x0020
158#define RFD_RX_ERROR 0x0010 /* receive error */
159#define RFD_RX_NO_ADR_MATCH 0x0004 /* no address match */
160#define RFD_RX_IA_MATCH 0x0002 /* individual address does not match */
161#define RFD_RX_TCO 0x0001 /* TCO indication */
162
163 /* Transmit frame descriptors
164 */
165struct TxFD { /* Transmit frame descriptor set. */
166 volatile u16 status;
167 volatile u16 command;
168 volatile u32 link; /* void * */
169 volatile u32 tx_desc_addr; /* Always points to the tx_buf_addr element. */
170 volatile s32 count;
171
172 volatile u32 tx_buf_addr0; /* void *, frame to be transmitted. */
173 volatile s32 tx_buf_size0; /* Length of Tx frame. */
174 volatile u32 tx_buf_addr1; /* void *, frame to be transmitted. */
175 volatile s32 tx_buf_size1; /* Length of Tx frame. */
176};
177
178#define TxCB_CMD_TRANSMIT 0x0004 /* transmit command */
179#define TxCB_CMD_SF 0x0008 /* 0=simplified, 1=flexible mode */
180#define TxCB_CMD_NC 0x0010 /* 0=CRC insert by controller */
181#define TxCB_CMD_I 0x2000 /* generate interrupt on completion */
182#define TxCB_CMD_S 0x4000 /* suspend on completion */
183#define TxCB_CMD_EL 0x8000 /* last command block in CBL */
184
185#define TxCB_COUNT_MASK 0x3fff
186#define TxCB_COUNT_EOF 0x8000
187
188 /* The Speedo3 Rx and Tx frame/buffer descriptors.
189 */
190struct descriptor { /* A generic descriptor. */
191 volatile u16 status;
192 volatile u16 command;
193 volatile u32 link; /* struct descriptor * */
194
195 unsigned char params[0];
196};
197
198#define CFG_CMD_EL 0x8000
199#define CFG_CMD_SUSPEND 0x4000
200#define CFG_CMD_INT 0x2000
201#define CFG_CMD_IAS 0x0001 /* individual address setup */
202#define CFG_CMD_CONFIGURE 0x0002 /* configure */
203
204#define CFG_STATUS_C 0x8000
205#define CFG_STATUS_OK 0x2000
206
207 /* Misc.
208 */
209#define NUM_RX_DESC PKTBUFSRX
210#define NUM_TX_DESC 1 /* Number of TX descriptors */
211
212#define TOUT_LOOP 1000000
213
214#define ETH_ALEN 6
215
216static struct RxFD rx_ring[NUM_RX_DESC]; /* RX descriptor ring */
217static struct TxFD tx_ring[NUM_TX_DESC]; /* TX descriptor ring */
218static int rx_next; /* RX descriptor ring pointer */
219static int tx_next; /* TX descriptor ring pointer */
220static int tx_threshold;
221
222/*
223 * The parameters for a CmdConfigure operation.
224 * There are so many options that it would be difficult to document
225 * each bit. We mostly use the default or recommended settings.
226 */
227static const char i82557_config_cmd[] = {
228 22, 0x08, 0, 0, 0, 0, 0x32, 0x03, 1, /* 1=Use MII 0=Use AUI */
229 0, 0x2E, 0, 0x60, 0,
230 0xf2, 0x48, 0, 0x40, 0xf2, 0x80, /* 0x40=Force full-duplex */
231 0x3f, 0x05,
232};
233static const char i82558_config_cmd[] = {
234 22, 0x08, 0, 1, 0, 0, 0x22, 0x03, 1, /* 1=Use MII 0=Use AUI */
235 0, 0x2E, 0, 0x60, 0x08, 0x88,
236 0x68, 0, 0x40, 0xf2, 0x84, /* Disable FC */
237 0x31, 0x05,
238};
239
240static void init_rx_ring (struct eth_device *dev);
241static void purge_tx_ring (struct eth_device *dev);
242
243static void read_hw_addr (struct eth_device *dev, bd_t * bis);
244
245static int eepro100_init (struct eth_device *dev, bd_t * bis);
246static int eepro100_send (struct eth_device *dev, volatile void *packet,
247 int length);
248static int eepro100_recv (struct eth_device *dev);
249static void eepro100_halt (struct eth_device *dev);
250
42d1f039
WD		 251#if defined(CONFIG_E500)
252#define bus_to_phys(a) (a)
253#define phys_to_bus(a) (a)
254#else
1df49e27
WD		 255#define bus_to_phys(a) pci_mem_to_phys((pci_dev_t)dev->priv, a)
256#define phys_to_bus(a) pci_phys_to_mem((pci_dev_t)dev->priv, a)
42d1f039 257#endif
1df49e27
WD		 258
259static inline int INW (struct eth_device *dev, u_long addr)
260{
261 return le16_to_cpu (*(volatile u16 *) (addr + dev->iobase));
262}
263
264static inline void OUTW (struct eth_device *dev, int command, u_long addr)
265{
266 *(volatile u16 *) ((addr + dev->iobase)) = cpu_to_le16 (command);
267}
268
269static inline void OUTL (struct eth_device *dev, int command, u_long addr)
270{
271 *(volatile u32 *) ((addr + dev->iobase)) = cpu_to_le32 (command);
272}
273
274 /* Wait for the chip get the command.
275 */
276static int wait_for_eepro100 (struct eth_device *dev)
277{
278 int i;
279
280 for (i = 0; INW (dev, SCBCmd) & (CU_CMD_MASK | RU_CMD_MASK); i++) {
281 if (i >= TOUT_LOOP) {
282 return 0;
283 }
284 }
285
286 return 1;
287}
288
289static struct pci_device_id supported[] = {
290 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82557},
291 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82559},
292 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82559ER},
293 {}
294};
295
296int eepro100_initialize (bd_t * bis)
297{
298 pci_dev_t devno;
299 int card_number = 0;
300 struct eth_device *dev;
301 u32 iobase, status;
302 int idx = 0;
303
304 while (1) {
305 /* Find PCI device
306 */
307 if ((devno = pci_find_devices (supported, idx++)) < 0) {
308 break;
309 }
310
311 pci_read_config_dword (devno, PCI_BASE_ADDRESS_0, &iobase);
312 iobase &= ~0xf;
313
314#ifdef DEBUG
315 printf ("eepro100: Intel i82559 PCI EtherExpressPro @0x%x\n",
316 iobase);
317#endif
318
319 pci_write_config_dword (devno,
320 PCI_COMMAND,
321 PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
322
323 /* Check if I/O accesses and Bus Mastering are enabled.
324 */
325 pci_read_config_dword (devno, PCI_COMMAND, &status);
326 if (!(status & PCI_COMMAND_MEMORY)) {
327 printf ("Error: Can not enable MEM access.\n");
328 continue;
329 }
330
331 if (!(status & PCI_COMMAND_MASTER)) {
332 printf ("Error: Can not enable Bus Mastering.\n");
333 continue;
334 }
335
336 dev = (struct eth_device *) malloc (sizeof *dev);
337
338 sprintf (dev->name, "i82559#%d", card_number);
7a8e9bed 339 dev->priv = (void *) devno; /* this have to come before bus_to_phys() */
1df49e27 340 dev->iobase = bus_to_phys (iobase);
1df49e27
WD		 341 dev->init = eepro100_init;
342 dev->halt = eepro100_halt;
343 dev->send = eepro100_send;
344 dev->recv = eepro100_recv;
345
346 eth_register (dev);
347
348 card_number++;
349
350 /* Set the latency timer for value.
351 */
352 pci_write_config_byte (devno, PCI_LATENCY_TIMER, 0x20);
353
354 udelay (10 * 1000);
355
356 read_hw_addr (dev, bis);
357 }
358
359 return card_number;
360}
361
362
363static int eepro100_init (struct eth_device *dev, bd_t * bis)
364{
365 int i, status = 0;
366 int tx_cur;
367 struct descriptor *ias_cmd, *cfg_cmd;
368
369 /* Reset the ethernet controller
370 */
371 OUTL (dev, I82559_SELECTIVE_RESET, SCBPort);
372 udelay (20);
373
374 OUTL (dev, I82559_RESET, SCBPort);
375 udelay (20);
376
377 if (!wait_for_eepro100 (dev)) {
378 printf ("Error: Can not reset ethernet controller.\n");
379 goto Done;
380 }
381 OUTL (dev, 0, SCBPointer);
382 OUTW (dev, SCB_M | RUC_ADDR_LOAD, SCBCmd);
383
384 if (!wait_for_eepro100 (dev)) {
385 printf ("Error: Can not reset ethernet controller.\n");
386 goto Done;
387 }
388 OUTL (dev, 0, SCBPointer);
389 OUTW (dev, SCB_M | CU_ADDR_LOAD, SCBCmd);
390
391 /* Initialize Rx and Tx rings.
392 */
393 init_rx_ring (dev);
394 purge_tx_ring (dev);
395
396 /* Tell the adapter where the RX ring is located.
397 */
398 if (!wait_for_eepro100 (dev)) {
399 printf ("Error: Can not reset ethernet controller.\n");
400 goto Done;
401 }
402
403 OUTL (dev, phys_to_bus ((u32) & rx_ring[rx_next]), SCBPointer);
404 OUTW (dev, SCB_M | RUC_START, SCBCmd);
405
406 /* Send the Configure frame */
407 tx_cur = tx_next;
408 tx_next = ((tx_next + 1) % NUM_TX_DESC);
409
410 cfg_cmd = (struct descriptor *) &tx_ring[tx_cur];
411 cfg_cmd->command = cpu_to_le16 ((CFG_CMD_SUSPEND | CFG_CMD_CONFIGURE));
412 cfg_cmd->status = 0;
413 cfg_cmd->link = cpu_to_le32 (phys_to_bus ((u32) & tx_ring[tx_next]));
414
415 memcpy (cfg_cmd->params, i82558_config_cmd,
416 sizeof (i82558_config_cmd));
417
418 if (!wait_for_eepro100 (dev)) {
419 printf ("Error---CFG_CMD_CONFIGURE: Can not reset ethernet controller.\n");
420 goto Done;
421 }
422
423 OUTL (dev, phys_to_bus ((u32) & tx_ring[tx_cur]), SCBPointer);
424 OUTW (dev, SCB_M | CU_START, SCBCmd);
425
426 for (i = 0;
427 !(le16_to_cpu (tx_ring[tx_cur].status) & CFG_STATUS_C);
428 i++) {
429 if (i >= TOUT_LOOP) {
430 printf ("%s: Tx error buffer not ready\n", dev->name);
431 goto Done;
432 }
433 }
434
435 if (!(le16_to_cpu (tx_ring[tx_cur].status) & CFG_STATUS_OK)) {
436 printf ("TX error status = 0x%08X\n",
437 le16_to_cpu (tx_ring[tx_cur].status));
438 goto Done;
439 }
440
441 /* Send the Individual Address Setup frame
442 */
443 tx_cur = tx_next;
444 tx_next = ((tx_next + 1) % NUM_TX_DESC);
445
446 ias_cmd = (struct descriptor *) &tx_ring[tx_cur];
447 ias_cmd->command = cpu_to_le16 ((CFG_CMD_SUSPEND | CFG_CMD_IAS));
448 ias_cmd->status = 0;
449 ias_cmd->link = cpu_to_le32 (phys_to_bus ((u32) & tx_ring[tx_next]));
450
451 memcpy (ias_cmd->params, dev->enetaddr, 6);
452
453 /* Tell the adapter where the TX ring is located.
454 */
455 if (!wait_for_eepro100 (dev)) {
456 printf ("Error: Can not reset ethernet controller.\n");
457 goto Done;
458 }
459
460 OUTL (dev, phys_to_bus ((u32) & tx_ring[tx_cur]), SCBPointer);
461 OUTW (dev, SCB_M | CU_START, SCBCmd);
462
463 for (i = 0; !(le16_to_cpu (tx_ring[tx_cur].status) & CFG_STATUS_C);
464 i++) {
465 if (i >= TOUT_LOOP) {
466 printf ("%s: Tx error buffer not ready\n",
467 dev->name);
468 goto Done;
469 }
470 }
471
472 if (!(le16_to_cpu (tx_ring[tx_cur].status) & CFG_STATUS_OK)) {
473 printf ("TX error status = 0x%08X\n",
474 le16_to_cpu (tx_ring[tx_cur].status));
475 goto Done;
476 }
477
478 status = 1;
479
480 Done:
481 return status;
482}
483
484static int eepro100_send (struct eth_device *dev, volatile void *packet, int length)
485{
486 int i, status = -1;
487 int tx_cur;
488
489 if (length <= 0) {
490 printf ("%s: bad packet size: %d\n", dev->name, length);
491 goto Done;
492 }
493
494 tx_cur = tx_next;
495 tx_next = (tx_next + 1) % NUM_TX_DESC;
496
497 tx_ring[tx_cur].command = cpu_to_le16 ( TxCB_CMD_TRANSMIT |
498 TxCB_CMD_SF |
499 TxCB_CMD_S |
500 TxCB_CMD_EL );
501 tx_ring[tx_cur].status = 0;
502 tx_ring[tx_cur].count = cpu_to_le32 (tx_threshold);
503 tx_ring[tx_cur].link =
504 cpu_to_le32 (phys_to_bus ((u32) & tx_ring[tx_next]));
505 tx_ring[tx_cur].tx_desc_addr =
506 cpu_to_le32 (phys_to_bus ((u32) & tx_ring[tx_cur].tx_buf_addr0));
507 tx_ring[tx_cur].tx_buf_addr0 =
508 cpu_to_le32 (phys_to_bus ((u_long) packet));
509 tx_ring[tx_cur].tx_buf_size0 = cpu_to_le32 (length);
510
511 if (!wait_for_eepro100 (dev)) {
512 printf ("%s: Tx error ethernet controller not ready.\n",
513 dev->name);
514 goto Done;
515 }
516
517 /* Send the packet.
518 */
519 OUTL (dev, phys_to_bus ((u32) & tx_ring[tx_cur]), SCBPointer);
520 OUTW (dev, SCB_M | CU_START, SCBCmd);
521
522 for (i = 0; !(le16_to_cpu (tx_ring[tx_cur].status) & CFG_STATUS_C);
523 i++) {
524 if (i >= TOUT_LOOP) {
525 printf ("%s: Tx error buffer not ready\n", dev->name);
526 goto Done;
527 }
528 }
529
530 if (!(le16_to_cpu (tx_ring[tx_cur].status) & CFG_STATUS_OK)) {
531 printf ("TX error status = 0x%08X\n",
532 le16_to_cpu (tx_ring[tx_cur].status));
533 goto Done;
534 }
535
536 status = length;
537
538 Done:
539 return status;
540}
541
542static int eepro100_recv (struct eth_device *dev)
543{
544 u16 status, stat;
545 int rx_prev, length = 0;
546
547 stat = INW (dev, SCBStatus);
548 OUTW (dev, stat & SCB_STATUS_RNR, SCBStatus);
549
550 for (;;) {
551 status = le16_to_cpu (rx_ring[rx_next].status);
552
553 if (!(status & RFD_STATUS_C)) {
554 break;
555 }
556
557 /* Valid frame status.
558 */
559 if ((status & RFD_STATUS_OK)) {
560 /* A valid frame received.
561 */
562 length = le32_to_cpu (rx_ring[rx_next].count) & 0x3fff;
563
564 /* Pass the packet up to the protocol
565 * layers.
566 */
567 NetReceive (rx_ring[rx_next].data, length);
568 } else {
569 /* There was an error.
570 */
571 printf ("RX error status = 0x%08X\n", status);
572 }
573
574 rx_ring[rx_next].control = cpu_to_le16 (RFD_CONTROL_S);
575 rx_ring[rx_next].status = 0;
576 rx_ring[rx_next].count = cpu_to_le32 (PKTSIZE_ALIGN << 16);
577
578 rx_prev = (rx_next + NUM_RX_DESC - 1) % NUM_RX_DESC;
579 rx_ring[rx_prev].control = 0;
580
581 /* Update entry information.
582 */
583 rx_next = (rx_next + 1) % NUM_RX_DESC;
584 }
585
586 if (stat & SCB_STATUS_RNR) {
587
588 printf ("%s: Receiver is not ready, restart it !\n", dev->name);
589
590 /* Reinitialize Rx ring.
591 */
592 init_rx_ring (dev);
593
594 if (!wait_for_eepro100 (dev)) {
595 printf ("Error: Can not restart ethernet controller.\n");
596 goto Done;
597 }
598
599 OUTL (dev, phys_to_bus ((u32) & rx_ring[rx_next]), SCBPointer);
600 OUTW (dev, SCB_M | RUC_START, SCBCmd);
601 }
602
603 Done:
604 return length;
605}
606
607static void eepro100_halt (struct eth_device *dev)
608{
609 /* Reset the ethernet controller
610 */
611 OUTL (dev, I82559_SELECTIVE_RESET, SCBPort);
612 udelay (20);
613
614 OUTL (dev, I82559_RESET, SCBPort);
615 udelay (20);
616
617 if (!wait_for_eepro100 (dev)) {
618 printf ("Error: Can not reset ethernet controller.\n");
619 goto Done;
620 }
621 OUTL (dev, 0, SCBPointer);
622 OUTW (dev, SCB_M | RUC_ADDR_LOAD, SCBCmd);
623
624 if (!wait_for_eepro100 (dev)) {
625 printf ("Error: Can not reset ethernet controller.\n");
626 goto Done;
627 }
628 OUTL (dev, 0, SCBPointer);
629 OUTW (dev, SCB_M | CU_ADDR_LOAD, SCBCmd);
630
631 Done:
632 return;
633}
634
635 /* SROM Read.
636 */
637static int read_eeprom (struct eth_device *dev, int location, int addr_len)
638{
639 unsigned short retval = 0;
640 int read_cmd = location | EE_READ_CMD;
641 int i;
642
643 OUTW (dev, EE_ENB & ~EE_CS, SCBeeprom);
644 OUTW (dev, EE_ENB, SCBeeprom);
645
646 /* Shift the read command bits out. */
647 for (i = 12; i >= 0; i--) {
648 short dataval = (read_cmd & (1 << i)) ? EE_DATA_WRITE : 0;
649
650 OUTW (dev, EE_ENB | dataval, SCBeeprom);
651 udelay (1);
652 OUTW (dev, EE_ENB | dataval | EE_SHIFT_CLK, SCBeeprom);
653 udelay (1);
654 }
655 OUTW (dev, EE_ENB, SCBeeprom);
656
657 for (i = 15; i >= 0; i--) {
658 OUTW (dev, EE_ENB | EE_SHIFT_CLK, SCBeeprom);
659 udelay (1);
660 retval = (retval << 1) |
661 ((INW (dev, SCBeeprom) & EE_DATA_READ) ? 1 : 0);
662 OUTW (dev, EE_ENB, SCBeeprom);
663 udelay (1);
664 }
665
666 /* Terminate the EEPROM access. */
667 OUTW (dev, EE_ENB & ~EE_CS, SCBeeprom);
668 return retval;
669}
670
671#ifdef CONFIG_EEPRO100_SROM_WRITE
672int eepro100_write_eeprom (struct eth_device* dev, int location, int addr_len, unsigned short data)
673{
674 unsigned short dataval;
675 int enable_cmd = 0x3f | EE_EWENB_CMD;
676 int write_cmd = location | EE_WRITE_CMD;
677 int i;
678 unsigned long datalong, tmplong;
679
680 OUTW(dev, EE_ENB & ~EE_CS, SCBeeprom);
681 udelay(1);
682 OUTW(dev, EE_ENB, SCBeeprom);
683
684 /* Shift the enable command bits out. */
685 for (i = (addr_len+EE_CMD_BITS-1); i >= 0; i--)
686 {
8bde7f77
WD		 687 dataval = (enable_cmd & (1 << i)) ? EE_DATA_WRITE : 0;
688 OUTW(dev, EE_ENB | dataval, SCBeeprom);
689 udelay(1);
690 OUTW(dev, EE_ENB | dataval | EE_SHIFT_CLK, SCBeeprom);
691 udelay(1);
1df49e27
WD		 692 }
693
694 OUTW(dev, EE_ENB, SCBeeprom);
695 udelay(1);
696 OUTW(dev, EE_ENB & ~EE_CS, SCBeeprom);
697 udelay(1);
698 OUTW(dev, EE_ENB, SCBeeprom);
699
700
701 /* Shift the write command bits out. */
702 for (i = (addr_len+EE_CMD_BITS-1); i >= 0; i--)
703 {
8bde7f77
WD		 704 dataval = (write_cmd & (1 << i)) ? EE_DATA_WRITE : 0;
705 OUTW(dev, EE_ENB | dataval, SCBeeprom);
706 udelay(1);
707 OUTW(dev, EE_ENB | dataval | EE_SHIFT_CLK, SCBeeprom);
708 udelay(1);
1df49e27
WD		 709 }
710
711 /* Write the data */
712 datalong= (unsigned long) ((((data) & 0x00ff) << 8) | ( (data) >> 8));
713
714 for (i = 0; i< EE_DATA_BITS; i++)
715 {
716 /* Extract and move data bit to bit DI */
717 dataval = ((datalong & 0x8000)>>13) ? EE_DATA_WRITE : 0;
718
719 OUTW(dev, EE_ENB | dataval, SCBeeprom);
720 udelay(1);
721 OUTW(dev, EE_ENB | dataval | EE_SHIFT_CLK, SCBeeprom);
722 udelay(1);
723 OUTW(dev, EE_ENB | dataval, SCBeeprom);
724 udelay(1);
725
726 datalong = datalong << 1; /* Adjust significant data bit*/
727 }
728
729 /* Finish up command (toggle CS) */
730 OUTW(dev, EE_ENB & ~EE_CS, SCBeeprom);
731 udelay(1); /* delay for more than 250 ns */
732 OUTW(dev, EE_ENB, SCBeeprom);
733
734 /* Wait for programming ready (D0 = 1) */
735 tmplong = 10;
736 do
737 {
8bde7f77
WD		 738 dataval = INW(dev, SCBeeprom);
739 if (dataval & EE_DATA_READ)
740 break;
741 udelay(10000);
1df49e27
WD		 742 }
743 while (-- tmplong);
744
745 if (tmplong == 0)
746 {
8bde7f77
WD		 747 printf ("Write i82559 eeprom timed out (100 ms waiting for data ready.\n");
748 return -1;
1df49e27
WD		 749 }
750
751 /* Terminate the EEPROM access. */
752 OUTW(dev, EE_ENB & ~EE_CS, SCBeeprom);
753
754 return 0;
755}
756#endif
757
758static void init_rx_ring (struct eth_device *dev)
759{
760 int i;
761
762 for (i = 0; i < NUM_RX_DESC; i++) {
763 rx_ring[i].status = 0;
764 rx_ring[i].control =
765 (i == NUM_RX_DESC - 1) ? cpu_to_le16 (RFD_CONTROL_S) : 0;
766 rx_ring[i].link =
767 cpu_to_le32 (phys_to_bus
768 ((u32) & rx_ring[(i + 1) % NUM_RX_DESC]));
769 rx_ring[i].rx_buf_addr = 0xffffffff;
770 rx_ring[i].count = cpu_to_le32 (PKTSIZE_ALIGN << 16);
771 }
772
773 rx_next = 0;
774}
775
776static void purge_tx_ring (struct eth_device *dev)
777{
778 int i;
779
780 tx_next = 0;
781 tx_threshold = 0x01208000;
782
783 for (i = 0; i < NUM_TX_DESC; i++) {
784 tx_ring[i].status = 0;
785 tx_ring[i].command = 0;
786 tx_ring[i].link = 0;
787 tx_ring[i].tx_desc_addr = 0;
788 tx_ring[i].count = 0;
789
790 tx_ring[i].tx_buf_addr0 = 0;
791 tx_ring[i].tx_buf_size0 = 0;
792 tx_ring[i].tx_buf_addr1 = 0;
793 tx_ring[i].tx_buf_size1 = 0;
794 }
795}
796
797static void read_hw_addr (struct eth_device *dev, bd_t * bis)
798{
799 u16 eeprom[0x40];
800 u16 sum = 0;
801 int i, j;
802 int addr_len = read_eeprom (dev, 0, 6) == 0xffff ? 8 : 6;
803
804 for (j = 0, i = 0; i < 0x40; i++) {
805 u16 value = read_eeprom (dev, i, addr_len);
806
807 eeprom[i] = value;
808 sum += value;
809 if (i < 3) {
810 dev->enetaddr[j++] = value;
811 dev->enetaddr[j++] = value >> 8;
812 }
813 }
814
815 if (sum != 0xBABA) {
816 memset (dev->enetaddr, 0, ETH_ALEN);
817#ifdef DEBUG
818 printf ("%s: Invalid EEPROM checksum %#4.4x, "
819 "check settings before activating this device!\n",
820 dev->name, sum);
821#endif
822 }
823}
824
825#endif
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