[thirdparty/u-boot.git] / drivers / gpio / gpio-aspeed.c

// SPDX-License-Identifier: GPL-2.0-or-later
/*
 * Copyright 2015 IBM Corp.
 * Joel Stanley <joel@jms.id.au>
 * Ryan Chen <ryan_chen@aspeedtech.com>
 *
 * Implementation extracted from the Linux kernel and adapted for u-boot.
 */
#include <common.h>
#include <asm/io.h>
#include <asm/gpio.h>

#include <config.h>
#include <clk.h>
#include <dm.h>
#include <asm/io.h>
#include <linux/bug.h>
#include <linux/sizes.h>

struct aspeed_gpio_priv {
	void *regs;
};

struct aspeed_gpio_bank {
	u16		val_regs;	/* +0: Rd: read input value, Wr: set write latch
					 * +4: Rd/Wr: Direction (0=in, 1=out)
					 */
	u16		rdata_reg;	/*     Rd: read write latch, Wr: <none>  */
	u16		irq_regs;
	u16		debounce_regs;
	u16		tolerance_regs;
	u16		cmdsrc_regs;
	const char	names[4][3];
};

static const struct aspeed_gpio_bank aspeed_gpio_banks[] = {
	{
		.val_regs = 0x0000,
		.rdata_reg = 0x00c0,
		.irq_regs = 0x0008,
		.debounce_regs = 0x0040,
		.tolerance_regs = 0x001c,
		.cmdsrc_regs = 0x0060,
		.names = { "A", "B", "C", "D" },
	},
	{
		.val_regs = 0x0020,
		.rdata_reg = 0x00c4,
		.irq_regs = 0x0028,
		.debounce_regs = 0x0048,
		.tolerance_regs = 0x003c,
		.cmdsrc_regs = 0x0068,
		.names = { "E", "F", "G", "H" },
	},
	{
		.val_regs = 0x0070,
		.rdata_reg = 0x00c8,
		.irq_regs = 0x0098,
		.debounce_regs = 0x00b0,
		.tolerance_regs = 0x00ac,
		.cmdsrc_regs = 0x0090,
		.names = { "I", "J", "K", "L" },
	},
	{
		.val_regs = 0x0078,
		.rdata_reg = 0x00cc,
		.irq_regs = 0x00e8,
		.debounce_regs = 0x0100,
		.tolerance_regs = 0x00fc,
		.cmdsrc_regs = 0x00e0,
		.names = { "M", "N", "O", "P" },
	},
	{
		.val_regs = 0x0080,
		.rdata_reg = 0x00d0,
		.irq_regs = 0x0118,
		.debounce_regs = 0x0130,
		.tolerance_regs = 0x012c,
		.cmdsrc_regs = 0x0110,
		.names = { "Q", "R", "S", "T" },
	},
	{
		.val_regs = 0x0088,
		.rdata_reg = 0x00d4,
		.irq_regs = 0x0148,
		.debounce_regs = 0x0160,
		.tolerance_regs = 0x015c,
		.cmdsrc_regs = 0x0140,
		.names = { "U", "V", "W", "X" },
	},
	{
		.val_regs = 0x01E0,
		.rdata_reg = 0x00d8,
		.irq_regs = 0x0178,
		.debounce_regs = 0x0190,
		.tolerance_regs = 0x018c,
		.cmdsrc_regs = 0x0170,
		.names = { "Y", "Z", "AA", "AB" },
	},
	{
		.val_regs = 0x01e8,
		.rdata_reg = 0x00dc,
		.irq_regs = 0x01a8,
		.debounce_regs = 0x01c0,
		.tolerance_regs = 0x01bc,
		.cmdsrc_regs = 0x01a0,
		.names = { "AC", "", "", "" },
	},
};

enum aspeed_gpio_reg {
	reg_val,
	reg_rdata,
	reg_dir,
	reg_irq_enable,
	reg_irq_type0,
	reg_irq_type1,
	reg_irq_type2,
	reg_irq_status,
	reg_debounce_sel1,
	reg_debounce_sel2,
	reg_tolerance,
	reg_cmdsrc0,
	reg_cmdsrc1,
};

#define GPIO_VAL_VALUE	0x00
#define GPIO_VAL_DIR	0x04

#define GPIO_IRQ_ENABLE	0x00
#define GPIO_IRQ_TYPE0	0x04
#define GPIO_IRQ_TYPE1	0x08
#define GPIO_IRQ_TYPE2	0x0c
#define GPIO_IRQ_STATUS	0x10

#define GPIO_DEBOUNCE_SEL1 0x00
#define GPIO_DEBOUNCE_SEL2 0x04

#define GPIO_CMDSRC_0	0x00
#define GPIO_CMDSRC_1	0x04
#define  GPIO_CMDSRC_ARM		0
#define  GPIO_CMDSRC_LPC		1
#define  GPIO_CMDSRC_COLDFIRE		2
#define  GPIO_CMDSRC_RESERVED		3

/* This will be resolved at compile time */
static inline void __iomem *bank_reg(struct aspeed_gpio_priv *gpio,
				     const struct aspeed_gpio_bank *bank,
				     const enum aspeed_gpio_reg reg)
{
	switch (reg) {
	case reg_val:
		return gpio->regs + bank->val_regs + GPIO_VAL_VALUE;
	case reg_rdata:
		return gpio->regs + bank->rdata_reg;
	case reg_dir:
		return gpio->regs + bank->val_regs + GPIO_VAL_DIR;
	case reg_irq_enable:
		return gpio->regs + bank->irq_regs + GPIO_IRQ_ENABLE;
	case reg_irq_type0:
		return gpio->regs + bank->irq_regs + GPIO_IRQ_TYPE0;
	case reg_irq_type1:
		return gpio->regs + bank->irq_regs + GPIO_IRQ_TYPE1;
	case reg_irq_type2:
		return gpio->regs + bank->irq_regs + GPIO_IRQ_TYPE2;
	case reg_irq_status:
		return gpio->regs + bank->irq_regs + GPIO_IRQ_STATUS;
	case reg_debounce_sel1:
		return gpio->regs + bank->debounce_regs + GPIO_DEBOUNCE_SEL1;
	case reg_debounce_sel2:
		return gpio->regs + bank->debounce_regs + GPIO_DEBOUNCE_SEL2;
	case reg_tolerance:
		return gpio->regs + bank->tolerance_regs;
	case reg_cmdsrc0:
		return gpio->regs + bank->cmdsrc_regs + GPIO_CMDSRC_0;
	case reg_cmdsrc1:
		return gpio->regs + bank->cmdsrc_regs + GPIO_CMDSRC_1;
	}
	BUG();
}

#define GPIO_BANK(x)	((x) >> 5)
#define GPIO_OFFSET(x)	((x) & 0x1f)
#define GPIO_BIT(x)	BIT(GPIO_OFFSET(x))

static const struct aspeed_gpio_bank *to_bank(unsigned int offset)
{
	unsigned int bank = GPIO_BANK(offset);

	WARN_ON(bank >= ARRAY_SIZE(aspeed_gpio_banks));
	return &aspeed_gpio_banks[bank];
}

static int
aspeed_gpio_direction_input(struct udevice *dev, unsigned int offset)
{
	struct aspeed_gpio_priv *priv = dev_get_priv(dev);
	const struct aspeed_gpio_bank *bank = to_bank(offset);
	u32 dir = readl(bank_reg(priv, bank, reg_dir));

	dir &= ~GPIO_BIT(offset);
	writel(dir, bank_reg(priv, bank, reg_dir));

	return 0;
}

static int aspeed_gpio_direction_output(struct udevice *dev, unsigned int offset,
					int value)
{
	struct aspeed_gpio_priv *priv = dev_get_priv(dev);
	const struct aspeed_gpio_bank *bank = to_bank(offset);
	u32 dir = readl(bank_reg(priv, bank, reg_dir));
	u32 output = readl(bank_reg(priv, bank, reg_rdata));

	dir |= GPIO_BIT(offset);
	writel(dir, bank_reg(priv, bank, reg_dir));

	if (value)
		output |= GPIO_BIT(offset);
	else
		output &= ~GPIO_BIT(offset);

	writel(output, bank_reg(priv, bank, reg_val));

	return 0;
}

static int aspeed_gpio_get_value(struct udevice *dev, unsigned int offset)
{
	struct aspeed_gpio_priv *priv = dev_get_priv(dev);
	const struct aspeed_gpio_bank *bank = to_bank(offset);

	return !!(readl(bank_reg(priv, bank, reg_val)) & GPIO_BIT(offset));
}

static int
aspeed_gpio_set_value(struct udevice *dev, unsigned int offset, int value)
{
	struct aspeed_gpio_priv *priv = dev_get_priv(dev);
	const struct aspeed_gpio_bank *bank = to_bank(offset);
	u32 data = readl(bank_reg(priv, bank, reg_rdata));

	if (value)
		data |= GPIO_BIT(offset);
	else
		data &= ~GPIO_BIT(offset);

	writel(data, bank_reg(priv, bank, reg_val));

	return 0;
}

static int aspeed_gpio_get_function(struct udevice *dev, unsigned int offset)
{
	struct aspeed_gpio_priv *priv = dev_get_priv(dev);
	const struct aspeed_gpio_bank *bank = to_bank(offset);

	if (readl(bank_reg(priv, bank, reg_dir)) & GPIO_BIT(offset))
		return GPIOF_OUTPUT;

	return GPIOF_INPUT;
}

static const struct dm_gpio_ops aspeed_gpio_ops = {
	.direction_input	= aspeed_gpio_direction_input,
	.direction_output	= aspeed_gpio_direction_output,
	.get_value		= aspeed_gpio_get_value,
	.set_value		= aspeed_gpio_set_value,
	.get_function		= aspeed_gpio_get_function,
};

static int aspeed_gpio_probe(struct udevice *dev)
{
	struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
	struct aspeed_gpio_priv *priv = dev_get_priv(dev);

	uc_priv->bank_name = dev->name;
	ofnode_read_u32(dev_ofnode(dev), "ngpios", &uc_priv->gpio_count);
	priv->regs = devfdt_get_addr_ptr(dev);

	return 0;
}

static const struct udevice_id aspeed_gpio_ids[] = {
	{ .compatible = "aspeed,ast2400-gpio",  },
	{ .compatible = "aspeed,ast2500-gpio",	},
	{ .compatible = "aspeed,ast2600-gpio",	},
	{ }
};

U_BOOT_DRIVER(gpio_aspeed) = {
	.name   = "gpio-aspeed",
	.id     = UCLASS_GPIO,
	.of_match = aspeed_gpio_ids,
	.ops    = &aspeed_gpio_ops,
	.probe  = aspeed_gpio_probe,
	.priv_auto = sizeof(struct aspeed_gpio_priv),
};
Commit	Line	Data
7ad889b0 AJ	1	// SPDX-License-Identifier: GPL-2.0-or-later
	2	/*
	3	* Copyright 2015 IBM Corp.
	4	* Joel Stanley <joel@jms.id.au>
	5	* Ryan Chen <ryan_chen@aspeedtech.com>
	6	*
	7	* Implementation extracted from the Linux kernel and adapted for u-boot.
	8	*/
d678a59d	9	#include <common.h>
7ad889b0 AJ	10	#include <asm/io.h>
	11	#include <asm/gpio.h>
	12
	13	#include <config.h>
7ad889b0 AJ	14	#include <clk.h>
	15	#include <dm.h>
	16	#include <asm/io.h>
	17	#include <linux/bug.h>
	18	#include <linux/sizes.h>
	19
	20	struct aspeed_gpio_priv {
	21	void *regs;
	22	};
	23
	24	struct aspeed_gpio_bank {
	25	u16 val_regs; /* +0: Rd: read input value, Wr: set write latch
	26	* +4: Rd/Wr: Direction (0=in, 1=out)
	27	*/
	28	u16 rdata_reg; /* Rd: read write latch, Wr: <none> */
	29	u16 irq_regs;
	30	u16 debounce_regs;
	31	u16 tolerance_regs;
	32	u16 cmdsrc_regs;
	33	const char names[4][3];
	34	};
	35
	36	static const struct aspeed_gpio_bank aspeed_gpio_banks[] = {
	37	{
	38	.val_regs = 0x0000,
	39	.rdata_reg = 0x00c0,
	40	.irq_regs = 0x0008,
	41	.debounce_regs = 0x0040,
	42	.tolerance_regs = 0x001c,
	43	.cmdsrc_regs = 0x0060,
	44	.names = { "A", "B", "C", "D" },
	45	},
	46	{
	47	.val_regs = 0x0020,
	48	.rdata_reg = 0x00c4,
	49	.irq_regs = 0x0028,
	50	.debounce_regs = 0x0048,
	51	.tolerance_regs = 0x003c,
	52	.cmdsrc_regs = 0x0068,
	53	.names = { "E", "F", "G", "H" },
	54	},
	55	{
	56	.val_regs = 0x0070,
	57	.rdata_reg = 0x00c8,
	58	.irq_regs = 0x0098,
	59	.debounce_regs = 0x00b0,
	60	.tolerance_regs = 0x00ac,
	61	.cmdsrc_regs = 0x0090,
	62	.names = { "I", "J", "K", "L" },
	63	},
	64	{
	65	.val_regs = 0x0078,
	66	.rdata_reg = 0x00cc,
	67	.irq_regs = 0x00e8,
	68	.debounce_regs = 0x0100,
	69	.tolerance_regs = 0x00fc,
	70	.cmdsrc_regs = 0x00e0,
	71	.names = { "M", "N", "O", "P" },
	72	},
	73	{
	74	.val_regs = 0x0080,
	75	.rdata_reg = 0x00d0,
	76	.irq_regs = 0x0118,
	77	.debounce_regs = 0x0130,
78	.tolerance_regs = 0x012c,
79	.cmdsrc_regs = 0x0110,
80	.names = { "Q", "R", "S", "T" },
81	},
82	{
83	.val_regs = 0x0088,
84	.rdata_reg = 0x00d4,
85	.irq_regs = 0x0148,
86	.debounce_regs = 0x0160,
87	.tolerance_regs = 0x015c,
88	.cmdsrc_regs = 0x0140,
89	.names = { "U", "V", "W", "X" },
90	},
91	{
92	.val_regs = 0x01E0,
93	.rdata_reg = 0x00d8,
94	.irq_regs = 0x0178,
95	.debounce_regs = 0x0190,
96	.tolerance_regs = 0x018c,
97	.cmdsrc_regs = 0x0170,
98	.names = { "Y", "Z", "AA", "AB" },
99	},
100	{
101	.val_regs = 0x01e8,
102	.rdata_reg = 0x00dc,
103	.irq_regs = 0x01a8,
104	.debounce_regs = 0x01c0,
105	.tolerance_regs = 0x01bc,
106	.cmdsrc_regs = 0x01a0,
107	.names = { "AC", "", "", "" },
108	},
109	};
110
111	enum aspeed_gpio_reg {
112	reg_val,
113	reg_rdata,
114	reg_dir,
115	reg_irq_enable,
116	reg_irq_type0,
117	reg_irq_type1,
118	reg_irq_type2,
119	reg_irq_status,
120	reg_debounce_sel1,
121	reg_debounce_sel2,
122	reg_tolerance,
123	reg_cmdsrc0,
124	reg_cmdsrc1,
125	};
126
127	#define GPIO_VAL_VALUE 0x00
128	#define GPIO_VAL_DIR 0x04
129
130	#define GPIO_IRQ_ENABLE 0x00
131	#define GPIO_IRQ_TYPE0 0x04
132	#define GPIO_IRQ_TYPE1 0x08
133	#define GPIO_IRQ_TYPE2 0x0c
134	#define GPIO_IRQ_STATUS 0x10
135
136	#define GPIO_DEBOUNCE_SEL1 0x00
137	#define GPIO_DEBOUNCE_SEL2 0x04
138
139	#define GPIO_CMDSRC_0 0x00
140	#define GPIO_CMDSRC_1 0x04
141	#define GPIO_CMDSRC_ARM 0
142	#define GPIO_CMDSRC_LPC 1
143	#define GPIO_CMDSRC_COLDFIRE 2
144	#define GPIO_CMDSRC_RESERVED 3
145
146	/* This will be resolved at compile time */
147	static inline void __iomem bank_reg(struct aspeed_gpio_priv gpio,
148	const struct aspeed_gpio_bank *bank,
149	const enum aspeed_gpio_reg reg)
150	{
151	switch (reg) {
152	case reg_val:
153	return gpio->regs + bank->val_regs + GPIO_VAL_VALUE;
154	case reg_rdata:
155	return gpio->regs + bank->rdata_reg;
156	case reg_dir:
157	return gpio->regs + bank->val_regs + GPIO_VAL_DIR;
158	case reg_irq_enable:
159	return gpio->regs + bank->irq_regs + GPIO_IRQ_ENABLE;
160	case reg_irq_type0:
161	return gpio->regs + bank->irq_regs + GPIO_IRQ_TYPE0;
162	case reg_irq_type1:
163	return gpio->regs + bank->irq_regs + GPIO_IRQ_TYPE1;
164	case reg_irq_type2:
165	return gpio->regs + bank->irq_regs + GPIO_IRQ_TYPE2;
166	case reg_irq_status:
167	return gpio->regs + bank->irq_regs + GPIO_IRQ_STATUS;
168	case reg_debounce_sel1:
169	return gpio->regs + bank->debounce_regs + GPIO_DEBOUNCE_SEL1;
170	case reg_debounce_sel2:
171	return gpio->regs + bank->debounce_regs + GPIO_DEBOUNCE_SEL2;
172	case reg_tolerance:
173	return gpio->regs + bank->tolerance_regs;
174	case reg_cmdsrc0:
175	return gpio->regs + bank->cmdsrc_regs + GPIO_CMDSRC_0;
176	case reg_cmdsrc1:
177	return gpio->regs + bank->cmdsrc_regs + GPIO_CMDSRC_1;
178	}
179	BUG();
180	}
181
182	#define GPIO_BANK(x) ((x) >> 5)
183	#define GPIO_OFFSET(x) ((x) & 0x1f)
184	#define GPIO_BIT(x) BIT(GPIO_OFFSET(x))
185
186	static const struct aspeed_gpio_bank *to_bank(unsigned int offset)
187	{
188	unsigned int bank = GPIO_BANK(offset);
189
190	WARN_ON(bank >= ARRAY_SIZE(aspeed_gpio_banks));
191	return &aspeed_gpio_banks[bank];
192	}
193
194	static int
195	aspeed_gpio_direction_input(struct udevice *dev, unsigned int offset)
196	{
197	struct aspeed_gpio_priv *priv = dev_get_priv(dev);
198	const struct aspeed_gpio_bank *bank = to_bank(offset);
199	u32 dir = readl(bank_reg(priv, bank, reg_dir));
200
201	dir &= ~GPIO_BIT(offset);
202	writel(dir, bank_reg(priv, bank, reg_dir));
203
204	return 0;
205	}
206
207	static int aspeed_gpio_direction_output(struct udevice *dev, unsigned int offset,
208	int value)
209	{
210	struct aspeed_gpio_priv *priv = dev_get_priv(dev);
211	const struct aspeed_gpio_bank *bank = to_bank(offset);
212	u32 dir = readl(bank_reg(priv, bank, reg_dir));
fe2f2842	213	u32 output = readl(bank_reg(priv, bank, reg_rdata));
7ad889b0 AJ	214
	215	dir \|= GPIO_BIT(offset);
	216	writel(dir, bank_reg(priv, bank, reg_dir));
	217
	218	if (value)
	219	output \|= GPIO_BIT(offset);
	220	else
	221	output &= ~GPIO_BIT(offset);
	222
	223	writel(output, bank_reg(priv, bank, reg_val));
	224
	225	return 0;
	226	}
	227
	228	static int aspeed_gpio_get_value(struct udevice *dev, unsigned int offset)
	229	{
	230	struct aspeed_gpio_priv *priv = dev_get_priv(dev);
	231	const struct aspeed_gpio_bank *bank = to_bank(offset);
	232
	233	return !!(readl(bank_reg(priv, bank, reg_val)) & GPIO_BIT(offset));
	234	}
	235
	236	static int
	237	aspeed_gpio_set_value(struct udevice *dev, unsigned int offset, int value)
	238	{
	239	struct aspeed_gpio_priv *priv = dev_get_priv(dev);
	240	const struct aspeed_gpio_bank *bank = to_bank(offset);
fe2f2842	241	u32 data = readl(bank_reg(priv, bank, reg_rdata));
7ad889b0 AJ	242
	243	if (value)
	244	data \|= GPIO_BIT(offset);
	245	else
	246	data &= ~GPIO_BIT(offset);
	247
	248	writel(data, bank_reg(priv, bank, reg_val));
	249
	250	return 0;
	251	}
	252
	253	static int aspeed_gpio_get_function(struct udevice *dev, unsigned int offset)
	254	{
	255	struct aspeed_gpio_priv *priv = dev_get_priv(dev);
	256	const struct aspeed_gpio_bank *bank = to_bank(offset);
	257
	258	if (readl(bank_reg(priv, bank, reg_dir)) & GPIO_BIT(offset))
	259	return GPIOF_OUTPUT;
	260
	261	return GPIOF_INPUT;
	262	}
	263
	264	static const struct dm_gpio_ops aspeed_gpio_ops = {
	265	.direction_input = aspeed_gpio_direction_input,
	266	.direction_output = aspeed_gpio_direction_output,
	267	.get_value = aspeed_gpio_get_value,
	268	.set_value = aspeed_gpio_set_value,
	269	.get_function = aspeed_gpio_get_function,
	270	};
	271
	272	static int aspeed_gpio_probe(struct udevice *dev)
	273	{
	274	struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
	275	struct aspeed_gpio_priv *priv = dev_get_priv(dev);
	276
	277	uc_priv->bank_name = dev->name;
	278	ofnode_read_u32(dev_ofnode(dev), "ngpios", &uc_priv->gpio_count);
	279	priv->regs = devfdt_get_addr_ptr(dev);
	280
	281	return 0;
	282	}
	283
	284	static const struct udevice_id aspeed_gpio_ids[] = {
	285	{ .compatible = "aspeed,ast2400-gpio", },
	286	{ .compatible = "aspeed,ast2500-gpio", },
	287	{ .compatible = "aspeed,ast2600-gpio", },
	288	{ }
	289	};
	290
	291	U_BOOT_DRIVER(gpio_aspeed) = {
	292	.name = "gpio-aspeed",
	293	.id = UCLASS_GPIO,
	294	.of_match = aspeed_gpio_ids,
	295	.ops = &aspeed_gpio_ops,
	296	.probe = aspeed_gpio_probe,
	297	.priv_auto = sizeof(struct aspeed_gpio_priv),
	298	};