[thirdparty/u-boot.git] / drivers / gpio / hsdk-creg-gpio.c

/*
 * Synopsys HSDK SDP Generic PLL clock driver
 *
 * Copyright (C) 2017 Synopsys
 * Author: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
 *
 * This file is licensed under the terms of the GNU General Public
 * License version 2. This program is licensed "as is" without any
 * warranty of any kind, whether express or implied.
 */

#include <log.h>
#include <asm-generic/gpio.h>
#include <asm/io.h>
#include <common.h>
#include <dm.h>
#include <errno.h>
#include <linux/bitops.h>
#include <linux/printk.h>

#define DRV_NAME	"gpio_creg"

struct hsdk_creg_gpio {
	u32	*regs;
	u8	shift;
	u8	activate;
	u8	deactivate;
	u8	bit_per_gpio;
};

static int hsdk_creg_gpio_set_value(struct udevice *dev, unsigned oft, int val)
{
	struct hsdk_creg_gpio *hcg = dev_get_priv(dev);
	u8 reg_shift = oft * hcg->bit_per_gpio + hcg->shift;
	u32 reg = readl(hcg->regs);

	reg &= ~(GENMASK(hcg->bit_per_gpio - 1, 0) << reg_shift);
	reg |=  ((val ? hcg->deactivate : hcg->activate) << reg_shift);

	writel(reg, hcg->regs);

	return 0;
}

static int hsdk_creg_gpio_direction_output(struct udevice *dev, unsigned oft,
					   int val)
{
	hsdk_creg_gpio_set_value(dev, oft, val);

	return 0;
}

static int hsdk_creg_gpio_direction_input(struct udevice *dev, unsigned oft)
{
	struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);

	pr_err("%s can't be used as input!\n", uc_priv->bank_name);

	return -ENOTSUPP;
}

static int hsdk_creg_gpio_get_value(struct udevice *dev, unsigned int oft)
{
	struct hsdk_creg_gpio *hcg = dev_get_priv(dev);
	u32 val = readl(hcg->regs);

	val >>= oft * hcg->bit_per_gpio + hcg->shift;
	val &= GENMASK(hcg->bit_per_gpio - 1, 0);
	return (val == hcg->deactivate) ? 1 : 0;
}

static const struct dm_gpio_ops hsdk_creg_gpio_ops = {
	.direction_output	= hsdk_creg_gpio_direction_output,
	.direction_input	= hsdk_creg_gpio_direction_input,
	.set_value		= hsdk_creg_gpio_set_value,
	.get_value		= hsdk_creg_gpio_get_value,
};

static int hsdk_creg_gpio_probe(struct udevice *dev)
{
	struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
	struct hsdk_creg_gpio *hcg = dev_get_priv(dev);
	u32 shift, bit_per_gpio, activate, deactivate, gpio_count;
	const u8 *defaults;

	hcg->regs = dev_read_addr_ptr(dev);
	gpio_count = dev_read_u32_default(dev, "gpio-count", 1);
	shift = dev_read_u32_default(dev, "gpio-first-shift", 0);
	bit_per_gpio = dev_read_u32_default(dev, "gpio-bit-per-line", 1);
	activate = dev_read_u32_default(dev, "gpio-activate-val", 1);
	deactivate = dev_read_u32_default(dev, "gpio-deactivate-val", 0);
	defaults = dev_read_u8_array_ptr(dev, "gpio-default-val", gpio_count);

	uc_priv->bank_name = dev_read_string(dev, "gpio-bank-name");
	if (!uc_priv->bank_name)
		uc_priv->bank_name = dev_read_name(dev);

	if (!bit_per_gpio) {
		pr_err("%s: 'gpio-bit-per-line' can't be 0\n",
		       uc_priv->bank_name);

		return -EINVAL;
	}

	if (!gpio_count) {
		pr_err("%s: 'gpio-count' can't be 0\n",
		       uc_priv->bank_name);

		return -EINVAL;
	}

	if ((gpio_count * bit_per_gpio + shift) > 32) {
		pr_err("%s: u32 io register overflow: try to use %u bits\n",
		       uc_priv->bank_name, gpio_count * bit_per_gpio + shift);

		return -EINVAL;
	}

	if (GENMASK(31, bit_per_gpio) & activate) {
		pr_err("%s: 'gpio-activate-val' can't be more than %lu\n",
		       uc_priv->bank_name, GENMASK(bit_per_gpio - 1, 0));

		return -EINVAL;
	}

	if (GENMASK(31, bit_per_gpio) & deactivate) {
		pr_err("%s: 'gpio-deactivate-val' can't be more than %lu\n",
		       uc_priv->bank_name, GENMASK(bit_per_gpio - 1, 0));

		return -EINVAL;
	}

	if (activate == deactivate) {
		pr_err("%s: 'gpio-deactivate-val' and 'gpio-activate-val' can't be equal\n",
		       uc_priv->bank_name);

		return -EINVAL;
	}

	hcg->shift = (u8)shift;
	hcg->bit_per_gpio = (u8)bit_per_gpio;
	hcg->activate = (u8)activate;
	hcg->deactivate = (u8)deactivate;
	uc_priv->gpio_count = gpio_count;

	/* Setup default GPIO value if we have "gpio-default-val" array */
	if (defaults)
		for (u8 i = 0; i < gpio_count; i++)
			hsdk_creg_gpio_set_value(dev, i, defaults[i]);

	pr_debug("%s GPIO [0x%p] controller with %d gpios probed\n",
		 uc_priv->bank_name, hcg->regs, uc_priv->gpio_count);

	return 0;
}

static const struct udevice_id hsdk_creg_gpio_ids[] = {
	{ .compatible = "snps,creg-gpio" },
	{ }
};

U_BOOT_DRIVER(gpio_hsdk_creg) = {
	.name	= DRV_NAME,
	.id	= UCLASS_GPIO,
	.ops	= &hsdk_creg_gpio_ops,
	.probe	= hsdk_creg_gpio_probe,
	.of_match = hsdk_creg_gpio_ids,
	.plat_auto	= sizeof(struct hsdk_creg_gpio),
};
Commit	Line	Data
3194c3cd EP	1	/*
	2	* Synopsys HSDK SDP Generic PLL clock driver
	3	*
	4	* Copyright (C) 2017 Synopsys
	5	* Author: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
	6	*
	7	* This file is licensed under the terms of the GNU General Public
	8	* License version 2. This program is licensed "as is" without any
	9	* warranty of any kind, whether express or implied.
	10	*/
	11
f7ae49fc	12	#include <log.h>
3194c3cd EP	13	#include <asm-generic/gpio.h>
3194c3cd EP	14	#include <asm/io.h>
d678a59d	15	#include <common.h>
3194c3cd EP	16	#include <dm.h>
3194c3cd EP	17	#include <errno.h>
cd93d625	18	#include <linux/bitops.h>
3194c3cd EP	19	#include <linux/printk.h>
3194c3cd EP	20
fe3eb7a8	21	#define DRV_NAME "gpio_creg"
3194c3cd EP	22
3194c3cd EP	23	struct hsdk_creg_gpio {
fe3eb7a8 EP	24	u32 *regs;
	25	u8 shift;
	26	u8 activate;
	27	u8 deactivate;
	28	u8 bit_per_gpio;
3194c3cd EP	29	};
	30
	31	static int hsdk_creg_gpio_set_value(struct udevice *dev, unsigned oft, int val)
	32	{
	33	struct hsdk_creg_gpio *hcg = dev_get_priv(dev);
fe3eb7a8 EP	34	u8 reg_shift = oft * hcg->bit_per_gpio + hcg->shift;
fe3eb7a8 EP	35	u32 reg = readl(hcg->regs);
3194c3cd	36
fe3eb7a8 EP	37	reg &= ~(GENMASK(hcg->bit_per_gpio - 1, 0) << reg_shift);
fe3eb7a8 EP	38	reg \|= ((val ? hcg->deactivate : hcg->activate) << reg_shift);
3194c3cd EP	39
	40	writel(reg, hcg->regs);
	41
	42	return 0;
	43	}
	44
	45	static int hsdk_creg_gpio_direction_output(struct udevice *dev, unsigned oft,
	46	int val)
	47	{
	48	hsdk_creg_gpio_set_value(dev, oft, val);
	49
	50	return 0;
	51	}
	52
	53	static int hsdk_creg_gpio_direction_input(struct udevice *dev, unsigned oft)
	54	{
fe3eb7a8 EP	55	struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
	56
	57	pr_err("%s can't be used as input!\n", uc_priv->bank_name);
3194c3cd EP	58
	59	return -ENOTSUPP;
	60	}
	61
	62	static int hsdk_creg_gpio_get_value(struct udevice *dev, unsigned int oft)
	63	{
	64	struct hsdk_creg_gpio *hcg = dev_get_priv(dev);
fe3eb7a8	65	u32 val = readl(hcg->regs);
3194c3cd	66
fe3eb7a8 EP	67	val >>= oft * hcg->bit_per_gpio + hcg->shift;
	68	val &= GENMASK(hcg->bit_per_gpio - 1, 0);
	69	return (val == hcg->deactivate) ? 1 : 0;
3194c3cd EP	70	}
	71
	72	static const struct dm_gpio_ops hsdk_creg_gpio_ops = {
	73	.direction_output = hsdk_creg_gpio_direction_output,
	74	.direction_input = hsdk_creg_gpio_direction_input,
	75	.set_value = hsdk_creg_gpio_set_value,
	76	.get_value = hsdk_creg_gpio_get_value,
	77	};
	78
	79	static int hsdk_creg_gpio_probe(struct udevice *dev)
	80	{
	81	struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
	82	struct hsdk_creg_gpio *hcg = dev_get_priv(dev);
fe3eb7a8 EP	83	u32 shift, bit_per_gpio, activate, deactivate, gpio_count;
fe3eb7a8 EP	84	const u8 *defaults;
3194c3cd	85
702e57e1	86	hcg->regs = dev_read_addr_ptr(dev);
fe3eb7a8 EP	87	gpio_count = dev_read_u32_default(dev, "gpio-count", 1);
	88	shift = dev_read_u32_default(dev, "gpio-first-shift", 0);
	89	bit_per_gpio = dev_read_u32_default(dev, "gpio-bit-per-line", 1);
	90	activate = dev_read_u32_default(dev, "gpio-activate-val", 1);
	91	deactivate = dev_read_u32_default(dev, "gpio-deactivate-val", 0);
	92	defaults = dev_read_u8_array_ptr(dev, "gpio-default-val", gpio_count);
3194c3cd EP	93
	94	uc_priv->bank_name = dev_read_string(dev, "gpio-bank-name");
	95	if (!uc_priv->bank_name)
	96	uc_priv->bank_name = dev_read_name(dev);
	97
fe3eb7a8 EP	98	if (!bit_per_gpio) {
	99	pr_err("%s: 'gpio-bit-per-line' can't be 0\n",
	100	uc_priv->bank_name);
	101
	102	return -EINVAL;
	103	}
	104
	105	if (!gpio_count) {
	106	pr_err("%s: 'gpio-count' can't be 0\n",
	107	uc_priv->bank_name);
	108
	109	return -EINVAL;
	110	}
	111
	112	if ((gpio_count * bit_per_gpio + shift) > 32) {
	113	pr_err("%s: u32 io register overflow: try to use %u bits\n",
	114	uc_priv->bank_name, gpio_count * bit_per_gpio + shift);
	115
	116	return -EINVAL;
	117	}
	118
	119	if (GENMASK(31, bit_per_gpio) & activate) {
	120	pr_err("%s: 'gpio-activate-val' can't be more than %lu\n",
	121	uc_priv->bank_name, GENMASK(bit_per_gpio - 1, 0));
	122
	123	return -EINVAL;
	124	}
	125
	126	if (GENMASK(31, bit_per_gpio) & deactivate) {
	127	pr_err("%s: 'gpio-deactivate-val' can't be more than %lu\n",
	128	uc_priv->bank_name, GENMASK(bit_per_gpio - 1, 0));
	129
	130	return -EINVAL;
	131	}
	132
	133	if (activate == deactivate) {
	134	pr_err("%s: 'gpio-deactivate-val' and 'gpio-activate-val' can't be equal\n",
	135	uc_priv->bank_name);
	136
	137	return -EINVAL;
	138	}
	139
	140	hcg->shift = (u8)shift;
	141	hcg->bit_per_gpio = (u8)bit_per_gpio;
	142	hcg->activate = (u8)activate;
	143	hcg->deactivate = (u8)deactivate;
	144	uc_priv->gpio_count = gpio_count;
	145
	146	/* Setup default GPIO value if we have "gpio-default-val" array */
	147	if (defaults)
	148	for (u8 i = 0; i < gpio_count; i++)
	149	hsdk_creg_gpio_set_value(dev, i, defaults[i]);
	150
3194c3cd EP	151	pr_debug("%s GPIO [0x%p] controller with %d gpios probed\n",
	152	uc_priv->bank_name, hcg->regs, uc_priv->gpio_count);
	153
	154	return 0;
	155	}
	156
	157	static const struct udevice_id hsdk_creg_gpio_ids[] = {
fe3eb7a8	158	{ .compatible = "snps,creg-gpio" },
3194c3cd EP	159	{ }
	160	};
	161
	162	U_BOOT_DRIVER(gpio_hsdk_creg) = {
fe3eb7a8	163	.name = DRV_NAME,
3194c3cd EP	164	.id = UCLASS_GPIO,
	165	.ops = &hsdk_creg_gpio_ops,
	166	.probe = hsdk_creg_gpio_probe,
	167	.of_match = hsdk_creg_gpio_ids,
caa4daa2	168	.plat_auto = sizeof(struct hsdk_creg_gpio),
3194c3cd	169	};