[thirdparty/u-boot.git] / drivers / gpio / qcom_pmic_gpio.c

// SPDX-License-Identifier: GPL-2.0+
/*
 * Qualcomm generic pmic gpio driver
 *
 * (C) Copyright 2015 Mateusz Kulikowski <mateusz.kulikowski@gmail.com>
 */

#include <common.h>
#include <dm.h>
#include <dm/device-internal.h>
#include <dm/lists.h>
#include <dm/pinctrl.h>
#include <log.h>
#include <power/pmic.h>
#include <spmi/spmi.h>
#include <asm/io.h>
#include <stdlib.h>
#include <asm/gpio.h>
#include <linux/bitops.h>

/* Register offset for each gpio */
#define REG_OFFSET(x)          ((x) * 0x100)

/* Register maps */

/* Type and subtype are shared for all PMIC peripherals */
#define REG_TYPE               0x4
#define REG_SUBTYPE            0x5

/* GPIO peripheral type and subtype out_values */
#define REG_TYPE_VAL		0x10
#define REG_SUBTYPE_GPIO_4CH	0x1
#define REG_SUBTYPE_GPIOC_4CH	0x5
#define REG_SUBTYPE_GPIO_8CH	0x9
#define REG_SUBTYPE_GPIOC_8CH	0xd
#define REG_SUBTYPE_GPIO_LV	0x10
#define REG_SUBTYPE_GPIO_MV	0x11
#define REG_SUBTYPE_GPIO_LV_VIN2          0x12
#define REG_SUBTYPE_GPIO_MV_VIN3          0x13

#define REG_STATUS             0x08
#define REG_STATUS_VAL_MASK    0x1

/* MODE_CTL */
#define REG_CTL		0x40
#define REG_CTL_MODE_MASK       0x70
#define REG_CTL_MODE_INPUT      0x00
#define REG_CTL_MODE_INOUT      0x20
#define REG_CTL_MODE_OUTPUT     0x10
#define REG_CTL_OUTPUT_MASK     0x0F
#define REG_CTL_LV_MV_MODE_MASK		0x3
#define REG_CTL_LV_MV_MODE_INPUT	0x0
#define REG_CTL_LV_MV_MODE_INOUT	0x2
#define REG_CTL_LV_MV_MODE_OUTPUT	0x1

#define REG_DIG_VIN_CTL        0x41
#define REG_DIG_VIN_VIN0       0

#define REG_DIG_PULL_CTL       0x42
#define REG_DIG_PULL_NO_PU     0x5

#define REG_LV_MV_OUTPUT_CTL	0x44
#define REG_LV_MV_OUTPUT_CTL_MASK	0x80
#define REG_LV_MV_OUTPUT_CTL_SHIFT	7

#define REG_DIG_OUT_CTL        0x45
#define REG_DIG_OUT_CTL_CMOS   (0x0 << 4)
#define REG_DIG_OUT_CTL_DRIVE_L 0x1

#define REG_EN_CTL             0x46
#define REG_EN_CTL_ENABLE      (1 << 7)

/**
 * pmic_gpio_match_data - platform specific configuration
 *
 * @PMIC_MATCH_READONLY: treat all GPIOs as readonly, don't attempt to configure them.
 * This is a workaround for an unknown bug on some platforms where trying to write the
 * GPIO configuration registers causes the board to hang.
 */
enum pmic_gpio_quirks {
	QCOM_PMIC_QUIRK_READONLY = (1 << 0),
};

struct qcom_pmic_gpio_data {
	uint32_t pid; /* Peripheral ID on SPMI bus */
	bool     lv_mv_type; /* If subtype is GPIO_LV(0x10) or GPIO_MV(0x11) */
	u32 pin_count;
	struct udevice *pmic; /* Reference to pmic device for read/write */
};

/* dev can be the GPIO or pinctrl device */
static int _qcom_gpio_set_direction(struct udevice *dev, u32 offset, bool input, int value)
{
	struct qcom_pmic_gpio_data *plat = dev_get_plat(dev);
	u32 gpio_base = plat->pid + REG_OFFSET(offset);
	u32 reg_ctl_val;
	int ret = 0;

	/* Select the mode and output */
	if (plat->lv_mv_type) {
		if (input)
			reg_ctl_val = REG_CTL_LV_MV_MODE_INPUT;
		else
			reg_ctl_val = REG_CTL_LV_MV_MODE_INOUT;
	} else {
		if (input)
			reg_ctl_val = REG_CTL_MODE_INPUT;
		else
			reg_ctl_val = REG_CTL_MODE_INOUT | !!value;
	}

	ret = pmic_reg_write(plat->pmic, gpio_base + REG_CTL, reg_ctl_val);
	if (ret < 0)
		return ret;

	if (plat->lv_mv_type && !input) {
		ret = pmic_reg_write(plat->pmic,
				     gpio_base + REG_LV_MV_OUTPUT_CTL,
				     !!value << REG_LV_MV_OUTPUT_CTL_SHIFT);
		if (ret < 0)
			return ret;
	}

	return 0;
}

static int qcom_gpio_set_direction(struct udevice *dev, unsigned int offset,
				   bool input, int value)
{
	struct qcom_pmic_gpio_data *plat = dev_get_plat(dev);
	uint32_t gpio_base = plat->pid + REG_OFFSET(offset);
	ulong quirks = dev_get_driver_data(dev);
	int ret = 0;

	/* Some PMICs don't like their GPIOs being configured */
	if (quirks & QCOM_PMIC_QUIRK_READONLY)
		return 0;

	/* Disable the GPIO */
	ret = pmic_clrsetbits(dev->parent, gpio_base + REG_EN_CTL,
			      REG_EN_CTL_ENABLE, 0);
	if (ret < 0)
		return ret;

	_qcom_gpio_set_direction(dev, offset, input, value);

	/* Set the right pull (no pull) */
	ret = pmic_reg_write(plat->pmic, gpio_base + REG_DIG_PULL_CTL,
			     REG_DIG_PULL_NO_PU);
	if (ret < 0)
		return ret;

	/* Configure output pin drivers if needed */
	if (!input) {
		/* Select the VIN - VIN0, pin is input so it doesn't matter */
		ret = pmic_reg_write(plat->pmic, gpio_base + REG_DIG_VIN_CTL,
				     REG_DIG_VIN_VIN0);
		if (ret < 0)
			return ret;

		/* Set the right dig out control */
		ret = pmic_reg_write(plat->pmic, gpio_base + REG_DIG_OUT_CTL,
				     REG_DIG_OUT_CTL_CMOS |
				     REG_DIG_OUT_CTL_DRIVE_L);
		if (ret < 0)
			return ret;
	}

	/* Enable the GPIO */
	return pmic_clrsetbits(dev->parent, gpio_base + REG_EN_CTL, 0,
			       REG_EN_CTL_ENABLE);
}

static int qcom_gpio_direction_input(struct udevice *dev, unsigned offset)
{
	return qcom_gpio_set_direction(dev, offset, true, 0);
}

static int qcom_gpio_direction_output(struct udevice *dev, unsigned offset,
				      int value)
{
	return qcom_gpio_set_direction(dev, offset, false, value);
}

static int qcom_gpio_get_function(struct udevice *dev, unsigned offset)
{
	struct qcom_pmic_gpio_data *plat = dev_get_plat(dev);
	uint32_t gpio_base = plat->pid + REG_OFFSET(offset);
	int reg;

	reg = pmic_reg_read(plat->pmic, gpio_base + REG_CTL);
	if (reg < 0)
		return reg;

	if (plat->lv_mv_type) {
		switch (reg & REG_CTL_LV_MV_MODE_MASK) {
		case REG_CTL_LV_MV_MODE_INPUT:
			return GPIOF_INPUT;
		case REG_CTL_LV_MV_MODE_INOUT: /* Fallthrough */
		case REG_CTL_LV_MV_MODE_OUTPUT:
			return GPIOF_OUTPUT;
		default:
			return GPIOF_UNKNOWN;
		}
	} else {
		switch (reg & REG_CTL_MODE_MASK) {
		case REG_CTL_MODE_INPUT:
			return GPIOF_INPUT;
		case REG_CTL_MODE_INOUT: /* Fallthrough */
		case REG_CTL_MODE_OUTPUT:
			return GPIOF_OUTPUT;
		default:
			return GPIOF_UNKNOWN;
		}
	}
}

static int qcom_gpio_get_value(struct udevice *dev, unsigned offset)
{
	struct qcom_pmic_gpio_data *plat = dev_get_plat(dev);
	uint32_t gpio_base = plat->pid + REG_OFFSET(offset);
	int reg;

	reg = pmic_reg_read(plat->pmic, gpio_base + REG_STATUS);
	if (reg < 0)
		return reg;

	return !!(reg & REG_STATUS_VAL_MASK);
}

static int qcom_gpio_set_value(struct udevice *dev, unsigned offset,
			       int value)
{
	struct qcom_pmic_gpio_data *plat = dev_get_plat(dev);
	uint32_t gpio_base = plat->pid + REG_OFFSET(offset);

	/* Set the output value of the gpio */
	if (plat->lv_mv_type)
		return pmic_clrsetbits(dev->parent,
				       gpio_base + REG_LV_MV_OUTPUT_CTL,
				       REG_LV_MV_OUTPUT_CTL_MASK,
				       !!value << REG_LV_MV_OUTPUT_CTL_SHIFT);
	else
		return pmic_clrsetbits(dev->parent, gpio_base + REG_CTL,
				       REG_CTL_OUTPUT_MASK, !!value);
}

static int qcom_gpio_xlate(struct udevice *dev, struct gpio_desc *desc,
			   struct ofnode_phandle_args *args)
{
	struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);

	if (args->args_count < 1)
		return -EINVAL;

	/* GPIOs in DT are 1-based */
	desc->offset = args->args[0] - 1;
	if (desc->offset >= uc_priv->gpio_count)
		return -EINVAL;

	if (args->args_count < 2)
		return 0;

	desc->flags = gpio_flags_xlate(args->args[1]);

	return 0;
}

static const struct dm_gpio_ops qcom_gpio_ops = {
	.direction_input	= qcom_gpio_direction_input,
	.direction_output	= qcom_gpio_direction_output,
	.get_value		= qcom_gpio_get_value,
	.set_value		= qcom_gpio_set_value,
	.get_function		= qcom_gpio_get_function,
	.xlate			= qcom_gpio_xlate,
};

static int qcom_gpio_bind(struct udevice *dev)
{

	struct qcom_pmic_gpio_data *plat = dev_get_plat(dev);
	ulong quirks = dev_get_driver_data(dev);
	struct udevice *child;
	struct driver *drv;
	int ret;

	drv = lists_driver_lookup_name("qcom_pmic_pinctrl");
	if (!drv) {
		log_warning("Cannot find driver '%s'\n", "qcom_pmic_pinctrl");
		return -ENOENT;
	}

	/* Bind the GPIO driver as a child of the PMIC. */
	ret = device_bind_with_driver_data(dev, drv,
					   dev->name,
					   quirks, dev_ofnode(dev), &child);
	if (ret)
		return log_msg_ret("bind", ret);

	dev_set_plat(child, plat);

	return 0;
}

static int qcom_gpio_probe(struct udevice *dev)
{
	struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
	struct qcom_pmic_gpio_data *plat = dev_get_plat(dev);
	struct ofnode_phandle_args args;
	int val, ret;
	u64 pid;

	plat->pmic = dev->parent;

	pid = dev_read_addr(dev);
	if (pid == FDT_ADDR_T_NONE)
		return log_msg_ret("bad address", -EINVAL);

	plat->pid = pid;

	/* Do a sanity check */
	val = pmic_reg_read(plat->pmic, plat->pid + REG_TYPE);
	if (val != REG_TYPE_VAL)
		return log_msg_ret("bad type", -ENXIO);

	val = pmic_reg_read(plat->pmic, plat->pid + REG_SUBTYPE);
	switch (val) {
	case REG_SUBTYPE_GPIO_4CH:
	case REG_SUBTYPE_GPIOC_4CH:
		plat->lv_mv_type = false;
		break;
	case REG_SUBTYPE_GPIO_LV:
	case REG_SUBTYPE_GPIO_MV:
	case REG_SUBTYPE_GPIO_LV_VIN2:
	case REG_SUBTYPE_GPIO_MV_VIN3:
		plat->lv_mv_type = true;
		break;
	default:
		return log_msg_ret("bad subtype", -ENXIO);
	}

	plat->lv_mv_type = val == REG_SUBTYPE_GPIO_LV ||
			   val == REG_SUBTYPE_GPIO_MV;

	/*
	 * Parse basic GPIO count specified via the gpio-ranges property
	 * as specified in upstream devicetrees
	 */
	ret = ofnode_parse_phandle_with_args(dev_ofnode(dev), "gpio-ranges",
					     NULL, 3, 0, &args);
	if (ret)
		return log_msg_ret("gpio-ranges", ret);

	plat->pin_count = args.args[2];

	uc_priv->gpio_count = plat->pin_count;
	uc_priv->bank_name = "pmic";

	return 0;
}

static const struct udevice_id qcom_gpio_ids[] = {
	{ .compatible = "qcom,pm8916-gpio" },
	{ .compatible = "qcom,pm8994-gpio" },	/* 22 GPIO's */
	{ .compatible = "qcom,pm8998-gpio", .data = QCOM_PMIC_QUIRK_READONLY },
	{ .compatible = "qcom,pms405-gpio" },
	{ .compatible = "qcom,pm6125-gpio", .data = QCOM_PMIC_QUIRK_READONLY },
	{ .compatible = "qcom,pm8150-gpio", .data = QCOM_PMIC_QUIRK_READONLY },
	{ .compatible = "qcom,pm8550-gpio", .data = QCOM_PMIC_QUIRK_READONLY },
	{ }
};

U_BOOT_DRIVER(qcom_pmic_gpio) = {
	.name	= "qcom_pmic_gpio",
	.id	= UCLASS_GPIO,
	.of_match = qcom_gpio_ids,
	.bind	= qcom_gpio_bind,
	.probe = qcom_gpio_probe,
	.ops	= &qcom_gpio_ops,
	.plat_auto = sizeof(struct qcom_pmic_gpio_data),
	.flags = DM_FLAG_ALLOC_PDATA,
};

static const struct pinconf_param qcom_pmic_pinctrl_conf_params[] = {
	{ "output-high", PIN_CONFIG_OUTPUT_ENABLE, 1 },
	{ "output-low", PIN_CONFIG_OUTPUT, 0 },
};

static int qcom_pmic_pinctrl_get_pins_count(struct udevice *dev)
{
	struct qcom_pmic_gpio_data *plat = dev_get_plat(dev);

	return plat->pin_count;
}

static const char *qcom_pmic_pinctrl_get_pin_name(struct udevice *dev, unsigned int selector)
{
	static char name[8];

	/* DT indexes from 1 */
	snprintf(name, sizeof(name), "gpio%u", selector + 1);

	return name;
}

static int qcom_pmic_pinctrl_pinconf_set(struct udevice *dev, unsigned int selector,
					 unsigned int param, unsigned int arg)
{
	/* We only support configuring the pin as an output, either low or high */
	return _qcom_gpio_set_direction(dev, selector, false,
					param == PIN_CONFIG_OUTPUT_ENABLE);
}

static const char *qcom_pmic_pinctrl_get_function_name(struct udevice *dev, unsigned int selector)
{
	if (!selector)
		return "normal";
	return NULL;
}

static int qcom_pmic_pinctrl_generic_get_functions_count(struct udevice *dev)
{
	return 1;
}

static int qcom_pmic_pinctrl_generic_pinmux_set_mux(struct udevice *dev, unsigned int selector,
						    unsigned int func_selector)
{
	return 0;
}

struct pinctrl_ops qcom_pmic_pinctrl_ops = {
	.get_pins_count = qcom_pmic_pinctrl_get_pins_count,
	.get_pin_name = qcom_pmic_pinctrl_get_pin_name,
	.set_state = pinctrl_generic_set_state,
	.pinconf_num_params = ARRAY_SIZE(qcom_pmic_pinctrl_conf_params),
	.pinconf_params = qcom_pmic_pinctrl_conf_params,
	.pinconf_set = qcom_pmic_pinctrl_pinconf_set,
	.get_function_name = qcom_pmic_pinctrl_get_function_name,
	.get_functions_count = qcom_pmic_pinctrl_generic_get_functions_count,
	.pinmux_set = qcom_pmic_pinctrl_generic_pinmux_set_mux,
};

U_BOOT_DRIVER(qcom_pmic_pinctrl) = {
	.name	= "qcom_pmic_pinctrl",
	.id	= UCLASS_PINCTRL,
	.ops	= &qcom_pmic_pinctrl_ops,
};
Commit	Line	Data
83d290c5	1	// SPDX-License-Identifier: GPL-2.0+
120800df	2	/*
e555d4ca	3	* Qualcomm generic pmic gpio driver
120800df MK	4	*
120800df MK	5	* (C) Copyright 2015 Mateusz Kulikowski <mateusz.kulikowski@gmail.com>
120800df MK	6	*/
120800df MK	7
d678a59d	8	#include <common.h>
120800df	9	#include <dm.h>
eb2393d7 CC	10	#include <dm/device-internal.h>
	11	#include <dm/lists.h>
	12	#include <dm/pinctrl.h>
f7ae49fc	13	#include <log.h>
120800df MK	14	#include <power/pmic.h>
	15	#include <spmi/spmi.h>
	16	#include <asm/io.h>
eb2393d7	17	#include <stdlib.h>
120800df MK	18	#include <asm/gpio.h>
	19	#include <linux/bitops.h>
	20
120800df MK	21	/* Register offset for each gpio */
	22	#define REG_OFFSET(x) ((x) * 0x100)
	23
	24	/* Register maps */
	25
e555d4ca	26	/* Type and subtype are shared for all PMIC peripherals */
120800df MK	27	#define REG_TYPE 0x4
	28	#define REG_SUBTYPE 0x5
	29
cf515842 SG	30	/* GPIO peripheral type and subtype out_values */
	31	#define REG_TYPE_VAL 0x10
	32	#define REG_SUBTYPE_GPIO_4CH 0x1
	33	#define REG_SUBTYPE_GPIOC_4CH 0x5
	34	#define REG_SUBTYPE_GPIO_8CH 0x9
	35	#define REG_SUBTYPE_GPIOC_8CH 0xd
	36	#define REG_SUBTYPE_GPIO_LV 0x10
	37	#define REG_SUBTYPE_GPIO_MV 0x11
b6f1d335 NA	38	#define REG_SUBTYPE_GPIO_LV_VIN2 0x12
b6f1d335 NA	39	#define REG_SUBTYPE_GPIO_MV_VIN3 0x13
cf515842	40
120800df MK	41	#define REG_STATUS 0x08
	42	#define REG_STATUS_VAL_MASK 0x1
	43
	44	/* MODE_CTL */
e0cc0b6c	45	#define REG_CTL 0x40
120800df MK	46	#define REG_CTL_MODE_MASK 0x70
	47	#define REG_CTL_MODE_INPUT 0x00
	48	#define REG_CTL_MODE_INOUT 0x20
	49	#define REG_CTL_MODE_OUTPUT 0x10
	50	#define REG_CTL_OUTPUT_MASK 0x0F
cf515842 SG	51	#define REG_CTL_LV_MV_MODE_MASK 0x3
	52	#define REG_CTL_LV_MV_MODE_INPUT 0x0
	53	#define REG_CTL_LV_MV_MODE_INOUT 0x2
	54	#define REG_CTL_LV_MV_MODE_OUTPUT 0x1
120800df MK	55
	56	#define REG_DIG_VIN_CTL 0x41
	57	#define REG_DIG_VIN_VIN0 0
	58
	59	#define REG_DIG_PULL_CTL 0x42
	60	#define REG_DIG_PULL_NO_PU 0x5
	61
cf515842 SG	62	#define REG_LV_MV_OUTPUT_CTL 0x44
	63	#define REG_LV_MV_OUTPUT_CTL_MASK 0x80
	64	#define REG_LV_MV_OUTPUT_CTL_SHIFT 7
	65
120800df MK	66	#define REG_DIG_OUT_CTL 0x45
	67	#define REG_DIG_OUT_CTL_CMOS (0x0 << 4)
	68	#define REG_DIG_OUT_CTL_DRIVE_L 0x1
	69
	70	#define REG_EN_CTL 0x46
	71	#define REG_EN_CTL_ENABLE (1 << 7)
	72
19f000b7 CC	73	/**
	74	* pmic_gpio_match_data - platform specific configuration
	75	*
	76	* @PMIC_MATCH_READONLY: treat all GPIOs as readonly, don't attempt to configure them.
	77	* This is a workaround for an unknown bug on some platforms where trying to write the
	78	* GPIO configuration registers causes the board to hang.
	79	*/
	80	enum pmic_gpio_quirks {
	81	QCOM_PMIC_QUIRK_READONLY = (1 << 0),
	82	};
	83
eb2393d7	84	struct qcom_pmic_gpio_data {
aa997d1d	85	uint32_t pid; /* Peripheral ID on SPMI bus */
cf515842	86	bool lv_mv_type; /* If subtype is GPIO_LV(0x10) or GPIO_MV(0x11) */
eb2393d7 CC	87	u32 pin_count;
eb2393d7 CC	88	struct udevice pmic; / Reference to pmic device for read/write */
120800df MK	89	};
120800df MK	90
eb2393d7 CC	91	/* dev can be the GPIO or pinctrl device */
eb2393d7 CC	92	static int _qcom_gpio_set_direction(struct udevice *dev, u32 offset, bool input, int value)
120800df	93	{
eb2393d7 CC	94	struct qcom_pmic_gpio_data *plat = dev_get_plat(dev);
	95	u32 gpio_base = plat->pid + REG_OFFSET(offset);
	96	u32 reg_ctl_val;
19f000b7	97	int ret = 0;
120800df	98
cf515842	99	/* Select the mode and output */
eb2393d7	100	if (plat->lv_mv_type) {
cf515842 SG	101	if (input)
	102	reg_ctl_val = REG_CTL_LV_MV_MODE_INPUT;
	103	else
	104	reg_ctl_val = REG_CTL_LV_MV_MODE_INOUT;
	105	} else {
	106	if (input)
	107	reg_ctl_val = REG_CTL_MODE_INPUT;
	108	else
	109	reg_ctl_val = REG_CTL_MODE_INOUT \| !!value;
	110	}
	111
eb2393d7	112	ret = pmic_reg_write(plat->pmic, gpio_base + REG_CTL, reg_ctl_val);
120800df MK	113	if (ret < 0)
	114	return ret;
	115
eb2393d7 CC	116	if (plat->lv_mv_type && !input) {
eb2393d7 CC	117	ret = pmic_reg_write(plat->pmic,
cf515842 SG	118	gpio_base + REG_LV_MV_OUTPUT_CTL,
	119	!!value << REG_LV_MV_OUTPUT_CTL_SHIFT);
	120	if (ret < 0)
	121	return ret;
	122	}
	123
eb2393d7 CC	124	return 0;
	125	}
	126
	127	static int qcom_gpio_set_direction(struct udevice *dev, unsigned int offset,
	128	bool input, int value)
	129	{
	130	struct qcom_pmic_gpio_data *plat = dev_get_plat(dev);
	131	uint32_t gpio_base = plat->pid + REG_OFFSET(offset);
	132	ulong quirks = dev_get_driver_data(dev);
	133	int ret = 0;
	134
	135	/* Some PMICs don't like their GPIOs being configured */
	136	if (quirks & QCOM_PMIC_QUIRK_READONLY)
	137	return 0;
	138
	139	/* Disable the GPIO */
	140	ret = pmic_clrsetbits(dev->parent, gpio_base + REG_EN_CTL,
	141	REG_EN_CTL_ENABLE, 0);
	142	if (ret < 0)
	143	return ret;
	144
	145	_qcom_gpio_set_direction(dev, offset, input, value);
	146
120800df	147	/* Set the right pull (no pull) */
eb2393d7	148	ret = pmic_reg_write(plat->pmic, gpio_base + REG_DIG_PULL_CTL,
120800df MK	149	REG_DIG_PULL_NO_PU);
	150	if (ret < 0)
	151	return ret;
	152
	153	/* Configure output pin drivers if needed */
	154	if (!input) {
	155	/* Select the VIN - VIN0, pin is input so it doesn't matter */
eb2393d7	156	ret = pmic_reg_write(plat->pmic, gpio_base + REG_DIG_VIN_CTL,
120800df MK	157	REG_DIG_VIN_VIN0);
	158	if (ret < 0)
	159	return ret;
	160
	161	/* Set the right dig out control */
eb2393d7	162	ret = pmic_reg_write(plat->pmic, gpio_base + REG_DIG_OUT_CTL,
120800df MK	163	REG_DIG_OUT_CTL_CMOS \|
	164	REG_DIG_OUT_CTL_DRIVE_L);
	165	if (ret < 0)
	166	return ret;
	167	}
	168
	169	/* Enable the GPIO */
	170	return pmic_clrsetbits(dev->parent, gpio_base + REG_EN_CTL, 0,
	171	REG_EN_CTL_ENABLE);
	172	}
	173
e555d4ca	174	static int qcom_gpio_direction_input(struct udevice *dev, unsigned offset)
120800df	175	{
e555d4ca	176	return qcom_gpio_set_direction(dev, offset, true, 0);
120800df MK	177	}
120800df MK	178
e555d4ca SG	179	static int qcom_gpio_direction_output(struct udevice *dev, unsigned offset,
e555d4ca SG	180	int value)
120800df	181	{
e555d4ca	182	return qcom_gpio_set_direction(dev, offset, false, value);
120800df MK	183	}
120800df MK	184
e555d4ca	185	static int qcom_gpio_get_function(struct udevice *dev, unsigned offset)
120800df	186	{
eb2393d7 CC	187	struct qcom_pmic_gpio_data *plat = dev_get_plat(dev);
eb2393d7 CC	188	uint32_t gpio_base = plat->pid + REG_OFFSET(offset);
120800df MK	189	int reg;
120800df MK	190
eb2393d7	191	reg = pmic_reg_read(plat->pmic, gpio_base + REG_CTL);
120800df MK	192	if (reg < 0)
	193	return reg;
	194
eb2393d7	195	if (plat->lv_mv_type) {
cf515842 SG	196	switch (reg & REG_CTL_LV_MV_MODE_MASK) {
	197	case REG_CTL_LV_MV_MODE_INPUT:
	198	return GPIOF_INPUT;
	199	case REG_CTL_LV_MV_MODE_INOUT: /* Fallthrough */
	200	case REG_CTL_LV_MV_MODE_OUTPUT:
	201	return GPIOF_OUTPUT;
	202	default:
	203	return GPIOF_UNKNOWN;
	204	}
	205	} else {
	206	switch (reg & REG_CTL_MODE_MASK) {
	207	case REG_CTL_MODE_INPUT:
	208	return GPIOF_INPUT;
	209	case REG_CTL_MODE_INOUT: /* Fallthrough */
	210	case REG_CTL_MODE_OUTPUT:
	211	return GPIOF_OUTPUT;
	212	default:
	213	return GPIOF_UNKNOWN;
	214	}
120800df MK	215	}
	216	}
	217
e555d4ca	218	static int qcom_gpio_get_value(struct udevice *dev, unsigned offset)
120800df	219	{
eb2393d7 CC	220	struct qcom_pmic_gpio_data *plat = dev_get_plat(dev);
eb2393d7 CC	221	uint32_t gpio_base = plat->pid + REG_OFFSET(offset);
120800df MK	222	int reg;
120800df MK	223
eb2393d7	224	reg = pmic_reg_read(plat->pmic, gpio_base + REG_STATUS);
120800df MK	225	if (reg < 0)
	226	return reg;
	227
	228	return !!(reg & REG_STATUS_VAL_MASK);
	229	}
	230
e555d4ca SG	231	static int qcom_gpio_set_value(struct udevice *dev, unsigned offset,
e555d4ca SG	232	int value)
120800df	233	{
eb2393d7 CC	234	struct qcom_pmic_gpio_data *plat = dev_get_plat(dev);
eb2393d7 CC	235	uint32_t gpio_base = plat->pid + REG_OFFSET(offset);
120800df MK	236
120800df MK	237	/* Set the output value of the gpio */
eb2393d7	238	if (plat->lv_mv_type)
cf515842 SG	239	return pmic_clrsetbits(dev->parent,
	240	gpio_base + REG_LV_MV_OUTPUT_CTL,
	241	REG_LV_MV_OUTPUT_CTL_MASK,
	242	!!value << REG_LV_MV_OUTPUT_CTL_SHIFT);
	243	else
	244	return pmic_clrsetbits(dev->parent, gpio_base + REG_CTL,
	245	REG_CTL_OUTPUT_MASK, !!value);
120800df MK	246	}
120800df MK	247
a2ce3aac CC	248	static int qcom_gpio_xlate(struct udevice dev, struct gpio_desc desc,
	249	struct ofnode_phandle_args *args)
	250	{
	251	struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
	252
	253	if (args->args_count < 1)
	254	return -EINVAL;
	255
	256	/* GPIOs in DT are 1-based */
	257	desc->offset = args->args[0] - 1;
	258	if (desc->offset >= uc_priv->gpio_count)
	259	return -EINVAL;
	260
	261	if (args->args_count < 2)
	262	return 0;
	263
	264	desc->flags = gpio_flags_xlate(args->args[1]);
	265
	266	return 0;
	267	}
	268
e555d4ca SG	269	static const struct dm_gpio_ops qcom_gpio_ops = {
	270	.direction_input = qcom_gpio_direction_input,
	271	.direction_output = qcom_gpio_direction_output,
	272	.get_value = qcom_gpio_get_value,
	273	.set_value = qcom_gpio_set_value,
	274	.get_function = qcom_gpio_get_function,
a2ce3aac	275	.xlate = qcom_gpio_xlate,
120800df MK	276	};
120800df MK	277
eb2393d7 CC	278	static int qcom_gpio_bind(struct udevice *dev)
eb2393d7 CC	279	{
b9f5620a	280
eb2393d7 CC	281	struct qcom_pmic_gpio_data *plat = dev_get_plat(dev);
	282	ulong quirks = dev_get_driver_data(dev);
	283	struct udevice *child;
	284	struct driver *drv;
	285	int ret;
	286
	287	drv = lists_driver_lookup_name("qcom_pmic_pinctrl");
	288	if (!drv) {
	289	log_warning("Cannot find driver '%s'\n", "qcom_pmic_pinctrl");
	290	return -ENOENT;
	291	}
	292
	293	/* Bind the GPIO driver as a child of the PMIC. */
	294	ret = device_bind_with_driver_data(dev, drv,
	295	dev->name,
	296	quirks, dev_ofnode(dev), &child);
	297	if (ret)
	298	return log_msg_ret("bind", ret);
	299
	300	dev_set_plat(child, plat);
	301
	302	return 0;
	303	}
	304
e555d4ca	305	static int qcom_gpio_probe(struct udevice *dev)
120800df	306	{
eb2393d7 CC	307	struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
	308	struct qcom_pmic_gpio_data *plat = dev_get_plat(dev);
	309	struct ofnode_phandle_args args;
	310	int val, ret;
033f09b4	311	u64 pid;
120800df	312
eb2393d7 CC	313	plat->pmic = dev->parent;
eb2393d7 CC	314
033f09b4 CC	315	pid = dev_read_addr(dev);
033f09b4 CC	316	if (pid == FDT_ADDR_T_NONE)
a605b0f7	317	return log_msg_ret("bad address", -EINVAL);
120800df	318
eb2393d7	319	plat->pid = pid;
033f09b4	320
120800df	321	/* Do a sanity check */
eb2393d7 CC	322	val = pmic_reg_read(plat->pmic, plat->pid + REG_TYPE);
eb2393d7 CC	323	if (val != REG_TYPE_VAL)
a605b0f7	324	return log_msg_ret("bad type", -ENXIO);
120800df	325
eb2393d7	326	val = pmic_reg_read(plat->pmic, plat->pid + REG_SUBTYPE);
b6f1d335 NA	327	switch (val) {
	328	case REG_SUBTYPE_GPIO_4CH:
	329	case REG_SUBTYPE_GPIOC_4CH:
	330	plat->lv_mv_type = false;
	331	break;
	332	case REG_SUBTYPE_GPIO_LV:
	333	case REG_SUBTYPE_GPIO_MV:
	334	case REG_SUBTYPE_GPIO_LV_VIN2:
	335	case REG_SUBTYPE_GPIO_MV_VIN3:
	336	plat->lv_mv_type = true;
	337	break;
	338	default:
a605b0f7	339	return log_msg_ret("bad subtype", -ENXIO);
b6f1d335	340	}
120800df	341
eb2393d7 CC	342	plat->lv_mv_type = val == REG_SUBTYPE_GPIO_LV \|\|
eb2393d7 CC	343	val == REG_SUBTYPE_GPIO_MV;
ab421433	344
eb2393d7 CC	345	/*
	346	* Parse basic GPIO count specified via the gpio-ranges property
	347	* as specified in upstream devicetrees
	348	*/
ab421433 CC	349	ret = ofnode_parse_phandle_with_args(dev_ofnode(dev), "gpio-ranges",
	350	NULL, 3, 0, &args);
	351	if (ret)
	352	return log_msg_ret("gpio-ranges", ret);
	353
eb2393d7	354	plat->pin_count = args.args[2];
ab421433	355
eb2393d7	356	uc_priv->gpio_count = plat->pin_count;
ab421433	357	uc_priv->bank_name = "pmic";
120800df MK	358
	359	return 0;
	360	}
	361
e555d4ca	362	static const struct udevice_id qcom_gpio_ids[] = {
120800df	363	{ .compatible = "qcom,pm8916-gpio" },
e0cc0b6c	364	{ .compatible = "qcom,pm8994-gpio" }, /* 22 GPIO's */
19f000b7	365	{ .compatible = "qcom,pm8998-gpio", .data = QCOM_PMIC_QUIRK_READONLY },
cf515842	366	{ .compatible = "qcom,pms405-gpio" },
733f6d98	367	{ .compatible = "qcom,pm6125-gpio", .data = QCOM_PMIC_QUIRK_READONLY },
8bf1eb9a	368	{ .compatible = "qcom,pm8150-gpio", .data = QCOM_PMIC_QUIRK_READONLY },
b6f1d335	369	{ .compatible = "qcom,pm8550-gpio", .data = QCOM_PMIC_QUIRK_READONLY },
120800df MK	370	{ }
	371	};
	372
e555d4ca SG	373	U_BOOT_DRIVER(qcom_pmic_gpio) = {
e555d4ca SG	374	.name = "qcom_pmic_gpio",
120800df	375	.id = UCLASS_GPIO,
e555d4ca	376	.of_match = qcom_gpio_ids,
eb2393d7 CC	377	.bind = qcom_gpio_bind,
eb2393d7 CC	378	.probe = qcom_gpio_probe,
e555d4ca	379	.ops = &qcom_gpio_ops,
eb2393d7 CC	380	.plat_auto = sizeof(struct qcom_pmic_gpio_data),
eb2393d7 CC	381	.flags = DM_FLAG_ALLOC_PDATA,
120800df MK	382	};
120800df MK	383
eb2393d7 CC	384	static const struct pinconf_param qcom_pmic_pinctrl_conf_params[] = {
	385	{ "output-high", PIN_CONFIG_OUTPUT_ENABLE, 1 },
	386	{ "output-low", PIN_CONFIG_OUTPUT, 0 },
	387	};
	388
	389	static int qcom_pmic_pinctrl_get_pins_count(struct udevice *dev)
	390	{
	391	struct qcom_pmic_gpio_data *plat = dev_get_plat(dev);
	392
	393	return plat->pin_count;
	394	}
	395
	396	static const char qcom_pmic_pinctrl_get_pin_name(struct udevice dev, unsigned int selector)
	397	{
	398	static char name[8];
	399
	400	/* DT indexes from 1 */
	401	snprintf(name, sizeof(name), "gpio%u", selector + 1);
	402
	403	return name;
	404	}
	405
	406	static int qcom_pmic_pinctrl_pinconf_set(struct udevice *dev, unsigned int selector,
	407	unsigned int param, unsigned int arg)
	408	{
	409	/* We only support configuring the pin as an output, either low or high */
	410	return _qcom_gpio_set_direction(dev, selector, false,
	411	param == PIN_CONFIG_OUTPUT_ENABLE);
	412	}
	413
	414	static const char qcom_pmic_pinctrl_get_function_name(struct udevice dev, unsigned int selector)
	415	{
	416	if (!selector)
	417	return "normal";
	418	return NULL;
	419	}
	420
	421	static int qcom_pmic_pinctrl_generic_get_functions_count(struct udevice *dev)
	422	{
	423	return 1;
	424	}
	425
	426	static int qcom_pmic_pinctrl_generic_pinmux_set_mux(struct udevice *dev, unsigned int selector,
	427	unsigned int func_selector)
	428	{
	429	return 0;
	430	}
	431
	432	struct pinctrl_ops qcom_pmic_pinctrl_ops = {
	433	.get_pins_count = qcom_pmic_pinctrl_get_pins_count,
	434	.get_pin_name = qcom_pmic_pinctrl_get_pin_name,
	435	.set_state = pinctrl_generic_set_state,
	436	.pinconf_num_params = ARRAY_SIZE(qcom_pmic_pinctrl_conf_params),
	437	.pinconf_params = qcom_pmic_pinctrl_conf_params,
	438	.pinconf_set = qcom_pmic_pinctrl_pinconf_set,
	439	.get_function_name = qcom_pmic_pinctrl_get_function_name,
	440	.get_functions_count = qcom_pmic_pinctrl_generic_get_functions_count,
	441	.pinmux_set = qcom_pmic_pinctrl_generic_pinmux_set_mux,
120800df MK	442	};
120800df MK	443
eb2393d7 CC	444	U_BOOT_DRIVER(qcom_pmic_pinctrl) = {
	445	.name = "qcom_pmic_pinctrl",
	446	.id = UCLASS_PINCTRL,
	447	.ops = &qcom_pmic_pinctrl_ops,
	448	};