[people/ms/u-boot.git] / drivers / gpio / s5p_gpio.c

/*
 * (C) Copyright 2009 Samsung Electronics
 * Minkyu Kang <mk7.kang@samsung.com>
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#include <common.h>
#include <dm.h>
#include <errno.h>
#include <fdtdec.h>
#include <malloc.h>
#include <asm/io.h>
#include <asm/gpio.h>
#include <dm/device-internal.h>
#include <dt-bindings/gpio/gpio.h>

DECLARE_GLOBAL_DATA_PTR;

#define S5P_GPIO_GET_PIN(x)	(x % GPIO_PER_BANK)

#define CON_MASK(val)			(0xf << ((val) << 2))
#define CON_SFR(gpio, cfg)		((cfg) << ((gpio) << 2))
#define CON_SFR_UNSHIFT(val, gpio)	((val) >> ((gpio) << 2))

#define DAT_MASK(gpio)			(0x1 << (gpio))
#define DAT_SET(gpio)			(0x1 << (gpio))

#define PULL_MASK(gpio)		(0x3 << ((gpio) << 1))
#define PULL_MODE(gpio, pull)		((pull) << ((gpio) << 1))

#define DRV_MASK(gpio)			(0x3 << ((gpio) << 1))
#define DRV_SET(gpio, mode)		((mode) << ((gpio) << 1))
#define RATE_MASK(gpio)		(0x1 << (gpio + 16))
#define RATE_SET(gpio)			(0x1 << (gpio + 16))

/* Platform data for each bank */
struct exynos_gpio_platdata {
	struct s5p_gpio_bank *bank;
	const char *bank_name;	/* Name of port, e.g. 'gpa0" */
};

/* Information about each bank at run-time */
struct exynos_bank_info {
	struct s5p_gpio_bank *bank;
};

static struct s5p_gpio_bank *s5p_gpio_get_bank(unsigned int gpio)
{
	const struct gpio_info *data;
	unsigned int upto;
	int i, count;

	data = get_gpio_data();
	count = get_bank_num();
	upto = 0;

	for (i = 0; i < count; i++) {
		debug("i=%d, upto=%d\n", i, upto);
		if (gpio < data->max_gpio) {
			struct s5p_gpio_bank *bank;
			bank = (struct s5p_gpio_bank *)data->reg_addr;
			bank += (gpio - upto) / GPIO_PER_BANK;
			debug("gpio=%d, bank=%p\n", gpio, bank);
			return bank;
		}

		upto = data->max_gpio;
		data++;
	}

	return NULL;
}

static void s5p_gpio_cfg_pin(struct s5p_gpio_bank *bank, int gpio, int cfg)
{
	unsigned int value;

	value = readl(&bank->con);
	value &= ~CON_MASK(gpio);
	value |= CON_SFR(gpio, cfg);
	writel(value, &bank->con);
}

static void s5p_gpio_set_value(struct s5p_gpio_bank *bank, int gpio, int en)
{
	unsigned int value;

	value = readl(&bank->dat);
	value &= ~DAT_MASK(gpio);
	if (en)
		value |= DAT_SET(gpio);
	writel(value, &bank->dat);
}

#ifdef CONFIG_SPL_BUILD
/* Common GPIO API - SPL does not support driver model yet */
int gpio_set_value(unsigned gpio, int value)
{
	s5p_gpio_set_value(s5p_gpio_get_bank(gpio),
			   s5p_gpio_get_pin(gpio), value);

	return 0;
}
#else
static int s5p_gpio_get_cfg_pin(struct s5p_gpio_bank *bank, int gpio)
{
	unsigned int value;

	value = readl(&bank->con);
	value &= CON_MASK(gpio);
	return CON_SFR_UNSHIFT(value, gpio);
}

static unsigned int s5p_gpio_get_value(struct s5p_gpio_bank *bank, int gpio)
{
	unsigned int value;

	value = readl(&bank->dat);
	return !!(value & DAT_MASK(gpio));
}
#endif /* CONFIG_SPL_BUILD */

static void s5p_gpio_set_pull(struct s5p_gpio_bank *bank, int gpio, int mode)
{
	unsigned int value;

	value = readl(&bank->pull);
	value &= ~PULL_MASK(gpio);

	switch (mode) {
	case S5P_GPIO_PULL_DOWN:
	case S5P_GPIO_PULL_UP:
		value |= PULL_MODE(gpio, mode);
		break;
	default:
		break;
	}

	writel(value, &bank->pull);
}

static void s5p_gpio_set_drv(struct s5p_gpio_bank *bank, int gpio, int mode)
{
	unsigned int value;

	value = readl(&bank->drv);
	value &= ~DRV_MASK(gpio);

	switch (mode) {
	case S5P_GPIO_DRV_1X:
	case S5P_GPIO_DRV_2X:
	case S5P_GPIO_DRV_3X:
	case S5P_GPIO_DRV_4X:
		value |= DRV_SET(gpio, mode);
		break;
	default:
		return;
	}

	writel(value, &bank->drv);
}

static void s5p_gpio_set_rate(struct s5p_gpio_bank *bank, int gpio, int mode)
{
	unsigned int value;

	value = readl(&bank->drv);
	value &= ~RATE_MASK(gpio);

	switch (mode) {
	case S5P_GPIO_DRV_FAST:
	case S5P_GPIO_DRV_SLOW:
		value |= RATE_SET(gpio);
		break;
	default:
		return;
	}

	writel(value, &bank->drv);
}

int s5p_gpio_get_pin(unsigned gpio)
{
	return S5P_GPIO_GET_PIN(gpio);
}

/* Driver model interface */
#ifndef CONFIG_SPL_BUILD
/* set GPIO pin 'gpio' as an input */
static int exynos_gpio_direction_input(struct udevice *dev, unsigned offset)
{
	struct exynos_bank_info *state = dev_get_priv(dev);

	/* Configure GPIO direction as input. */
	s5p_gpio_cfg_pin(state->bank, offset, S5P_GPIO_INPUT);

	return 0;
}

/* set GPIO pin 'gpio' as an output, with polarity 'value' */
static int exynos_gpio_direction_output(struct udevice *dev, unsigned offset,
				       int value)
{
	struct exynos_bank_info *state = dev_get_priv(dev);

	/* Configure GPIO output value. */
	s5p_gpio_set_value(state->bank, offset, value);

	/* Configure GPIO direction as output. */
	s5p_gpio_cfg_pin(state->bank, offset, S5P_GPIO_OUTPUT);

	return 0;
}

/* read GPIO IN value of pin 'gpio' */
static int exynos_gpio_get_value(struct udevice *dev, unsigned offset)
{
	struct exynos_bank_info *state = dev_get_priv(dev);

	return s5p_gpio_get_value(state->bank, offset);
}

/* write GPIO OUT value to pin 'gpio' */
static int exynos_gpio_set_value(struct udevice *dev, unsigned offset,
				 int value)
{
	struct exynos_bank_info *state = dev_get_priv(dev);

	s5p_gpio_set_value(state->bank, offset, value);

	return 0;
}
#endif /* nCONFIG_SPL_BUILD */

/*
 * There is no common GPIO API for pull, drv, pin, rate (yet). These
 * functions are kept here to preserve function ordering for review.
 */
void gpio_set_pull(int gpio, int mode)
{
	s5p_gpio_set_pull(s5p_gpio_get_bank(gpio),
			  s5p_gpio_get_pin(gpio), mode);
}

void gpio_set_drv(int gpio, int mode)
{
	s5p_gpio_set_drv(s5p_gpio_get_bank(gpio),
			 s5p_gpio_get_pin(gpio), mode);
}

void gpio_cfg_pin(int gpio, int cfg)
{
	s5p_gpio_cfg_pin(s5p_gpio_get_bank(gpio),
			 s5p_gpio_get_pin(gpio), cfg);
}

void gpio_set_rate(int gpio, int mode)
{
	s5p_gpio_set_rate(s5p_gpio_get_bank(gpio),
			  s5p_gpio_get_pin(gpio), mode);
}

#ifndef CONFIG_SPL_BUILD
static int exynos_gpio_get_function(struct udevice *dev, unsigned offset)
{
	struct exynos_bank_info *state = dev_get_priv(dev);
	int cfg;

	cfg = s5p_gpio_get_cfg_pin(state->bank, offset);
	if (cfg == S5P_GPIO_OUTPUT)
		return GPIOF_OUTPUT;
	else if (cfg == S5P_GPIO_INPUT)
		return GPIOF_INPUT;
	else
		return GPIOF_FUNC;
}

static int exynos_gpio_xlate(struct udevice *dev, struct gpio_desc *desc,
			     struct fdtdec_phandle_args *args)
{
	desc->offset = args->args[0];
	desc->flags = args->args[1] & GPIO_ACTIVE_LOW ? GPIOD_ACTIVE_LOW : 0;

	return 0;
}

static const struct dm_gpio_ops gpio_exynos_ops = {
	.direction_input	= exynos_gpio_direction_input,
	.direction_output	= exynos_gpio_direction_output,
	.get_value		= exynos_gpio_get_value,
	.set_value		= exynos_gpio_set_value,
	.get_function		= exynos_gpio_get_function,
	.xlate			= exynos_gpio_xlate,
};

static int gpio_exynos_probe(struct udevice *dev)
{
	struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
	struct exynos_bank_info *priv = dev->priv;
	struct exynos_gpio_platdata *plat = dev->platdata;

	/* Only child devices have ports */
	if (!plat)
		return 0;

	priv->bank = plat->bank;

	uc_priv->gpio_count = GPIO_PER_BANK;
	uc_priv->bank_name = plat->bank_name;

	return 0;
}

/**
 * We have a top-level GPIO device with no actual GPIOs. It has a child
 * device for each Exynos GPIO bank.
 */
static int gpio_exynos_bind(struct udevice *parent)
{
	struct exynos_gpio_platdata *plat = parent->platdata;
	struct s5p_gpio_bank *bank, *base;
	const void *blob = gd->fdt_blob;
	int node;

	/* If this is a child device, there is nothing to do here */
	if (plat)
		return 0;

	base = (struct s5p_gpio_bank *)fdtdec_get_addr(gd->fdt_blob,
						   parent->of_offset, "reg");
	for (node = fdt_first_subnode(blob, parent->of_offset), bank = base;
	     node > 0;
	     node = fdt_next_subnode(blob, node), bank++) {
		struct exynos_gpio_platdata *plat;
		struct udevice *dev;
		fdt_addr_t reg;
		int ret;

		if (!fdtdec_get_bool(blob, node, "gpio-controller"))
			continue;
		plat = calloc(1, sizeof(*plat));
		if (!plat)
			return -ENOMEM;
		reg = fdtdec_get_addr(blob, node, "reg");
		if (reg != FDT_ADDR_T_NONE)
			bank = (struct s5p_gpio_bank *)((ulong)base + reg);
		plat->bank = bank;
		plat->bank_name = fdt_get_name(blob, node, NULL);
		debug("dev at %p: %s\n", bank, plat->bank_name);

		ret = device_bind(parent, parent->driver,
					plat->bank_name, plat, -1, &dev);
		if (ret)
			return ret;
		dev->of_offset = node;
	}

	return 0;
}

static const struct udevice_id exynos_gpio_ids[] = {
	{ .compatible = "samsung,s5pc100-pinctrl" },
	{ .compatible = "samsung,s5pc110-pinctrl" },
	{ .compatible = "samsung,exynos4210-pinctrl" },
	{ .compatible = "samsung,exynos4x12-pinctrl" },
	{ .compatible = "samsung,exynos5250-pinctrl" },
	{ .compatible = "samsung,exynos5420-pinctrl" },
	{ }
};

U_BOOT_DRIVER(gpio_exynos) = {
	.name	= "gpio_exynos",
	.id	= UCLASS_GPIO,
	.of_match = exynos_gpio_ids,
	.bind	= gpio_exynos_bind,
	.probe = gpio_exynos_probe,
	.priv_auto_alloc_size = sizeof(struct exynos_bank_info),
	.ops	= &gpio_exynos_ops,
};
#endif
Commit	Line	Data
ab693e9c MK	1	/*
	2	* (C) Copyright 2009 Samsung Electronics
	3	* Minkyu Kang <mk7.kang@samsung.com>
	4	*
1a459660	5	* SPDX-License-Identifier: GPL-2.0+
ab693e9c MK	6	*/
	7
	8	#include <common.h>
b8809e60 SG	9	#include <dm.h>
	10	#include <errno.h>
	11	#include <fdtdec.h>
	12	#include <malloc.h>
ab693e9c	13	#include <asm/io.h>
365d6070	14	#include <asm/gpio.h>
b8809e60	15	#include <dm/device-internal.h>
1d08b4b7	16	#include <dt-bindings/gpio/gpio.h>
b8809e60 SG	17
b8809e60 SG	18	DECLARE_GLOBAL_DATA_PTR;
ab693e9c	19
f6ae1ca0	20	#define S5P_GPIO_GET_PIN(x) (x % GPIO_PER_BANK)
8475c869	21
3a233dbf SG	22	#define CON_MASK(val) (0xf << ((val) << 2))
	23	#define CON_SFR(gpio, cfg) ((cfg) << ((gpio) << 2))
	24	#define CON_SFR_UNSHIFT(val, gpio) ((val) >> ((gpio) << 2))
ab693e9c	25
3a233dbf SG	26	#define DAT_MASK(gpio) (0x1 << (gpio))
3a233dbf SG	27	#define DAT_SET(gpio) (0x1 << (gpio))
ab693e9c	28
3a233dbf SG	29	#define PULL_MASK(gpio) (0x3 << ((gpio) << 1))
3a233dbf SG	30	#define PULL_MODE(gpio, pull) ((pull) << ((gpio) << 1))
ab693e9c	31
3a233dbf SG	32	#define DRV_MASK(gpio) (0x3 << ((gpio) << 1))
	33	#define DRV_SET(gpio, mode) ((mode) << ((gpio) << 1))
	34	#define RATE_MASK(gpio) (0x1 << (gpio + 16))
	35	#define RATE_SET(gpio) (0x1 << (gpio + 16))
ab693e9c	36
b8809e60 SG	37	/* Platform data for each bank */
	38	struct exynos_gpio_platdata {
	39	struct s5p_gpio_bank *bank;
	40	const char bank_name; / Name of port, e.g. 'gpa0" */
	41	};
	42
	43	/* Information about each bank at run-time */
	44	struct exynos_bank_info {
b8809e60 SG	45	struct s5p_gpio_bank *bank;
	46	};
	47
	48	static struct s5p_gpio_bank *s5p_gpio_get_bank(unsigned int gpio)
f6ae1ca0	49	{
b8809e60 SG	50	const struct gpio_info *data;
	51	unsigned int upto;
	52	int i, count;
f6ae1ca0	53
b8809e60 SG	54	data = get_gpio_data();
	55	count = get_bank_num();
	56	upto = 0;
	57
	58	for (i = 0; i < count; i++) {
	59	debug("i=%d, upto=%d\n", i, upto);
	60	if (gpio < data->max_gpio) {
	61	struct s5p_gpio_bank *bank;
	62	bank = (struct s5p_gpio_bank *)data->reg_addr;
	63	bank += (gpio - upto) / GPIO_PER_BANK;
	64	debug("gpio=%d, bank=%p\n", gpio, bank);
	65	return bank;
f6ae1ca0	66	}
f6ae1ca0	67
b8809e60 SG	68	upto = data->max_gpio;
	69	data++;
	70	}
	71
	72	return NULL;
f6ae1ca0 AS	73	}
	74
	75	static void s5p_gpio_cfg_pin(struct s5p_gpio_bank *bank, int gpio, int cfg)
ab693e9c MK	76	{
	77	unsigned int value;
	78
	79	value = readl(&bank->con);
	80	value &= ~CON_MASK(gpio);
	81	value \|= CON_SFR(gpio, cfg);
	82	writel(value, &bank->con);
	83	}
	84
f6ae1ca0	85	static void s5p_gpio_set_value(struct s5p_gpio_bank *bank, int gpio, int en)
ab693e9c MK	86	{
	87	unsigned int value;
	88
	89	value = readl(&bank->dat);
	90	value &= ~DAT_MASK(gpio);
	91	if (en)
	92	value \|= DAT_SET(gpio);
	93	writel(value, &bank->dat);
	94	}
	95
b8809e60 SG	96	#ifdef CONFIG_SPL_BUILD
	97	/* Common GPIO API - SPL does not support driver model yet */
	98	int gpio_set_value(unsigned gpio, int value)
f6ae1ca0	99	{
b8809e60 SG	100	s5p_gpio_set_value(s5p_gpio_get_bank(gpio),
b8809e60 SG	101	s5p_gpio_get_pin(gpio), value);
f6ae1ca0	102
b8809e60 SG	103	return 0;
	104	}
	105	#else
	106	static int s5p_gpio_get_cfg_pin(struct s5p_gpio_bank *bank, int gpio)
f6ae1ca0	107	{
b8809e60 SG	108	unsigned int value;
	109
	110	value = readl(&bank->con);
	111	value &= CON_MASK(gpio);
	112	return CON_SFR_UNSHIFT(value, gpio);
f6ae1ca0 AS	113	}
	114
	115	static unsigned int s5p_gpio_get_value(struct s5p_gpio_bank *bank, int gpio)
ab693e9c MK	116	{
	117	unsigned int value;
	118
	119	value = readl(&bank->dat);
	120	return !!(value & DAT_MASK(gpio));
	121	}
b8809e60	122	#endif /* CONFIG_SPL_BUILD */
ab693e9c	123
f6ae1ca0	124	static void s5p_gpio_set_pull(struct s5p_gpio_bank *bank, int gpio, int mode)
ab693e9c MK	125	{
	126	unsigned int value;
	127
	128	value = readl(&bank->pull);
	129	value &= ~PULL_MASK(gpio);
	130
	131	switch (mode) {
f6ae1ca0 AS	132	case S5P_GPIO_PULL_DOWN:
f6ae1ca0 AS	133	case S5P_GPIO_PULL_UP:
ab693e9c MK	134	value \|= PULL_MODE(gpio, mode);
	135	break;
	136	default:
ffb4b025	137	break;
ab693e9c MK	138	}
	139
	140	writel(value, &bank->pull);
	141	}
	142
f6ae1ca0	143	static void s5p_gpio_set_drv(struct s5p_gpio_bank *bank, int gpio, int mode)
ab693e9c MK	144	{
	145	unsigned int value;
	146
	147	value = readl(&bank->drv);
	148	value &= ~DRV_MASK(gpio);
	149
	150	switch (mode) {
f6ae1ca0 AS	151	case S5P_GPIO_DRV_1X:
	152	case S5P_GPIO_DRV_2X:
	153	case S5P_GPIO_DRV_3X:
	154	case S5P_GPIO_DRV_4X:
ab693e9c MK	155	value \|= DRV_SET(gpio, mode);
	156	break;
	157	default:
	158	return;
	159	}
	160
	161	writel(value, &bank->drv);
	162	}
	163
f6ae1ca0	164	static void s5p_gpio_set_rate(struct s5p_gpio_bank *bank, int gpio, int mode)
ab693e9c MK	165	{
	166	unsigned int value;
	167
	168	value = readl(&bank->drv);
	169	value &= ~RATE_MASK(gpio);
	170
	171	switch (mode) {
f6ae1ca0 AS	172	case S5P_GPIO_DRV_FAST:
f6ae1ca0 AS	173	case S5P_GPIO_DRV_SLOW:
ab693e9c MK	174	value \|= RATE_SET(gpio);
	175	break;
	176	default:
	177	return;
	178	}
	179
	180	writel(value, &bank->drv);
	181	}
9f15bc0c	182
b8809e60	183	int s5p_gpio_get_pin(unsigned gpio)
9f15bc0c	184	{
b8809e60 SG	185	return S5P_GPIO_GET_PIN(gpio);
b8809e60 SG	186	}
f6ae1ca0	187
b8809e60 SG	188	/* Driver model interface */
b8809e60 SG	189	#ifndef CONFIG_SPL_BUILD
b8809e60 SG	190	/* set GPIO pin 'gpio' as an input */
b8809e60 SG	191	static int exynos_gpio_direction_input(struct udevice *dev, unsigned offset)
9f15bc0c	192	{
b8809e60	193	struct exynos_bank_info *state = dev_get_priv(dev);
b8809e60 SG	194
	195	/* Configure GPIO direction as input. */
	196	s5p_gpio_cfg_pin(state->bank, offset, S5P_GPIO_INPUT);
365d6070	197
9f15bc0c ŁM	198	return 0;
	199	}
	200
b8809e60 SG	201	/* set GPIO pin 'gpio' as an output, with polarity 'value' */
	202	static int exynos_gpio_direction_output(struct udevice *dev, unsigned offset,
	203	int value)
9f15bc0c	204	{
b8809e60	205	struct exynos_bank_info *state = dev_get_priv(dev);
b8809e60 SG	206
	207	/* Configure GPIO output value. */
	208	s5p_gpio_set_value(state->bank, offset, value);
	209
	210	/* Configure GPIO direction as output. */
	211	s5p_gpio_cfg_pin(state->bank, offset, S5P_GPIO_OUTPUT);
	212
9f15bc0c ŁM	213	return 0;
	214	}
	215
b8809e60 SG	216	/* read GPIO IN value of pin 'gpio' */
b8809e60 SG	217	static int exynos_gpio_get_value(struct udevice *dev, unsigned offset)
9f15bc0c	218	{
b8809e60	219	struct exynos_bank_info *state = dev_get_priv(dev);
b8809e60 SG	220
b8809e60 SG	221	return s5p_gpio_get_value(state->bank, offset);
9f15bc0c ŁM	222	}
9f15bc0c ŁM	223
b8809e60 SG	224	/* write GPIO OUT value to pin 'gpio' */
	225	static int exynos_gpio_set_value(struct udevice *dev, unsigned offset,
	226	int value)
9f15bc0c	227	{
b8809e60	228	struct exynos_bank_info *state = dev_get_priv(dev);
b8809e60 SG	229
	230	s5p_gpio_set_value(state->bank, offset, value);
	231
365d6070	232	return 0;
9f15bc0c	233	}
b8809e60	234	#endif /* nCONFIG_SPL_BUILD */
f6ae1ca0	235
b8809e60 SG	236	/*
	237	* There is no common GPIO API for pull, drv, pin, rate (yet). These
	238	* functions are kept here to preserve function ordering for review.
	239	*/
f6ae1ca0 AS	240	void gpio_set_pull(int gpio, int mode)
	241	{
	242	s5p_gpio_set_pull(s5p_gpio_get_bank(gpio),
	243	s5p_gpio_get_pin(gpio), mode);
	244	}
	245
	246	void gpio_set_drv(int gpio, int mode)
	247	{
	248	s5p_gpio_set_drv(s5p_gpio_get_bank(gpio),
	249	s5p_gpio_get_pin(gpio), mode);
	250	}
	251
	252	void gpio_cfg_pin(int gpio, int cfg)
	253	{
	254	s5p_gpio_cfg_pin(s5p_gpio_get_bank(gpio),
	255	s5p_gpio_get_pin(gpio), cfg);
	256	}
	257
	258	void gpio_set_rate(int gpio, int mode)
	259	{
	260	s5p_gpio_set_rate(s5p_gpio_get_bank(gpio),
	261	s5p_gpio_get_pin(gpio), mode);
	262	}
b8809e60 SG	263
	264	#ifndef CONFIG_SPL_BUILD
	265	static int exynos_gpio_get_function(struct udevice *dev, unsigned offset)
	266	{
	267	struct exynos_bank_info *state = dev_get_priv(dev);
	268	int cfg;
	269
b8809e60 SG	270	cfg = s5p_gpio_get_cfg_pin(state->bank, offset);
	271	if (cfg == S5P_GPIO_OUTPUT)
	272	return GPIOF_OUTPUT;
	273	else if (cfg == S5P_GPIO_INPUT)
	274	return GPIOF_INPUT;
	275	else
	276	return GPIOF_FUNC;
	277	}
	278
1d08b4b7 SG	279	static int exynos_gpio_xlate(struct udevice dev, struct gpio_desc desc,
	280	struct fdtdec_phandle_args *args)
	281	{
	282	desc->offset = args->args[0];
	283	desc->flags = args->args[1] & GPIO_ACTIVE_LOW ? GPIOD_ACTIVE_LOW : 0;
	284
	285	return 0;
	286	}
	287
b8809e60	288	static const struct dm_gpio_ops gpio_exynos_ops = {
b8809e60 SG	289	.direction_input = exynos_gpio_direction_input,
	290	.direction_output = exynos_gpio_direction_output,
	291	.get_value = exynos_gpio_get_value,
	292	.set_value = exynos_gpio_set_value,
	293	.get_function = exynos_gpio_get_function,
1d08b4b7	294	.xlate = exynos_gpio_xlate,
b8809e60 SG	295	};
	296
	297	static int gpio_exynos_probe(struct udevice *dev)
	298	{
e564f054	299	struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
b8809e60 SG	300	struct exynos_bank_info *priv = dev->priv;
	301	struct exynos_gpio_platdata *plat = dev->platdata;
	302
	303	/* Only child devices have ports */
	304	if (!plat)
	305	return 0;
	306
	307	priv->bank = plat->bank;
	308
	309	uc_priv->gpio_count = GPIO_PER_BANK;
	310	uc_priv->bank_name = plat->bank_name;
	311
	312	return 0;
	313	}
	314
	315	/**
	316	* We have a top-level GPIO device with no actual GPIOs. It has a child
	317	* device for each Exynos GPIO bank.
	318	*/
	319	static int gpio_exynos_bind(struct udevice *parent)
	320	{
	321	struct exynos_gpio_platdata *plat = parent->platdata;
	322	struct s5p_gpio_bank bank, base;
	323	const void *blob = gd->fdt_blob;
	324	int node;
	325
	326	/* If this is a child device, there is nothing to do here */
	327	if (plat)
	328	return 0;
	329
	330	base = (struct s5p_gpio_bank *)fdtdec_get_addr(gd->fdt_blob,
	331	parent->of_offset, "reg");
	332	for (node = fdt_first_subnode(blob, parent->of_offset), bank = base;
	333	node > 0;
	334	node = fdt_next_subnode(blob, node), bank++) {
	335	struct exynos_gpio_platdata *plat;
	336	struct udevice *dev;
	337	fdt_addr_t reg;
	338	int ret;
	339
	340	if (!fdtdec_get_bool(blob, node, "gpio-controller"))
	341	continue;
	342	plat = calloc(1, sizeof(*plat));
	343	if (!plat)
	344	return -ENOMEM;
	345	reg = fdtdec_get_addr(blob, node, "reg");
	346	if (reg != FDT_ADDR_T_NONE)
	347	bank = (struct s5p_gpio_bank *)((ulong)base + reg);
	348	plat->bank = bank;
	349	plat->bank_name = fdt_get_name(blob, node, NULL);
	350	debug("dev at %p: %s\n", bank, plat->bank_name);
	351
	352	ret = device_bind(parent, parent->driver,
	353	plat->bank_name, plat, -1, &dev);
	354	if (ret)
	355	return ret;
1d08b4b7	356	dev->of_offset = node;
b8809e60 SG	357	}
	358
	359	return 0;
	360	}
	361
	362	static const struct udevice_id exynos_gpio_ids[] = {
	363	{ .compatible = "samsung,s5pc100-pinctrl" },
	364	{ .compatible = "samsung,s5pc110-pinctrl" },
	365	{ .compatible = "samsung,exynos4210-pinctrl" },
	366	{ .compatible = "samsung,exynos4x12-pinctrl" },
	367	{ .compatible = "samsung,exynos5250-pinctrl" },
	368	{ .compatible = "samsung,exynos5420-pinctrl" },
	369	{ }
	370	};
	371
	372	U_BOOT_DRIVER(gpio_exynos) = {
	373	.name = "gpio_exynos",
	374	.id = UCLASS_GPIO,
	375	.of_match = exynos_gpio_ids,
	376	.bind = gpio_exynos_bind,
	377	.probe = gpio_exynos_probe,
	378	.priv_auto_alloc_size = sizeof(struct exynos_bank_info),
	379	.ops = &gpio_exynos_ops,
	380	};
	381	#endif