[thirdparty/u-boot.git] / drivers / gpio / stm32_gpio.c

// SPDX-License-Identifier: GPL-2.0+
/*
 * Copyright (C) 2017, STMicroelectronics - All Rights Reserved
 * Author(s): Vikas Manocha, <vikas.manocha@st.com> for STMicroelectronics.
 */

#define LOG_CATEGORY UCLASS_GPIO

#include <common.h>
#include <clk.h>
#include <dm.h>
#include <fdtdec.h>
#include <log.h>
#include <asm/arch/stm32.h>
#include <asm/gpio.h>
#include <asm/io.h>
#include <dm/device_compat.h>
#include <linux/bitops.h>
#include <linux/errno.h>
#include <linux/io.h>

#include "stm32_gpio_priv.h"

#define STM32_GPIOS_PER_BANK		16

#define MODE_BITS(gpio_pin)		((gpio_pin) * 2)
#define MODE_BITS_MASK			3
#define BSRR_BIT(gpio_pin, value)	BIT((gpio_pin) + (value ? 0 : 16))

#define PUPD_BITS(gpio_pin)		((gpio_pin) * 2)
#define PUPD_MASK			3

#define OTYPE_BITS(gpio_pin)		(gpio_pin)
#define OTYPE_MSK			1

static void stm32_gpio_set_moder(struct stm32_gpio_regs *regs,
				 int idx,
				 int mode)
{
	int bits_index;
	int mask;

	bits_index = MODE_BITS(idx);
	mask = MODE_BITS_MASK << bits_index;

	clrsetbits_le32(&regs->moder, mask, mode << bits_index);
}

static int stm32_gpio_get_moder(struct stm32_gpio_regs *regs, int idx)
{
	return (readl(&regs->moder) >> MODE_BITS(idx)) & MODE_BITS_MASK;
}

static void stm32_gpio_set_otype(struct stm32_gpio_regs *regs,
				 int idx,
				 enum stm32_gpio_otype otype)
{
	int bits;

	bits = OTYPE_BITS(idx);
	clrsetbits_le32(&regs->otyper, OTYPE_MSK << bits, otype << bits);
}

static enum stm32_gpio_otype stm32_gpio_get_otype(struct stm32_gpio_regs *regs,
						  int idx)
{
	return (readl(&regs->otyper) >> OTYPE_BITS(idx)) & OTYPE_MSK;
}

static void stm32_gpio_set_pupd(struct stm32_gpio_regs *regs,
				int idx,
				enum stm32_gpio_pupd pupd)
{
	int bits;

	bits = PUPD_BITS(idx);
	clrsetbits_le32(&regs->pupdr, PUPD_MASK << bits, pupd << bits);
}

static enum stm32_gpio_pupd stm32_gpio_get_pupd(struct stm32_gpio_regs *regs,
						int idx)
{
	return (readl(&regs->pupdr) >> PUPD_BITS(idx)) & PUPD_MASK;
}

static bool stm32_gpio_is_mapped(struct udevice *dev, int offset)
{
	struct stm32_gpio_priv *priv = dev_get_priv(dev);

	return !!(priv->gpio_range & BIT(offset));
}

static int stm32_gpio_direction_input(struct udevice *dev, unsigned offset)
{
	struct stm32_gpio_priv *priv = dev_get_priv(dev);
	struct stm32_gpio_regs *regs = priv->regs;

	if (!stm32_gpio_is_mapped(dev, offset))
		return -ENXIO;

	stm32_gpio_set_moder(regs, offset, STM32_GPIO_MODE_IN);

	return 0;
}

static int stm32_gpio_direction_output(struct udevice *dev, unsigned offset,
				       int value)
{
	struct stm32_gpio_priv *priv = dev_get_priv(dev);
	struct stm32_gpio_regs *regs = priv->regs;

	if (!stm32_gpio_is_mapped(dev, offset))
		return -ENXIO;

	stm32_gpio_set_moder(regs, offset, STM32_GPIO_MODE_OUT);

	writel(BSRR_BIT(offset, value), &regs->bsrr);

	return 0;
}

static int stm32_gpio_get_value(struct udevice *dev, unsigned offset)
{
	struct stm32_gpio_priv *priv = dev_get_priv(dev);
	struct stm32_gpio_regs *regs = priv->regs;

	if (!stm32_gpio_is_mapped(dev, offset))
		return -ENXIO;

	return readl(&regs->idr) & BIT(offset) ? 1 : 0;
}

static int stm32_gpio_set_value(struct udevice *dev, unsigned offset, int value)
{
	struct stm32_gpio_priv *priv = dev_get_priv(dev);
	struct stm32_gpio_regs *regs = priv->regs;

	if (!stm32_gpio_is_mapped(dev, offset))
		return -ENXIO;

	writel(BSRR_BIT(offset, value), &regs->bsrr);

	return 0;
}

static int stm32_gpio_get_function(struct udevice *dev, unsigned int offset)
{
	struct stm32_gpio_priv *priv = dev_get_priv(dev);
	struct stm32_gpio_regs *regs = priv->regs;
	int bits_index;
	int mask;
	u32 mode;

	if (!stm32_gpio_is_mapped(dev, offset))
		return GPIOF_UNKNOWN;

	bits_index = MODE_BITS(offset);
	mask = MODE_BITS_MASK << bits_index;

	mode = (readl(&regs->moder) & mask) >> bits_index;
	if (mode == STM32_GPIO_MODE_OUT)
		return GPIOF_OUTPUT;
	if (mode == STM32_GPIO_MODE_IN)
		return GPIOF_INPUT;
	if (mode == STM32_GPIO_MODE_AN)
		return GPIOF_UNUSED;

	return GPIOF_FUNC;
}

static int stm32_gpio_set_flags(struct udevice *dev, unsigned int offset,
				ulong flags)
{
	struct stm32_gpio_priv *priv = dev_get_priv(dev);
	struct stm32_gpio_regs *regs = priv->regs;

	if (!stm32_gpio_is_mapped(dev, offset))
		return -ENXIO;

	if (flags & GPIOD_IS_OUT) {
		bool value = flags & GPIOD_IS_OUT_ACTIVE;

		if (flags & GPIOD_OPEN_DRAIN)
			stm32_gpio_set_otype(regs, offset, STM32_GPIO_OTYPE_OD);
		else
			stm32_gpio_set_otype(regs, offset, STM32_GPIO_OTYPE_PP);

		stm32_gpio_set_moder(regs, offset, STM32_GPIO_MODE_OUT);
		writel(BSRR_BIT(offset, value), &regs->bsrr);

	} else if (flags & GPIOD_IS_IN) {
		stm32_gpio_set_moder(regs, offset, STM32_GPIO_MODE_IN);
	}
	if (flags & GPIOD_PULL_UP)
		stm32_gpio_set_pupd(regs, offset, STM32_GPIO_PUPD_UP);
	else if (flags & GPIOD_PULL_DOWN)
		stm32_gpio_set_pupd(regs, offset, STM32_GPIO_PUPD_DOWN);

	return 0;
}

static int stm32_gpio_get_flags(struct udevice *dev, unsigned int offset,
				ulong *flagsp)
{
	struct stm32_gpio_priv *priv = dev_get_priv(dev);
	struct stm32_gpio_regs *regs = priv->regs;
	ulong dir_flags = 0;

	if (!stm32_gpio_is_mapped(dev, offset))
		return -ENXIO;

	switch (stm32_gpio_get_moder(regs, offset)) {
	case STM32_GPIO_MODE_OUT:
		dir_flags |= GPIOD_IS_OUT;
		if (stm32_gpio_get_otype(regs, offset) == STM32_GPIO_OTYPE_OD)
			dir_flags |= GPIOD_OPEN_DRAIN;
		if (readl(&regs->idr) & BIT(offset))
			dir_flags |= GPIOD_IS_OUT_ACTIVE;
		break;
	case STM32_GPIO_MODE_IN:
		dir_flags |= GPIOD_IS_IN;
		break;
	default:
		break;
	}
	switch (stm32_gpio_get_pupd(regs, offset)) {
	case STM32_GPIO_PUPD_UP:
		dir_flags |= GPIOD_PULL_UP;
		break;
	case STM32_GPIO_PUPD_DOWN:
		dir_flags |= GPIOD_PULL_DOWN;
		break;
	default:
		break;
	}
	*flagsp = dir_flags;

	return 0;
}

static const struct dm_gpio_ops gpio_stm32_ops = {
	.direction_input	= stm32_gpio_direction_input,
	.direction_output	= stm32_gpio_direction_output,
	.get_value		= stm32_gpio_get_value,
	.set_value		= stm32_gpio_set_value,
	.get_function		= stm32_gpio_get_function,
	.set_flags		= stm32_gpio_set_flags,
	.get_flags		= stm32_gpio_get_flags,
};

static int gpio_stm32_probe(struct udevice *dev)
{
	struct stm32_gpio_priv *priv = dev_get_priv(dev);
	struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
	struct ofnode_phandle_args args;
	const char *name;
	struct clk clk;
	fdt_addr_t addr;
	int ret, i;

	addr = dev_read_addr(dev);
	if (addr == FDT_ADDR_T_NONE)
		return -EINVAL;

	priv->regs = (struct stm32_gpio_regs *)addr;

	name = dev_read_string(dev, "st,bank-name");
	if (!name)
		return -EINVAL;
	uc_priv->bank_name = name;

	i = 0;
	ret = dev_read_phandle_with_args(dev, "gpio-ranges",
					 NULL, 3, i, &args);

	if (!ret && args.args_count < 3)
		return -EINVAL;

	uc_priv->gpio_count = STM32_GPIOS_PER_BANK;
	if (ret == -ENOENT)
		priv->gpio_range = GENMASK(STM32_GPIOS_PER_BANK - 1, 0);

	while (ret != -ENOENT) {
		priv->gpio_range |= GENMASK(args.args[2] + args.args[0] - 1,
				    args.args[0]);

		ret = dev_read_phandle_with_args(dev, "gpio-ranges", NULL, 3,
						 ++i, &args);
		if (!ret && args.args_count < 3)
			return -EINVAL;
	}

	dev_dbg(dev, "addr = 0x%p bank_name = %s gpio_count = %d gpio_range = 0x%x\n",
		(u32 *)priv->regs, uc_priv->bank_name, uc_priv->gpio_count,
		priv->gpio_range);

	ret = clk_get_by_index(dev, 0, &clk);
	if (ret < 0)
		return ret;

	ret = clk_enable(&clk);

	if (ret) {
		dev_err(dev, "failed to enable clock\n");
		return ret;
	}
	dev_dbg(dev, "clock enabled\n");

	return 0;
}

U_BOOT_DRIVER(gpio_stm32) = {
	.name	= "gpio_stm32",
	.id	= UCLASS_GPIO,
	.probe	= gpio_stm32_probe,
	.ops	= &gpio_stm32_ops,
	.flags	= DM_UC_FLAG_SEQ_ALIAS,
	.priv_auto	= sizeof(struct stm32_gpio_priv),
};
Commit	Line	Data
83d290c5	1	// SPDX-License-Identifier: GPL-2.0+
77417102	2	/*
3bc599c9 PC	3	* Copyright (C) 2017, STMicroelectronics - All Rights Reserved
3bc599c9 PC	4	* Author(s): Vikas Manocha, <vikas.manocha@st.com> for STMicroelectronics.
77417102 VM	5	*/
77417102 VM	6
6dd89d9d PD	7	#define LOG_CATEGORY UCLASS_GPIO
6dd89d9d PD	8
d678a59d	9	#include <common.h>
77417102 VM	10	#include <clk.h>
	11	#include <dm.h>
	12	#include <fdtdec.h>
f7ae49fc	13	#include <log.h>
77417102 VM	14	#include <asm/arch/stm32.h>
	15	#include <asm/gpio.h>
	16	#include <asm/io.h>
336d4615	17	#include <dm/device_compat.h>
cd93d625	18	#include <linux/bitops.h>
77417102 VM	19	#include <linux/errno.h>
	20	#include <linux/io.h>
	21
56a368f6 PD	22	#include "stm32_gpio_priv.h"
56a368f6 PD	23
6af78d03 PD	24	#define STM32_GPIOS_PER_BANK 16
6af78d03 PD	25
f13ff88b	26	#define MODE_BITS(gpio_pin) ((gpio_pin) * 2)
77417102	27	#define MODE_BITS_MASK 3
f13ff88b PD	28	#define BSRR_BIT(gpio_pin, value) BIT((gpio_pin) + (value ? 0 : 16))
	29
	30	#define PUPD_BITS(gpio_pin) ((gpio_pin) * 2)
	31	#define PUPD_MASK 3
	32
	33	#define OTYPE_BITS(gpio_pin) (gpio_pin)
	34	#define OTYPE_MSK 1
	35
	36	static void stm32_gpio_set_moder(struct stm32_gpio_regs *regs,
	37	int idx,
	38	int mode)
	39	{
	40	int bits_index;
	41	int mask;
	42
	43	bits_index = MODE_BITS(idx);
	44	mask = MODE_BITS_MASK << bits_index;
	45
	46	clrsetbits_le32(&regs->moder, mask, mode << bits_index);
	47	}
	48
43efbb6a PD	49	static int stm32_gpio_get_moder(struct stm32_gpio_regs *regs, int idx)
	50	{
	51	return (readl(&regs->moder) >> MODE_BITS(idx)) & MODE_BITS_MASK;
	52	}
	53
f13ff88b PD	54	static void stm32_gpio_set_otype(struct stm32_gpio_regs *regs,
	55	int idx,
	56	enum stm32_gpio_otype otype)
	57	{
	58	int bits;
	59
	60	bits = OTYPE_BITS(idx);
	61	clrsetbits_le32(&regs->otyper, OTYPE_MSK << bits, otype << bits);
	62	}
	63
43efbb6a PD	64	static enum stm32_gpio_otype stm32_gpio_get_otype(struct stm32_gpio_regs *regs,
	65	int idx)
	66	{
	67	return (readl(&regs->otyper) >> OTYPE_BITS(idx)) & OTYPE_MSK;
	68	}
	69
f13ff88b PD	70	static void stm32_gpio_set_pupd(struct stm32_gpio_regs *regs,
	71	int idx,
	72	enum stm32_gpio_pupd pupd)
	73	{
	74	int bits;
	75
	76	bits = PUPD_BITS(idx);
	77	clrsetbits_le32(&regs->pupdr, PUPD_MASK << bits, pupd << bits);
	78	}
77417102	79
43efbb6a PD	80	static enum stm32_gpio_pupd stm32_gpio_get_pupd(struct stm32_gpio_regs *regs,
	81	int idx)
	82	{
	83	return (readl(&regs->pupdr) >> PUPD_BITS(idx)) & PUPD_MASK;
	84	}
	85
427f452c	86	static bool stm32_gpio_is_mapped(struct udevice *dev, int offset)
dbf928dd PC	87	{
dbf928dd PC	88	struct stm32_gpio_priv *priv = dev_get_priv(dev);
427f452c PC	89
427f452c PC	90	return !!(priv->gpio_range & BIT(offset));
dbf928dd PC	91	}
dbf928dd PC	92
77417102 VM	93	static int stm32_gpio_direction_input(struct udevice *dev, unsigned offset)
	94	{
	95	struct stm32_gpio_priv *priv = dev_get_priv(dev);
	96	struct stm32_gpio_regs *regs = priv->regs;
dbf928dd	97
427f452c PC	98	if (!stm32_gpio_is_mapped(dev, offset))
427f452c PC	99	return -ENXIO;
dbf928dd	100
427f452c	101	stm32_gpio_set_moder(regs, offset, STM32_GPIO_MODE_IN);
77417102 VM	102
	103	return 0;
	104	}
	105
	106	static int stm32_gpio_direction_output(struct udevice *dev, unsigned offset,
	107	int value)
	108	{
	109	struct stm32_gpio_priv *priv = dev_get_priv(dev);
	110	struct stm32_gpio_regs *regs = priv->regs;
dbf928dd	111
427f452c PC	112	if (!stm32_gpio_is_mapped(dev, offset))
427f452c PC	113	return -ENXIO;
dbf928dd	114
427f452c	115	stm32_gpio_set_moder(regs, offset, STM32_GPIO_MODE_OUT);
798cd708	116
427f452c	117	writel(BSRR_BIT(offset, value), &regs->bsrr);
77417102 VM	118
	119	return 0;
	120	}
	121
	122	static int stm32_gpio_get_value(struct udevice *dev, unsigned offset)
	123	{
	124	struct stm32_gpio_priv *priv = dev_get_priv(dev);
	125	struct stm32_gpio_regs *regs = priv->regs;
dbf928dd	126
427f452c PC	127	if (!stm32_gpio_is_mapped(dev, offset))
427f452c PC	128	return -ENXIO;
77417102	129
427f452c	130	return readl(&regs->idr) & BIT(offset) ? 1 : 0;
77417102 VM	131	}
	132
	133	static int stm32_gpio_set_value(struct udevice *dev, unsigned offset, int value)
	134	{
	135	struct stm32_gpio_priv *priv = dev_get_priv(dev);
	136	struct stm32_gpio_regs *regs = priv->regs;
77417102	137
427f452c PC	138	if (!stm32_gpio_is_mapped(dev, offset))
427f452c PC	139	return -ENXIO;
dbf928dd	140
427f452c	141	writel(BSRR_BIT(offset, value), &regs->bsrr);
77417102 VM	142
	143	return 0;
	144	}
	145
cad73249 PC	146	static int stm32_gpio_get_function(struct udevice *dev, unsigned int offset)
	147	{
	148	struct stm32_gpio_priv *priv = dev_get_priv(dev);
	149	struct stm32_gpio_regs *regs = priv->regs;
dbf928dd PC	150	int bits_index;
dbf928dd PC	151	int mask;
cad73249 PC	152	u32 mode;
cad73249 PC	153
427f452c PC	154	if (!stm32_gpio_is_mapped(dev, offset))
427f452c PC	155	return GPIOF_UNKNOWN;
dbf928dd	156
427f452c	157	bits_index = MODE_BITS(offset);
dbf928dd PC	158	mask = MODE_BITS_MASK << bits_index;
dbf928dd PC	159
cad73249 PC	160	mode = (readl(&regs->moder) & mask) >> bits_index;
	161	if (mode == STM32_GPIO_MODE_OUT)
	162	return GPIOF_OUTPUT;
	163	if (mode == STM32_GPIO_MODE_IN)
	164	return GPIOF_INPUT;
	165	if (mode == STM32_GPIO_MODE_AN)
	166	return GPIOF_UNUSED;
	167
	168	return GPIOF_FUNC;
	169	}
	170
13979fc4 SG	171	static int stm32_gpio_set_flags(struct udevice *dev, unsigned int offset,
13979fc4 SG	172	ulong flags)
f13ff88b PD	173	{
	174	struct stm32_gpio_priv *priv = dev_get_priv(dev);
	175	struct stm32_gpio_regs *regs = priv->regs;
f13ff88b	176
427f452c PC	177	if (!stm32_gpio_is_mapped(dev, offset))
427f452c PC	178	return -ENXIO;
f13ff88b PD	179
f13ff88b PD	180	if (flags & GPIOD_IS_OUT) {
7e0a96d5	181	bool value = flags & GPIOD_IS_OUT_ACTIVE;
f13ff88b PD	182
f13ff88b PD	183	if (flags & GPIOD_OPEN_DRAIN)
427f452c	184	stm32_gpio_set_otype(regs, offset, STM32_GPIO_OTYPE_OD);
f13ff88b	185	else
427f452c	186	stm32_gpio_set_otype(regs, offset, STM32_GPIO_OTYPE_PP);
7e0a96d5	187
427f452c PC	188	stm32_gpio_set_moder(regs, offset, STM32_GPIO_MODE_OUT);
427f452c PC	189	writel(BSRR_BIT(offset, value), &regs->bsrr);
f13ff88b PD	190
f13ff88b PD	191	} else if (flags & GPIOD_IS_IN) {
427f452c	192	stm32_gpio_set_moder(regs, offset, STM32_GPIO_MODE_IN);
f13ff88b	193	}
2c6df94c	194	if (flags & GPIOD_PULL_UP)
427f452c	195	stm32_gpio_set_pupd(regs, offset, STM32_GPIO_PUPD_UP);
2c6df94c	196	else if (flags & GPIOD_PULL_DOWN)
427f452c	197	stm32_gpio_set_pupd(regs, offset, STM32_GPIO_PUPD_DOWN);
f13ff88b PD	198
	199	return 0;
	200	}
	201
9648789e SG	202	static int stm32_gpio_get_flags(struct udevice *dev, unsigned int offset,
9648789e SG	203	ulong *flagsp)
43efbb6a PD	204	{
	205	struct stm32_gpio_priv *priv = dev_get_priv(dev);
	206	struct stm32_gpio_regs *regs = priv->regs;
43efbb6a PD	207	ulong dir_flags = 0;
43efbb6a PD	208
427f452c PC	209	if (!stm32_gpio_is_mapped(dev, offset))
427f452c PC	210	return -ENXIO;
43efbb6a	211
427f452c	212	switch (stm32_gpio_get_moder(regs, offset)) {
43efbb6a PD	213	case STM32_GPIO_MODE_OUT:
43efbb6a PD	214	dir_flags \|= GPIOD_IS_OUT;
427f452c	215	if (stm32_gpio_get_otype(regs, offset) == STM32_GPIO_OTYPE_OD)
43efbb6a	216	dir_flags \|= GPIOD_OPEN_DRAIN;
427f452c	217	if (readl(&regs->idr) & BIT(offset))
43efbb6a PD	218	dir_flags \|= GPIOD_IS_OUT_ACTIVE;
	219	break;
	220	case STM32_GPIO_MODE_IN:
	221	dir_flags \|= GPIOD_IS_IN;
2c6df94c PD	222	break;
	223	default:
	224	break;
	225	}
427f452c	226	switch (stm32_gpio_get_pupd(regs, offset)) {
2c6df94c PD	227	case STM32_GPIO_PUPD_UP:
	228	dir_flags \|= GPIOD_PULL_UP;
	229	break;
	230	case STM32_GPIO_PUPD_DOWN:
	231	dir_flags \|= GPIOD_PULL_DOWN;
43efbb6a PD	232	break;
	233	default:
	234	break;
	235	}
9648789e	236	*flagsp = dir_flags;
43efbb6a PD	237
	238	return 0;
	239	}
	240
77417102 VM	241	static const struct dm_gpio_ops gpio_stm32_ops = {
	242	.direction_input = stm32_gpio_direction_input,
	243	.direction_output = stm32_gpio_direction_output,
	244	.get_value = stm32_gpio_get_value,
	245	.set_value = stm32_gpio_set_value,
cad73249	246	.get_function = stm32_gpio_get_function,
13979fc4	247	.set_flags = stm32_gpio_set_flags,
9648789e	248	.get_flags = stm32_gpio_get_flags,
77417102 VM	249	};
	250
	251	static int gpio_stm32_probe(struct udevice *dev)
	252	{
77417102	253	struct stm32_gpio_priv *priv = dev_get_priv(dev);
15c8cbfc PD	254	struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
	255	struct ofnode_phandle_args args;
	256	const char *name;
8b6d45ab	257	struct clk clk;
77417102	258	fdt_addr_t addr;
15c8cbfc	259	int ret, i;
77417102	260
d876eaf2	261	addr = dev_read_addr(dev);
77417102 VM	262	if (addr == FDT_ADDR_T_NONE)
	263	return -EINVAL;
	264
	265	priv->regs = (struct stm32_gpio_regs *)addr;
4fb22463	266
d876eaf2	267	name = dev_read_string(dev, "st,bank-name");
77417102 VM	268	if (!name)
	269	return -EINVAL;
	270	uc_priv->bank_name = name;
dbf928dd PC	271
	272	i = 0;
	273	ret = dev_read_phandle_with_args(dev, "gpio-ranges",
	274	NULL, 3, i, &args);
	275
cb08e84d PD	276	if (!ret && args.args_count < 3)
	277	return -EINVAL;
	278
427f452c PC	279	uc_priv->gpio_count = STM32_GPIOS_PER_BANK;
427f452c PC	280	if (ret == -ENOENT)
39a8f0be	281	priv->gpio_range = GENMASK(STM32_GPIOS_PER_BANK - 1, 0);
39a8f0be	282
dbf928dd PC	283	while (ret != -ENOENT) {
	284	priv->gpio_range \|= GENMASK(args.args[2] + args.args[0] - 1,
	285	args.args[0]);
	286
dbf928dd PC	287	ret = dev_read_phandle_with_args(dev, "gpio-ranges", NULL, 3,
dbf928dd PC	288	++i, &args);
cb08e84d PD	289	if (!ret && args.args_count < 3)
cb08e84d PD	290	return -EINVAL;
dbf928dd PC	291	}
	292
	293	dev_dbg(dev, "addr = 0x%p bank_name = %s gpio_count = %d gpio_range = 0x%x\n",
	294	(u32 *)priv->regs, uc_priv->bank_name, uc_priv->gpio_count,
	295	priv->gpio_range);
f17412ed	296
77417102 VM	297	ret = clk_get_by_index(dev, 0, &clk);
	298	if (ret < 0)
	299	return ret;
	300
	301	ret = clk_enable(&clk);
	302
	303	if (ret) {
	304	dev_err(dev, "failed to enable clock\n");
	305	return ret;
	306	}
6dd89d9d	307	dev_dbg(dev, "clock enabled\n");
77417102 VM	308
	309	return 0;
	310	}
	311
77417102 VM	312	U_BOOT_DRIVER(gpio_stm32) = {
	313	.name = "gpio_stm32",
	314	.id = UCLASS_GPIO,
77417102 VM	315	.probe = gpio_stm32_probe,
77417102 VM	316	.ops = &gpio_stm32_ops,
695c4994	317	.flags = DM_UC_FLAG_SEQ_ALIAS,
41575d8e	318	.priv_auto = sizeof(struct stm32_gpio_priv),
77417102	319	};