[thirdparty/u-boot.git] / drivers / gpio / xilinx_gpio.c

// SPDX-License-Identifier: GPL-2.0+
/*
 * Copyright (c) 2013 - 2018 Xilinx, Michal Simek
 */

#include <common.h>
#include <errno.h>
#include <log.h>
#include <malloc.h>
#include <linux/list.h>
#include <asm/io.h>
#include <asm/gpio.h>
#include <dm.h>
#include <dt-bindings/gpio/gpio.h>

#define XILINX_GPIO_MAX_BANK	2

/* Gpio simple map */
struct gpio_regs {
	u32 gpiodata;
	u32 gpiodir;
};

struct xilinx_gpio_plat {
	struct gpio_regs *regs;
	int bank_max[XILINX_GPIO_MAX_BANK];
	int bank_input[XILINX_GPIO_MAX_BANK];
	int bank_output[XILINX_GPIO_MAX_BANK];
	u32 dout_default[XILINX_GPIO_MAX_BANK];
};

struct xilinx_gpio_privdata {
	u32 output_val[XILINX_GPIO_MAX_BANK];
};

static int xilinx_gpio_get_bank_pin(unsigned offset, u32 *bank_num,
				    u32 *bank_pin_num, struct udevice *dev)
{
	struct xilinx_gpio_plat *plat = dev_get_plat(dev);
	u32 bank, max_pins;
	/* the first gpio is 0 not 1 */
	u32 pin_num = offset;

	for (bank = 0; bank < XILINX_GPIO_MAX_BANK; bank++) {
		max_pins = plat->bank_max[bank];
		if (pin_num < max_pins) {
			debug("%s: found at bank 0x%x pin 0x%x\n", __func__,
			      bank, pin_num);
			*bank_num = bank;
			*bank_pin_num = pin_num;
			return 0;
		}
		pin_num -= max_pins;
	}

	return -EINVAL;
}

static int xilinx_gpio_set_value(struct udevice *dev, unsigned offset,
				 int value)
{
	struct xilinx_gpio_plat *plat = dev_get_plat(dev);
	struct xilinx_gpio_privdata *priv = dev_get_priv(dev);
	int val, ret;
	u32 bank, pin;

	ret = xilinx_gpio_get_bank_pin(offset, &bank, &pin, dev);
	if (ret)
		return ret;

	val = priv->output_val[bank];

	debug("%s: regs: %lx, value: %x, gpio: %x, bank %x, pin %x, out %x\n",
	      __func__, (ulong)plat->regs, value, offset, bank, pin, val);

	if (value)
		val = val | (1 << pin);
	else
		val = val & ~(1 << pin);

	writel(val, &plat->regs->gpiodata + bank * 2);

	priv->output_val[bank] = val;

	return 0;
};

static int xilinx_gpio_get_value(struct udevice *dev, unsigned offset)
{
	struct xilinx_gpio_plat *plat = dev_get_plat(dev);
	struct xilinx_gpio_privdata *priv = dev_get_priv(dev);
	int val, ret;
	u32 bank, pin;

	ret = xilinx_gpio_get_bank_pin(offset, &bank, &pin, dev);
	if (ret)
		return ret;

	debug("%s: regs: %lx, gpio: %x, bank %x, pin %x\n", __func__,
	      (ulong)plat->regs, offset, bank, pin);

	if (plat->bank_output[bank]) {
		debug("%s: Read saved output value\n", __func__);
		val = priv->output_val[bank];
	} else {
		debug("%s: Read input value from reg\n", __func__);
		val = readl(&plat->regs->gpiodata + bank * 2);
	}

	val = !!(val & (1 << pin));

	return val;
};

static int xilinx_gpio_get_function(struct udevice *dev, unsigned offset)
{
	struct xilinx_gpio_plat *plat = dev_get_plat(dev);
	int val, ret;
	u32 bank, pin;

	ret = xilinx_gpio_get_bank_pin(offset, &bank, &pin, dev);
	if (ret)
		return ret;

	/* Check if all pins are inputs */
	if (plat->bank_input[bank])
		return GPIOF_INPUT;

	/* Check if all pins are outputs */
	if (plat->bank_output[bank])
		return GPIOF_OUTPUT;

	/* FIXME test on dual */
	val = readl(&plat->regs->gpiodir + bank * 2);
	val = !(val & (1 << pin));

	/* input is 1 in reg but GPIOF_INPUT is 0 */
	/* output is 0 in reg but GPIOF_OUTPUT is 1 */

	return val;
}

static int xilinx_gpio_direction_output(struct udevice *dev, unsigned offset,
					int value)
{
	struct xilinx_gpio_plat *plat = dev_get_plat(dev);
	int val, ret;
	u32 bank, pin;

	ret = xilinx_gpio_get_bank_pin(offset, &bank, &pin, dev);
	if (ret)
		return ret;

	/* can't change it if all is input by default */
	if (plat->bank_input[bank])
		return -EINVAL;

	xilinx_gpio_set_value(dev, offset, value);

	if (!plat->bank_output[bank]) {
		val = readl(&plat->regs->gpiodir + bank * 2);
		val = val & ~(1 << pin);
		writel(val, &plat->regs->gpiodir + bank * 2);
	}

	return 0;
}

static int xilinx_gpio_direction_input(struct udevice *dev, unsigned offset)
{
	struct xilinx_gpio_plat *plat = dev_get_plat(dev);
	int val, ret;
	u32 bank, pin;

	ret = xilinx_gpio_get_bank_pin(offset, &bank, &pin, dev);
	if (ret)
		return ret;

	/* Already input */
	if (plat->bank_input[bank])
		return 0;

	/* can't change it if all is output by default */
	if (plat->bank_output[bank])
		return -EINVAL;

	val = readl(&plat->regs->gpiodir + bank * 2);
	val = val | (1 << pin);
	writel(val, &plat->regs->gpiodir + bank * 2);

	return 0;
}

static int xilinx_gpio_xlate(struct udevice *dev, struct gpio_desc *desc,
			     struct ofnode_phandle_args *args)
{
	struct xilinx_gpio_plat *plat = dev_get_plat(dev);

	desc->offset = args->args[0];

	debug("%s: argc: %x, [0]: %x, [1]: %x, [2]: %x\n", __func__,
	      args->args_count, args->args[0], args->args[1], args->args[2]);

	/*
	 * The second cell is channel offset:
	 *  0 is first channel, 8 is second channel
	 *
	 * U-Boot driver just combine channels together that's why simply
	 * add amount of pins in second channel if present.
	 */
	if (args->args[1]) {
		if (!plat->bank_max[1]) {
			printf("%s: %s has no second channel\n",
			       __func__, dev->name);
			return -EINVAL;
		}

		desc->offset += plat->bank_max[0];
	}

	/* The third cell is optional */
	if (args->args_count > 2)
		desc->flags = (args->args[2] &
			       GPIO_ACTIVE_LOW ? GPIOD_ACTIVE_LOW : 0);

	debug("%s: offset %x, flags %lx\n",
	      __func__, desc->offset, desc->flags);
	return 0;
}

static const struct dm_gpio_ops xilinx_gpio_ops = {
	.direction_input = xilinx_gpio_direction_input,
	.direction_output = xilinx_gpio_direction_output,
	.get_value = xilinx_gpio_get_value,
	.set_value = xilinx_gpio_set_value,
	.get_function = xilinx_gpio_get_function,
	.xlate = xilinx_gpio_xlate,
};

static int xilinx_gpio_probe(struct udevice *dev)
{
	struct xilinx_gpio_plat *plat = dev_get_plat(dev);
	struct xilinx_gpio_privdata *priv = dev_get_priv(dev);
	struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
	const void *label_ptr;

	label_ptr = dev_read_prop(dev, "label", NULL);
	if (label_ptr) {
		uc_priv->bank_name = strdup(label_ptr);
		if (!uc_priv->bank_name)
			return -ENOMEM;
	} else {
		uc_priv->bank_name = dev->name;
	}

	uc_priv->gpio_count = plat->bank_max[0] + plat->bank_max[1];

	priv->output_val[0] = plat->dout_default[0];

	if (plat->bank_max[1])
		priv->output_val[1] = plat->dout_default[1];

	return 0;
}

static int xilinx_gpio_of_to_plat(struct udevice *dev)
{
	struct xilinx_gpio_plat *plat = dev_get_plat(dev);
	int is_dual;

	plat->regs = dev_read_addr_ptr(dev);

	plat->bank_max[0] = dev_read_u32_default(dev, "xlnx,gpio-width", 0);
	plat->bank_input[0] = dev_read_u32_default(dev, "xlnx,all-inputs", 0);
	plat->bank_output[0] = dev_read_u32_default(dev, "xlnx,all-outputs", 0);
	plat->dout_default[0] = dev_read_u32_default(dev, "xlnx,dout-default",
						     0);

	is_dual = dev_read_u32_default(dev, "xlnx,is-dual", 0);
	if (is_dual) {
		plat->bank_max[1] = dev_read_u32_default(dev,
							 "xlnx,gpio2-width", 0);
		plat->bank_input[1] = dev_read_u32_default(dev,
						"xlnx,all-inputs-2", 0);
		plat->bank_output[1] = dev_read_u32_default(dev,
						"xlnx,all-outputs-2", 0);
		plat->dout_default[1] = dev_read_u32_default(dev,
						"xlnx,dout-default-2", 0);
	}

	return 0;
}

static const struct udevice_id xilinx_gpio_ids[] = {
	{ .compatible = "xlnx,xps-gpio-1.00.a",},
	{ }
};

U_BOOT_DRIVER(xilinx_gpio) = {
	.name = "xlnx_gpio",
	.id = UCLASS_GPIO,
	.ops = &xilinx_gpio_ops,
	.of_match = xilinx_gpio_ids,
	.of_to_plat = xilinx_gpio_of_to_plat,
	.probe = xilinx_gpio_probe,
	.plat_auto	= sizeof(struct xilinx_gpio_plat),
	.priv_auto	= sizeof(struct xilinx_gpio_privdata),
};
Commit	Line	Data
83d290c5	1	// SPDX-License-Identifier: GPL-2.0+
4e779ad2	2	/*
10441ec9	3	* Copyright (c) 2013 - 2018 Xilinx, Michal Simek
4e779ad2 MS	4	*/
4e779ad2 MS	5
d678a59d	6	#include <common.h>
4e779ad2	7	#include <errno.h>
f7ae49fc	8	#include <log.h>
4e779ad2 MS	9	#include <malloc.h>
	10	#include <linux/list.h>
	11	#include <asm/io.h>
	12	#include <asm/gpio.h>
10441ec9	13	#include <dm.h>
6f81ff04	14	#include <dt-bindings/gpio/gpio.h>
4e779ad2	15
6f81ff04	16	#define XILINX_GPIO_MAX_BANK 2
4e779ad2 MS	17
	18	/* Gpio simple map */
	19	struct gpio_regs {
	20	u32 gpiodata;
	21	u32 gpiodir;
	22	};
	23
8a8d24bd	24	struct xilinx_gpio_plat {
10441ec9 MS	25	struct gpio_regs *regs;
	26	int bank_max[XILINX_GPIO_MAX_BANK];
	27	int bank_input[XILINX_GPIO_MAX_BANK];
	28	int bank_output[XILINX_GPIO_MAX_BANK];
c714aeae MS	29	u32 dout_default[XILINX_GPIO_MAX_BANK];
	30	};
	31
	32	struct xilinx_gpio_privdata {
	33	u32 output_val[XILINX_GPIO_MAX_BANK];
10441ec9 MS	34	};
	35
	36	static int xilinx_gpio_get_bank_pin(unsigned offset, u32 *bank_num,
	37	u32 bank_pin_num, struct udevice dev)
	38	{
8a8d24bd	39	struct xilinx_gpio_plat *plat = dev_get_plat(dev);
10441ec9 MS	40	u32 bank, max_pins;
	41	/* the first gpio is 0 not 1 */
	42	u32 pin_num = offset;
	43
	44	for (bank = 0; bank < XILINX_GPIO_MAX_BANK; bank++) {
caa4daa2	45	max_pins = plat->bank_max[bank];
10441ec9 MS	46	if (pin_num < max_pins) {
	47	debug("%s: found at bank 0x%x pin 0x%x\n", __func__,
	48	bank, pin_num);
	49	*bank_num = bank;
	50	*bank_pin_num = pin_num;
	51	return 0;
	52	}
	53	pin_num -= max_pins;
	54	}
	55
	56	return -EINVAL;
	57	}
	58
	59	static int xilinx_gpio_set_value(struct udevice *dev, unsigned offset,
	60	int value)
	61	{
8a8d24bd	62	struct xilinx_gpio_plat *plat = dev_get_plat(dev);
c714aeae	63	struct xilinx_gpio_privdata *priv = dev_get_priv(dev);
10441ec9 MS	64	int val, ret;
	65	u32 bank, pin;
	66
	67	ret = xilinx_gpio_get_bank_pin(offset, &bank, &pin, dev);
	68	if (ret)
	69	return ret;
	70
c714aeae	71	val = priv->output_val[bank];
642a8604	72
c714aeae	73	debug("%s: regs: %lx, value: %x, gpio: %x, bank %x, pin %x, out %x\n",
caa4daa2	74	__func__, (ulong)plat->regs, value, offset, bank, pin, val);
10441ec9	75
642a8604	76	if (value)
10441ec9	77	val = val \| (1 << pin);
642a8604	78	else
10441ec9	79	val = val & ~(1 << pin);
642a8604	80
caa4daa2	81	writel(val, &plat->regs->gpiodata + bank * 2);
10441ec9	82
c714aeae MS	83	priv->output_val[bank] = val;
c714aeae MS	84
ac7f0613	85	return 0;
10441ec9 MS	86	};
	87
	88	static int xilinx_gpio_get_value(struct udevice *dev, unsigned offset)
	89	{
8a8d24bd	90	struct xilinx_gpio_plat *plat = dev_get_plat(dev);
c714aeae	91	struct xilinx_gpio_privdata *priv = dev_get_priv(dev);
10441ec9 MS	92	int val, ret;
	93	u32 bank, pin;
	94
	95	ret = xilinx_gpio_get_bank_pin(offset, &bank, &pin, dev);
	96	if (ret)
	97	return ret;
	98
	99	debug("%s: regs: %lx, gpio: %x, bank %x, pin %x\n", __func__,
caa4daa2	100	(ulong)plat->regs, offset, bank, pin);
10441ec9	101
caa4daa2	102	if (plat->bank_output[bank]) {
c714aeae MS	103	debug("%s: Read saved output value\n", __func__);
	104	val = priv->output_val[bank];
	105	} else {
	106	debug("%s: Read input value from reg\n", __func__);
caa4daa2	107	val = readl(&plat->regs->gpiodata + bank * 2);
c714aeae MS	108	}
c714aeae MS	109
10441ec9 MS	110	val = !!(val & (1 << pin));
	111
	112	return val;
	113	};
	114
	115	static int xilinx_gpio_get_function(struct udevice *dev, unsigned offset)
	116	{
8a8d24bd	117	struct xilinx_gpio_plat *plat = dev_get_plat(dev);
10441ec9 MS	118	int val, ret;
	119	u32 bank, pin;
	120
ddd7b3fa MS	121	ret = xilinx_gpio_get_bank_pin(offset, &bank, &pin, dev);
	122	if (ret)
	123	return ret;
	124
10441ec9	125	/* Check if all pins are inputs */
caa4daa2	126	if (plat->bank_input[bank])
10441ec9 MS	127	return GPIOF_INPUT;
	128
	129	/* Check if all pins are outputs */
caa4daa2	130	if (plat->bank_output[bank])
10441ec9 MS	131	return GPIOF_OUTPUT;
10441ec9 MS	132
10441ec9	133	/* FIXME test on dual */
caa4daa2	134	val = readl(&plat->regs->gpiodir + bank * 2);
10441ec9 MS	135	val = !(val & (1 << pin));
	136
	137	/* input is 1 in reg but GPIOF_INPUT is 0 */
	138	/* output is 0 in reg but GPIOF_OUTPUT is 1 */
	139
	140	return val;
	141	}
	142
	143	static int xilinx_gpio_direction_output(struct udevice *dev, unsigned offset,
	144	int value)
	145	{
8a8d24bd	146	struct xilinx_gpio_plat *plat = dev_get_plat(dev);
10441ec9 MS	147	int val, ret;
	148	u32 bank, pin;
	149
	150	ret = xilinx_gpio_get_bank_pin(offset, &bank, &pin, dev);
	151	if (ret)
	152	return ret;
	153
	154	/* can't change it if all is input by default */
caa4daa2	155	if (plat->bank_input[bank])
10441ec9 MS	156	return -EINVAL;
10441ec9 MS	157
bf2a69de MS	158	xilinx_gpio_set_value(dev, offset, value);
bf2a69de MS	159
caa4daa2 SG	160	if (!plat->bank_output[bank]) {
caa4daa2 SG	161	val = readl(&plat->regs->gpiodir + bank * 2);
10441ec9	162	val = val & ~(1 << pin);
caa4daa2	163	writel(val, &plat->regs->gpiodir + bank * 2);
10441ec9 MS	164	}
10441ec9 MS	165
10441ec9 MS	166	return 0;
	167	}
	168
	169	static int xilinx_gpio_direction_input(struct udevice *dev, unsigned offset)
	170	{
8a8d24bd	171	struct xilinx_gpio_plat *plat = dev_get_plat(dev);
10441ec9 MS	172	int val, ret;
	173	u32 bank, pin;
	174
	175	ret = xilinx_gpio_get_bank_pin(offset, &bank, &pin, dev);
	176	if (ret)
	177	return ret;
	178
	179	/* Already input */
caa4daa2	180	if (plat->bank_input[bank])
10441ec9 MS	181	return 0;
	182
	183	/* can't change it if all is output by default */
caa4daa2	184	if (plat->bank_output[bank])
10441ec9 MS	185	return -EINVAL;
10441ec9 MS	186
caa4daa2	187	val = readl(&plat->regs->gpiodir + bank * 2);
10441ec9	188	val = val \| (1 << pin);
caa4daa2	189	writel(val, &plat->regs->gpiodir + bank * 2);
10441ec9 MS	190
	191	return 0;
	192	}
	193
	194	static int xilinx_gpio_xlate(struct udevice dev, struct gpio_desc desc,
	195	struct ofnode_phandle_args *args)
	196	{
8a8d24bd	197	struct xilinx_gpio_plat *plat = dev_get_plat(dev);
10441ec9 MS	198
	199	desc->offset = args->args[0];
	200
	201	debug("%s: argc: %x, [0]: %x, [1]: %x, [2]: %x\n", __func__,
	202	args->args_count, args->args[0], args->args[1], args->args[2]);
	203
	204	/*
	205	* The second cell is channel offset:
	206	* 0 is first channel, 8 is second channel
	207	*
	208	* U-Boot driver just combine channels together that's why simply
	209	* add amount of pins in second channel if present.
	210	*/
	211	if (args->args[1]) {
caa4daa2	212	if (!plat->bank_max[1]) {
10441ec9 MS	213	printf("%s: %s has no second channel\n",
	214	__func__, dev->name);
	215	return -EINVAL;
	216	}
	217
caa4daa2	218	desc->offset += plat->bank_max[0];
10441ec9 MS	219	}
	220
	221	/* The third cell is optional */
	222	if (args->args_count > 2)
	223	desc->flags = (args->args[2] &
	224	GPIO_ACTIVE_LOW ? GPIOD_ACTIVE_LOW : 0);
	225
	226	debug("%s: offset %x, flags %lx\n",
	227	__func__, desc->offset, desc->flags);
	228	return 0;
	229	}
	230
	231	static const struct dm_gpio_ops xilinx_gpio_ops = {
	232	.direction_input = xilinx_gpio_direction_input,
	233	.direction_output = xilinx_gpio_direction_output,
	234	.get_value = xilinx_gpio_get_value,
	235	.set_value = xilinx_gpio_set_value,
	236	.get_function = xilinx_gpio_get_function,
	237	.xlate = xilinx_gpio_xlate,
	238	};
	239
	240	static int xilinx_gpio_probe(struct udevice *dev)
	241	{
8a8d24bd	242	struct xilinx_gpio_plat *plat = dev_get_plat(dev);
c714aeae	243	struct xilinx_gpio_privdata *priv = dev_get_priv(dev);
10441ec9	244	struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
312dd1c5	245	const void *label_ptr;
10441ec9	246
312dd1c5 MS	247	label_ptr = dev_read_prop(dev, "label", NULL);
	248	if (label_ptr) {
	249	uc_priv->bank_name = strdup(label_ptr);
	250	if (!uc_priv->bank_name)
	251	return -ENOMEM;
	252	} else {
	253	uc_priv->bank_name = dev->name;
	254	}
10441ec9	255
caa4daa2	256	uc_priv->gpio_count = plat->bank_max[0] + plat->bank_max[1];
10441ec9	257
caa4daa2	258	priv->output_val[0] = plat->dout_default[0];
c714aeae	259
caa4daa2 SG	260	if (plat->bank_max[1])
caa4daa2 SG	261	priv->output_val[1] = plat->dout_default[1];
c714aeae	262
10441ec9 MS	263	return 0;
	264	}
	265
d1998a9f	266	static int xilinx_gpio_of_to_plat(struct udevice *dev)
10441ec9	267	{
8a8d24bd	268	struct xilinx_gpio_plat *plat = dev_get_plat(dev);
10441ec9 MS	269	int is_dual;
10441ec9 MS	270
a12a73b6	271	plat->regs = dev_read_addr_ptr(dev);
10441ec9	272
caa4daa2 SG	273	plat->bank_max[0] = dev_read_u32_default(dev, "xlnx,gpio-width", 0);
	274	plat->bank_input[0] = dev_read_u32_default(dev, "xlnx,all-inputs", 0);
	275	plat->bank_output[0] = dev_read_u32_default(dev, "xlnx,all-outputs", 0);
	276	plat->dout_default[0] = dev_read_u32_default(dev, "xlnx,dout-default",
	277	0);
10441ec9 MS	278
	279	is_dual = dev_read_u32_default(dev, "xlnx,is-dual", 0);
	280	if (is_dual) {
caa4daa2 SG	281	plat->bank_max[1] = dev_read_u32_default(dev,
	282	"xlnx,gpio2-width", 0);
	283	plat->bank_input[1] = dev_read_u32_default(dev,
10441ec9	284	"xlnx,all-inputs-2", 0);
caa4daa2	285	plat->bank_output[1] = dev_read_u32_default(dev,
10441ec9	286	"xlnx,all-outputs-2", 0);
caa4daa2	287	plat->dout_default[1] = dev_read_u32_default(dev,
c714aeae	288	"xlnx,dout-default-2", 0);
10441ec9 MS	289	}
	290
	291	return 0;
	292	}
	293
	294	static const struct udevice_id xilinx_gpio_ids[] = {
	295	{ .compatible = "xlnx,xps-gpio-1.00.a",},
	296	{ }
	297	};
	298
	299	U_BOOT_DRIVER(xilinx_gpio) = {
	300	.name = "xlnx_gpio",
	301	.id = UCLASS_GPIO,
	302	.ops = &xilinx_gpio_ops,
	303	.of_match = xilinx_gpio_ids,
d1998a9f	304	.of_to_plat = xilinx_gpio_of_to_plat,
10441ec9	305	.probe = xilinx_gpio_probe,
8a8d24bd	306	.plat_auto = sizeof(struct xilinx_gpio_plat),
41575d8e	307	.priv_auto = sizeof(struct xilinx_gpio_privdata),
10441ec9	308	};