[people/ms/u-boot.git] / drivers / gpio / zynq_gpio.c

/*
 * Xilinx Zynq GPIO device driver
 *
 * Copyright (C) 2015 DAVE Embedded Systems <devel@dave.eu>
 *
 * Most of code taken from linux kernel driver (linux/drivers/gpio/gpio-zynq.c)
 * Copyright (C) 2009 - 2014 Xilinx, Inc.
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#include <common.h>
#include <asm/gpio.h>
#include <asm/io.h>
#include <asm/errno.h>
#include <dm.h>
#include <fdtdec.h>

DECLARE_GLOBAL_DATA_PTR;

/* Maximum banks */
#define ZYNQ_GPIO_MAX_BANK	4

#define ZYNQ_GPIO_BANK0_NGPIO	32
#define ZYNQ_GPIO_BANK1_NGPIO	22
#define ZYNQ_GPIO_BANK2_NGPIO	32
#define ZYNQ_GPIO_BANK3_NGPIO	32

#define ZYNQ_GPIO_NR_GPIOS	(ZYNQ_GPIO_BANK0_NGPIO + \
				 ZYNQ_GPIO_BANK1_NGPIO + \
				 ZYNQ_GPIO_BANK2_NGPIO + \
				 ZYNQ_GPIO_BANK3_NGPIO)

#define ZYNQ_GPIO_BANK0_PIN_MIN	0
#define ZYNQ_GPIO_BANK0_PIN_MAX	(ZYNQ_GPIO_BANK0_PIN_MIN + \
					ZYNQ_GPIO_BANK0_NGPIO - 1)
#define ZYNQ_GPIO_BANK1_PIN_MIN	(ZYNQ_GPIO_BANK0_PIN_MAX + 1)
#define ZYNQ_GPIO_BANK1_PIN_MAX	(ZYNQ_GPIO_BANK1_PIN_MIN + \
					ZYNQ_GPIO_BANK1_NGPIO - 1)
#define ZYNQ_GPIO_BANK2_PIN_MIN	(ZYNQ_GPIO_BANK1_PIN_MAX + 1)
#define ZYNQ_GPIO_BANK2_PIN_MAX	(ZYNQ_GPIO_BANK2_PIN_MIN + \
					ZYNQ_GPIO_BANK2_NGPIO - 1)
#define ZYNQ_GPIO_BANK3_PIN_MIN	(ZYNQ_GPIO_BANK2_PIN_MAX + 1)
#define ZYNQ_GPIO_BANK3_PIN_MAX	(ZYNQ_GPIO_BANK3_PIN_MIN + \
					ZYNQ_GPIO_BANK3_NGPIO - 1)

/* Register offsets for the GPIO device */
/* LSW Mask & Data -WO */
#define ZYNQ_GPIO_DATA_LSW_OFFSET(BANK)	(0x000 + (8 * BANK))
/* MSW Mask & Data -WO */
#define ZYNQ_GPIO_DATA_MSW_OFFSET(BANK)	(0x004 + (8 * BANK))
/* Data Register-RW */
#define ZYNQ_GPIO_DATA_RO_OFFSET(BANK)	(0x060 + (4 * BANK))
/* Direction mode reg-RW */
#define ZYNQ_GPIO_DIRM_OFFSET(BANK)	(0x204 + (0x40 * BANK))
/* Output enable reg-RW */
#define ZYNQ_GPIO_OUTEN_OFFSET(BANK)	(0x208 + (0x40 * BANK))
/* Interrupt mask reg-RO */
#define ZYNQ_GPIO_INTMASK_OFFSET(BANK)	(0x20C + (0x40 * BANK))
/* Interrupt enable reg-WO */
#define ZYNQ_GPIO_INTEN_OFFSET(BANK)	(0x210 + (0x40 * BANK))
/* Interrupt disable reg-WO */
#define ZYNQ_GPIO_INTDIS_OFFSET(BANK)	(0x214 + (0x40 * BANK))
/* Interrupt status reg-RO */
#define ZYNQ_GPIO_INTSTS_OFFSET(BANK)	(0x218 + (0x40 * BANK))
/* Interrupt type reg-RW */
#define ZYNQ_GPIO_INTTYPE_OFFSET(BANK)	(0x21C + (0x40 * BANK))
/* Interrupt polarity reg-RW */
#define ZYNQ_GPIO_INTPOL_OFFSET(BANK)	(0x220 + (0x40 * BANK))
/* Interrupt on any, reg-RW */
#define ZYNQ_GPIO_INTANY_OFFSET(BANK)	(0x224 + (0x40 * BANK))

/* Disable all interrupts mask */
#define ZYNQ_GPIO_IXR_DISABLE_ALL	0xFFFFFFFF

/* Mid pin number of a bank */
#define ZYNQ_GPIO_MID_PIN_NUM 16

/* GPIO upper 16 bit mask */
#define ZYNQ_GPIO_UPPER_MASK 0xFFFF0000

struct zynq_gpio_privdata {
	phys_addr_t base;
};

/**
 * zynq_gpio_get_bank_pin - Get the bank number and pin number within that bank
 * for a given pin in the GPIO device
 * @pin_num:	gpio pin number within the device
 * @bank_num:	an output parameter used to return the bank number of the gpio
 *		pin
 * @bank_pin_num: an output parameter used to return pin number within a bank
 *		  for the given gpio pin
 *
 * Returns the bank number and pin offset within the bank.
 */
static inline void zynq_gpio_get_bank_pin(unsigned int pin_num,
					  unsigned int *bank_num,
					  unsigned int *bank_pin_num)
{
	switch (pin_num) {
	case ZYNQ_GPIO_BANK0_PIN_MIN ... ZYNQ_GPIO_BANK0_PIN_MAX:
		*bank_num = 0;
		*bank_pin_num = pin_num;
		break;
	case ZYNQ_GPIO_BANK1_PIN_MIN ... ZYNQ_GPIO_BANK1_PIN_MAX:
		*bank_num = 1;
		*bank_pin_num = pin_num - ZYNQ_GPIO_BANK1_PIN_MIN;
		break;
	case ZYNQ_GPIO_BANK2_PIN_MIN ... ZYNQ_GPIO_BANK2_PIN_MAX:
		*bank_num = 2;
		*bank_pin_num = pin_num - ZYNQ_GPIO_BANK2_PIN_MIN;
		break;
	case ZYNQ_GPIO_BANK3_PIN_MIN ... ZYNQ_GPIO_BANK3_PIN_MAX:
		*bank_num = 3;
		*bank_pin_num = pin_num - ZYNQ_GPIO_BANK3_PIN_MIN;
		break;
	default:
		printf("invalid GPIO pin number: %u\n", pin_num);
		*bank_num = 0;
		*bank_pin_num = 0;
		break;
	}
}

static int gpio_is_valid(unsigned gpio)
{
	return (gpio >= 0) && (gpio < ZYNQ_GPIO_NR_GPIOS);
}

static int check_gpio(unsigned gpio)
{
	if (!gpio_is_valid(gpio)) {
		printf("ERROR : check_gpio: invalid GPIO %d\n", gpio);
		return -1;
	}
	return 0;
}

static int zynq_gpio_get_value(struct udevice *dev, unsigned gpio)
{
	u32 data;
	unsigned int bank_num, bank_pin_num;
	struct zynq_gpio_privdata *priv = dev_get_priv(dev);

	if (check_gpio(gpio) < 0)
		return -1;

	zynq_gpio_get_bank_pin(gpio, &bank_num, &bank_pin_num);

	data = readl(priv->base +
			     ZYNQ_GPIO_DATA_RO_OFFSET(bank_num));

	return (data >> bank_pin_num) & 1;
}

static int zynq_gpio_set_value(struct udevice *dev, unsigned gpio, int value)
{
	unsigned int reg_offset, bank_num, bank_pin_num;
	struct zynq_gpio_privdata *priv = dev_get_priv(dev);

	if (check_gpio(gpio) < 0)
		return -1;

	zynq_gpio_get_bank_pin(gpio, &bank_num, &bank_pin_num);

	if (bank_pin_num >= ZYNQ_GPIO_MID_PIN_NUM) {
		/* only 16 data bits in bit maskable reg */
		bank_pin_num -= ZYNQ_GPIO_MID_PIN_NUM;
		reg_offset = ZYNQ_GPIO_DATA_MSW_OFFSET(bank_num);
	} else {
		reg_offset = ZYNQ_GPIO_DATA_LSW_OFFSET(bank_num);
	}

	/*
	 * get the 32 bit value to be written to the mask/data register where
	 * the upper 16 bits is the mask and lower 16 bits is the data
	 */
	value = !!value;
	value = ~(1 << (bank_pin_num + ZYNQ_GPIO_MID_PIN_NUM)) &
		((value << bank_pin_num) | ZYNQ_GPIO_UPPER_MASK);

	writel(value, priv->base + reg_offset);

	return 0;
}

static int zynq_gpio_direction_input(struct udevice *dev, unsigned gpio)
{
	u32 reg;
	unsigned int bank_num, bank_pin_num;
	struct zynq_gpio_privdata *priv = dev_get_priv(dev);

	if (check_gpio(gpio) < 0)
		return -1;

	zynq_gpio_get_bank_pin(gpio, &bank_num, &bank_pin_num);

	/* bank 0 pins 7 and 8 are special and cannot be used as inputs */
	if (bank_num == 0 && (bank_pin_num == 7 || bank_pin_num == 8))
		return -1;

	/* clear the bit in direction mode reg to set the pin as input */
	reg = readl(priv->base + ZYNQ_GPIO_DIRM_OFFSET(bank_num));
	reg &= ~BIT(bank_pin_num);
	writel(reg, priv->base + ZYNQ_GPIO_DIRM_OFFSET(bank_num));

	return 0;
}

static int zynq_gpio_direction_output(struct udevice *dev, unsigned gpio,
				      int value)
{
	u32 reg;
	unsigned int bank_num, bank_pin_num;
	struct zynq_gpio_privdata *priv = dev_get_priv(dev);

	if (check_gpio(gpio) < 0)
		return -1;

	zynq_gpio_get_bank_pin(gpio, &bank_num, &bank_pin_num);

	/* set the GPIO pin as output */
	reg = readl(priv->base + ZYNQ_GPIO_DIRM_OFFSET(bank_num));
	reg |= BIT(bank_pin_num);
	writel(reg, priv->base + ZYNQ_GPIO_DIRM_OFFSET(bank_num));

	/* configure the output enable reg for the pin */
	reg = readl(priv->base + ZYNQ_GPIO_OUTEN_OFFSET(bank_num));
	reg |= BIT(bank_pin_num);
	writel(reg, priv->base + ZYNQ_GPIO_OUTEN_OFFSET(bank_num));

	/* set the state of the pin */
	gpio_set_value(gpio, value);
	return 0;
}

static const struct dm_gpio_ops gpio_zynq_ops = {
	.direction_input	= zynq_gpio_direction_input,
	.direction_output	= zynq_gpio_direction_output,
	.get_value		= zynq_gpio_get_value,
	.set_value		= zynq_gpio_set_value,
};

static int zynq_gpio_probe(struct udevice *dev)
{
	struct zynq_gpio_privdata *priv = dev_get_priv(dev);

	priv->base = dev_get_addr(dev);

	return 0;
}

static int zynq_gpio_ofdata_to_platdata(struct udevice *dev)
{
	struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);

	uc_priv->gpio_count = ZYNQ_GPIO_NR_GPIOS;

	return 0;
}

static const struct udevice_id zynq_gpio_ids[] = {
	{ .compatible = "xlnx,zynq-gpio-1.0" },
	{ }
};

U_BOOT_DRIVER(gpio_zynq) = {
	.name	= "gpio_zynq",
	.id	= UCLASS_GPIO,
	.ops	= &gpio_zynq_ops,
	.of_match = zynq_gpio_ids,
	.ofdata_to_platdata = zynq_gpio_ofdata_to_platdata,
	.probe	= zynq_gpio_probe,
	.priv_auto_alloc_size = sizeof(struct zynq_gpio_privdata),
};
Commit	Line	Data
d37c6288 AS	1	/*
	2	* Xilinx Zynq GPIO device driver
	3	*
	4	* Copyright (C) 2015 DAVE Embedded Systems <devel@dave.eu>
	5	*
	6	* Most of code taken from linux kernel driver (linux/drivers/gpio/gpio-zynq.c)
	7	* Copyright (C) 2009 - 2014 Xilinx, Inc.
	8	*
	9	* SPDX-License-Identifier: GPL-2.0+
	10	*/
	11
	12	#include <common.h>
	13	#include <asm/gpio.h>
	14	#include <asm/io.h>
	15	#include <asm/errno.h>
68c7026e SDPP	16	#include <dm.h>
	17	#include <fdtdec.h>
	18
	19	DECLARE_GLOBAL_DATA_PTR;
	20
f17abcae SDPP	21	/* Maximum banks */
	22	#define ZYNQ_GPIO_MAX_BANK 4
	23
	24	#define ZYNQ_GPIO_BANK0_NGPIO 32
	25	#define ZYNQ_GPIO_BANK1_NGPIO 22
	26	#define ZYNQ_GPIO_BANK2_NGPIO 32
	27	#define ZYNQ_GPIO_BANK3_NGPIO 32
	28
	29	#define ZYNQ_GPIO_NR_GPIOS (ZYNQ_GPIO_BANK0_NGPIO + \
	30	ZYNQ_GPIO_BANK1_NGPIO + \
	31	ZYNQ_GPIO_BANK2_NGPIO + \
	32	ZYNQ_GPIO_BANK3_NGPIO)
	33
	34	#define ZYNQ_GPIO_BANK0_PIN_MIN 0
	35	#define ZYNQ_GPIO_BANK0_PIN_MAX (ZYNQ_GPIO_BANK0_PIN_MIN + \
	36	ZYNQ_GPIO_BANK0_NGPIO - 1)
	37	#define ZYNQ_GPIO_BANK1_PIN_MIN (ZYNQ_GPIO_BANK0_PIN_MAX + 1)
	38	#define ZYNQ_GPIO_BANK1_PIN_MAX (ZYNQ_GPIO_BANK1_PIN_MIN + \
	39	ZYNQ_GPIO_BANK1_NGPIO - 1)
	40	#define ZYNQ_GPIO_BANK2_PIN_MIN (ZYNQ_GPIO_BANK1_PIN_MAX + 1)
	41	#define ZYNQ_GPIO_BANK2_PIN_MAX (ZYNQ_GPIO_BANK2_PIN_MIN + \
	42	ZYNQ_GPIO_BANK2_NGPIO - 1)
	43	#define ZYNQ_GPIO_BANK3_PIN_MIN (ZYNQ_GPIO_BANK2_PIN_MAX + 1)
	44	#define ZYNQ_GPIO_BANK3_PIN_MAX (ZYNQ_GPIO_BANK3_PIN_MIN + \
	45	ZYNQ_GPIO_BANK3_NGPIO - 1)
	46
	47	/* Register offsets for the GPIO device */
	48	/* LSW Mask & Data -WO */
	49	#define ZYNQ_GPIO_DATA_LSW_OFFSET(BANK) (0x000 + (8 * BANK))
	50	/* MSW Mask & Data -WO */
	51	#define ZYNQ_GPIO_DATA_MSW_OFFSET(BANK) (0x004 + (8 * BANK))
	52	/* Data Register-RW */
	53	#define ZYNQ_GPIO_DATA_RO_OFFSET(BANK) (0x060 + (4 * BANK))
	54	/* Direction mode reg-RW */
	55	#define ZYNQ_GPIO_DIRM_OFFSET(BANK) (0x204 + (0x40 * BANK))
	56	/* Output enable reg-RW */
	57	#define ZYNQ_GPIO_OUTEN_OFFSET(BANK) (0x208 + (0x40 * BANK))
	58	/* Interrupt mask reg-RO */
	59	#define ZYNQ_GPIO_INTMASK_OFFSET(BANK) (0x20C + (0x40 * BANK))
	60	/* Interrupt enable reg-WO */
	61	#define ZYNQ_GPIO_INTEN_OFFSET(BANK) (0x210 + (0x40 * BANK))
	62	/* Interrupt disable reg-WO */
	63	#define ZYNQ_GPIO_INTDIS_OFFSET(BANK) (0x214 + (0x40 * BANK))
	64	/* Interrupt status reg-RO */
	65	#define ZYNQ_GPIO_INTSTS_OFFSET(BANK) (0x218 + (0x40 * BANK))
	66	/* Interrupt type reg-RW */
	67	#define ZYNQ_GPIO_INTTYPE_OFFSET(BANK) (0x21C + (0x40 * BANK))
	68	/* Interrupt polarity reg-RW */
	69	#define ZYNQ_GPIO_INTPOL_OFFSET(BANK) (0x220 + (0x40 * BANK))
	70	/* Interrupt on any, reg-RW */
	71	#define ZYNQ_GPIO_INTANY_OFFSET(BANK) (0x224 + (0x40 * BANK))
	72
	73	/* Disable all interrupts mask */
	74	#define ZYNQ_GPIO_IXR_DISABLE_ALL 0xFFFFFFFF
	75
	76	/* Mid pin number of a bank */
	77	#define ZYNQ_GPIO_MID_PIN_NUM 16
	78
	79	/* GPIO upper 16 bit mask */
	80	#define ZYNQ_GPIO_UPPER_MASK 0xFFFF0000
	81
68c7026e SDPP	82	struct zynq_gpio_privdata {
	83	phys_addr_t base;
	84	};
68c7026e	85
d37c6288 AS	86	/**
	87	* zynq_gpio_get_bank_pin - Get the bank number and pin number within that bank
	88	* for a given pin in the GPIO device
	89	* @pin_num: gpio pin number within the device
	90	* @bank_num: an output parameter used to return the bank number of the gpio
	91	* pin
	92	* @bank_pin_num: an output parameter used to return pin number within a bank
	93	* for the given gpio pin
	94	*
	95	* Returns the bank number and pin offset within the bank.
	96	*/
	97	static inline void zynq_gpio_get_bank_pin(unsigned int pin_num,
	98	unsigned int *bank_num,
	99	unsigned int *bank_pin_num)
	100	{
	101	switch (pin_num) {
	102	case ZYNQ_GPIO_BANK0_PIN_MIN ... ZYNQ_GPIO_BANK0_PIN_MAX:
	103	*bank_num = 0;
	104	*bank_pin_num = pin_num;
	105	break;
	106	case ZYNQ_GPIO_BANK1_PIN_MIN ... ZYNQ_GPIO_BANK1_PIN_MAX:
	107	*bank_num = 1;
	108	*bank_pin_num = pin_num - ZYNQ_GPIO_BANK1_PIN_MIN;
	109	break;
	110	case ZYNQ_GPIO_BANK2_PIN_MIN ... ZYNQ_GPIO_BANK2_PIN_MAX:
	111	*bank_num = 2;
	112	*bank_pin_num = pin_num - ZYNQ_GPIO_BANK2_PIN_MIN;
	113	break;
	114	case ZYNQ_GPIO_BANK3_PIN_MIN ... ZYNQ_GPIO_BANK3_PIN_MAX:
	115	*bank_num = 3;
	116	*bank_pin_num = pin_num - ZYNQ_GPIO_BANK3_PIN_MIN;
	117	break;
	118	default:
	119	printf("invalid GPIO pin number: %u\n", pin_num);
	120	*bank_num = 0;
	121	*bank_pin_num = 0;
	122	break;
	123	}
	124	}
	125
de77a03b	126	static int gpio_is_valid(unsigned gpio)
d37c6288 AS	127	{
	128	return (gpio >= 0) && (gpio < ZYNQ_GPIO_NR_GPIOS);
	129	}
	130
	131	static int check_gpio(unsigned gpio)
	132	{
	133	if (!gpio_is_valid(gpio)) {
	134	printf("ERROR : check_gpio: invalid GPIO %d\n", gpio);
	135	return -1;
	136	}
	137	return 0;
	138	}
	139
68c7026e SDPP	140	static int zynq_gpio_get_value(struct udevice *dev, unsigned gpio)
	141	{
	142	u32 data;
	143	unsigned int bank_num, bank_pin_num;
	144	struct zynq_gpio_privdata *priv = dev_get_priv(dev);
	145
	146	if (check_gpio(gpio) < 0)
	147	return -1;
	148
	149	zynq_gpio_get_bank_pin(gpio, &bank_num, &bank_pin_num);
	150
	151	data = readl(priv->base +
	152	ZYNQ_GPIO_DATA_RO_OFFSET(bank_num));
	153
	154	return (data >> bank_pin_num) & 1;
	155	}
	156
	157	static int zynq_gpio_set_value(struct udevice *dev, unsigned gpio, int value)
	158	{
	159	unsigned int reg_offset, bank_num, bank_pin_num;
	160	struct zynq_gpio_privdata *priv = dev_get_priv(dev);
	161
	162	if (check_gpio(gpio) < 0)
	163	return -1;
	164
	165	zynq_gpio_get_bank_pin(gpio, &bank_num, &bank_pin_num);
	166
	167	if (bank_pin_num >= ZYNQ_GPIO_MID_PIN_NUM) {
	168	/* only 16 data bits in bit maskable reg */
	169	bank_pin_num -= ZYNQ_GPIO_MID_PIN_NUM;
	170	reg_offset = ZYNQ_GPIO_DATA_MSW_OFFSET(bank_num);
	171	} else {
	172	reg_offset = ZYNQ_GPIO_DATA_LSW_OFFSET(bank_num);
	173	}
	174
	175	/*
	176	* get the 32 bit value to be written to the mask/data register where
	177	* the upper 16 bits is the mask and lower 16 bits is the data
	178	*/
	179	value = !!value;
	180	value = ~(1 << (bank_pin_num + ZYNQ_GPIO_MID_PIN_NUM)) &
	181	((value << bank_pin_num) \| ZYNQ_GPIO_UPPER_MASK);
	182
	183	writel(value, priv->base + reg_offset);
	184
	185	return 0;
	186	}
	187
	188	static int zynq_gpio_direction_input(struct udevice *dev, unsigned gpio)
	189	{
	190	u32 reg;
	191	unsigned int bank_num, bank_pin_num;
	192	struct zynq_gpio_privdata *priv = dev_get_priv(dev);
	193
	194	if (check_gpio(gpio) < 0)
	195	return -1;
	196
	197	zynq_gpio_get_bank_pin(gpio, &bank_num, &bank_pin_num);
	198
	199	/* bank 0 pins 7 and 8 are special and cannot be used as inputs */
	200	if (bank_num == 0 && (bank_pin_num == 7 \|\| bank_pin_num == 8))
	201	return -1;
	202
	203	/* clear the bit in direction mode reg to set the pin as input */
204	reg = readl(priv->base + ZYNQ_GPIO_DIRM_OFFSET(bank_num));
205	reg &= ~BIT(bank_pin_num);
206	writel(reg, priv->base + ZYNQ_GPIO_DIRM_OFFSET(bank_num));
207
208	return 0;
209	}
210
211	static int zynq_gpio_direction_output(struct udevice *dev, unsigned gpio,
212	int value)
213	{
214	u32 reg;
215	unsigned int bank_num, bank_pin_num;
216	struct zynq_gpio_privdata *priv = dev_get_priv(dev);
217
218	if (check_gpio(gpio) < 0)
219	return -1;
220
221	zynq_gpio_get_bank_pin(gpio, &bank_num, &bank_pin_num);
222
223	/* set the GPIO pin as output */
224	reg = readl(priv->base + ZYNQ_GPIO_DIRM_OFFSET(bank_num));
225	reg \|= BIT(bank_pin_num);
226	writel(reg, priv->base + ZYNQ_GPIO_DIRM_OFFSET(bank_num));
227
228	/* configure the output enable reg for the pin */
229	reg = readl(priv->base + ZYNQ_GPIO_OUTEN_OFFSET(bank_num));
230	reg \|= BIT(bank_pin_num);
231	writel(reg, priv->base + ZYNQ_GPIO_OUTEN_OFFSET(bank_num));
232
233	/* set the state of the pin */
234	gpio_set_value(gpio, value);
235	return 0;
236	}
237
238	static const struct dm_gpio_ops gpio_zynq_ops = {
239	.direction_input = zynq_gpio_direction_input,
240	.direction_output = zynq_gpio_direction_output,
241	.get_value = zynq_gpio_get_value,
242	.set_value = zynq_gpio_set_value,
243	};
244
245	static int zynq_gpio_probe(struct udevice *dev)
246	{
247	struct zynq_gpio_privdata *priv = dev_get_priv(dev);
248
249	priv->base = dev_get_addr(dev);
250
251	return 0;
252	}
253
254	static int zynq_gpio_ofdata_to_platdata(struct udevice *dev)
255	{
256	struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
257
258	uc_priv->gpio_count = ZYNQ_GPIO_NR_GPIOS;
259
260	return 0;
261	}
262
263	static const struct udevice_id zynq_gpio_ids[] = {
264	{ .compatible = "xlnx,zynq-gpio-1.0" },
265	{ }
266	};
267
268	U_BOOT_DRIVER(gpio_zynq) = {
269	.name = "gpio_zynq",
270	.id = UCLASS_GPIO,
271	.ops = &gpio_zynq_ops,
272	.of_match = zynq_gpio_ids,
273	.ofdata_to_platdata = zynq_gpio_ofdata_to_platdata,
274	.probe = zynq_gpio_probe,
275	.priv_auto_alloc_size = sizeof(struct zynq_gpio_privdata),
276	};