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4562236b HW |
1 | /* |
2 | * Copyright 2015 Advanced Micro Devices, Inc. | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice shall be included in | |
12 | * all copies or substantial portions of the Software. | |
13 | * | |
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
20 | * OTHER DEALINGS IN THE SOFTWARE. | |
21 | * | |
22 | * Authors: AMD | |
23 | * | |
24 | */ | |
25 | ||
0cf5eb76 DF |
26 | /* The caprices of the preprocessor require that this be declared right here */ |
27 | #define CREATE_TRACE_POINTS | |
28 | ||
4562236b HW |
29 | #include "dm_services_types.h" |
30 | #include "dc.h" | |
f6e03f80 | 31 | #include "link_enc_cfg.h" |
1dc90497 | 32 | #include "dc/inc/core_types.h" |
a7669aff | 33 | #include "dal_asic_id.h" |
cdca3f21 | 34 | #include "dmub/dmub_srv.h" |
743b9786 NK |
35 | #include "dc/inc/hw/dmcu.h" |
36 | #include "dc/inc/hw/abm.h" | |
9a71c7d3 | 37 | #include "dc/dc_dmub_srv.h" |
f9b4f20c | 38 | #include "dc/dc_edid_parser.h" |
81927e28 | 39 | #include "dc/dc_stat.h" |
9d83722d | 40 | #include "amdgpu_dm_trace.h" |
028c4ccf | 41 | #include "dpcd_defs.h" |
bc33f5e5 | 42 | #include "link/protocols/link_dpcd.h" |
028c4ccf | 43 | #include "link_service_types.h" |
1e5d4d8e RL |
44 | #include "link/protocols/link_dp_capability.h" |
45 | #include "link/protocols/link_ddc.h" | |
4562236b HW |
46 | |
47 | #include "vid.h" | |
48 | #include "amdgpu.h" | |
a49dcb88 | 49 | #include "amdgpu_display.h" |
a94d5569 | 50 | #include "amdgpu_ucode.h" |
4562236b HW |
51 | #include "atom.h" |
52 | #include "amdgpu_dm.h" | |
5d945cbc | 53 | #include "amdgpu_dm_plane.h" |
473683a0 | 54 | #include "amdgpu_dm_crtc.h" |
52704fca | 55 | #include "amdgpu_dm_hdcp.h" |
6a99099f | 56 | #include <drm/display/drm_hdcp_helper.h> |
e7b07cee | 57 | #include "amdgpu_pm.h" |
1f579254 | 58 | #include "amdgpu_atombios.h" |
4562236b HW |
59 | |
60 | #include "amd_shared.h" | |
61 | #include "amdgpu_dm_irq.h" | |
62 | #include "dm_helpers.h" | |
e7b07cee | 63 | #include "amdgpu_dm_mst_types.h" |
dc38fd9d DF |
64 | #if defined(CONFIG_DEBUG_FS) |
65 | #include "amdgpu_dm_debugfs.h" | |
66 | #endif | |
f4594cd1 | 67 | #include "amdgpu_dm_psr.h" |
4562236b HW |
68 | |
69 | #include "ivsrcid/ivsrcid_vislands30.h" | |
70 | ||
a6276e92 | 71 | #include <linux/backlight.h> |
4562236b HW |
72 | #include <linux/module.h> |
73 | #include <linux/moduleparam.h> | |
e7b07cee | 74 | #include <linux/types.h> |
97028037 | 75 | #include <linux/pm_runtime.h> |
09d21852 | 76 | #include <linux/pci.h> |
a94d5569 | 77 | #include <linux/firmware.h> |
6ce8f316 | 78 | #include <linux/component.h> |
57b9f338 | 79 | #include <linux/dmi.h> |
4562236b | 80 | |
da68386d | 81 | #include <drm/display/drm_dp_mst_helper.h> |
4fc8cb47 | 82 | #include <drm/display/drm_hdmi_helper.h> |
4562236b | 83 | #include <drm/drm_atomic.h> |
674e78ac | 84 | #include <drm/drm_atomic_uapi.h> |
4562236b | 85 | #include <drm/drm_atomic_helper.h> |
90bb087f | 86 | #include <drm/drm_blend.h> |
09d21852 | 87 | #include <drm/drm_fourcc.h> |
e7b07cee | 88 | #include <drm/drm_edid.h> |
09d21852 | 89 | #include <drm/drm_vblank.h> |
6ce8f316 | 90 | #include <drm/drm_audio_component.h> |
047de3f1 | 91 | #include <drm/drm_gem_atomic_helper.h> |
30c63715 | 92 | #include <drm/drm_plane_helper.h> |
4562236b | 93 | |
da11ef83 HG |
94 | #include <acpi/video.h> |
95 | ||
5527cd06 | 96 | #include "ivsrcid/dcn/irqsrcs_dcn_1_0.h" |
ff5ef992 | 97 | |
ad941f7a FX |
98 | #include "dcn/dcn_1_0_offset.h" |
99 | #include "dcn/dcn_1_0_sh_mask.h" | |
407e7517 | 100 | #include "soc15_hw_ip.h" |
543036a2 | 101 | #include "soc15_common.h" |
407e7517 | 102 | #include "vega10_ip_offset.h" |
ff5ef992 | 103 | |
543036a2 AP |
104 | #include "gc/gc_11_0_0_offset.h" |
105 | #include "gc/gc_11_0_0_sh_mask.h" | |
106 | ||
e7b07cee | 107 | #include "modules/inc/mod_freesync.h" |
bbf854dc | 108 | #include "modules/power/power_helpers.h" |
e7b07cee | 109 | |
743b9786 NK |
110 | #define FIRMWARE_RENOIR_DMUB "amdgpu/renoir_dmcub.bin" |
111 | MODULE_FIRMWARE(FIRMWARE_RENOIR_DMUB); | |
79037324 BL |
112 | #define FIRMWARE_SIENNA_CICHLID_DMUB "amdgpu/sienna_cichlid_dmcub.bin" |
113 | MODULE_FIRMWARE(FIRMWARE_SIENNA_CICHLID_DMUB); | |
5ce868fc BL |
114 | #define FIRMWARE_NAVY_FLOUNDER_DMUB "amdgpu/navy_flounder_dmcub.bin" |
115 | MODULE_FIRMWARE(FIRMWARE_NAVY_FLOUNDER_DMUB); | |
71c0fd92 RL |
116 | #define FIRMWARE_GREEN_SARDINE_DMUB "amdgpu/green_sardine_dmcub.bin" |
117 | MODULE_FIRMWARE(FIRMWARE_GREEN_SARDINE_DMUB); | |
469989ca RL |
118 | #define FIRMWARE_VANGOGH_DMUB "amdgpu/vangogh_dmcub.bin" |
119 | MODULE_FIRMWARE(FIRMWARE_VANGOGH_DMUB); | |
2a411205 BL |
120 | #define FIRMWARE_DIMGREY_CAVEFISH_DMUB "amdgpu/dimgrey_cavefish_dmcub.bin" |
121 | MODULE_FIRMWARE(FIRMWARE_DIMGREY_CAVEFISH_DMUB); | |
656fe9b6 AP |
122 | #define FIRMWARE_BEIGE_GOBY_DMUB "amdgpu/beige_goby_dmcub.bin" |
123 | MODULE_FIRMWARE(FIRMWARE_BEIGE_GOBY_DMUB); | |
1ebcaebd NK |
124 | #define FIRMWARE_YELLOW_CARP_DMUB "amdgpu/yellow_carp_dmcub.bin" |
125 | MODULE_FIRMWARE(FIRMWARE_YELLOW_CARP_DMUB); | |
e850f6b1 RL |
126 | #define FIRMWARE_DCN_314_DMUB "amdgpu/dcn_3_1_4_dmcub.bin" |
127 | MODULE_FIRMWARE(FIRMWARE_DCN_314_DMUB); | |
b5b8ed44 QZ |
128 | #define FIRMWARE_DCN_315_DMUB "amdgpu/dcn_3_1_5_dmcub.bin" |
129 | MODULE_FIRMWARE(FIRMWARE_DCN_315_DMUB); | |
de7cc1b4 PL |
130 | #define FIRMWARE_DCN316_DMUB "amdgpu/dcn_3_1_6_dmcub.bin" |
131 | MODULE_FIRMWARE(FIRMWARE_DCN316_DMUB); | |
2200eb9e | 132 | |
577359ca AP |
133 | #define FIRMWARE_DCN_V3_2_0_DMCUB "amdgpu/dcn_3_2_0_dmcub.bin" |
134 | MODULE_FIRMWARE(FIRMWARE_DCN_V3_2_0_DMCUB); | |
135 | #define FIRMWARE_DCN_V3_2_1_DMCUB "amdgpu/dcn_3_2_1_dmcub.bin" | |
136 | MODULE_FIRMWARE(FIRMWARE_DCN_V3_2_1_DMCUB); | |
137 | ||
a94d5569 DF |
138 | #define FIRMWARE_RAVEN_DMCU "amdgpu/raven_dmcu.bin" |
139 | MODULE_FIRMWARE(FIRMWARE_RAVEN_DMCU); | |
e7b07cee | 140 | |
5ea23931 RL |
141 | #define FIRMWARE_NAVI12_DMCU "amdgpu/navi12_dmcu.bin" |
142 | MODULE_FIRMWARE(FIRMWARE_NAVI12_DMCU); | |
143 | ||
8c7aea40 NK |
144 | /* Number of bytes in PSP header for firmware. */ |
145 | #define PSP_HEADER_BYTES 0x100 | |
146 | ||
147 | /* Number of bytes in PSP footer for firmware. */ | |
148 | #define PSP_FOOTER_BYTES 0x100 | |
149 | ||
b8592b48 LL |
150 | /** |
151 | * DOC: overview | |
152 | * | |
153 | * The AMDgpu display manager, **amdgpu_dm** (or even simpler, | |
ec5c0ffa | 154 | * **dm**) sits between DRM and DC. It acts as a liaison, converting DRM |
b8592b48 LL |
155 | * requests into DC requests, and DC responses into DRM responses. |
156 | * | |
157 | * The root control structure is &struct amdgpu_display_manager. | |
158 | */ | |
159 | ||
7578ecda AD |
160 | /* basic init/fini API */ |
161 | static int amdgpu_dm_init(struct amdgpu_device *adev); | |
162 | static void amdgpu_dm_fini(struct amdgpu_device *adev); | |
fe8858bb | 163 | static bool is_freesync_video_mode(const struct drm_display_mode *mode, struct amdgpu_dm_connector *aconnector); |
7578ecda | 164 | |
0f877894 OV |
165 | static enum drm_mode_subconnector get_subconnector_type(struct dc_link *link) |
166 | { | |
167 | switch (link->dpcd_caps.dongle_type) { | |
168 | case DISPLAY_DONGLE_NONE: | |
169 | return DRM_MODE_SUBCONNECTOR_Native; | |
170 | case DISPLAY_DONGLE_DP_VGA_CONVERTER: | |
171 | return DRM_MODE_SUBCONNECTOR_VGA; | |
172 | case DISPLAY_DONGLE_DP_DVI_CONVERTER: | |
173 | case DISPLAY_DONGLE_DP_DVI_DONGLE: | |
174 | return DRM_MODE_SUBCONNECTOR_DVID; | |
175 | case DISPLAY_DONGLE_DP_HDMI_CONVERTER: | |
176 | case DISPLAY_DONGLE_DP_HDMI_DONGLE: | |
177 | return DRM_MODE_SUBCONNECTOR_HDMIA; | |
178 | case DISPLAY_DONGLE_DP_HDMI_MISMATCHED_DONGLE: | |
179 | default: | |
180 | return DRM_MODE_SUBCONNECTOR_Unknown; | |
181 | } | |
182 | } | |
183 | ||
184 | static void update_subconnector_property(struct amdgpu_dm_connector *aconnector) | |
185 | { | |
186 | struct dc_link *link = aconnector->dc_link; | |
187 | struct drm_connector *connector = &aconnector->base; | |
188 | enum drm_mode_subconnector subconnector = DRM_MODE_SUBCONNECTOR_Unknown; | |
189 | ||
190 | if (connector->connector_type != DRM_MODE_CONNECTOR_DisplayPort) | |
191 | return; | |
192 | ||
193 | if (aconnector->dc_sink) | |
194 | subconnector = get_subconnector_type(link); | |
195 | ||
196 | drm_object_property_set_value(&connector->base, | |
197 | connector->dev->mode_config.dp_subconnector_property, | |
198 | subconnector); | |
199 | } | |
200 | ||
1f6010a9 DF |
201 | /* |
202 | * initializes drm_device display related structures, based on the information | |
7578ecda AD |
203 | * provided by DAL. The drm strcutures are: drm_crtc, drm_connector, |
204 | * drm_encoder, drm_mode_config | |
205 | * | |
206 | * Returns 0 on success | |
207 | */ | |
208 | static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev); | |
209 | /* removes and deallocates the drm structures, created by the above function */ | |
210 | static void amdgpu_dm_destroy_drm_device(struct amdgpu_display_manager *dm); | |
211 | ||
7578ecda AD |
212 | static int amdgpu_dm_connector_init(struct amdgpu_display_manager *dm, |
213 | struct amdgpu_dm_connector *amdgpu_dm_connector, | |
ae67558b | 214 | u32 link_index, |
7578ecda AD |
215 | struct amdgpu_encoder *amdgpu_encoder); |
216 | static int amdgpu_dm_encoder_init(struct drm_device *dev, | |
217 | struct amdgpu_encoder *aencoder, | |
218 | uint32_t link_index); | |
219 | ||
220 | static int amdgpu_dm_connector_get_modes(struct drm_connector *connector); | |
221 | ||
7578ecda AD |
222 | static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state); |
223 | ||
224 | static int amdgpu_dm_atomic_check(struct drm_device *dev, | |
225 | struct drm_atomic_state *state); | |
226 | ||
e27c41d5 | 227 | static void handle_hpd_irq_helper(struct amdgpu_dm_connector *aconnector); |
c40a09e5 | 228 | static void handle_hpd_rx_irq(void *param); |
e27c41d5 | 229 | |
a85ba005 NC |
230 | static bool |
231 | is_timing_unchanged_for_freesync(struct drm_crtc_state *old_crtc_state, | |
232 | struct drm_crtc_state *new_crtc_state); | |
4562236b HW |
233 | /* |
234 | * dm_vblank_get_counter | |
235 | * | |
236 | * @brief | |
237 | * Get counter for number of vertical blanks | |
238 | * | |
239 | * @param | |
240 | * struct amdgpu_device *adev - [in] desired amdgpu device | |
241 | * int disp_idx - [in] which CRTC to get the counter from | |
242 | * | |
243 | * @return | |
244 | * Counter for vertical blanks | |
245 | */ | |
246 | static u32 dm_vblank_get_counter(struct amdgpu_device *adev, int crtc) | |
247 | { | |
248 | if (crtc >= adev->mode_info.num_crtc) | |
249 | return 0; | |
250 | else { | |
251 | struct amdgpu_crtc *acrtc = adev->mode_info.crtcs[crtc]; | |
252 | ||
585d450c | 253 | if (acrtc->dm_irq_params.stream == NULL) { |
0971c40e HW |
254 | DRM_ERROR("dc_stream_state is NULL for crtc '%d'!\n", |
255 | crtc); | |
4562236b HW |
256 | return 0; |
257 | } | |
258 | ||
585d450c | 259 | return dc_stream_get_vblank_counter(acrtc->dm_irq_params.stream); |
4562236b HW |
260 | } |
261 | } | |
262 | ||
263 | static int dm_crtc_get_scanoutpos(struct amdgpu_device *adev, int crtc, | |
3ee6b26b | 264 | u32 *vbl, u32 *position) |
4562236b | 265 | { |
ae67558b | 266 | u32 v_blank_start, v_blank_end, h_position, v_position; |
81c50963 | 267 | |
4562236b HW |
268 | if ((crtc < 0) || (crtc >= adev->mode_info.num_crtc)) |
269 | return -EINVAL; | |
270 | else { | |
271 | struct amdgpu_crtc *acrtc = adev->mode_info.crtcs[crtc]; | |
272 | ||
585d450c | 273 | if (acrtc->dm_irq_params.stream == NULL) { |
0971c40e HW |
274 | DRM_ERROR("dc_stream_state is NULL for crtc '%d'!\n", |
275 | crtc); | |
4562236b HW |
276 | return 0; |
277 | } | |
278 | ||
81c50963 ST |
279 | /* |
280 | * TODO rework base driver to use values directly. | |
281 | * for now parse it back into reg-format | |
282 | */ | |
585d450c | 283 | dc_stream_get_scanoutpos(acrtc->dm_irq_params.stream, |
81c50963 ST |
284 | &v_blank_start, |
285 | &v_blank_end, | |
286 | &h_position, | |
287 | &v_position); | |
288 | ||
e806208d AG |
289 | *position = v_position | (h_position << 16); |
290 | *vbl = v_blank_start | (v_blank_end << 16); | |
4562236b HW |
291 | } |
292 | ||
293 | return 0; | |
294 | } | |
295 | ||
296 | static bool dm_is_idle(void *handle) | |
297 | { | |
298 | /* XXX todo */ | |
299 | return true; | |
300 | } | |
301 | ||
302 | static int dm_wait_for_idle(void *handle) | |
303 | { | |
304 | /* XXX todo */ | |
305 | return 0; | |
306 | } | |
307 | ||
308 | static bool dm_check_soft_reset(void *handle) | |
309 | { | |
310 | return false; | |
311 | } | |
312 | ||
313 | static int dm_soft_reset(void *handle) | |
314 | { | |
315 | /* XXX todo */ | |
316 | return 0; | |
317 | } | |
318 | ||
3ee6b26b AD |
319 | static struct amdgpu_crtc * |
320 | get_crtc_by_otg_inst(struct amdgpu_device *adev, | |
321 | int otg_inst) | |
4562236b | 322 | { |
4a580877 | 323 | struct drm_device *dev = adev_to_drm(adev); |
4562236b HW |
324 | struct drm_crtc *crtc; |
325 | struct amdgpu_crtc *amdgpu_crtc; | |
326 | ||
bcd74374 | 327 | if (WARN_ON(otg_inst == -1)) |
4562236b | 328 | return adev->mode_info.crtcs[0]; |
4562236b HW |
329 | |
330 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { | |
331 | amdgpu_crtc = to_amdgpu_crtc(crtc); | |
332 | ||
333 | if (amdgpu_crtc->otg_inst == otg_inst) | |
334 | return amdgpu_crtc; | |
335 | } | |
336 | ||
337 | return NULL; | |
338 | } | |
339 | ||
a85ba005 NC |
340 | static inline bool is_dc_timing_adjust_needed(struct dm_crtc_state *old_state, |
341 | struct dm_crtc_state *new_state) | |
342 | { | |
343 | if (new_state->freesync_config.state == VRR_STATE_ACTIVE_FIXED) | |
344 | return true; | |
6c5e25a0 | 345 | else if (amdgpu_dm_crtc_vrr_active(old_state) != amdgpu_dm_crtc_vrr_active(new_state)) |
a85ba005 NC |
346 | return true; |
347 | else | |
348 | return false; | |
349 | } | |
350 | ||
bb46a6a9 RS |
351 | static inline void reverse_planes_order(struct dc_surface_update *array_of_surface_update, |
352 | int planes_count) | |
353 | { | |
354 | int i, j; | |
bb46a6a9 | 355 | |
8866d627 JC |
356 | for (i = 0, j = planes_count - 1; i < j; i++, j--) |
357 | swap(array_of_surface_update[i], array_of_surface_update[j]); | |
bb46a6a9 RS |
358 | } |
359 | ||
81f743a0 RS |
360 | /** |
361 | * update_planes_and_stream_adapter() - Send planes to be updated in DC | |
362 | * | |
363 | * DC has a generic way to update planes and stream via | |
364 | * dc_update_planes_and_stream function; however, DM might need some | |
365 | * adjustments and preparation before calling it. This function is a wrapper | |
366 | * for the dc_update_planes_and_stream that does any required configuration | |
367 | * before passing control to DC. | |
368 | */ | |
369 | static inline bool update_planes_and_stream_adapter(struct dc *dc, | |
370 | int update_type, | |
371 | int planes_count, | |
372 | struct dc_stream_state *stream, | |
373 | struct dc_stream_update *stream_update, | |
374 | struct dc_surface_update *array_of_surface_update) | |
375 | { | |
bb46a6a9 RS |
376 | reverse_planes_order(array_of_surface_update, planes_count); |
377 | ||
81f743a0 RS |
378 | /* |
379 | * Previous frame finished and HW is ready for optimization. | |
380 | */ | |
381 | if (update_type == UPDATE_TYPE_FAST) | |
382 | dc_post_update_surfaces_to_stream(dc); | |
383 | ||
384 | return dc_update_planes_and_stream(dc, | |
385 | array_of_surface_update, | |
386 | planes_count, | |
387 | stream, | |
388 | stream_update); | |
389 | } | |
390 | ||
b8e8c934 HW |
391 | /** |
392 | * dm_pflip_high_irq() - Handle pageflip interrupt | |
393 | * @interrupt_params: ignored | |
394 | * | |
395 | * Handles the pageflip interrupt by notifying all interested parties | |
396 | * that the pageflip has been completed. | |
397 | */ | |
4562236b HW |
398 | static void dm_pflip_high_irq(void *interrupt_params) |
399 | { | |
4562236b HW |
400 | struct amdgpu_crtc *amdgpu_crtc; |
401 | struct common_irq_params *irq_params = interrupt_params; | |
402 | struct amdgpu_device *adev = irq_params->adev; | |
403 | unsigned long flags; | |
71bbe51a | 404 | struct drm_pending_vblank_event *e; |
ae67558b | 405 | u32 vpos, hpos, v_blank_start, v_blank_end; |
71bbe51a | 406 | bool vrr_active; |
4562236b HW |
407 | |
408 | amdgpu_crtc = get_crtc_by_otg_inst(adev, irq_params->irq_src - IRQ_TYPE_PFLIP); | |
409 | ||
410 | /* IRQ could occur when in initial stage */ | |
1f6010a9 | 411 | /* TODO work and BO cleanup */ |
4562236b | 412 | if (amdgpu_crtc == NULL) { |
cb2318b7 | 413 | DC_LOG_PFLIP("CRTC is null, returning.\n"); |
4562236b HW |
414 | return; |
415 | } | |
416 | ||
4a580877 | 417 | spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags); |
4562236b HW |
418 | |
419 | if (amdgpu_crtc->pflip_status != AMDGPU_FLIP_SUBMITTED){ | |
cb2318b7 | 420 | DC_LOG_PFLIP("amdgpu_crtc->pflip_status = %d !=AMDGPU_FLIP_SUBMITTED(%d) on crtc:%d[%p] \n", |
4562236b HW |
421 | amdgpu_crtc->pflip_status, |
422 | AMDGPU_FLIP_SUBMITTED, | |
423 | amdgpu_crtc->crtc_id, | |
424 | amdgpu_crtc); | |
4a580877 | 425 | spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags); |
4562236b HW |
426 | return; |
427 | } | |
428 | ||
71bbe51a MK |
429 | /* page flip completed. */ |
430 | e = amdgpu_crtc->event; | |
431 | amdgpu_crtc->event = NULL; | |
4562236b | 432 | |
bcd74374 | 433 | WARN_ON(!e); |
1159898a | 434 | |
6c5e25a0 | 435 | vrr_active = amdgpu_dm_crtc_vrr_active_irq(amdgpu_crtc); |
71bbe51a MK |
436 | |
437 | /* Fixed refresh rate, or VRR scanout position outside front-porch? */ | |
438 | if (!vrr_active || | |
585d450c | 439 | !dc_stream_get_scanoutpos(amdgpu_crtc->dm_irq_params.stream, &v_blank_start, |
71bbe51a MK |
440 | &v_blank_end, &hpos, &vpos) || |
441 | (vpos < v_blank_start)) { | |
442 | /* Update to correct count and vblank timestamp if racing with | |
443 | * vblank irq. This also updates to the correct vblank timestamp | |
444 | * even in VRR mode, as scanout is past the front-porch atm. | |
445 | */ | |
446 | drm_crtc_accurate_vblank_count(&amdgpu_crtc->base); | |
1159898a | 447 | |
71bbe51a MK |
448 | /* Wake up userspace by sending the pageflip event with proper |
449 | * count and timestamp of vblank of flip completion. | |
450 | */ | |
451 | if (e) { | |
452 | drm_crtc_send_vblank_event(&amdgpu_crtc->base, e); | |
453 | ||
454 | /* Event sent, so done with vblank for this flip */ | |
455 | drm_crtc_vblank_put(&amdgpu_crtc->base); | |
456 | } | |
457 | } else if (e) { | |
458 | /* VRR active and inside front-porch: vblank count and | |
459 | * timestamp for pageflip event will only be up to date after | |
460 | * drm_crtc_handle_vblank() has been executed from late vblank | |
461 | * irq handler after start of back-porch (vline 0). We queue the | |
462 | * pageflip event for send-out by drm_crtc_handle_vblank() with | |
463 | * updated timestamp and count, once it runs after us. | |
464 | * | |
465 | * We need to open-code this instead of using the helper | |
466 | * drm_crtc_arm_vblank_event(), as that helper would | |
467 | * call drm_crtc_accurate_vblank_count(), which we must | |
468 | * not call in VRR mode while we are in front-porch! | |
469 | */ | |
470 | ||
471 | /* sequence will be replaced by real count during send-out. */ | |
472 | e->sequence = drm_crtc_vblank_count(&amdgpu_crtc->base); | |
473 | e->pipe = amdgpu_crtc->crtc_id; | |
474 | ||
4a580877 | 475 | list_add_tail(&e->base.link, &adev_to_drm(adev)->vblank_event_list); |
71bbe51a MK |
476 | e = NULL; |
477 | } | |
4562236b | 478 | |
fdd1fe57 MK |
479 | /* Keep track of vblank of this flip for flip throttling. We use the |
480 | * cooked hw counter, as that one incremented at start of this vblank | |
481 | * of pageflip completion, so last_flip_vblank is the forbidden count | |
482 | * for queueing new pageflips if vsync + VRR is enabled. | |
483 | */ | |
5d1c59c4 | 484 | amdgpu_crtc->dm_irq_params.last_flip_vblank = |
e3eff4b5 | 485 | amdgpu_get_vblank_counter_kms(&amdgpu_crtc->base); |
fdd1fe57 | 486 | |
54f5499a | 487 | amdgpu_crtc->pflip_status = AMDGPU_FLIP_NONE; |
4a580877 | 488 | spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags); |
4562236b | 489 | |
cb2318b7 VL |
490 | DC_LOG_PFLIP("crtc:%d[%p], pflip_stat:AMDGPU_FLIP_NONE, vrr[%d]-fp %d\n", |
491 | amdgpu_crtc->crtc_id, amdgpu_crtc, | |
492 | vrr_active, (int) !e); | |
4562236b HW |
493 | } |
494 | ||
d2574c33 MK |
495 | static void dm_vupdate_high_irq(void *interrupt_params) |
496 | { | |
497 | struct common_irq_params *irq_params = interrupt_params; | |
498 | struct amdgpu_device *adev = irq_params->adev; | |
499 | struct amdgpu_crtc *acrtc; | |
47588233 RS |
500 | struct drm_device *drm_dev; |
501 | struct drm_vblank_crtc *vblank; | |
502 | ktime_t frame_duration_ns, previous_timestamp; | |
09aef2c4 | 503 | unsigned long flags; |
585d450c | 504 | int vrr_active; |
d2574c33 MK |
505 | |
506 | acrtc = get_crtc_by_otg_inst(adev, irq_params->irq_src - IRQ_TYPE_VUPDATE); | |
507 | ||
508 | if (acrtc) { | |
6c5e25a0 | 509 | vrr_active = amdgpu_dm_crtc_vrr_active_irq(acrtc); |
47588233 RS |
510 | drm_dev = acrtc->base.dev; |
511 | vblank = &drm_dev->vblank[acrtc->base.index]; | |
512 | previous_timestamp = atomic64_read(&irq_params->previous_timestamp); | |
513 | frame_duration_ns = vblank->time - previous_timestamp; | |
514 | ||
515 | if (frame_duration_ns > 0) { | |
516 | trace_amdgpu_refresh_rate_track(acrtc->base.index, | |
517 | frame_duration_ns, | |
518 | ktime_divns(NSEC_PER_SEC, frame_duration_ns)); | |
519 | atomic64_set(&irq_params->previous_timestamp, vblank->time); | |
520 | } | |
d2574c33 | 521 | |
cb2318b7 | 522 | DC_LOG_VBLANK("crtc:%d, vupdate-vrr:%d\n", |
7f2be468 | 523 | acrtc->crtc_id, |
585d450c | 524 | vrr_active); |
d2574c33 MK |
525 | |
526 | /* Core vblank handling is done here after end of front-porch in | |
527 | * vrr mode, as vblank timestamping will give valid results | |
528 | * while now done after front-porch. This will also deliver | |
529 | * page-flip completion events that have been queued to us | |
530 | * if a pageflip happened inside front-porch. | |
531 | */ | |
585d450c | 532 | if (vrr_active) { |
6c5e25a0 | 533 | amdgpu_dm_crtc_handle_vblank(acrtc); |
09aef2c4 MK |
534 | |
535 | /* BTR processing for pre-DCE12 ASICs */ | |
585d450c | 536 | if (acrtc->dm_irq_params.stream && |
09aef2c4 | 537 | adev->family < AMDGPU_FAMILY_AI) { |
4a580877 | 538 | spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags); |
09aef2c4 MK |
539 | mod_freesync_handle_v_update( |
540 | adev->dm.freesync_module, | |
585d450c AP |
541 | acrtc->dm_irq_params.stream, |
542 | &acrtc->dm_irq_params.vrr_params); | |
09aef2c4 MK |
543 | |
544 | dc_stream_adjust_vmin_vmax( | |
545 | adev->dm.dc, | |
585d450c AP |
546 | acrtc->dm_irq_params.stream, |
547 | &acrtc->dm_irq_params.vrr_params.adjust); | |
4a580877 | 548 | spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags); |
09aef2c4 MK |
549 | } |
550 | } | |
d2574c33 MK |
551 | } |
552 | } | |
553 | ||
b8e8c934 HW |
554 | /** |
555 | * dm_crtc_high_irq() - Handles CRTC interrupt | |
2346ef47 | 556 | * @interrupt_params: used for determining the CRTC instance |
b8e8c934 HW |
557 | * |
558 | * Handles the CRTC/VSYNC interrupt by notfying DRM's VBLANK | |
559 | * event handler. | |
560 | */ | |
4562236b HW |
561 | static void dm_crtc_high_irq(void *interrupt_params) |
562 | { | |
563 | struct common_irq_params *irq_params = interrupt_params; | |
564 | struct amdgpu_device *adev = irq_params->adev; | |
4562236b | 565 | struct amdgpu_crtc *acrtc; |
09aef2c4 | 566 | unsigned long flags; |
585d450c | 567 | int vrr_active; |
4562236b | 568 | |
b57de80a | 569 | acrtc = get_crtc_by_otg_inst(adev, irq_params->irq_src - IRQ_TYPE_VBLANK); |
16f17eda LL |
570 | if (!acrtc) |
571 | return; | |
572 | ||
6c5e25a0 | 573 | vrr_active = amdgpu_dm_crtc_vrr_active_irq(acrtc); |
16f17eda | 574 | |
cb2318b7 | 575 | DC_LOG_VBLANK("crtc:%d, vupdate-vrr:%d, planes:%d\n", acrtc->crtc_id, |
585d450c | 576 | vrr_active, acrtc->dm_irq_params.active_planes); |
16f17eda | 577 | |
2346ef47 NK |
578 | /** |
579 | * Core vblank handling at start of front-porch is only possible | |
580 | * in non-vrr mode, as only there vblank timestamping will give | |
581 | * valid results while done in front-porch. Otherwise defer it | |
582 | * to dm_vupdate_high_irq after end of front-porch. | |
583 | */ | |
585d450c | 584 | if (!vrr_active) |
6c5e25a0 | 585 | amdgpu_dm_crtc_handle_vblank(acrtc); |
2346ef47 NK |
586 | |
587 | /** | |
588 | * Following stuff must happen at start of vblank, for crc | |
589 | * computation and below-the-range btr support in vrr mode. | |
590 | */ | |
16f17eda | 591 | amdgpu_dm_crtc_handle_crc_irq(&acrtc->base); |
2346ef47 NK |
592 | |
593 | /* BTR updates need to happen before VUPDATE on Vega and above. */ | |
594 | if (adev->family < AMDGPU_FAMILY_AI) | |
595 | return; | |
16f17eda | 596 | |
4a580877 | 597 | spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags); |
16f17eda | 598 | |
585d450c AP |
599 | if (acrtc->dm_irq_params.stream && |
600 | acrtc->dm_irq_params.vrr_params.supported && | |
601 | acrtc->dm_irq_params.freesync_config.state == | |
602 | VRR_STATE_ACTIVE_VARIABLE) { | |
2346ef47 | 603 | mod_freesync_handle_v_update(adev->dm.freesync_module, |
585d450c AP |
604 | acrtc->dm_irq_params.stream, |
605 | &acrtc->dm_irq_params.vrr_params); | |
16f17eda | 606 | |
585d450c AP |
607 | dc_stream_adjust_vmin_vmax(adev->dm.dc, acrtc->dm_irq_params.stream, |
608 | &acrtc->dm_irq_params.vrr_params.adjust); | |
16f17eda LL |
609 | } |
610 | ||
2b5aed9a MK |
611 | /* |
612 | * If there aren't any active_planes then DCH HUBP may be clock-gated. | |
613 | * In that case, pageflip completion interrupts won't fire and pageflip | |
614 | * completion events won't get delivered. Prevent this by sending | |
615 | * pending pageflip events from here if a flip is still pending. | |
616 | * | |
617 | * If any planes are enabled, use dm_pflip_high_irq() instead, to | |
618 | * avoid race conditions between flip programming and completion, | |
619 | * which could cause too early flip completion events. | |
620 | */ | |
2346ef47 NK |
621 | if (adev->family >= AMDGPU_FAMILY_RV && |
622 | acrtc->pflip_status == AMDGPU_FLIP_SUBMITTED && | |
585d450c | 623 | acrtc->dm_irq_params.active_planes == 0) { |
16f17eda LL |
624 | if (acrtc->event) { |
625 | drm_crtc_send_vblank_event(&acrtc->base, acrtc->event); | |
626 | acrtc->event = NULL; | |
627 | drm_crtc_vblank_put(&acrtc->base); | |
628 | } | |
629 | acrtc->pflip_status = AMDGPU_FLIP_NONE; | |
630 | } | |
631 | ||
4a580877 | 632 | spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags); |
16f17eda LL |
633 | } |
634 | ||
9e1178ef | 635 | #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY) |
86bc2219 WL |
636 | /** |
637 | * dm_dcn_vertical_interrupt0_high_irq() - Handles OTG Vertical interrupt0 for | |
638 | * DCN generation ASICs | |
48e01bf4 | 639 | * @interrupt_params: interrupt parameters |
86bc2219 WL |
640 | * |
641 | * Used to set crc window/read out crc value at vertical line 0 position | |
642 | */ | |
86bc2219 WL |
643 | static void dm_dcn_vertical_interrupt0_high_irq(void *interrupt_params) |
644 | { | |
645 | struct common_irq_params *irq_params = interrupt_params; | |
646 | struct amdgpu_device *adev = irq_params->adev; | |
647 | struct amdgpu_crtc *acrtc; | |
648 | ||
649 | acrtc = get_crtc_by_otg_inst(adev, irq_params->irq_src - IRQ_TYPE_VLINE0); | |
650 | ||
651 | if (!acrtc) | |
652 | return; | |
653 | ||
654 | amdgpu_dm_crtc_handle_crc_window_irq(&acrtc->base); | |
655 | } | |
433e5dec | 656 | #endif /* CONFIG_DRM_AMD_SECURE_DISPLAY */ |
86bc2219 | 657 | |
e27c41d5 | 658 | /** |
03f2abb0 | 659 | * dmub_aux_setconfig_callback - Callback for AUX or SET_CONFIG command. |
e27c41d5 JS |
660 | * @adev: amdgpu_device pointer |
661 | * @notify: dmub notification structure | |
662 | * | |
663 | * Dmub AUX or SET_CONFIG command completion processing callback | |
664 | * Copies dmub notification to DM which is to be read by AUX command. | |
665 | * issuing thread and also signals the event to wake up the thread. | |
666 | */ | |
240e6d25 IB |
667 | static void dmub_aux_setconfig_callback(struct amdgpu_device *adev, |
668 | struct dmub_notification *notify) | |
e27c41d5 JS |
669 | { |
670 | if (adev->dm.dmub_notify) | |
671 | memcpy(adev->dm.dmub_notify, notify, sizeof(struct dmub_notification)); | |
672 | if (notify->type == DMUB_NOTIFICATION_AUX_REPLY) | |
673 | complete(&adev->dm.dmub_aux_transfer_done); | |
674 | } | |
675 | ||
676 | /** | |
677 | * dmub_hpd_callback - DMUB HPD interrupt processing callback. | |
678 | * @adev: amdgpu_device pointer | |
679 | * @notify: dmub notification structure | |
680 | * | |
681 | * Dmub Hpd interrupt processing callback. Gets displayindex through the | |
682 | * ink index and calls helper to do the processing. | |
683 | */ | |
240e6d25 IB |
684 | static void dmub_hpd_callback(struct amdgpu_device *adev, |
685 | struct dmub_notification *notify) | |
e27c41d5 JS |
686 | { |
687 | struct amdgpu_dm_connector *aconnector; | |
f6e03f80 | 688 | struct amdgpu_dm_connector *hpd_aconnector = NULL; |
e27c41d5 JS |
689 | struct drm_connector *connector; |
690 | struct drm_connector_list_iter iter; | |
691 | struct dc_link *link; | |
ae67558b | 692 | u8 link_index = 0; |
978ffac8 | 693 | struct drm_device *dev; |
e27c41d5 JS |
694 | |
695 | if (adev == NULL) | |
696 | return; | |
697 | ||
698 | if (notify == NULL) { | |
699 | DRM_ERROR("DMUB HPD callback notification was NULL"); | |
700 | return; | |
701 | } | |
702 | ||
703 | if (notify->link_index > adev->dm.dc->link_count) { | |
704 | DRM_ERROR("DMUB HPD index (%u)is abnormal", notify->link_index); | |
705 | return; | |
706 | } | |
707 | ||
e27c41d5 | 708 | link_index = notify->link_index; |
e27c41d5 | 709 | link = adev->dm.dc->links[link_index]; |
978ffac8 | 710 | dev = adev->dm.ddev; |
e27c41d5 JS |
711 | |
712 | drm_connector_list_iter_begin(dev, &iter); | |
713 | drm_for_each_connector_iter(connector, &iter) { | |
714 | aconnector = to_amdgpu_dm_connector(connector); | |
715 | if (link && aconnector->dc_link == link) { | |
c416a9e4 SW |
716 | if (notify->type == DMUB_NOTIFICATION_HPD) |
717 | DRM_INFO("DMUB HPD callback: link_index=%u\n", link_index); | |
718 | else if (notify->type == DMUB_NOTIFICATION_HPD_IRQ) | |
719 | DRM_INFO("DMUB HPD IRQ callback: link_index=%u\n", link_index); | |
720 | else | |
721 | DRM_WARN("DMUB Unknown HPD callback type %d, link_index=%u\n", | |
722 | notify->type, link_index); | |
723 | ||
f6e03f80 | 724 | hpd_aconnector = aconnector; |
e27c41d5 JS |
725 | break; |
726 | } | |
727 | } | |
728 | drm_connector_list_iter_end(&iter); | |
e27c41d5 | 729 | |
c40a09e5 NK |
730 | if (hpd_aconnector) { |
731 | if (notify->type == DMUB_NOTIFICATION_HPD) | |
732 | handle_hpd_irq_helper(hpd_aconnector); | |
733 | else if (notify->type == DMUB_NOTIFICATION_HPD_IRQ) | |
734 | handle_hpd_rx_irq(hpd_aconnector); | |
735 | } | |
e27c41d5 JS |
736 | } |
737 | ||
738 | /** | |
739 | * register_dmub_notify_callback - Sets callback for DMUB notify | |
740 | * @adev: amdgpu_device pointer | |
741 | * @type: Type of dmub notification | |
742 | * @callback: Dmub interrupt callback function | |
743 | * @dmub_int_thread_offload: offload indicator | |
744 | * | |
745 | * API to register a dmub callback handler for a dmub notification | |
746 | * Also sets indicator whether callback processing to be offloaded. | |
747 | * to dmub interrupt handling thread | |
748 | * Return: true if successfully registered, false if there is existing registration | |
749 | */ | |
240e6d25 IB |
750 | static bool register_dmub_notify_callback(struct amdgpu_device *adev, |
751 | enum dmub_notification_type type, | |
752 | dmub_notify_interrupt_callback_t callback, | |
753 | bool dmub_int_thread_offload) | |
e27c41d5 JS |
754 | { |
755 | if (callback != NULL && type < ARRAY_SIZE(adev->dm.dmub_thread_offload)) { | |
756 | adev->dm.dmub_callback[type] = callback; | |
757 | adev->dm.dmub_thread_offload[type] = dmub_int_thread_offload; | |
758 | } else | |
759 | return false; | |
760 | ||
761 | return true; | |
762 | } | |
763 | ||
764 | static void dm_handle_hpd_work(struct work_struct *work) | |
765 | { | |
766 | struct dmub_hpd_work *dmub_hpd_wrk; | |
767 | ||
768 | dmub_hpd_wrk = container_of(work, struct dmub_hpd_work, handle_hpd_work); | |
769 | ||
770 | if (!dmub_hpd_wrk->dmub_notify) { | |
771 | DRM_ERROR("dmub_hpd_wrk dmub_notify is NULL"); | |
772 | return; | |
773 | } | |
774 | ||
775 | if (dmub_hpd_wrk->dmub_notify->type < ARRAY_SIZE(dmub_hpd_wrk->adev->dm.dmub_callback)) { | |
776 | dmub_hpd_wrk->adev->dm.dmub_callback[dmub_hpd_wrk->dmub_notify->type](dmub_hpd_wrk->adev, | |
777 | dmub_hpd_wrk->dmub_notify); | |
778 | } | |
094b21c1 JS |
779 | |
780 | kfree(dmub_hpd_wrk->dmub_notify); | |
e27c41d5 JS |
781 | kfree(dmub_hpd_wrk); |
782 | ||
783 | } | |
784 | ||
e25515e2 | 785 | #define DMUB_TRACE_MAX_READ 64 |
81927e28 JS |
786 | /** |
787 | * dm_dmub_outbox1_low_irq() - Handles Outbox interrupt | |
788 | * @interrupt_params: used for determining the Outbox instance | |
789 | * | |
790 | * Handles the Outbox Interrupt | |
791 | * event handler. | |
792 | */ | |
81927e28 JS |
793 | static void dm_dmub_outbox1_low_irq(void *interrupt_params) |
794 | { | |
795 | struct dmub_notification notify; | |
796 | struct common_irq_params *irq_params = interrupt_params; | |
797 | struct amdgpu_device *adev = irq_params->adev; | |
798 | struct amdgpu_display_manager *dm = &adev->dm; | |
799 | struct dmcub_trace_buf_entry entry = { 0 }; | |
ae67558b | 800 | u32 count = 0; |
e27c41d5 | 801 | struct dmub_hpd_work *dmub_hpd_wrk; |
f6e03f80 | 802 | struct dc_link *plink = NULL; |
81927e28 | 803 | |
f6e03f80 JS |
804 | if (dc_enable_dmub_notifications(adev->dm.dc) && |
805 | irq_params->irq_src == DC_IRQ_SOURCE_DMCUB_OUTBOX) { | |
e27c41d5 | 806 | |
f6e03f80 JS |
807 | do { |
808 | dc_stat_get_dmub_notification(adev->dm.dc, ¬ify); | |
a35faec3 | 809 | if (notify.type >= ARRAY_SIZE(dm->dmub_thread_offload)) { |
f6e03f80 JS |
810 | DRM_ERROR("DM: notify type %d invalid!", notify.type); |
811 | continue; | |
812 | } | |
c40a09e5 NK |
813 | if (!dm->dmub_callback[notify.type]) { |
814 | DRM_DEBUG_DRIVER("DMUB notification skipped, no handler: type=%d\n", notify.type); | |
815 | continue; | |
816 | } | |
f6e03f80 | 817 | if (dm->dmub_thread_offload[notify.type] == true) { |
094b21c1 JS |
818 | dmub_hpd_wrk = kzalloc(sizeof(*dmub_hpd_wrk), GFP_ATOMIC); |
819 | if (!dmub_hpd_wrk) { | |
820 | DRM_ERROR("Failed to allocate dmub_hpd_wrk"); | |
821 | return; | |
822 | } | |
0e909e4f CJ |
823 | dmub_hpd_wrk->dmub_notify = kmemdup(¬ify, sizeof(struct dmub_notification), |
824 | GFP_ATOMIC); | |
094b21c1 JS |
825 | if (!dmub_hpd_wrk->dmub_notify) { |
826 | kfree(dmub_hpd_wrk); | |
827 | DRM_ERROR("Failed to allocate dmub_hpd_wrk->dmub_notify"); | |
828 | return; | |
829 | } | |
830 | INIT_WORK(&dmub_hpd_wrk->handle_hpd_work, dm_handle_hpd_work); | |
f6e03f80 JS |
831 | dmub_hpd_wrk->adev = adev; |
832 | if (notify.type == DMUB_NOTIFICATION_HPD) { | |
833 | plink = adev->dm.dc->links[notify.link_index]; | |
834 | if (plink) { | |
835 | plink->hpd_status = | |
b97788e5 | 836 | notify.hpd_status == DP_HPD_PLUG; |
f6e03f80 | 837 | } |
e27c41d5 | 838 | } |
f6e03f80 JS |
839 | queue_work(adev->dm.delayed_hpd_wq, &dmub_hpd_wrk->handle_hpd_work); |
840 | } else { | |
841 | dm->dmub_callback[notify.type](adev, ¬ify); | |
842 | } | |
843 | } while (notify.pending_notification); | |
81927e28 JS |
844 | } |
845 | ||
846 | ||
847 | do { | |
848 | if (dc_dmub_srv_get_dmub_outbox0_msg(dm->dc, &entry)) { | |
849 | trace_amdgpu_dmub_trace_high_irq(entry.trace_code, entry.tick_count, | |
850 | entry.param0, entry.param1); | |
851 | ||
852 | DRM_DEBUG_DRIVER("trace_code:%u, tick_count:%u, param0:%u, param1:%u\n", | |
853 | entry.trace_code, entry.tick_count, entry.param0, entry.param1); | |
854 | } else | |
855 | break; | |
856 | ||
857 | count++; | |
858 | ||
859 | } while (count <= DMUB_TRACE_MAX_READ); | |
860 | ||
f6e03f80 JS |
861 | if (count > DMUB_TRACE_MAX_READ) |
862 | DRM_DEBUG_DRIVER("Warning : count > DMUB_TRACE_MAX_READ"); | |
81927e28 | 863 | } |
86bc2219 | 864 | |
4562236b HW |
865 | static int dm_set_clockgating_state(void *handle, |
866 | enum amd_clockgating_state state) | |
867 | { | |
868 | return 0; | |
869 | } | |
870 | ||
871 | static int dm_set_powergating_state(void *handle, | |
872 | enum amd_powergating_state state) | |
873 | { | |
874 | return 0; | |
875 | } | |
876 | ||
877 | /* Prototypes of private functions */ | |
878 | static int dm_early_init(void* handle); | |
879 | ||
a32e24b4 | 880 | /* Allocate memory for FBC compressed data */ |
3e332d3a | 881 | static void amdgpu_dm_fbc_init(struct drm_connector *connector) |
a32e24b4 | 882 | { |
3e332d3a | 883 | struct drm_device *dev = connector->dev; |
1348969a | 884 | struct amdgpu_device *adev = drm_to_adev(dev); |
4d154b85 | 885 | struct dm_compressor_info *compressor = &adev->dm.compressor; |
3e332d3a RL |
886 | struct amdgpu_dm_connector *aconn = to_amdgpu_dm_connector(connector); |
887 | struct drm_display_mode *mode; | |
42e67c3b RL |
888 | unsigned long max_size = 0; |
889 | ||
890 | if (adev->dm.dc->fbc_compressor == NULL) | |
891 | return; | |
a32e24b4 | 892 | |
3e332d3a | 893 | if (aconn->dc_link->connector_signal != SIGNAL_TYPE_EDP) |
42e67c3b RL |
894 | return; |
895 | ||
3e332d3a RL |
896 | if (compressor->bo_ptr) |
897 | return; | |
42e67c3b | 898 | |
42e67c3b | 899 | |
3e332d3a RL |
900 | list_for_each_entry(mode, &connector->modes, head) { |
901 | if (max_size < mode->htotal * mode->vtotal) | |
902 | max_size = mode->htotal * mode->vtotal; | |
42e67c3b RL |
903 | } |
904 | ||
905 | if (max_size) { | |
906 | int r = amdgpu_bo_create_kernel(adev, max_size * 4, PAGE_SIZE, | |
0e5916ff | 907 | AMDGPU_GEM_DOMAIN_GTT, &compressor->bo_ptr, |
42e67c3b | 908 | &compressor->gpu_addr, &compressor->cpu_addr); |
a32e24b4 RL |
909 | |
910 | if (r) | |
42e67c3b RL |
911 | DRM_ERROR("DM: Failed to initialize FBC\n"); |
912 | else { | |
913 | adev->dm.dc->ctx->fbc_gpu_addr = compressor->gpu_addr; | |
914 | DRM_INFO("DM: FBC alloc %lu\n", max_size*4); | |
915 | } | |
916 | ||
a32e24b4 RL |
917 | } |
918 | ||
919 | } | |
a32e24b4 | 920 | |
6ce8f316 NK |
921 | static int amdgpu_dm_audio_component_get_eld(struct device *kdev, int port, |
922 | int pipe, bool *enabled, | |
923 | unsigned char *buf, int max_bytes) | |
924 | { | |
925 | struct drm_device *dev = dev_get_drvdata(kdev); | |
1348969a | 926 | struct amdgpu_device *adev = drm_to_adev(dev); |
6ce8f316 NK |
927 | struct drm_connector *connector; |
928 | struct drm_connector_list_iter conn_iter; | |
929 | struct amdgpu_dm_connector *aconnector; | |
930 | int ret = 0; | |
931 | ||
932 | *enabled = false; | |
933 | ||
934 | mutex_lock(&adev->dm.audio_lock); | |
935 | ||
936 | drm_connector_list_iter_begin(dev, &conn_iter); | |
937 | drm_for_each_connector_iter(connector, &conn_iter) { | |
938 | aconnector = to_amdgpu_dm_connector(connector); | |
939 | if (aconnector->audio_inst != port) | |
940 | continue; | |
941 | ||
942 | *enabled = true; | |
943 | ret = drm_eld_size(connector->eld); | |
944 | memcpy(buf, connector->eld, min(max_bytes, ret)); | |
945 | ||
946 | break; | |
947 | } | |
948 | drm_connector_list_iter_end(&conn_iter); | |
949 | ||
950 | mutex_unlock(&adev->dm.audio_lock); | |
951 | ||
952 | DRM_DEBUG_KMS("Get ELD : idx=%d ret=%d en=%d\n", port, ret, *enabled); | |
953 | ||
954 | return ret; | |
955 | } | |
956 | ||
957 | static const struct drm_audio_component_ops amdgpu_dm_audio_component_ops = { | |
958 | .get_eld = amdgpu_dm_audio_component_get_eld, | |
959 | }; | |
960 | ||
961 | static int amdgpu_dm_audio_component_bind(struct device *kdev, | |
962 | struct device *hda_kdev, void *data) | |
963 | { | |
964 | struct drm_device *dev = dev_get_drvdata(kdev); | |
1348969a | 965 | struct amdgpu_device *adev = drm_to_adev(dev); |
6ce8f316 NK |
966 | struct drm_audio_component *acomp = data; |
967 | ||
968 | acomp->ops = &amdgpu_dm_audio_component_ops; | |
969 | acomp->dev = kdev; | |
970 | adev->dm.audio_component = acomp; | |
971 | ||
972 | return 0; | |
973 | } | |
974 | ||
975 | static void amdgpu_dm_audio_component_unbind(struct device *kdev, | |
976 | struct device *hda_kdev, void *data) | |
977 | { | |
978 | struct drm_device *dev = dev_get_drvdata(kdev); | |
1348969a | 979 | struct amdgpu_device *adev = drm_to_adev(dev); |
6ce8f316 NK |
980 | struct drm_audio_component *acomp = data; |
981 | ||
982 | acomp->ops = NULL; | |
983 | acomp->dev = NULL; | |
984 | adev->dm.audio_component = NULL; | |
985 | } | |
986 | ||
987 | static const struct component_ops amdgpu_dm_audio_component_bind_ops = { | |
988 | .bind = amdgpu_dm_audio_component_bind, | |
989 | .unbind = amdgpu_dm_audio_component_unbind, | |
990 | }; | |
991 | ||
992 | static int amdgpu_dm_audio_init(struct amdgpu_device *adev) | |
993 | { | |
994 | int i, ret; | |
995 | ||
996 | if (!amdgpu_audio) | |
997 | return 0; | |
998 | ||
999 | adev->mode_info.audio.enabled = true; | |
1000 | ||
1001 | adev->mode_info.audio.num_pins = adev->dm.dc->res_pool->audio_count; | |
1002 | ||
1003 | for (i = 0; i < adev->mode_info.audio.num_pins; i++) { | |
1004 | adev->mode_info.audio.pin[i].channels = -1; | |
1005 | adev->mode_info.audio.pin[i].rate = -1; | |
1006 | adev->mode_info.audio.pin[i].bits_per_sample = -1; | |
1007 | adev->mode_info.audio.pin[i].status_bits = 0; | |
1008 | adev->mode_info.audio.pin[i].category_code = 0; | |
1009 | adev->mode_info.audio.pin[i].connected = false; | |
1010 | adev->mode_info.audio.pin[i].id = | |
1011 | adev->dm.dc->res_pool->audios[i]->inst; | |
1012 | adev->mode_info.audio.pin[i].offset = 0; | |
1013 | } | |
1014 | ||
1015 | ret = component_add(adev->dev, &amdgpu_dm_audio_component_bind_ops); | |
1016 | if (ret < 0) | |
1017 | return ret; | |
1018 | ||
1019 | adev->dm.audio_registered = true; | |
1020 | ||
1021 | return 0; | |
1022 | } | |
1023 | ||
1024 | static void amdgpu_dm_audio_fini(struct amdgpu_device *adev) | |
1025 | { | |
1026 | if (!amdgpu_audio) | |
1027 | return; | |
1028 | ||
1029 | if (!adev->mode_info.audio.enabled) | |
1030 | return; | |
1031 | ||
1032 | if (adev->dm.audio_registered) { | |
1033 | component_del(adev->dev, &amdgpu_dm_audio_component_bind_ops); | |
1034 | adev->dm.audio_registered = false; | |
1035 | } | |
1036 | ||
1037 | /* TODO: Disable audio? */ | |
1038 | ||
1039 | adev->mode_info.audio.enabled = false; | |
1040 | } | |
1041 | ||
dfd84d90 | 1042 | static void amdgpu_dm_audio_eld_notify(struct amdgpu_device *adev, int pin) |
6ce8f316 NK |
1043 | { |
1044 | struct drm_audio_component *acomp = adev->dm.audio_component; | |
1045 | ||
1046 | if (acomp && acomp->audio_ops && acomp->audio_ops->pin_eld_notify) { | |
1047 | DRM_DEBUG_KMS("Notify ELD: %d\n", pin); | |
1048 | ||
1049 | acomp->audio_ops->pin_eld_notify(acomp->audio_ops->audio_ptr, | |
1050 | pin, -1); | |
1051 | } | |
1052 | } | |
1053 | ||
743b9786 NK |
1054 | static int dm_dmub_hw_init(struct amdgpu_device *adev) |
1055 | { | |
743b9786 NK |
1056 | const struct dmcub_firmware_header_v1_0 *hdr; |
1057 | struct dmub_srv *dmub_srv = adev->dm.dmub_srv; | |
8c7aea40 | 1058 | struct dmub_srv_fb_info *fb_info = adev->dm.dmub_fb_info; |
743b9786 NK |
1059 | const struct firmware *dmub_fw = adev->dm.dmub_fw; |
1060 | struct dmcu *dmcu = adev->dm.dc->res_pool->dmcu; | |
1061 | struct abm *abm = adev->dm.dc->res_pool->abm; | |
743b9786 NK |
1062 | struct dmub_srv_hw_params hw_params; |
1063 | enum dmub_status status; | |
1064 | const unsigned char *fw_inst_const, *fw_bss_data; | |
ae67558b | 1065 | u32 i, fw_inst_const_size, fw_bss_data_size; |
743b9786 NK |
1066 | bool has_hw_support; |
1067 | ||
1068 | if (!dmub_srv) | |
1069 | /* DMUB isn't supported on the ASIC. */ | |
1070 | return 0; | |
1071 | ||
8c7aea40 NK |
1072 | if (!fb_info) { |
1073 | DRM_ERROR("No framebuffer info for DMUB service.\n"); | |
1074 | return -EINVAL; | |
1075 | } | |
1076 | ||
743b9786 NK |
1077 | if (!dmub_fw) { |
1078 | /* Firmware required for DMUB support. */ | |
1079 | DRM_ERROR("No firmware provided for DMUB.\n"); | |
1080 | return -EINVAL; | |
1081 | } | |
1082 | ||
1083 | status = dmub_srv_has_hw_support(dmub_srv, &has_hw_support); | |
1084 | if (status != DMUB_STATUS_OK) { | |
1085 | DRM_ERROR("Error checking HW support for DMUB: %d\n", status); | |
1086 | return -EINVAL; | |
1087 | } | |
1088 | ||
1089 | if (!has_hw_support) { | |
1090 | DRM_INFO("DMUB unsupported on ASIC\n"); | |
1091 | return 0; | |
1092 | } | |
1093 | ||
47e62dbd NK |
1094 | /* Reset DMCUB if it was previously running - before we overwrite its memory. */ |
1095 | status = dmub_srv_hw_reset(dmub_srv); | |
1096 | if (status != DMUB_STATUS_OK) | |
1097 | DRM_WARN("Error resetting DMUB HW: %d\n", status); | |
1098 | ||
743b9786 NK |
1099 | hdr = (const struct dmcub_firmware_header_v1_0 *)dmub_fw->data; |
1100 | ||
743b9786 NK |
1101 | fw_inst_const = dmub_fw->data + |
1102 | le32_to_cpu(hdr->header.ucode_array_offset_bytes) + | |
8c7aea40 | 1103 | PSP_HEADER_BYTES; |
743b9786 NK |
1104 | |
1105 | fw_bss_data = dmub_fw->data + | |
1106 | le32_to_cpu(hdr->header.ucode_array_offset_bytes) + | |
1107 | le32_to_cpu(hdr->inst_const_bytes); | |
1108 | ||
1109 | /* Copy firmware and bios info into FB memory. */ | |
8c7aea40 NK |
1110 | fw_inst_const_size = le32_to_cpu(hdr->inst_const_bytes) - |
1111 | PSP_HEADER_BYTES - PSP_FOOTER_BYTES; | |
1112 | ||
1113 | fw_bss_data_size = le32_to_cpu(hdr->bss_data_bytes); | |
1114 | ||
ddde28a5 HW |
1115 | /* if adev->firmware.load_type == AMDGPU_FW_LOAD_PSP, |
1116 | * amdgpu_ucode_init_single_fw will load dmub firmware | |
1117 | * fw_inst_const part to cw0; otherwise, the firmware back door load | |
1118 | * will be done by dm_dmub_hw_init | |
1119 | */ | |
1120 | if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) { | |
1121 | memcpy(fb_info->fb[DMUB_WINDOW_0_INST_CONST].cpu_addr, fw_inst_const, | |
1122 | fw_inst_const_size); | |
1123 | } | |
1124 | ||
a576b345 NK |
1125 | if (fw_bss_data_size) |
1126 | memcpy(fb_info->fb[DMUB_WINDOW_2_BSS_DATA].cpu_addr, | |
1127 | fw_bss_data, fw_bss_data_size); | |
ddde28a5 HW |
1128 | |
1129 | /* Copy firmware bios info into FB memory. */ | |
8c7aea40 NK |
1130 | memcpy(fb_info->fb[DMUB_WINDOW_3_VBIOS].cpu_addr, adev->bios, |
1131 | adev->bios_size); | |
1132 | ||
1133 | /* Reset regions that need to be reset. */ | |
1134 | memset(fb_info->fb[DMUB_WINDOW_4_MAILBOX].cpu_addr, 0, | |
1135 | fb_info->fb[DMUB_WINDOW_4_MAILBOX].size); | |
1136 | ||
1137 | memset(fb_info->fb[DMUB_WINDOW_5_TRACEBUFF].cpu_addr, 0, | |
1138 | fb_info->fb[DMUB_WINDOW_5_TRACEBUFF].size); | |
1139 | ||
1140 | memset(fb_info->fb[DMUB_WINDOW_6_FW_STATE].cpu_addr, 0, | |
1141 | fb_info->fb[DMUB_WINDOW_6_FW_STATE].size); | |
743b9786 NK |
1142 | |
1143 | /* Initialize hardware. */ | |
1144 | memset(&hw_params, 0, sizeof(hw_params)); | |
1145 | hw_params.fb_base = adev->gmc.fb_start; | |
949933b0 | 1146 | hw_params.fb_offset = adev->vm_manager.vram_base_offset; |
743b9786 | 1147 | |
31a7f4bb HW |
1148 | /* backdoor load firmware and trigger dmub running */ |
1149 | if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) | |
1150 | hw_params.load_inst_const = true; | |
1151 | ||
743b9786 NK |
1152 | if (dmcu) |
1153 | hw_params.psp_version = dmcu->psp_version; | |
1154 | ||
8c7aea40 NK |
1155 | for (i = 0; i < fb_info->num_fb; ++i) |
1156 | hw_params.fb[i] = &fb_info->fb[i]; | |
743b9786 | 1157 | |
3b36f50d | 1158 | switch (adev->ip_versions[DCE_HWIP][0]) { |
f6aa84b8 RL |
1159 | case IP_VERSION(3, 1, 3): |
1160 | case IP_VERSION(3, 1, 4): | |
3b36f50d | 1161 | hw_params.dpia_supported = true; |
7367540b | 1162 | hw_params.disable_dpia = adev->dm.dc->debug.dpia_debug.bits.disable_dpia; |
5b109397 JS |
1163 | break; |
1164 | default: | |
1165 | break; | |
1166 | } | |
1167 | ||
743b9786 NK |
1168 | status = dmub_srv_hw_init(dmub_srv, &hw_params); |
1169 | if (status != DMUB_STATUS_OK) { | |
1170 | DRM_ERROR("Error initializing DMUB HW: %d\n", status); | |
1171 | return -EINVAL; | |
1172 | } | |
1173 | ||
1174 | /* Wait for firmware load to finish. */ | |
1175 | status = dmub_srv_wait_for_auto_load(dmub_srv, 100000); | |
1176 | if (status != DMUB_STATUS_OK) | |
1177 | DRM_WARN("Wait for DMUB auto-load failed: %d\n", status); | |
1178 | ||
1179 | /* Init DMCU and ABM if available. */ | |
1180 | if (dmcu && abm) { | |
1181 | dmcu->funcs->dmcu_init(dmcu); | |
1182 | abm->dmcu_is_running = dmcu->funcs->is_dmcu_initialized(dmcu); | |
1183 | } | |
1184 | ||
051b7887 RL |
1185 | if (!adev->dm.dc->ctx->dmub_srv) |
1186 | adev->dm.dc->ctx->dmub_srv = dc_dmub_srv_create(adev->dm.dc, dmub_srv); | |
9a71c7d3 NK |
1187 | if (!adev->dm.dc->ctx->dmub_srv) { |
1188 | DRM_ERROR("Couldn't allocate DC DMUB server!\n"); | |
1189 | return -ENOMEM; | |
1190 | } | |
1191 | ||
743b9786 NK |
1192 | DRM_INFO("DMUB hardware initialized: version=0x%08X\n", |
1193 | adev->dm.dmcub_fw_version); | |
1194 | ||
1195 | return 0; | |
1196 | } | |
1197 | ||
79d6b935 NK |
1198 | static void dm_dmub_hw_resume(struct amdgpu_device *adev) |
1199 | { | |
1200 | struct dmub_srv *dmub_srv = adev->dm.dmub_srv; | |
1201 | enum dmub_status status; | |
1202 | bool init; | |
1203 | ||
1204 | if (!dmub_srv) { | |
1205 | /* DMUB isn't supported on the ASIC. */ | |
1206 | return; | |
1207 | } | |
1208 | ||
1209 | status = dmub_srv_is_hw_init(dmub_srv, &init); | |
1210 | if (status != DMUB_STATUS_OK) | |
1211 | DRM_WARN("DMUB hardware init check failed: %d\n", status); | |
1212 | ||
1213 | if (status == DMUB_STATUS_OK && init) { | |
1214 | /* Wait for firmware load to finish. */ | |
1215 | status = dmub_srv_wait_for_auto_load(dmub_srv, 100000); | |
1216 | if (status != DMUB_STATUS_OK) | |
1217 | DRM_WARN("Wait for DMUB auto-load failed: %d\n", status); | |
1218 | } else { | |
1219 | /* Perform the full hardware initialization. */ | |
1220 | dm_dmub_hw_init(adev); | |
1221 | } | |
1222 | } | |
1223 | ||
c0fb85ae | 1224 | static void mmhub_read_system_context(struct amdgpu_device *adev, struct dc_phy_addr_space_config *pa_config) |
c44a22b3 | 1225 | { |
ae67558b SS |
1226 | u64 pt_base; |
1227 | u32 logical_addr_low; | |
1228 | u32 logical_addr_high; | |
1229 | u32 agp_base, agp_bot, agp_top; | |
c0fb85ae | 1230 | PHYSICAL_ADDRESS_LOC page_table_start, page_table_end, page_table_base; |
c44a22b3 | 1231 | |
a0f884f5 NK |
1232 | memset(pa_config, 0, sizeof(*pa_config)); |
1233 | ||
c0fb85ae YZ |
1234 | agp_base = 0; |
1235 | agp_bot = adev->gmc.agp_start >> 24; | |
1236 | agp_top = adev->gmc.agp_end >> 24; | |
c44a22b3 | 1237 | |
0294868f AD |
1238 | /* AGP aperture is disabled */ |
1239 | if (agp_bot == agp_top) { | |
4d2c6e89 | 1240 | logical_addr_low = adev->gmc.fb_start >> 18; |
0294868f AD |
1241 | if (adev->apu_flags & AMD_APU_IS_RAVEN2) |
1242 | /* | |
1243 | * Raven2 has a HW issue that it is unable to use the vram which | |
1244 | * is out of MC_VM_SYSTEM_APERTURE_HIGH_ADDR. So here is the | |
1245 | * workaround that increase system aperture high address (add 1) | |
1246 | * to get rid of the VM fault and hardware hang. | |
1247 | */ | |
1248 | logical_addr_high = (adev->gmc.fb_end >> 18) + 0x1; | |
1249 | else | |
4d2c6e89 | 1250 | logical_addr_high = adev->gmc.fb_end >> 18; |
0294868f | 1251 | } else { |
4d2c6e89 | 1252 | logical_addr_low = min(adev->gmc.fb_start, adev->gmc.agp_start) >> 18; |
0294868f AD |
1253 | if (adev->apu_flags & AMD_APU_IS_RAVEN2) |
1254 | /* | |
1255 | * Raven2 has a HW issue that it is unable to use the vram which | |
1256 | * is out of MC_VM_SYSTEM_APERTURE_HIGH_ADDR. So here is the | |
1257 | * workaround that increase system aperture high address (add 1) | |
1258 | * to get rid of the VM fault and hardware hang. | |
1259 | */ | |
1260 | logical_addr_high = max((adev->gmc.fb_end >> 18) + 0x1, adev->gmc.agp_end >> 18); | |
1261 | else | |
1262 | logical_addr_high = max(adev->gmc.fb_end, adev->gmc.agp_end) >> 18; | |
1263 | } | |
1264 | ||
1265 | pt_base = amdgpu_gmc_pd_addr(adev->gart.bo); | |
c44a22b3 | 1266 | |
c0fb85ae YZ |
1267 | page_table_start.high_part = (u32)(adev->gmc.gart_start >> 44) & 0xF; |
1268 | page_table_start.low_part = (u32)(adev->gmc.gart_start >> 12); | |
1269 | page_table_end.high_part = (u32)(adev->gmc.gart_end >> 44) & 0xF; | |
1270 | page_table_end.low_part = (u32)(adev->gmc.gart_end >> 12); | |
1271 | page_table_base.high_part = upper_32_bits(pt_base) & 0xF; | |
1272 | page_table_base.low_part = lower_32_bits(pt_base); | |
c44a22b3 | 1273 | |
c0fb85ae YZ |
1274 | pa_config->system_aperture.start_addr = (uint64_t)logical_addr_low << 18; |
1275 | pa_config->system_aperture.end_addr = (uint64_t)logical_addr_high << 18; | |
1276 | ||
1277 | pa_config->system_aperture.agp_base = (uint64_t)agp_base << 24 ; | |
1278 | pa_config->system_aperture.agp_bot = (uint64_t)agp_bot << 24; | |
1279 | pa_config->system_aperture.agp_top = (uint64_t)agp_top << 24; | |
1280 | ||
1281 | pa_config->system_aperture.fb_base = adev->gmc.fb_start; | |
949933b0 | 1282 | pa_config->system_aperture.fb_offset = adev->vm_manager.vram_base_offset; |
c0fb85ae YZ |
1283 | pa_config->system_aperture.fb_top = adev->gmc.fb_end; |
1284 | ||
1285 | pa_config->gart_config.page_table_start_addr = page_table_start.quad_part << 12; | |
1286 | pa_config->gart_config.page_table_end_addr = page_table_end.quad_part << 12; | |
1287 | pa_config->gart_config.page_table_base_addr = page_table_base.quad_part; | |
1288 | ||
40e9f3f0 | 1289 | pa_config->is_hvm_enabled = adev->mode_info.gpu_vm_support; |
c44a22b3 | 1290 | |
c44a22b3 | 1291 | } |
cae5c1ab | 1292 | |
028c4ccf QZ |
1293 | static void force_connector_state( |
1294 | struct amdgpu_dm_connector *aconnector, | |
1295 | enum drm_connector_force force_state) | |
1296 | { | |
1297 | struct drm_connector *connector = &aconnector->base; | |
1298 | ||
1299 | mutex_lock(&connector->dev->mode_config.mutex); | |
1300 | aconnector->base.force = force_state; | |
1301 | mutex_unlock(&connector->dev->mode_config.mutex); | |
1302 | ||
1303 | mutex_lock(&aconnector->hpd_lock); | |
1304 | drm_kms_helper_connector_hotplug_event(connector); | |
1305 | mutex_unlock(&aconnector->hpd_lock); | |
1306 | } | |
1307 | ||
8e794421 WL |
1308 | static void dm_handle_hpd_rx_offload_work(struct work_struct *work) |
1309 | { | |
1310 | struct hpd_rx_irq_offload_work *offload_work; | |
1311 | struct amdgpu_dm_connector *aconnector; | |
1312 | struct dc_link *dc_link; | |
1313 | struct amdgpu_device *adev; | |
1314 | enum dc_connection_type new_connection_type = dc_connection_none; | |
1315 | unsigned long flags; | |
028c4ccf QZ |
1316 | union test_response test_response; |
1317 | ||
1318 | memset(&test_response, 0, sizeof(test_response)); | |
8e794421 WL |
1319 | |
1320 | offload_work = container_of(work, struct hpd_rx_irq_offload_work, work); | |
1321 | aconnector = offload_work->offload_wq->aconnector; | |
1322 | ||
1323 | if (!aconnector) { | |
1324 | DRM_ERROR("Can't retrieve aconnector in hpd_rx_irq_offload_work"); | |
1325 | goto skip; | |
1326 | } | |
1327 | ||
1328 | adev = drm_to_adev(aconnector->base.dev); | |
1329 | dc_link = aconnector->dc_link; | |
1330 | ||
1331 | mutex_lock(&aconnector->hpd_lock); | |
54618888 | 1332 | if (!dc_link_detect_connection_type(dc_link, &new_connection_type)) |
8e794421 WL |
1333 | DRM_ERROR("KMS: Failed to detect connector\n"); |
1334 | mutex_unlock(&aconnector->hpd_lock); | |
1335 | ||
1336 | if (new_connection_type == dc_connection_none) | |
1337 | goto skip; | |
1338 | ||
1339 | if (amdgpu_in_reset(adev)) | |
1340 | goto skip; | |
1341 | ||
1342 | mutex_lock(&adev->dm.dc_lock); | |
028c4ccf | 1343 | if (offload_work->data.bytes.device_service_irq.bits.AUTOMATED_TEST) { |
8e794421 | 1344 | dc_link_dp_handle_automated_test(dc_link); |
028c4ccf QZ |
1345 | |
1346 | if (aconnector->timing_changed) { | |
1347 | /* force connector disconnect and reconnect */ | |
1348 | force_connector_state(aconnector, DRM_FORCE_OFF); | |
1349 | msleep(100); | |
1350 | force_connector_state(aconnector, DRM_FORCE_UNSPECIFIED); | |
1351 | } | |
1352 | ||
1353 | test_response.bits.ACK = 1; | |
1354 | ||
1355 | core_link_write_dpcd( | |
1356 | dc_link, | |
1357 | DP_TEST_RESPONSE, | |
1358 | &test_response.raw, | |
1359 | sizeof(test_response)); | |
1360 | } | |
8e794421 | 1361 | else if ((dc_link->connector_signal != SIGNAL_TYPE_EDP) && |
c5a31f17 | 1362 | dc_link_check_link_loss_status(dc_link, &offload_work->data) && |
8e794421 | 1363 | dc_link_dp_allow_hpd_rx_irq(dc_link)) { |
e322843e HW |
1364 | /* offload_work->data is from handle_hpd_rx_irq-> |
1365 | * schedule_hpd_rx_offload_work.this is defer handle | |
1366 | * for hpd short pulse. upon here, link status may be | |
1367 | * changed, need get latest link status from dpcd | |
1368 | * registers. if link status is good, skip run link | |
1369 | * training again. | |
1370 | */ | |
1371 | union hpd_irq_data irq_data; | |
1372 | ||
1373 | memset(&irq_data, 0, sizeof(irq_data)); | |
1374 | ||
1375 | /* before dc_link_dp_handle_link_loss, allow new link lost handle | |
1376 | * request be added to work queue if link lost at end of dc_link_ | |
1377 | * dp_handle_link_loss | |
1378 | */ | |
8e794421 WL |
1379 | spin_lock_irqsave(&offload_work->offload_wq->offload_lock, flags); |
1380 | offload_work->offload_wq->is_handling_link_loss = false; | |
1381 | spin_unlock_irqrestore(&offload_work->offload_wq->offload_lock, flags); | |
e322843e | 1382 | |
54618888 | 1383 | if ((dc_link_dp_read_hpd_rx_irq_data(dc_link, &irq_data) == DC_OK) && |
e322843e HW |
1384 | dc_link_check_link_loss_status(dc_link, &irq_data)) |
1385 | dc_link_dp_handle_link_loss(dc_link); | |
8e794421 WL |
1386 | } |
1387 | mutex_unlock(&adev->dm.dc_lock); | |
1388 | ||
1389 | skip: | |
1390 | kfree(offload_work); | |
1391 | ||
1392 | } | |
1393 | ||
1394 | static struct hpd_rx_irq_offload_work_queue *hpd_rx_irq_create_workqueue(struct dc *dc) | |
1395 | { | |
1396 | int max_caps = dc->caps.max_links; | |
1397 | int i = 0; | |
1398 | struct hpd_rx_irq_offload_work_queue *hpd_rx_offload_wq = NULL; | |
1399 | ||
1400 | hpd_rx_offload_wq = kcalloc(max_caps, sizeof(*hpd_rx_offload_wq), GFP_KERNEL); | |
1401 | ||
1402 | if (!hpd_rx_offload_wq) | |
1403 | return NULL; | |
1404 | ||
1405 | ||
1406 | for (i = 0; i < max_caps; i++) { | |
1407 | hpd_rx_offload_wq[i].wq = | |
1408 | create_singlethread_workqueue("amdgpu_dm_hpd_rx_offload_wq"); | |
1409 | ||
1410 | if (hpd_rx_offload_wq[i].wq == NULL) { | |
1411 | DRM_ERROR("create amdgpu_dm_hpd_rx_offload_wq fail!"); | |
7136f956 | 1412 | goto out_err; |
8e794421 WL |
1413 | } |
1414 | ||
1415 | spin_lock_init(&hpd_rx_offload_wq[i].offload_lock); | |
1416 | } | |
1417 | ||
1418 | return hpd_rx_offload_wq; | |
7136f956 RM |
1419 | |
1420 | out_err: | |
1421 | for (i = 0; i < max_caps; i++) { | |
1422 | if (hpd_rx_offload_wq[i].wq) | |
1423 | destroy_workqueue(hpd_rx_offload_wq[i].wq); | |
1424 | } | |
1425 | kfree(hpd_rx_offload_wq); | |
1426 | return NULL; | |
8e794421 WL |
1427 | } |
1428 | ||
3ce51649 AD |
1429 | struct amdgpu_stutter_quirk { |
1430 | u16 chip_vendor; | |
1431 | u16 chip_device; | |
1432 | u16 subsys_vendor; | |
1433 | u16 subsys_device; | |
1434 | u8 revision; | |
1435 | }; | |
1436 | ||
1437 | static const struct amdgpu_stutter_quirk amdgpu_stutter_quirk_list[] = { | |
1438 | /* https://bugzilla.kernel.org/show_bug.cgi?id=214417 */ | |
1439 | { 0x1002, 0x15dd, 0x1002, 0x15dd, 0xc8 }, | |
1440 | { 0, 0, 0, 0, 0 }, | |
1441 | }; | |
1442 | ||
1443 | static bool dm_should_disable_stutter(struct pci_dev *pdev) | |
1444 | { | |
1445 | const struct amdgpu_stutter_quirk *p = amdgpu_stutter_quirk_list; | |
1446 | ||
1447 | while (p && p->chip_device != 0) { | |
1448 | if (pdev->vendor == p->chip_vendor && | |
1449 | pdev->device == p->chip_device && | |
1450 | pdev->subsystem_vendor == p->subsys_vendor && | |
1451 | pdev->subsystem_device == p->subsys_device && | |
1452 | pdev->revision == p->revision) { | |
1453 | return true; | |
1454 | } | |
1455 | ++p; | |
1456 | } | |
1457 | return false; | |
1458 | } | |
1459 | ||
57b9f338 FZ |
1460 | static const struct dmi_system_id hpd_disconnect_quirk_table[] = { |
1461 | { | |
1462 | .matches = { | |
1463 | DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."), | |
1464 | DMI_MATCH(DMI_PRODUCT_NAME, "Precision 3660"), | |
1465 | }, | |
1466 | }, | |
1467 | { | |
1468 | .matches = { | |
1469 | DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."), | |
1470 | DMI_MATCH(DMI_PRODUCT_NAME, "Precision 3260"), | |
1471 | }, | |
1472 | }, | |
1473 | { | |
1474 | .matches = { | |
1475 | DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."), | |
1476 | DMI_MATCH(DMI_PRODUCT_NAME, "Precision 3460"), | |
1477 | }, | |
1478 | }, | |
503dc81c TL |
1479 | { |
1480 | .matches = { | |
1481 | DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."), | |
1482 | DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex Tower Plus 7010"), | |
1483 | }, | |
1484 | }, | |
1485 | { | |
1486 | .matches = { | |
1487 | DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."), | |
1488 | DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex Tower 7010"), | |
1489 | }, | |
1490 | }, | |
1491 | { | |
1492 | .matches = { | |
1493 | DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."), | |
1494 | DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex SFF Plus 7010"), | |
1495 | }, | |
1496 | }, | |
1497 | { | |
1498 | .matches = { | |
1499 | DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."), | |
1500 | DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex SFF 7010"), | |
1501 | }, | |
1502 | }, | |
1503 | { | |
1504 | .matches = { | |
1505 | DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."), | |
1506 | DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex Micro Plus 7010"), | |
1507 | }, | |
1508 | }, | |
1509 | { | |
1510 | .matches = { | |
1511 | DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."), | |
1512 | DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex Micro 7010"), | |
1513 | }, | |
1514 | }, | |
57b9f338 | 1515 | {} |
503dc81c | 1516 | /* TODO: refactor this from a fixed table to a dynamic option */ |
57b9f338 FZ |
1517 | }; |
1518 | ||
1519 | static void retrieve_dmi_info(struct amdgpu_display_manager *dm) | |
1520 | { | |
1521 | const struct dmi_system_id *dmi_id; | |
1522 | ||
1523 | dm->aux_hpd_discon_quirk = false; | |
1524 | ||
1525 | dmi_id = dmi_first_match(hpd_disconnect_quirk_table); | |
1526 | if (dmi_id) { | |
1527 | dm->aux_hpd_discon_quirk = true; | |
1528 | DRM_INFO("aux_hpd_discon_quirk attached\n"); | |
1529 | } | |
1530 | } | |
1531 | ||
7578ecda | 1532 | static int amdgpu_dm_init(struct amdgpu_device *adev) |
4562236b HW |
1533 | { |
1534 | struct dc_init_data init_data; | |
52704fca | 1535 | struct dc_callback_init init_params; |
743b9786 | 1536 | int r; |
52704fca | 1537 | |
4a580877 | 1538 | adev->dm.ddev = adev_to_drm(adev); |
4562236b HW |
1539 | adev->dm.adev = adev; |
1540 | ||
4562236b HW |
1541 | /* Zero all the fields */ |
1542 | memset(&init_data, 0, sizeof(init_data)); | |
52704fca | 1543 | memset(&init_params, 0, sizeof(init_params)); |
4562236b | 1544 | |
ead08b95 | 1545 | mutex_init(&adev->dm.dpia_aux_lock); |
674e78ac | 1546 | mutex_init(&adev->dm.dc_lock); |
6ce8f316 | 1547 | mutex_init(&adev->dm.audio_lock); |
674e78ac | 1548 | |
4562236b HW |
1549 | if(amdgpu_dm_irq_init(adev)) { |
1550 | DRM_ERROR("amdgpu: failed to initialize DM IRQ support.\n"); | |
1551 | goto error; | |
1552 | } | |
1553 | ||
1554 | init_data.asic_id.chip_family = adev->family; | |
1555 | ||
2dc31ca1 | 1556 | init_data.asic_id.pci_revision_id = adev->pdev->revision; |
4562236b | 1557 | init_data.asic_id.hw_internal_rev = adev->external_rev_id; |
dae66a04 | 1558 | init_data.asic_id.chip_id = adev->pdev->device; |
4562236b | 1559 | |
770d13b1 | 1560 | init_data.asic_id.vram_width = adev->gmc.vram_width; |
4562236b HW |
1561 | /* TODO: initialize init_data.asic_id.vram_type here!!!! */ |
1562 | init_data.asic_id.atombios_base_address = | |
1563 | adev->mode_info.atom_context->bios; | |
1564 | ||
1565 | init_data.driver = adev; | |
1566 | ||
1567 | adev->dm.cgs_device = amdgpu_cgs_create_device(adev); | |
1568 | ||
1569 | if (!adev->dm.cgs_device) { | |
1570 | DRM_ERROR("amdgpu: failed to create cgs device.\n"); | |
1571 | goto error; | |
1572 | } | |
1573 | ||
1574 | init_data.cgs_device = adev->dm.cgs_device; | |
1575 | ||
4562236b HW |
1576 | init_data.dce_environment = DCE_ENV_PRODUCTION_DRV; |
1577 | ||
fd546bc5 AD |
1578 | switch (adev->ip_versions[DCE_HWIP][0]) { |
1579 | case IP_VERSION(2, 1, 0): | |
1580 | switch (adev->dm.dmcub_fw_version) { | |
1581 | case 0: /* development */ | |
1582 | case 0x1: /* linux-firmware.git hash 6d9f399 */ | |
1583 | case 0x01000000: /* linux-firmware.git hash 9a0b0f4 */ | |
1584 | init_data.flags.disable_dmcu = false; | |
1585 | break; | |
1586 | default: | |
1587 | init_data.flags.disable_dmcu = true; | |
1588 | } | |
1589 | break; | |
1590 | case IP_VERSION(2, 0, 3): | |
1591 | init_data.flags.disable_dmcu = true; | |
1592 | break; | |
1593 | default: | |
1594 | break; | |
1595 | } | |
1596 | ||
60fb100b AD |
1597 | switch (adev->asic_type) { |
1598 | case CHIP_CARRIZO: | |
1599 | case CHIP_STONEY: | |
1ebcaebd NK |
1600 | init_data.flags.gpu_vm_support = true; |
1601 | break; | |
60fb100b | 1602 | default: |
1d789535 | 1603 | switch (adev->ip_versions[DCE_HWIP][0]) { |
559f591d AD |
1604 | case IP_VERSION(1, 0, 0): |
1605 | case IP_VERSION(1, 0, 1): | |
a7f520bf AD |
1606 | /* enable S/G on PCO and RV2 */ |
1607 | if ((adev->apu_flags & AMD_APU_IS_RAVEN2) || | |
1608 | (adev->apu_flags & AMD_APU_IS_PICASSO)) | |
1609 | init_data.flags.gpu_vm_support = true; | |
1610 | break; | |
c4029779 | 1611 | case IP_VERSION(2, 1, 0): |
c08182f2 | 1612 | case IP_VERSION(3, 0, 1): |
8f56a0fe AD |
1613 | case IP_VERSION(3, 1, 2): |
1614 | case IP_VERSION(3, 1, 3): | |
69ed0c5d | 1615 | case IP_VERSION(3, 1, 4): |
512e8475 | 1616 | case IP_VERSION(3, 1, 5): |
0fe382fb | 1617 | case IP_VERSION(3, 1, 6): |
c08182f2 AD |
1618 | init_data.flags.gpu_vm_support = true; |
1619 | break; | |
c08182f2 AD |
1620 | default: |
1621 | break; | |
1622 | } | |
60fb100b AD |
1623 | break; |
1624 | } | |
bf0207e1 AD |
1625 | if (init_data.flags.gpu_vm_support && |
1626 | (amdgpu_sg_display == 0)) | |
1627 | init_data.flags.gpu_vm_support = false; | |
6e227308 | 1628 | |
a7f520bf AD |
1629 | if (init_data.flags.gpu_vm_support) |
1630 | adev->mode_info.gpu_vm_support = true; | |
1631 | ||
04b94af4 AD |
1632 | if (amdgpu_dc_feature_mask & DC_FBC_MASK) |
1633 | init_data.flags.fbc_support = true; | |
1634 | ||
d99f38ae AD |
1635 | if (amdgpu_dc_feature_mask & DC_MULTI_MON_PP_MCLK_SWITCH_MASK) |
1636 | init_data.flags.multi_mon_pp_mclk_switch = true; | |
1637 | ||
eaf56410 LL |
1638 | if (amdgpu_dc_feature_mask & DC_DISABLE_FRACTIONAL_PWM_MASK) |
1639 | init_data.flags.disable_fractional_pwm = true; | |
a5148245 ZL |
1640 | |
1641 | if (amdgpu_dc_feature_mask & DC_EDP_NO_POWER_SEQUENCING) | |
1642 | init_data.flags.edp_no_power_sequencing = true; | |
eaf56410 | 1643 | |
12320274 AP |
1644 | if (amdgpu_dc_feature_mask & DC_DISABLE_LTTPR_DP1_4A) |
1645 | init_data.flags.allow_lttpr_non_transparent_mode.bits.DP1_4A = true; | |
1646 | if (amdgpu_dc_feature_mask & DC_DISABLE_LTTPR_DP2_0) | |
1647 | init_data.flags.allow_lttpr_non_transparent_mode.bits.DP2_0 = true; | |
12320274 | 1648 | |
80c6d680 AP |
1649 | /* Disable SubVP + DRR config by default */ |
1650 | init_data.flags.disable_subvp_drr = true; | |
1651 | if (amdgpu_dc_feature_mask & DC_ENABLE_SUBVP_DRR) | |
1652 | init_data.flags.disable_subvp_drr = false; | |
1653 | ||
7aba117a | 1654 | init_data.flags.seamless_boot_edp_requested = false; |
78ad75f8 | 1655 | |
1edf5ae1 | 1656 | if (check_seamless_boot_capability(adev)) { |
7aba117a | 1657 | init_data.flags.seamless_boot_edp_requested = true; |
1edf5ae1 ZL |
1658 | init_data.flags.allow_seamless_boot_optimization = true; |
1659 | DRM_INFO("Seamless boot condition check passed\n"); | |
1660 | } | |
1661 | ||
a8201902 LM |
1662 | init_data.flags.enable_mipi_converter_optimization = true; |
1663 | ||
e5028e9f | 1664 | init_data.dcn_reg_offsets = adev->reg_offset[DCE_HWIP][0]; |
2a93292f | 1665 | init_data.nbio_reg_offsets = adev->reg_offset[NBIO_HWIP][0]; |
e5028e9f | 1666 | |
0dd79532 | 1667 | INIT_LIST_HEAD(&adev->dm.da_list); |
57b9f338 FZ |
1668 | |
1669 | retrieve_dmi_info(&adev->dm); | |
1670 | ||
4562236b HW |
1671 | /* Display Core create. */ |
1672 | adev->dm.dc = dc_create(&init_data); | |
1673 | ||
423788c7 | 1674 | if (adev->dm.dc) { |
76121231 | 1675 | DRM_INFO("Display Core initialized with v%s!\n", DC_VER); |
423788c7 | 1676 | } else { |
76121231 | 1677 | DRM_INFO("Display Core failed to initialize with v%s!\n", DC_VER); |
423788c7 ES |
1678 | goto error; |
1679 | } | |
4562236b | 1680 | |
8a791dab HW |
1681 | if (amdgpu_dc_debug_mask & DC_DISABLE_PIPE_SPLIT) { |
1682 | adev->dm.dc->debug.force_single_disp_pipe_split = false; | |
1683 | adev->dm.dc->debug.pipe_split_policy = MPC_SPLIT_AVOID; | |
1684 | } | |
1685 | ||
f99d8762 HW |
1686 | if (adev->asic_type != CHIP_CARRIZO && adev->asic_type != CHIP_STONEY) |
1687 | adev->dm.dc->debug.disable_stutter = amdgpu_pp_feature_mask & PP_STUTTER_MODE ? false : true; | |
3ce51649 AD |
1688 | if (dm_should_disable_stutter(adev->pdev)) |
1689 | adev->dm.dc->debug.disable_stutter = true; | |
f99d8762 | 1690 | |
8a791dab HW |
1691 | if (amdgpu_dc_debug_mask & DC_DISABLE_STUTTER) |
1692 | adev->dm.dc->debug.disable_stutter = true; | |
1693 | ||
2665f63a | 1694 | if (amdgpu_dc_debug_mask & DC_DISABLE_DSC) { |
8a791dab | 1695 | adev->dm.dc->debug.disable_dsc = true; |
2665f63a | 1696 | } |
8a791dab HW |
1697 | |
1698 | if (amdgpu_dc_debug_mask & DC_DISABLE_CLOCK_GATING) | |
1699 | adev->dm.dc->debug.disable_clock_gate = true; | |
1700 | ||
cfb979f7 AP |
1701 | if (amdgpu_dc_debug_mask & DC_FORCE_SUBVP_MCLK_SWITCH) |
1702 | adev->dm.dc->debug.force_subvp_mclk_switch = true; | |
1703 | ||
792a0cdd LL |
1704 | adev->dm.dc->debug.visual_confirm = amdgpu_dc_visual_confirm; |
1705 | ||
d1bc26cb FZ |
1706 | /* TODO: Remove after DP2 receiver gets proper support of Cable ID feature */ |
1707 | adev->dm.dc->debug.ignore_cable_id = true; | |
1708 | ||
3d8fcc67 WL |
1709 | /* TODO: There is a new drm mst change where the freedom of |
1710 | * vc_next_start_slot update is revoked/moved into drm, instead of in | |
1711 | * driver. This forces us to make sure to get vc_next_start_slot updated | |
1712 | * in drm function each time without considering if mst_state is active | |
1713 | * or not. Otherwise, next time hotplug will give wrong start_slot | |
1714 | * number. We are implementing a temporary solution to even notify drm | |
1715 | * mst deallocation when link is no longer of MST type when uncommitting | |
1716 | * the stream so we will have more time to work on a proper solution. | |
1717 | * Ideally when dm_helpers_dp_mst_stop_top_mgr message is triggered, we | |
1718 | * should notify drm to do a complete "reset" of its states and stop | |
1719 | * calling further drm mst functions when link is no longer of an MST | |
1720 | * type. This could happen when we unplug an MST hubs/displays. When | |
1721 | * uncommit stream comes later after unplug, we should just reset | |
1722 | * hardware states only. | |
1723 | */ | |
1724 | adev->dm.dc->debug.temp_mst_deallocation_sequence = true; | |
1725 | ||
e3834491 FZ |
1726 | if (adev->dm.dc->caps.dp_hdmi21_pcon_support) |
1727 | DRM_INFO("DP-HDMI FRL PCON supported\n"); | |
1728 | ||
743b9786 NK |
1729 | r = dm_dmub_hw_init(adev); |
1730 | if (r) { | |
1731 | DRM_ERROR("DMUB interface failed to initialize: status=%d\n", r); | |
1732 | goto error; | |
1733 | } | |
1734 | ||
bb6785c1 NK |
1735 | dc_hardware_init(adev->dm.dc); |
1736 | ||
8e794421 WL |
1737 | adev->dm.hpd_rx_offload_wq = hpd_rx_irq_create_workqueue(adev->dm.dc); |
1738 | if (!adev->dm.hpd_rx_offload_wq) { | |
1739 | DRM_ERROR("amdgpu: failed to create hpd rx offload workqueue.\n"); | |
1740 | goto error; | |
1741 | } | |
1742 | ||
3ca001af | 1743 | if ((adev->flags & AMD_IS_APU) && (adev->asic_type >= CHIP_CARRIZO)) { |
e6cd859d AD |
1744 | struct dc_phy_addr_space_config pa_config; |
1745 | ||
0b08c54b | 1746 | mmhub_read_system_context(adev, &pa_config); |
c0fb85ae | 1747 | |
0b08c54b YZ |
1748 | // Call the DC init_memory func |
1749 | dc_setup_system_context(adev->dm.dc, &pa_config); | |
1750 | } | |
c0fb85ae | 1751 | |
4562236b HW |
1752 | adev->dm.freesync_module = mod_freesync_create(adev->dm.dc); |
1753 | if (!adev->dm.freesync_module) { | |
1754 | DRM_ERROR( | |
1755 | "amdgpu: failed to initialize freesync_module.\n"); | |
1756 | } else | |
f1ad2f5e | 1757 | DRM_DEBUG_DRIVER("amdgpu: freesync_module init done %p.\n", |
4562236b HW |
1758 | adev->dm.freesync_module); |
1759 | ||
e277adc5 LSL |
1760 | amdgpu_dm_init_color_mod(); |
1761 | ||
ea3b4242 | 1762 | if (adev->dm.dc->caps.max_links > 0) { |
09a5df6c NK |
1763 | adev->dm.vblank_control_workqueue = |
1764 | create_singlethread_workqueue("dm_vblank_control_workqueue"); | |
1765 | if (!adev->dm.vblank_control_workqueue) | |
ea3b4242 | 1766 | DRM_ERROR("amdgpu: failed to initialize vblank_workqueue.\n"); |
ea3b4242 | 1767 | } |
ea3b4242 | 1768 | |
c08182f2 | 1769 | if (adev->dm.dc->caps.max_links > 0 && adev->family >= AMDGPU_FAMILY_RV) { |
e50dc171 | 1770 | adev->dm.hdcp_workqueue = hdcp_create_workqueue(adev, &init_params.cp_psp, adev->dm.dc); |
52704fca | 1771 | |
96a3b32e BL |
1772 | if (!adev->dm.hdcp_workqueue) |
1773 | DRM_ERROR("amdgpu: failed to initialize hdcp_workqueue.\n"); | |
1774 | else | |
1775 | DRM_DEBUG_DRIVER("amdgpu: hdcp_workqueue init done %p.\n", adev->dm.hdcp_workqueue); | |
52704fca | 1776 | |
96a3b32e BL |
1777 | dc_init_callbacks(adev->dm.dc, &init_params); |
1778 | } | |
9a65df19 | 1779 | #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY) |
b8ff7e08 | 1780 | adev->dm.secure_display_ctxs = amdgpu_dm_crtc_secure_display_create_contexts(adev); |
cbd8f20b AL |
1781 | if (!adev->dm.secure_display_ctxs) { |
1782 | DRM_ERROR("amdgpu: failed to initialize secure_display_ctxs.\n"); | |
1783 | } | |
52704fca | 1784 | #endif |
11d526f1 | 1785 | if (dc_is_dmub_outbox_supported(adev->dm.dc)) { |
81927e28 JS |
1786 | init_completion(&adev->dm.dmub_aux_transfer_done); |
1787 | adev->dm.dmub_notify = kzalloc(sizeof(struct dmub_notification), GFP_KERNEL); | |
1788 | if (!adev->dm.dmub_notify) { | |
1789 | DRM_INFO("amdgpu: fail to allocate adev->dm.dmub_notify"); | |
1790 | goto error; | |
1791 | } | |
e27c41d5 JS |
1792 | |
1793 | adev->dm.delayed_hpd_wq = create_singlethread_workqueue("amdgpu_dm_hpd_wq"); | |
1794 | if (!adev->dm.delayed_hpd_wq) { | |
1795 | DRM_ERROR("amdgpu: failed to create hpd offload workqueue.\n"); | |
1796 | goto error; | |
1797 | } | |
1798 | ||
81927e28 | 1799 | amdgpu_dm_outbox_init(adev); |
e27c41d5 JS |
1800 | if (!register_dmub_notify_callback(adev, DMUB_NOTIFICATION_AUX_REPLY, |
1801 | dmub_aux_setconfig_callback, false)) { | |
1802 | DRM_ERROR("amdgpu: fail to register dmub aux callback"); | |
1803 | goto error; | |
1804 | } | |
1805 | if (!register_dmub_notify_callback(adev, DMUB_NOTIFICATION_HPD, dmub_hpd_callback, true)) { | |
1806 | DRM_ERROR("amdgpu: fail to register dmub hpd callback"); | |
1807 | goto error; | |
1808 | } | |
c40a09e5 NK |
1809 | if (!register_dmub_notify_callback(adev, DMUB_NOTIFICATION_HPD_IRQ, dmub_hpd_callback, true)) { |
1810 | DRM_ERROR("amdgpu: fail to register dmub hpd callback"); | |
1811 | goto error; | |
1812 | } | |
81927e28 JS |
1813 | } |
1814 | ||
11d526f1 SW |
1815 | /* Enable outbox notification only after IRQ handlers are registered and DMUB is alive. |
1816 | * It is expected that DMUB will resend any pending notifications at this point, for | |
1817 | * example HPD from DPIA. | |
1818 | */ | |
1819 | if (dc_is_dmub_outbox_supported(adev->dm.dc)) | |
1820 | dc_enable_dmub_outbox(adev->dm.dc); | |
1821 | ||
1c43a48b SW |
1822 | if (amdgpu_dm_initialize_drm_device(adev)) { |
1823 | DRM_ERROR( | |
1824 | "amdgpu: failed to initialize sw for display support.\n"); | |
1825 | goto error; | |
1826 | } | |
1827 | ||
f74367e4 AD |
1828 | /* create fake encoders for MST */ |
1829 | dm_dp_create_fake_mst_encoders(adev); | |
1830 | ||
4562236b HW |
1831 | /* TODO: Add_display_info? */ |
1832 | ||
1833 | /* TODO use dynamic cursor width */ | |
4a580877 LT |
1834 | adev_to_drm(adev)->mode_config.cursor_width = adev->dm.dc->caps.max_cursor_size; |
1835 | adev_to_drm(adev)->mode_config.cursor_height = adev->dm.dc->caps.max_cursor_size; | |
4562236b | 1836 | |
4a580877 | 1837 | if (drm_vblank_init(adev_to_drm(adev), adev->dm.display_indexes_num)) { |
4562236b HW |
1838 | DRM_ERROR( |
1839 | "amdgpu: failed to initialize sw for display support.\n"); | |
1840 | goto error; | |
1841 | } | |
1842 | ||
c0fb85ae | 1843 | |
f1ad2f5e | 1844 | DRM_DEBUG_DRIVER("KMS initialized.\n"); |
4562236b HW |
1845 | |
1846 | return 0; | |
1847 | error: | |
1848 | amdgpu_dm_fini(adev); | |
1849 | ||
59d0f396 | 1850 | return -EINVAL; |
4562236b HW |
1851 | } |
1852 | ||
e9669fb7 AG |
1853 | static int amdgpu_dm_early_fini(void *handle) |
1854 | { | |
1855 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; | |
1856 | ||
1857 | amdgpu_dm_audio_fini(adev); | |
1858 | ||
1859 | return 0; | |
1860 | } | |
1861 | ||
7578ecda | 1862 | static void amdgpu_dm_fini(struct amdgpu_device *adev) |
4562236b | 1863 | { |
f74367e4 AD |
1864 | int i; |
1865 | ||
09a5df6c NK |
1866 | if (adev->dm.vblank_control_workqueue) { |
1867 | destroy_workqueue(adev->dm.vblank_control_workqueue); | |
1868 | adev->dm.vblank_control_workqueue = NULL; | |
1869 | } | |
09a5df6c | 1870 | |
4562236b | 1871 | amdgpu_dm_destroy_drm_device(&adev->dm); |
c8bdf2b6 | 1872 | |
9a65df19 | 1873 | #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY) |
1b11ff76 | 1874 | if (adev->dm.secure_display_ctxs) { |
c3d74960 | 1875 | for (i = 0; i < adev->mode_info.num_crtc; i++) { |
1b11ff76 AL |
1876 | if (adev->dm.secure_display_ctxs[i].crtc) { |
1877 | flush_work(&adev->dm.secure_display_ctxs[i].notify_ta_work); | |
1878 | flush_work(&adev->dm.secure_display_ctxs[i].forward_roi_work); | |
1879 | } | |
1880 | } | |
1881 | kfree(adev->dm.secure_display_ctxs); | |
1882 | adev->dm.secure_display_ctxs = NULL; | |
9a65df19 WL |
1883 | } |
1884 | #endif | |
52704fca | 1885 | if (adev->dm.hdcp_workqueue) { |
e96b1b29 | 1886 | hdcp_destroy(&adev->dev->kobj, adev->dm.hdcp_workqueue); |
52704fca BL |
1887 | adev->dm.hdcp_workqueue = NULL; |
1888 | } | |
1889 | ||
1890 | if (adev->dm.dc) | |
1891 | dc_deinit_callbacks(adev->dm.dc); | |
51ba6912 | 1892 | |
52f1783f IA |
1893 | if (adev->dm.dc) |
1894 | dc_dmub_srv_destroy(&adev->dm.dc->ctx->dmub_srv); | |
9a71c7d3 | 1895 | |
81927e28 JS |
1896 | if (dc_enable_dmub_notifications(adev->dm.dc)) { |
1897 | kfree(adev->dm.dmub_notify); | |
1898 | adev->dm.dmub_notify = NULL; | |
e27c41d5 JS |
1899 | destroy_workqueue(adev->dm.delayed_hpd_wq); |
1900 | adev->dm.delayed_hpd_wq = NULL; | |
81927e28 JS |
1901 | } |
1902 | ||
743b9786 NK |
1903 | if (adev->dm.dmub_bo) |
1904 | amdgpu_bo_free_kernel(&adev->dm.dmub_bo, | |
1905 | &adev->dm.dmub_bo_gpu_addr, | |
1906 | &adev->dm.dmub_bo_cpu_addr); | |
52704fca | 1907 | |
006c26a0 AG |
1908 | if (adev->dm.hpd_rx_offload_wq) { |
1909 | for (i = 0; i < adev->dm.dc->caps.max_links; i++) { | |
1910 | if (adev->dm.hpd_rx_offload_wq[i].wq) { | |
1911 | destroy_workqueue(adev->dm.hpd_rx_offload_wq[i].wq); | |
1912 | adev->dm.hpd_rx_offload_wq[i].wq = NULL; | |
1913 | } | |
1914 | } | |
1915 | ||
1916 | kfree(adev->dm.hpd_rx_offload_wq); | |
1917 | adev->dm.hpd_rx_offload_wq = NULL; | |
1918 | } | |
1919 | ||
c8bdf2b6 ED |
1920 | /* DC Destroy TODO: Replace destroy DAL */ |
1921 | if (adev->dm.dc) | |
1922 | dc_destroy(&adev->dm.dc); | |
4562236b HW |
1923 | /* |
1924 | * TODO: pageflip, vlank interrupt | |
1925 | * | |
1926 | * amdgpu_dm_irq_fini(adev); | |
1927 | */ | |
1928 | ||
1929 | if (adev->dm.cgs_device) { | |
1930 | amdgpu_cgs_destroy_device(adev->dm.cgs_device); | |
1931 | adev->dm.cgs_device = NULL; | |
1932 | } | |
1933 | if (adev->dm.freesync_module) { | |
1934 | mod_freesync_destroy(adev->dm.freesync_module); | |
1935 | adev->dm.freesync_module = NULL; | |
1936 | } | |
674e78ac | 1937 | |
6ce8f316 | 1938 | mutex_destroy(&adev->dm.audio_lock); |
674e78ac | 1939 | mutex_destroy(&adev->dm.dc_lock); |
ead08b95 | 1940 | mutex_destroy(&adev->dm.dpia_aux_lock); |
674e78ac | 1941 | |
4562236b HW |
1942 | return; |
1943 | } | |
1944 | ||
a94d5569 | 1945 | static int load_dmcu_fw(struct amdgpu_device *adev) |
4562236b | 1946 | { |
a7669aff | 1947 | const char *fw_name_dmcu = NULL; |
a94d5569 DF |
1948 | int r; |
1949 | const struct dmcu_firmware_header_v1_0 *hdr; | |
1950 | ||
1951 | switch(adev->asic_type) { | |
55e56389 MR |
1952 | #if defined(CONFIG_DRM_AMD_DC_SI) |
1953 | case CHIP_TAHITI: | |
1954 | case CHIP_PITCAIRN: | |
1955 | case CHIP_VERDE: | |
1956 | case CHIP_OLAND: | |
1957 | #endif | |
a94d5569 DF |
1958 | case CHIP_BONAIRE: |
1959 | case CHIP_HAWAII: | |
1960 | case CHIP_KAVERI: | |
1961 | case CHIP_KABINI: | |
1962 | case CHIP_MULLINS: | |
1963 | case CHIP_TONGA: | |
1964 | case CHIP_FIJI: | |
1965 | case CHIP_CARRIZO: | |
1966 | case CHIP_STONEY: | |
1967 | case CHIP_POLARIS11: | |
1968 | case CHIP_POLARIS10: | |
1969 | case CHIP_POLARIS12: | |
1970 | case CHIP_VEGAM: | |
1971 | case CHIP_VEGA10: | |
1972 | case CHIP_VEGA12: | |
1973 | case CHIP_VEGA20: | |
1974 | return 0; | |
5ea23931 RL |
1975 | case CHIP_NAVI12: |
1976 | fw_name_dmcu = FIRMWARE_NAVI12_DMCU; | |
1977 | break; | |
a94d5569 | 1978 | case CHIP_RAVEN: |
a7669aff HW |
1979 | if (ASICREV_IS_PICASSO(adev->external_rev_id)) |
1980 | fw_name_dmcu = FIRMWARE_RAVEN_DMCU; | |
1981 | else if (ASICREV_IS_RAVEN2(adev->external_rev_id)) | |
1982 | fw_name_dmcu = FIRMWARE_RAVEN_DMCU; | |
1983 | else | |
a7669aff | 1984 | return 0; |
a94d5569 DF |
1985 | break; |
1986 | default: | |
1d789535 | 1987 | switch (adev->ip_versions[DCE_HWIP][0]) { |
c08182f2 AD |
1988 | case IP_VERSION(2, 0, 2): |
1989 | case IP_VERSION(2, 0, 3): | |
1990 | case IP_VERSION(2, 0, 0): | |
1991 | case IP_VERSION(2, 1, 0): | |
1992 | case IP_VERSION(3, 0, 0): | |
1993 | case IP_VERSION(3, 0, 2): | |
1994 | case IP_VERSION(3, 0, 3): | |
1995 | case IP_VERSION(3, 0, 1): | |
1996 | case IP_VERSION(3, 1, 2): | |
1997 | case IP_VERSION(3, 1, 3): | |
f3cd57e4 | 1998 | case IP_VERSION(3, 1, 4): |
b5b8ed44 | 1999 | case IP_VERSION(3, 1, 5): |
de7cc1b4 | 2000 | case IP_VERSION(3, 1, 6): |
577359ca AP |
2001 | case IP_VERSION(3, 2, 0): |
2002 | case IP_VERSION(3, 2, 1): | |
c08182f2 AD |
2003 | return 0; |
2004 | default: | |
2005 | break; | |
2006 | } | |
a94d5569 | 2007 | DRM_ERROR("Unsupported ASIC type: 0x%X\n", adev->asic_type); |
59d0f396 | 2008 | return -EINVAL; |
a94d5569 DF |
2009 | } |
2010 | ||
2011 | if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) { | |
2012 | DRM_DEBUG_KMS("dm: DMCU firmware not supported on direct or SMU loading\n"); | |
2013 | return 0; | |
2014 | } | |
2015 | ||
46fa9075 ML |
2016 | r = amdgpu_ucode_request(adev, &adev->dm.fw_dmcu, fw_name_dmcu); |
2017 | if (r == -ENODEV) { | |
a94d5569 DF |
2018 | /* DMCU firmware is not necessary, so don't raise a fuss if it's missing */ |
2019 | DRM_DEBUG_KMS("dm: DMCU firmware not found\n"); | |
2020 | adev->dm.fw_dmcu = NULL; | |
2021 | return 0; | |
2022 | } | |
a94d5569 DF |
2023 | if (r) { |
2024 | dev_err(adev->dev, "amdgpu_dm: Can't validate firmware \"%s\"\n", | |
2025 | fw_name_dmcu); | |
51526637 | 2026 | amdgpu_ucode_release(&adev->dm.fw_dmcu); |
a94d5569 DF |
2027 | return r; |
2028 | } | |
2029 | ||
2030 | hdr = (const struct dmcu_firmware_header_v1_0 *)adev->dm.fw_dmcu->data; | |
2031 | adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_ERAM].ucode_id = AMDGPU_UCODE_ID_DMCU_ERAM; | |
2032 | adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_ERAM].fw = adev->dm.fw_dmcu; | |
2033 | adev->firmware.fw_size += | |
2034 | ALIGN(le32_to_cpu(hdr->header.ucode_size_bytes) - le32_to_cpu(hdr->intv_size_bytes), PAGE_SIZE); | |
2035 | ||
2036 | adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_INTV].ucode_id = AMDGPU_UCODE_ID_DMCU_INTV; | |
2037 | adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_INTV].fw = adev->dm.fw_dmcu; | |
2038 | adev->firmware.fw_size += | |
2039 | ALIGN(le32_to_cpu(hdr->intv_size_bytes), PAGE_SIZE); | |
2040 | ||
ee6e89c0 DF |
2041 | adev->dm.dmcu_fw_version = le32_to_cpu(hdr->header.ucode_version); |
2042 | ||
a94d5569 DF |
2043 | DRM_DEBUG_KMS("PSP loading DMCU firmware\n"); |
2044 | ||
4562236b HW |
2045 | return 0; |
2046 | } | |
2047 | ||
743b9786 NK |
2048 | static uint32_t amdgpu_dm_dmub_reg_read(void *ctx, uint32_t address) |
2049 | { | |
2050 | struct amdgpu_device *adev = ctx; | |
2051 | ||
2052 | return dm_read_reg(adev->dm.dc->ctx, address); | |
2053 | } | |
2054 | ||
2055 | static void amdgpu_dm_dmub_reg_write(void *ctx, uint32_t address, | |
2056 | uint32_t value) | |
2057 | { | |
2058 | struct amdgpu_device *adev = ctx; | |
2059 | ||
2060 | return dm_write_reg(adev->dm.dc->ctx, address, value); | |
2061 | } | |
2062 | ||
2063 | static int dm_dmub_sw_init(struct amdgpu_device *adev) | |
2064 | { | |
2065 | struct dmub_srv_create_params create_params; | |
8c7aea40 NK |
2066 | struct dmub_srv_region_params region_params; |
2067 | struct dmub_srv_region_info region_info; | |
2068 | struct dmub_srv_fb_params fb_params; | |
2069 | struct dmub_srv_fb_info *fb_info; | |
2070 | struct dmub_srv *dmub_srv; | |
743b9786 | 2071 | const struct dmcub_firmware_header_v1_0 *hdr; |
743b9786 NK |
2072 | enum dmub_asic dmub_asic; |
2073 | enum dmub_status status; | |
2074 | int r; | |
2075 | ||
1d789535 | 2076 | switch (adev->ip_versions[DCE_HWIP][0]) { |
c08182f2 | 2077 | case IP_VERSION(2, 1, 0): |
743b9786 | 2078 | dmub_asic = DMUB_ASIC_DCN21; |
743b9786 | 2079 | break; |
c08182f2 | 2080 | case IP_VERSION(3, 0, 0): |
35a45d63 | 2081 | dmub_asic = DMUB_ASIC_DCN30; |
79037324 | 2082 | break; |
c08182f2 | 2083 | case IP_VERSION(3, 0, 1): |
469989ca | 2084 | dmub_asic = DMUB_ASIC_DCN301; |
469989ca | 2085 | break; |
c08182f2 | 2086 | case IP_VERSION(3, 0, 2): |
2a411205 | 2087 | dmub_asic = DMUB_ASIC_DCN302; |
2a411205 | 2088 | break; |
c08182f2 | 2089 | case IP_VERSION(3, 0, 3): |
656fe9b6 | 2090 | dmub_asic = DMUB_ASIC_DCN303; |
656fe9b6 | 2091 | break; |
c08182f2 AD |
2092 | case IP_VERSION(3, 1, 2): |
2093 | case IP_VERSION(3, 1, 3): | |
3137f792 | 2094 | dmub_asic = (adev->external_rev_id == YELLOW_CARP_B0) ? DMUB_ASIC_DCN31B : DMUB_ASIC_DCN31; |
1ebcaebd | 2095 | break; |
e850f6b1 RL |
2096 | case IP_VERSION(3, 1, 4): |
2097 | dmub_asic = DMUB_ASIC_DCN314; | |
e850f6b1 | 2098 | break; |
b5b8ed44 QZ |
2099 | case IP_VERSION(3, 1, 5): |
2100 | dmub_asic = DMUB_ASIC_DCN315; | |
b5b8ed44 | 2101 | break; |
de7cc1b4 | 2102 | case IP_VERSION(3, 1, 6): |
868f4357 | 2103 | dmub_asic = DMUB_ASIC_DCN316; |
de7cc1b4 | 2104 | break; |
577359ca AP |
2105 | case IP_VERSION(3, 2, 0): |
2106 | dmub_asic = DMUB_ASIC_DCN32; | |
577359ca AP |
2107 | break; |
2108 | case IP_VERSION(3, 2, 1): | |
2109 | dmub_asic = DMUB_ASIC_DCN321; | |
577359ca | 2110 | break; |
743b9786 NK |
2111 | default: |
2112 | /* ASIC doesn't support DMUB. */ | |
2113 | return 0; | |
2114 | } | |
2115 | ||
743b9786 | 2116 | hdr = (const struct dmcub_firmware_header_v1_0 *)adev->dm.dmub_fw->data; |
72a74a18 | 2117 | adev->dm.dmcub_fw_version = le32_to_cpu(hdr->header.ucode_version); |
743b9786 | 2118 | |
9a6ed547 NK |
2119 | if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { |
2120 | adev->firmware.ucode[AMDGPU_UCODE_ID_DMCUB].ucode_id = | |
2121 | AMDGPU_UCODE_ID_DMCUB; | |
2122 | adev->firmware.ucode[AMDGPU_UCODE_ID_DMCUB].fw = | |
2123 | adev->dm.dmub_fw; | |
2124 | adev->firmware.fw_size += | |
2125 | ALIGN(le32_to_cpu(hdr->inst_const_bytes), PAGE_SIZE); | |
743b9786 | 2126 | |
9a6ed547 NK |
2127 | DRM_INFO("Loading DMUB firmware via PSP: version=0x%08X\n", |
2128 | adev->dm.dmcub_fw_version); | |
2129 | } | |
2130 | ||
743b9786 | 2131 | |
8c7aea40 NK |
2132 | adev->dm.dmub_srv = kzalloc(sizeof(*adev->dm.dmub_srv), GFP_KERNEL); |
2133 | dmub_srv = adev->dm.dmub_srv; | |
2134 | ||
2135 | if (!dmub_srv) { | |
2136 | DRM_ERROR("Failed to allocate DMUB service!\n"); | |
2137 | return -ENOMEM; | |
2138 | } | |
2139 | ||
2140 | memset(&create_params, 0, sizeof(create_params)); | |
2141 | create_params.user_ctx = adev; | |
2142 | create_params.funcs.reg_read = amdgpu_dm_dmub_reg_read; | |
2143 | create_params.funcs.reg_write = amdgpu_dm_dmub_reg_write; | |
2144 | create_params.asic = dmub_asic; | |
2145 | ||
2146 | /* Create the DMUB service. */ | |
2147 | status = dmub_srv_create(dmub_srv, &create_params); | |
2148 | if (status != DMUB_STATUS_OK) { | |
2149 | DRM_ERROR("Error creating DMUB service: %d\n", status); | |
2150 | return -EINVAL; | |
2151 | } | |
2152 | ||
2153 | /* Calculate the size of all the regions for the DMUB service. */ | |
2154 | memset(®ion_params, 0, sizeof(region_params)); | |
2155 | ||
2156 | region_params.inst_const_size = le32_to_cpu(hdr->inst_const_bytes) - | |
2157 | PSP_HEADER_BYTES - PSP_FOOTER_BYTES; | |
2158 | region_params.bss_data_size = le32_to_cpu(hdr->bss_data_bytes); | |
2159 | region_params.vbios_size = adev->bios_size; | |
0922b899 | 2160 | region_params.fw_bss_data = region_params.bss_data_size ? |
1f0674fd NK |
2161 | adev->dm.dmub_fw->data + |
2162 | le32_to_cpu(hdr->header.ucode_array_offset_bytes) + | |
0922b899 | 2163 | le32_to_cpu(hdr->inst_const_bytes) : NULL; |
a576b345 NK |
2164 | region_params.fw_inst_const = |
2165 | adev->dm.dmub_fw->data + | |
2166 | le32_to_cpu(hdr->header.ucode_array_offset_bytes) + | |
2167 | PSP_HEADER_BYTES; | |
8c7aea40 NK |
2168 | |
2169 | status = dmub_srv_calc_region_info(dmub_srv, ®ion_params, | |
2170 | ®ion_info); | |
2171 | ||
2172 | if (status != DMUB_STATUS_OK) { | |
2173 | DRM_ERROR("Error calculating DMUB region info: %d\n", status); | |
2174 | return -EINVAL; | |
2175 | } | |
2176 | ||
2177 | /* | |
2178 | * Allocate a framebuffer based on the total size of all the regions. | |
2179 | * TODO: Move this into GART. | |
2180 | */ | |
2181 | r = amdgpu_bo_create_kernel(adev, region_info.fb_size, PAGE_SIZE, | |
58ab2c08 CK |
2182 | AMDGPU_GEM_DOMAIN_VRAM | |
2183 | AMDGPU_GEM_DOMAIN_GTT, | |
2184 | &adev->dm.dmub_bo, | |
8c7aea40 NK |
2185 | &adev->dm.dmub_bo_gpu_addr, |
2186 | &adev->dm.dmub_bo_cpu_addr); | |
2187 | if (r) | |
2188 | return r; | |
2189 | ||
2190 | /* Rebase the regions on the framebuffer address. */ | |
2191 | memset(&fb_params, 0, sizeof(fb_params)); | |
2192 | fb_params.cpu_addr = adev->dm.dmub_bo_cpu_addr; | |
2193 | fb_params.gpu_addr = adev->dm.dmub_bo_gpu_addr; | |
2194 | fb_params.region_info = ®ion_info; | |
2195 | ||
2196 | adev->dm.dmub_fb_info = | |
2197 | kzalloc(sizeof(*adev->dm.dmub_fb_info), GFP_KERNEL); | |
2198 | fb_info = adev->dm.dmub_fb_info; | |
2199 | ||
2200 | if (!fb_info) { | |
2201 | DRM_ERROR( | |
2202 | "Failed to allocate framebuffer info for DMUB service!\n"); | |
2203 | return -ENOMEM; | |
2204 | } | |
2205 | ||
2206 | status = dmub_srv_calc_fb_info(dmub_srv, &fb_params, fb_info); | |
2207 | if (status != DMUB_STATUS_OK) { | |
2208 | DRM_ERROR("Error calculating DMUB FB info: %d\n", status); | |
2209 | return -EINVAL; | |
2210 | } | |
2211 | ||
743b9786 NK |
2212 | return 0; |
2213 | } | |
2214 | ||
a94d5569 DF |
2215 | static int dm_sw_init(void *handle) |
2216 | { | |
2217 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; | |
743b9786 NK |
2218 | int r; |
2219 | ||
2220 | r = dm_dmub_sw_init(adev); | |
2221 | if (r) | |
2222 | return r; | |
a94d5569 DF |
2223 | |
2224 | return load_dmcu_fw(adev); | |
2225 | } | |
2226 | ||
4562236b HW |
2227 | static int dm_sw_fini(void *handle) |
2228 | { | |
a94d5569 DF |
2229 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
2230 | ||
8c7aea40 NK |
2231 | kfree(adev->dm.dmub_fb_info); |
2232 | adev->dm.dmub_fb_info = NULL; | |
2233 | ||
743b9786 NK |
2234 | if (adev->dm.dmub_srv) { |
2235 | dmub_srv_destroy(adev->dm.dmub_srv); | |
2236 | adev->dm.dmub_srv = NULL; | |
2237 | } | |
2238 | ||
51526637 ML |
2239 | amdgpu_ucode_release(&adev->dm.dmub_fw); |
2240 | amdgpu_ucode_release(&adev->dm.fw_dmcu); | |
a94d5569 | 2241 | |
4562236b HW |
2242 | return 0; |
2243 | } | |
2244 | ||
7abcf6b5 | 2245 | static int detect_mst_link_for_all_connectors(struct drm_device *dev) |
4562236b | 2246 | { |
c84dec2f | 2247 | struct amdgpu_dm_connector *aconnector; |
4562236b | 2248 | struct drm_connector *connector; |
f8d2d39e | 2249 | struct drm_connector_list_iter iter; |
7abcf6b5 | 2250 | int ret = 0; |
4562236b | 2251 | |
f8d2d39e LP |
2252 | drm_connector_list_iter_begin(dev, &iter); |
2253 | drm_for_each_connector_iter(connector, &iter) { | |
b349f76e | 2254 | aconnector = to_amdgpu_dm_connector(connector); |
30ec2b97 JFZ |
2255 | if (aconnector->dc_link->type == dc_connection_mst_branch && |
2256 | aconnector->mst_mgr.aux) { | |
f1ad2f5e | 2257 | DRM_DEBUG_DRIVER("DM_MST: starting TM on aconnector: %p [id: %d]\n", |
f8d2d39e LP |
2258 | aconnector, |
2259 | aconnector->base.base.id); | |
7abcf6b5 AG |
2260 | |
2261 | ret = drm_dp_mst_topology_mgr_set_mst(&aconnector->mst_mgr, true); | |
2262 | if (ret < 0) { | |
2263 | DRM_ERROR("DM_MST: Failed to start MST\n"); | |
f8d2d39e LP |
2264 | aconnector->dc_link->type = |
2265 | dc_connection_single; | |
3f6752b4 RL |
2266 | ret = dm_helpers_dp_mst_stop_top_mgr(aconnector->dc_link->ctx, |
2267 | aconnector->dc_link); | |
f8d2d39e | 2268 | break; |
7abcf6b5 | 2269 | } |
f8d2d39e | 2270 | } |
4562236b | 2271 | } |
f8d2d39e | 2272 | drm_connector_list_iter_end(&iter); |
4562236b | 2273 | |
7abcf6b5 AG |
2274 | return ret; |
2275 | } | |
2276 | ||
2277 | static int dm_late_init(void *handle) | |
2278 | { | |
42e67c3b | 2279 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
7abcf6b5 | 2280 | |
bbf854dc DF |
2281 | struct dmcu_iram_parameters params; |
2282 | unsigned int linear_lut[16]; | |
2283 | int i; | |
17bdb4a8 | 2284 | struct dmcu *dmcu = NULL; |
bbf854dc | 2285 | |
17bdb4a8 JFZ |
2286 | dmcu = adev->dm.dc->res_pool->dmcu; |
2287 | ||
bbf854dc DF |
2288 | for (i = 0; i < 16; i++) |
2289 | linear_lut[i] = 0xFFFF * i / 15; | |
2290 | ||
2291 | params.set = 0; | |
75068994 | 2292 | params.backlight_ramping_override = false; |
bbf854dc DF |
2293 | params.backlight_ramping_start = 0xCCCC; |
2294 | params.backlight_ramping_reduction = 0xCCCCCCCC; | |
2295 | params.backlight_lut_array_size = 16; | |
2296 | params.backlight_lut_array = linear_lut; | |
2297 | ||
2ad0cdf9 AK |
2298 | /* Min backlight level after ABM reduction, Don't allow below 1% |
2299 | * 0xFFFF x 0.01 = 0x28F | |
2300 | */ | |
2301 | params.min_abm_backlight = 0x28F; | |
5cb32419 | 2302 | /* In the case where abm is implemented on dmcub, |
3335a135 UKK |
2303 | * dmcu object will be null. |
2304 | * ABM 2.4 and up are implemented on dmcub. | |
2305 | */ | |
6e568e43 JW |
2306 | if (dmcu) { |
2307 | if (!dmcu_load_iram(dmcu, params)) | |
2308 | return -EINVAL; | |
2309 | } else if (adev->dm.dc->ctx->dmub_srv) { | |
2310 | struct dc_link *edp_links[MAX_NUM_EDP]; | |
2311 | int edp_num; | |
bbf854dc | 2312 | |
7ae1dbe6 | 2313 | dc_get_edp_links(adev->dm.dc, edp_links, &edp_num); |
6e568e43 JW |
2314 | for (i = 0; i < edp_num; i++) { |
2315 | if (!dmub_init_abm_config(adev->dm.dc->res_pool, params, i)) | |
2316 | return -EINVAL; | |
2317 | } | |
2318 | } | |
bbf854dc | 2319 | |
4a580877 | 2320 | return detect_mst_link_for_all_connectors(adev_to_drm(adev)); |
4562236b HW |
2321 | } |
2322 | ||
2323 | static void s3_handle_mst(struct drm_device *dev, bool suspend) | |
2324 | { | |
c84dec2f | 2325 | struct amdgpu_dm_connector *aconnector; |
4562236b | 2326 | struct drm_connector *connector; |
f8d2d39e | 2327 | struct drm_connector_list_iter iter; |
fe7553be LP |
2328 | struct drm_dp_mst_topology_mgr *mgr; |
2329 | int ret; | |
2330 | bool need_hotplug = false; | |
4562236b | 2331 | |
f8d2d39e LP |
2332 | drm_connector_list_iter_begin(dev, &iter); |
2333 | drm_for_each_connector_iter(connector, &iter) { | |
fe7553be LP |
2334 | aconnector = to_amdgpu_dm_connector(connector); |
2335 | if (aconnector->dc_link->type != dc_connection_mst_branch || | |
f0127cb1 | 2336 | aconnector->mst_root) |
fe7553be LP |
2337 | continue; |
2338 | ||
2339 | mgr = &aconnector->mst_mgr; | |
2340 | ||
2341 | if (suspend) { | |
2342 | drm_dp_mst_topology_mgr_suspend(mgr); | |
2343 | } else { | |
1e5d4d8e RL |
2344 | /* if extended timeout is supported in hardware, |
2345 | * default to LTTPR timeout (3.2ms) first as a W/A for DP link layer | |
2346 | * CTS 4.2.1.1 regression introduced by CTS specs requirement update. | |
2347 | */ | |
2348 | try_to_configure_aux_timeout(aconnector->dc_link->ddc, LINK_AUX_DEFAULT_LTTPR_TIMEOUT_PERIOD); | |
2349 | if (!dp_is_lttpr_present(aconnector->dc_link)) | |
2350 | try_to_configure_aux_timeout(aconnector->dc_link->ddc, LINK_AUX_DEFAULT_TIMEOUT_PERIOD); | |
2351 | ||
6f85f738 | 2352 | ret = drm_dp_mst_topology_mgr_resume(mgr, true); |
fe7553be | 2353 | if (ret < 0) { |
84a8b390 WL |
2354 | dm_helpers_dp_mst_stop_top_mgr(aconnector->dc_link->ctx, |
2355 | aconnector->dc_link); | |
fe7553be LP |
2356 | need_hotplug = true; |
2357 | } | |
2358 | } | |
4562236b | 2359 | } |
f8d2d39e | 2360 | drm_connector_list_iter_end(&iter); |
fe7553be LP |
2361 | |
2362 | if (need_hotplug) | |
2363 | drm_kms_helper_hotplug_event(dev); | |
4562236b HW |
2364 | } |
2365 | ||
9340dfd3 HW |
2366 | static int amdgpu_dm_smu_write_watermarks_table(struct amdgpu_device *adev) |
2367 | { | |
9340dfd3 HW |
2368 | int ret = 0; |
2369 | ||
9340dfd3 HW |
2370 | /* This interface is for dGPU Navi1x.Linux dc-pplib interface depends |
2371 | * on window driver dc implementation. | |
2372 | * For Navi1x, clock settings of dcn watermarks are fixed. the settings | |
2373 | * should be passed to smu during boot up and resume from s3. | |
2374 | * boot up: dc calculate dcn watermark clock settings within dc_create, | |
2375 | * dcn20_resource_construct | |
2376 | * then call pplib functions below to pass the settings to smu: | |
2377 | * smu_set_watermarks_for_clock_ranges | |
2378 | * smu_set_watermarks_table | |
2379 | * navi10_set_watermarks_table | |
2380 | * smu_write_watermarks_table | |
2381 | * | |
2382 | * For Renoir, clock settings of dcn watermark are also fixed values. | |
2383 | * dc has implemented different flow for window driver: | |
2384 | * dc_hardware_init / dc_set_power_state | |
2385 | * dcn10_init_hw | |
2386 | * notify_wm_ranges | |
2387 | * set_wm_ranges | |
2388 | * -- Linux | |
2389 | * smu_set_watermarks_for_clock_ranges | |
2390 | * renoir_set_watermarks_table | |
2391 | * smu_write_watermarks_table | |
2392 | * | |
2393 | * For Linux, | |
2394 | * dc_hardware_init -> amdgpu_dm_init | |
2395 | * dc_set_power_state --> dm_resume | |
2396 | * | |
2397 | * therefore, this function apply to navi10/12/14 but not Renoir | |
2398 | * * | |
2399 | */ | |
1d789535 | 2400 | switch (adev->ip_versions[DCE_HWIP][0]) { |
c08182f2 AD |
2401 | case IP_VERSION(2, 0, 2): |
2402 | case IP_VERSION(2, 0, 0): | |
9340dfd3 HW |
2403 | break; |
2404 | default: | |
2405 | return 0; | |
2406 | } | |
2407 | ||
13f5dbd6 | 2408 | ret = amdgpu_dpm_write_watermarks_table(adev); |
e7a95eea EQ |
2409 | if (ret) { |
2410 | DRM_ERROR("Failed to update WMTABLE!\n"); | |
2411 | return ret; | |
9340dfd3 HW |
2412 | } |
2413 | ||
9340dfd3 HW |
2414 | return 0; |
2415 | } | |
2416 | ||
b8592b48 LL |
2417 | /** |
2418 | * dm_hw_init() - Initialize DC device | |
28d687ea | 2419 | * @handle: The base driver device containing the amdgpu_dm device. |
b8592b48 LL |
2420 | * |
2421 | * Initialize the &struct amdgpu_display_manager device. This involves calling | |
2422 | * the initializers of each DM component, then populating the struct with them. | |
2423 | * | |
2424 | * Although the function implies hardware initialization, both hardware and | |
2425 | * software are initialized here. Splitting them out to their relevant init | |
2426 | * hooks is a future TODO item. | |
2427 | * | |
2428 | * Some notable things that are initialized here: | |
2429 | * | |
2430 | * - Display Core, both software and hardware | |
2431 | * - DC modules that we need (freesync and color management) | |
2432 | * - DRM software states | |
2433 | * - Interrupt sources and handlers | |
2434 | * - Vblank support | |
2435 | * - Debug FS entries, if enabled | |
2436 | */ | |
4562236b HW |
2437 | static int dm_hw_init(void *handle) |
2438 | { | |
2439 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; | |
2440 | /* Create DAL display manager */ | |
2441 | amdgpu_dm_init(adev); | |
4562236b HW |
2442 | amdgpu_dm_hpd_init(adev); |
2443 | ||
4562236b HW |
2444 | return 0; |
2445 | } | |
2446 | ||
b8592b48 LL |
2447 | /** |
2448 | * dm_hw_fini() - Teardown DC device | |
28d687ea | 2449 | * @handle: The base driver device containing the amdgpu_dm device. |
b8592b48 LL |
2450 | * |
2451 | * Teardown components within &struct amdgpu_display_manager that require | |
2452 | * cleanup. This involves cleaning up the DRM device, DC, and any modules that | |
2453 | * were loaded. Also flush IRQ workqueues and disable them. | |
2454 | */ | |
4562236b HW |
2455 | static int dm_hw_fini(void *handle) |
2456 | { | |
2457 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; | |
2458 | ||
2459 | amdgpu_dm_hpd_fini(adev); | |
2460 | ||
2461 | amdgpu_dm_irq_fini(adev); | |
21de3396 | 2462 | amdgpu_dm_fini(adev); |
4562236b HW |
2463 | return 0; |
2464 | } | |
2465 | ||
cdaae837 | 2466 | |
cdaae837 BL |
2467 | static void dm_gpureset_toggle_interrupts(struct amdgpu_device *adev, |
2468 | struct dc_state *state, bool enable) | |
2469 | { | |
2470 | enum dc_irq_source irq_source; | |
2471 | struct amdgpu_crtc *acrtc; | |
2472 | int rc = -EBUSY; | |
2473 | int i = 0; | |
2474 | ||
2475 | for (i = 0; i < state->stream_count; i++) { | |
2476 | acrtc = get_crtc_by_otg_inst( | |
2477 | adev, state->stream_status[i].primary_otg_inst); | |
2478 | ||
2479 | if (acrtc && state->stream_status[i].plane_count != 0) { | |
2480 | irq_source = IRQ_TYPE_PFLIP + acrtc->otg_inst; | |
2481 | rc = dc_interrupt_set(adev->dm.dc, irq_source, enable) ? 0 : -EBUSY; | |
4711c033 LT |
2482 | DRM_DEBUG_VBL("crtc %d - vupdate irq %sabling: r=%d\n", |
2483 | acrtc->crtc_id, enable ? "en" : "dis", rc); | |
cdaae837 BL |
2484 | if (rc) |
2485 | DRM_WARN("Failed to %s pflip interrupts\n", | |
2486 | enable ? "enable" : "disable"); | |
2487 | ||
2488 | if (enable) { | |
6c5e25a0 | 2489 | rc = amdgpu_dm_crtc_enable_vblank(&acrtc->base); |
cdaae837 BL |
2490 | if (rc) |
2491 | DRM_WARN("Failed to enable vblank interrupts\n"); | |
2492 | } else { | |
6c5e25a0 | 2493 | amdgpu_dm_crtc_disable_vblank(&acrtc->base); |
cdaae837 BL |
2494 | } |
2495 | ||
2496 | } | |
2497 | } | |
2498 | ||
2499 | } | |
2500 | ||
dfd84d90 | 2501 | static enum dc_status amdgpu_dm_commit_zero_streams(struct dc *dc) |
cdaae837 BL |
2502 | { |
2503 | struct dc_state *context = NULL; | |
2504 | enum dc_status res = DC_ERROR_UNEXPECTED; | |
2505 | int i; | |
2506 | struct dc_stream_state *del_streams[MAX_PIPES]; | |
2507 | int del_streams_count = 0; | |
2508 | ||
2509 | memset(del_streams, 0, sizeof(del_streams)); | |
2510 | ||
2511 | context = dc_create_state(dc); | |
2512 | if (context == NULL) | |
2513 | goto context_alloc_fail; | |
2514 | ||
2515 | dc_resource_state_copy_construct_current(dc, context); | |
2516 | ||
2517 | /* First remove from context all streams */ | |
2518 | for (i = 0; i < context->stream_count; i++) { | |
2519 | struct dc_stream_state *stream = context->streams[i]; | |
2520 | ||
2521 | del_streams[del_streams_count++] = stream; | |
2522 | } | |
2523 | ||
2524 | /* Remove all planes for removed streams and then remove the streams */ | |
2525 | for (i = 0; i < del_streams_count; i++) { | |
2526 | if (!dc_rem_all_planes_for_stream(dc, del_streams[i], context)) { | |
2527 | res = DC_FAIL_DETACH_SURFACES; | |
2528 | goto fail; | |
2529 | } | |
2530 | ||
2531 | res = dc_remove_stream_from_ctx(dc, context, del_streams[i]); | |
2532 | if (res != DC_OK) | |
2533 | goto fail; | |
2534 | } | |
2535 | ||
b8272241 | 2536 | res = dc_commit_streams(dc, context->streams, context->stream_count); |
cdaae837 BL |
2537 | |
2538 | fail: | |
2539 | dc_release_state(context); | |
2540 | ||
2541 | context_alloc_fail: | |
2542 | return res; | |
2543 | } | |
2544 | ||
8e794421 WL |
2545 | static void hpd_rx_irq_work_suspend(struct amdgpu_display_manager *dm) |
2546 | { | |
2547 | int i; | |
2548 | ||
2549 | if (dm->hpd_rx_offload_wq) { | |
2550 | for (i = 0; i < dm->dc->caps.max_links; i++) | |
2551 | flush_workqueue(dm->hpd_rx_offload_wq[i].wq); | |
2552 | } | |
2553 | } | |
2554 | ||
4562236b HW |
2555 | static int dm_suspend(void *handle) |
2556 | { | |
2557 | struct amdgpu_device *adev = handle; | |
2558 | struct amdgpu_display_manager *dm = &adev->dm; | |
2559 | int ret = 0; | |
4562236b | 2560 | |
53b3f8f4 | 2561 | if (amdgpu_in_reset(adev)) { |
cdaae837 | 2562 | mutex_lock(&dm->dc_lock); |
98ab5f35 | 2563 | |
98ab5f35 | 2564 | dc_allow_idle_optimizations(adev->dm.dc, false); |
98ab5f35 | 2565 | |
cdaae837 BL |
2566 | dm->cached_dc_state = dc_copy_state(dm->dc->current_state); |
2567 | ||
2568 | dm_gpureset_toggle_interrupts(adev, dm->cached_dc_state, false); | |
2569 | ||
2570 | amdgpu_dm_commit_zero_streams(dm->dc); | |
2571 | ||
2572 | amdgpu_dm_irq_suspend(adev); | |
2573 | ||
8e794421 WL |
2574 | hpd_rx_irq_work_suspend(dm); |
2575 | ||
cdaae837 BL |
2576 | return ret; |
2577 | } | |
4562236b | 2578 | |
d2f0b53b | 2579 | WARN_ON(adev->dm.cached_state); |
4a580877 | 2580 | adev->dm.cached_state = drm_atomic_helper_suspend(adev_to_drm(adev)); |
d2f0b53b | 2581 | |
4a580877 | 2582 | s3_handle_mst(adev_to_drm(adev), true); |
4562236b | 2583 | |
4562236b HW |
2584 | amdgpu_dm_irq_suspend(adev); |
2585 | ||
8e794421 WL |
2586 | hpd_rx_irq_work_suspend(dm); |
2587 | ||
32f5062d | 2588 | dc_set_power_state(dm->dc, DC_ACPI_CM_POWER_STATE_D3); |
4562236b | 2589 | |
1c2075d4 | 2590 | return 0; |
4562236b HW |
2591 | } |
2592 | ||
17ce8a69 | 2593 | struct amdgpu_dm_connector * |
1daf8c63 AD |
2594 | amdgpu_dm_find_first_crtc_matching_connector(struct drm_atomic_state *state, |
2595 | struct drm_crtc *crtc) | |
4562236b | 2596 | { |
ae67558b | 2597 | u32 i; |
c2cea706 | 2598 | struct drm_connector_state *new_con_state; |
4562236b HW |
2599 | struct drm_connector *connector; |
2600 | struct drm_crtc *crtc_from_state; | |
2601 | ||
c2cea706 LSL |
2602 | for_each_new_connector_in_state(state, connector, new_con_state, i) { |
2603 | crtc_from_state = new_con_state->crtc; | |
4562236b HW |
2604 | |
2605 | if (crtc_from_state == crtc) | |
c84dec2f | 2606 | return to_amdgpu_dm_connector(connector); |
4562236b HW |
2607 | } |
2608 | ||
2609 | return NULL; | |
2610 | } | |
2611 | ||
fbbdadf2 BL |
2612 | static void emulated_link_detect(struct dc_link *link) |
2613 | { | |
2614 | struct dc_sink_init_data sink_init_data = { 0 }; | |
2615 | struct display_sink_capability sink_caps = { 0 }; | |
2616 | enum dc_edid_status edid_status; | |
2617 | struct dc_context *dc_ctx = link->ctx; | |
2618 | struct dc_sink *sink = NULL; | |
2619 | struct dc_sink *prev_sink = NULL; | |
2620 | ||
2621 | link->type = dc_connection_none; | |
2622 | prev_sink = link->local_sink; | |
2623 | ||
30164a16 VL |
2624 | if (prev_sink) |
2625 | dc_sink_release(prev_sink); | |
fbbdadf2 BL |
2626 | |
2627 | switch (link->connector_signal) { | |
2628 | case SIGNAL_TYPE_HDMI_TYPE_A: { | |
2629 | sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C; | |
2630 | sink_caps.signal = SIGNAL_TYPE_HDMI_TYPE_A; | |
2631 | break; | |
2632 | } | |
2633 | ||
2634 | case SIGNAL_TYPE_DVI_SINGLE_LINK: { | |
2635 | sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C; | |
2636 | sink_caps.signal = SIGNAL_TYPE_DVI_SINGLE_LINK; | |
2637 | break; | |
2638 | } | |
2639 | ||
2640 | case SIGNAL_TYPE_DVI_DUAL_LINK: { | |
2641 | sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C; | |
2642 | sink_caps.signal = SIGNAL_TYPE_DVI_DUAL_LINK; | |
2643 | break; | |
2644 | } | |
2645 | ||
2646 | case SIGNAL_TYPE_LVDS: { | |
2647 | sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C; | |
2648 | sink_caps.signal = SIGNAL_TYPE_LVDS; | |
2649 | break; | |
2650 | } | |
2651 | ||
2652 | case SIGNAL_TYPE_EDP: { | |
2653 | sink_caps.transaction_type = | |
2654 | DDC_TRANSACTION_TYPE_I2C_OVER_AUX; | |
2655 | sink_caps.signal = SIGNAL_TYPE_EDP; | |
2656 | break; | |
2657 | } | |
2658 | ||
2659 | case SIGNAL_TYPE_DISPLAY_PORT: { | |
2660 | sink_caps.transaction_type = | |
2661 | DDC_TRANSACTION_TYPE_I2C_OVER_AUX; | |
2662 | sink_caps.signal = SIGNAL_TYPE_VIRTUAL; | |
2663 | break; | |
2664 | } | |
2665 | ||
2666 | default: | |
2667 | DC_ERROR("Invalid connector type! signal:%d\n", | |
2668 | link->connector_signal); | |
2669 | return; | |
2670 | } | |
2671 | ||
2672 | sink_init_data.link = link; | |
2673 | sink_init_data.sink_signal = sink_caps.signal; | |
2674 | ||
2675 | sink = dc_sink_create(&sink_init_data); | |
2676 | if (!sink) { | |
2677 | DC_ERROR("Failed to create sink!\n"); | |
2678 | return; | |
2679 | } | |
2680 | ||
dcd5fb82 | 2681 | /* dc_sink_create returns a new reference */ |
fbbdadf2 BL |
2682 | link->local_sink = sink; |
2683 | ||
2684 | edid_status = dm_helpers_read_local_edid( | |
2685 | link->ctx, | |
2686 | link, | |
2687 | sink); | |
2688 | ||
2689 | if (edid_status != EDID_OK) | |
2690 | DC_ERROR("Failed to read EDID"); | |
2691 | ||
2692 | } | |
2693 | ||
cdaae837 BL |
2694 | static void dm_gpureset_commit_state(struct dc_state *dc_state, |
2695 | struct amdgpu_display_manager *dm) | |
2696 | { | |
2697 | struct { | |
2698 | struct dc_surface_update surface_updates[MAX_SURFACES]; | |
2699 | struct dc_plane_info plane_infos[MAX_SURFACES]; | |
2700 | struct dc_scaling_info scaling_infos[MAX_SURFACES]; | |
2701 | struct dc_flip_addrs flip_addrs[MAX_SURFACES]; | |
2702 | struct dc_stream_update stream_update; | |
2703 | } * bundle; | |
2704 | int k, m; | |
2705 | ||
2706 | bundle = kzalloc(sizeof(*bundle), GFP_KERNEL); | |
2707 | ||
2708 | if (!bundle) { | |
2709 | dm_error("Failed to allocate update bundle\n"); | |
2710 | goto cleanup; | |
2711 | } | |
2712 | ||
2713 | for (k = 0; k < dc_state->stream_count; k++) { | |
2714 | bundle->stream_update.stream = dc_state->streams[k]; | |
2715 | ||
2716 | for (m = 0; m < dc_state->stream_status->plane_count; m++) { | |
2717 | bundle->surface_updates[m].surface = | |
2718 | dc_state->stream_status->plane_states[m]; | |
2719 | bundle->surface_updates[m].surface->force_full_update = | |
2720 | true; | |
2721 | } | |
f7511289 | 2722 | |
81f743a0 RS |
2723 | update_planes_and_stream_adapter(dm->dc, |
2724 | UPDATE_TYPE_FULL, | |
2725 | dc_state->stream_status->plane_count, | |
2726 | dc_state->streams[k], | |
2727 | &bundle->stream_update, | |
2728 | bundle->surface_updates); | |
cdaae837 BL |
2729 | } |
2730 | ||
2731 | cleanup: | |
2732 | kfree(bundle); | |
2733 | ||
2734 | return; | |
2735 | } | |
2736 | ||
4562236b HW |
2737 | static int dm_resume(void *handle) |
2738 | { | |
2739 | struct amdgpu_device *adev = handle; | |
4a580877 | 2740 | struct drm_device *ddev = adev_to_drm(adev); |
4562236b | 2741 | struct amdgpu_display_manager *dm = &adev->dm; |
c84dec2f | 2742 | struct amdgpu_dm_connector *aconnector; |
4562236b | 2743 | struct drm_connector *connector; |
f8d2d39e | 2744 | struct drm_connector_list_iter iter; |
4562236b | 2745 | struct drm_crtc *crtc; |
c2cea706 | 2746 | struct drm_crtc_state *new_crtc_state; |
fcb4019e LSL |
2747 | struct dm_crtc_state *dm_new_crtc_state; |
2748 | struct drm_plane *plane; | |
2749 | struct drm_plane_state *new_plane_state; | |
2750 | struct dm_plane_state *dm_new_plane_state; | |
113b7a01 | 2751 | struct dm_atomic_state *dm_state = to_dm_atomic_state(dm->atomic_obj.state); |
fbbdadf2 | 2752 | enum dc_connection_type new_connection_type = dc_connection_none; |
cdaae837 BL |
2753 | struct dc_state *dc_state; |
2754 | int i, r, j; | |
4562236b | 2755 | |
53b3f8f4 | 2756 | if (amdgpu_in_reset(adev)) { |
cdaae837 BL |
2757 | dc_state = dm->cached_dc_state; |
2758 | ||
6d63fcc2 NK |
2759 | /* |
2760 | * The dc->current_state is backed up into dm->cached_dc_state | |
2761 | * before we commit 0 streams. | |
2762 | * | |
2763 | * DC will clear link encoder assignments on the real state | |
2764 | * but the changes won't propagate over to the copy we made | |
2765 | * before the 0 streams commit. | |
2766 | * | |
2767 | * DC expects that link encoder assignments are *not* valid | |
32685b32 NK |
2768 | * when committing a state, so as a workaround we can copy |
2769 | * off of the current state. | |
2770 | * | |
2771 | * We lose the previous assignments, but we had already | |
2772 | * commit 0 streams anyway. | |
6d63fcc2 | 2773 | */ |
32685b32 | 2774 | link_enc_cfg_copy(adev->dm.dc->current_state, dc_state); |
6d63fcc2 | 2775 | |
cdaae837 BL |
2776 | r = dm_dmub_hw_init(adev); |
2777 | if (r) | |
2778 | DRM_ERROR("DMUB interface failed to initialize: status=%d\n", r); | |
2779 | ||
2780 | dc_set_power_state(dm->dc, DC_ACPI_CM_POWER_STATE_D0); | |
2781 | dc_resume(dm->dc); | |
2782 | ||
2783 | amdgpu_dm_irq_resume_early(adev); | |
2784 | ||
2785 | for (i = 0; i < dc_state->stream_count; i++) { | |
2786 | dc_state->streams[i]->mode_changed = true; | |
6984fa41 NK |
2787 | for (j = 0; j < dc_state->stream_status[i].plane_count; j++) { |
2788 | dc_state->stream_status[i].plane_states[j]->update_flags.raw | |
cdaae837 BL |
2789 | = 0xffffffff; |
2790 | } | |
2791 | } | |
2792 | ||
11d526f1 SW |
2793 | if (dc_is_dmub_outbox_supported(adev->dm.dc)) { |
2794 | amdgpu_dm_outbox_init(adev); | |
2795 | dc_enable_dmub_outbox(adev->dm.dc); | |
2796 | } | |
2797 | ||
b8272241 | 2798 | WARN_ON(!dc_commit_streams(dm->dc, dc_state->streams, dc_state->stream_count)); |
4562236b | 2799 | |
cdaae837 BL |
2800 | dm_gpureset_commit_state(dm->cached_dc_state, dm); |
2801 | ||
2802 | dm_gpureset_toggle_interrupts(adev, dm->cached_dc_state, true); | |
2803 | ||
2804 | dc_release_state(dm->cached_dc_state); | |
2805 | dm->cached_dc_state = NULL; | |
2806 | ||
2807 | amdgpu_dm_irq_resume_late(adev); | |
2808 | ||
2809 | mutex_unlock(&dm->dc_lock); | |
2810 | ||
2811 | return 0; | |
2812 | } | |
113b7a01 LL |
2813 | /* Recreate dc_state - DC invalidates it when setting power state to S3. */ |
2814 | dc_release_state(dm_state->context); | |
2815 | dm_state->context = dc_create_state(dm->dc); | |
2816 | /* TODO: Remove dc_state->dccg, use dc->dccg directly. */ | |
2817 | dc_resource_state_construct(dm->dc, dm_state->context); | |
2818 | ||
8c7aea40 | 2819 | /* Before powering on DC we need to re-initialize DMUB. */ |
79d6b935 | 2820 | dm_dmub_hw_resume(adev); |
8c7aea40 | 2821 | |
11d526f1 SW |
2822 | /* Re-enable outbox interrupts for DPIA. */ |
2823 | if (dc_is_dmub_outbox_supported(adev->dm.dc)) { | |
2824 | amdgpu_dm_outbox_init(adev); | |
2825 | dc_enable_dmub_outbox(adev->dm.dc); | |
2826 | } | |
2827 | ||
a80aa93d ML |
2828 | /* power on hardware */ |
2829 | dc_set_power_state(dm->dc, DC_ACPI_CM_POWER_STATE_D0); | |
2830 | ||
4562236b HW |
2831 | /* program HPD filter */ |
2832 | dc_resume(dm->dc); | |
2833 | ||
4562236b HW |
2834 | /* |
2835 | * early enable HPD Rx IRQ, should be done before set mode as short | |
2836 | * pulse interrupts are used for MST | |
2837 | */ | |
2838 | amdgpu_dm_irq_resume_early(adev); | |
2839 | ||
d20ebea8 | 2840 | /* On resume we need to rewrite the MSTM control bits to enable MST*/ |
684cd480 LP |
2841 | s3_handle_mst(ddev, false); |
2842 | ||
4562236b | 2843 | /* Do detection*/ |
f8d2d39e LP |
2844 | drm_connector_list_iter_begin(ddev, &iter); |
2845 | drm_for_each_connector_iter(connector, &iter) { | |
c84dec2f | 2846 | aconnector = to_amdgpu_dm_connector(connector); |
4562236b | 2847 | |
7a7175a2 RL |
2848 | if (!aconnector->dc_link) |
2849 | continue; | |
2850 | ||
4562236b HW |
2851 | /* |
2852 | * this is the case when traversing through already created | |
2853 | * MST connectors, should be skipped | |
2854 | */ | |
7a7175a2 | 2855 | if (aconnector->dc_link->type == dc_connection_mst_branch) |
4562236b HW |
2856 | continue; |
2857 | ||
03ea364c | 2858 | mutex_lock(&aconnector->hpd_lock); |
54618888 | 2859 | if (!dc_link_detect_connection_type(aconnector->dc_link, &new_connection_type)) |
fbbdadf2 BL |
2860 | DRM_ERROR("KMS: Failed to detect connector\n"); |
2861 | ||
15c735e7 | 2862 | if (aconnector->base.force && new_connection_type == dc_connection_none) { |
fbbdadf2 | 2863 | emulated_link_detect(aconnector->dc_link); |
15c735e7 WL |
2864 | } else { |
2865 | mutex_lock(&dm->dc_lock); | |
fbbdadf2 | 2866 | dc_link_detect(aconnector->dc_link, DETECT_REASON_HPD); |
15c735e7 WL |
2867 | mutex_unlock(&dm->dc_lock); |
2868 | } | |
3eb4eba4 RL |
2869 | |
2870 | if (aconnector->fake_enable && aconnector->dc_link->local_sink) | |
2871 | aconnector->fake_enable = false; | |
2872 | ||
dcd5fb82 MF |
2873 | if (aconnector->dc_sink) |
2874 | dc_sink_release(aconnector->dc_sink); | |
4562236b HW |
2875 | aconnector->dc_sink = NULL; |
2876 | amdgpu_dm_update_connector_after_detect(aconnector); | |
03ea364c | 2877 | mutex_unlock(&aconnector->hpd_lock); |
4562236b | 2878 | } |
f8d2d39e | 2879 | drm_connector_list_iter_end(&iter); |
4562236b | 2880 | |
1f6010a9 | 2881 | /* Force mode set in atomic commit */ |
a80aa93d | 2882 | for_each_new_crtc_in_state(dm->cached_state, crtc, new_crtc_state, i) |
c2cea706 | 2883 | new_crtc_state->active_changed = true; |
4f346e65 | 2884 | |
fcb4019e LSL |
2885 | /* |
2886 | * atomic_check is expected to create the dc states. We need to release | |
2887 | * them here, since they were duplicated as part of the suspend | |
2888 | * procedure. | |
2889 | */ | |
a80aa93d | 2890 | for_each_new_crtc_in_state(dm->cached_state, crtc, new_crtc_state, i) { |
fcb4019e LSL |
2891 | dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); |
2892 | if (dm_new_crtc_state->stream) { | |
2893 | WARN_ON(kref_read(&dm_new_crtc_state->stream->refcount) > 1); | |
2894 | dc_stream_release(dm_new_crtc_state->stream); | |
2895 | dm_new_crtc_state->stream = NULL; | |
2896 | } | |
2897 | } | |
2898 | ||
a80aa93d | 2899 | for_each_new_plane_in_state(dm->cached_state, plane, new_plane_state, i) { |
fcb4019e LSL |
2900 | dm_new_plane_state = to_dm_plane_state(new_plane_state); |
2901 | if (dm_new_plane_state->dc_state) { | |
2902 | WARN_ON(kref_read(&dm_new_plane_state->dc_state->refcount) > 1); | |
2903 | dc_plane_state_release(dm_new_plane_state->dc_state); | |
2904 | dm_new_plane_state->dc_state = NULL; | |
2905 | } | |
2906 | } | |
2907 | ||
2d1af6a1 | 2908 | drm_atomic_helper_resume(ddev, dm->cached_state); |
4562236b | 2909 | |
a80aa93d | 2910 | dm->cached_state = NULL; |
0a214e2f | 2911 | |
9faa4237 | 2912 | amdgpu_dm_irq_resume_late(adev); |
4562236b | 2913 | |
9340dfd3 HW |
2914 | amdgpu_dm_smu_write_watermarks_table(adev); |
2915 | ||
2d1af6a1 | 2916 | return 0; |
4562236b HW |
2917 | } |
2918 | ||
b8592b48 LL |
2919 | /** |
2920 | * DOC: DM Lifecycle | |
2921 | * | |
2922 | * DM (and consequently DC) is registered in the amdgpu base driver as a IP | |
2923 | * block. When CONFIG_DRM_AMD_DC is enabled, the DM device IP block is added to | |
2924 | * the base driver's device list to be initialized and torn down accordingly. | |
2925 | * | |
2926 | * The functions to do so are provided as hooks in &struct amd_ip_funcs. | |
2927 | */ | |
2928 | ||
4562236b HW |
2929 | static const struct amd_ip_funcs amdgpu_dm_funcs = { |
2930 | .name = "dm", | |
2931 | .early_init = dm_early_init, | |
7abcf6b5 | 2932 | .late_init = dm_late_init, |
4562236b HW |
2933 | .sw_init = dm_sw_init, |
2934 | .sw_fini = dm_sw_fini, | |
e9669fb7 | 2935 | .early_fini = amdgpu_dm_early_fini, |
4562236b HW |
2936 | .hw_init = dm_hw_init, |
2937 | .hw_fini = dm_hw_fini, | |
2938 | .suspend = dm_suspend, | |
2939 | .resume = dm_resume, | |
2940 | .is_idle = dm_is_idle, | |
2941 | .wait_for_idle = dm_wait_for_idle, | |
2942 | .check_soft_reset = dm_check_soft_reset, | |
2943 | .soft_reset = dm_soft_reset, | |
2944 | .set_clockgating_state = dm_set_clockgating_state, | |
2945 | .set_powergating_state = dm_set_powergating_state, | |
2946 | }; | |
2947 | ||
2948 | const struct amdgpu_ip_block_version dm_ip_block = | |
2949 | { | |
2950 | .type = AMD_IP_BLOCK_TYPE_DCE, | |
2951 | .major = 1, | |
2952 | .minor = 0, | |
2953 | .rev = 0, | |
2954 | .funcs = &amdgpu_dm_funcs, | |
2955 | }; | |
2956 | ||
ca3268c4 | 2957 | |
b8592b48 LL |
2958 | /** |
2959 | * DOC: atomic | |
2960 | * | |
2961 | * *WIP* | |
2962 | */ | |
0a323b84 | 2963 | |
b3663f70 | 2964 | static const struct drm_mode_config_funcs amdgpu_dm_mode_funcs = { |
4d4772f6 | 2965 | .fb_create = amdgpu_display_user_framebuffer_create, |
8bf0d9cd | 2966 | .get_format_info = amdgpu_dm_plane_get_format_info, |
4562236b | 2967 | .atomic_check = amdgpu_dm_atomic_check, |
0269764a | 2968 | .atomic_commit = drm_atomic_helper_commit, |
54f5499a AG |
2969 | }; |
2970 | ||
2971 | static struct drm_mode_config_helper_funcs amdgpu_dm_mode_config_helperfuncs = { | |
a5c2c0d1 LP |
2972 | .atomic_commit_tail = amdgpu_dm_atomic_commit_tail, |
2973 | .atomic_commit_setup = drm_dp_mst_atomic_setup_commit, | |
4562236b HW |
2974 | }; |
2975 | ||
94562810 RS |
2976 | static void update_connector_ext_caps(struct amdgpu_dm_connector *aconnector) |
2977 | { | |
94562810 | 2978 | struct amdgpu_dm_backlight_caps *caps; |
94562810 RS |
2979 | struct drm_connector *conn_base; |
2980 | struct amdgpu_device *adev; | |
a61bb342 | 2981 | struct drm_luminance_range_info *luminance_range; |
94562810 | 2982 | |
f196198c HG |
2983 | if (aconnector->bl_idx == -1 || |
2984 | aconnector->dc_link->connector_signal != SIGNAL_TYPE_EDP) | |
ec11fe37 | 2985 | return; |
2986 | ||
94562810 | 2987 | conn_base = &aconnector->base; |
1348969a | 2988 | adev = drm_to_adev(conn_base->dev); |
f196198c HG |
2989 | |
2990 | caps = &adev->dm.backlight_caps[aconnector->bl_idx]; | |
94562810 RS |
2991 | caps->ext_caps = &aconnector->dc_link->dpcd_sink_ext_caps; |
2992 | caps->aux_support = false; | |
94562810 | 2993 | |
d0ae0b64 | 2994 | if (caps->ext_caps->bits.oled == 1 /*|| |
94562810 | 2995 | caps->ext_caps->bits.sdr_aux_backlight_control == 1 || |
d0ae0b64 | 2996 | caps->ext_caps->bits.hdr_aux_backlight_control == 1*/) |
94562810 RS |
2997 | caps->aux_support = true; |
2998 | ||
7a46f05e TI |
2999 | if (amdgpu_backlight == 0) |
3000 | caps->aux_support = false; | |
3001 | else if (amdgpu_backlight == 1) | |
3002 | caps->aux_support = true; | |
3003 | ||
a61bb342 | 3004 | luminance_range = &conn_base->display_info.luminance_range; |
932698c8 SP |
3005 | |
3006 | if (luminance_range->max_luminance) { | |
3007 | caps->aux_min_input_signal = luminance_range->min_luminance; | |
3008 | caps->aux_max_input_signal = luminance_range->max_luminance; | |
3009 | } else { | |
3010 | caps->aux_min_input_signal = 0; | |
3011 | caps->aux_max_input_signal = 512; | |
3012 | } | |
94562810 RS |
3013 | } |
3014 | ||
97e51c16 HW |
3015 | void amdgpu_dm_update_connector_after_detect( |
3016 | struct amdgpu_dm_connector *aconnector) | |
4562236b HW |
3017 | { |
3018 | struct drm_connector *connector = &aconnector->base; | |
3019 | struct drm_device *dev = connector->dev; | |
b73a22d3 | 3020 | struct dc_sink *sink; |
4562236b HW |
3021 | |
3022 | /* MST handled by drm_mst framework */ | |
3023 | if (aconnector->mst_mgr.mst_state == true) | |
3024 | return; | |
3025 | ||
4562236b | 3026 | sink = aconnector->dc_link->local_sink; |
dcd5fb82 MF |
3027 | if (sink) |
3028 | dc_sink_retain(sink); | |
4562236b | 3029 | |
1f6010a9 DF |
3030 | /* |
3031 | * Edid mgmt connector gets first update only in mode_valid hook and then | |
4562236b | 3032 | * the connector sink is set to either fake or physical sink depends on link status. |
1f6010a9 | 3033 | * Skip if already done during boot. |
4562236b HW |
3034 | */ |
3035 | if (aconnector->base.force != DRM_FORCE_UNSPECIFIED | |
3036 | && aconnector->dc_em_sink) { | |
3037 | ||
1f6010a9 DF |
3038 | /* |
3039 | * For S3 resume with headless use eml_sink to fake stream | |
3040 | * because on resume connector->sink is set to NULL | |
4562236b HW |
3041 | */ |
3042 | mutex_lock(&dev->mode_config.mutex); | |
3043 | ||
3044 | if (sink) { | |
922aa1e1 | 3045 | if (aconnector->dc_sink) { |
98e6436d | 3046 | amdgpu_dm_update_freesync_caps(connector, NULL); |
1f6010a9 DF |
3047 | /* |
3048 | * retain and release below are used to | |
3049 | * bump up refcount for sink because the link doesn't point | |
3050 | * to it anymore after disconnect, so on next crtc to connector | |
922aa1e1 AG |
3051 | * reshuffle by UMD we will get into unwanted dc_sink release |
3052 | */ | |
dcd5fb82 | 3053 | dc_sink_release(aconnector->dc_sink); |
922aa1e1 | 3054 | } |
4562236b | 3055 | aconnector->dc_sink = sink; |
dcd5fb82 | 3056 | dc_sink_retain(aconnector->dc_sink); |
98e6436d AK |
3057 | amdgpu_dm_update_freesync_caps(connector, |
3058 | aconnector->edid); | |
4562236b | 3059 | } else { |
98e6436d | 3060 | amdgpu_dm_update_freesync_caps(connector, NULL); |
dcd5fb82 | 3061 | if (!aconnector->dc_sink) { |
4562236b | 3062 | aconnector->dc_sink = aconnector->dc_em_sink; |
922aa1e1 | 3063 | dc_sink_retain(aconnector->dc_sink); |
dcd5fb82 | 3064 | } |
4562236b HW |
3065 | } |
3066 | ||
3067 | mutex_unlock(&dev->mode_config.mutex); | |
dcd5fb82 MF |
3068 | |
3069 | if (sink) | |
3070 | dc_sink_release(sink); | |
4562236b HW |
3071 | return; |
3072 | } | |
3073 | ||
3074 | /* | |
3075 | * TODO: temporary guard to look for proper fix | |
3076 | * if this sink is MST sink, we should not do anything | |
3077 | */ | |
dcd5fb82 MF |
3078 | if (sink && sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT_MST) { |
3079 | dc_sink_release(sink); | |
4562236b | 3080 | return; |
dcd5fb82 | 3081 | } |
4562236b HW |
3082 | |
3083 | if (aconnector->dc_sink == sink) { | |
1f6010a9 DF |
3084 | /* |
3085 | * We got a DP short pulse (Link Loss, DP CTS, etc...). | |
3086 | * Do nothing!! | |
3087 | */ | |
f1ad2f5e | 3088 | DRM_DEBUG_DRIVER("DCHPD: connector_id=%d: dc_sink didn't change.\n", |
4562236b | 3089 | aconnector->connector_id); |
dcd5fb82 MF |
3090 | if (sink) |
3091 | dc_sink_release(sink); | |
4562236b HW |
3092 | return; |
3093 | } | |
3094 | ||
f1ad2f5e | 3095 | DRM_DEBUG_DRIVER("DCHPD: connector_id=%d: Old sink=%p New sink=%p\n", |
4562236b HW |
3096 | aconnector->connector_id, aconnector->dc_sink, sink); |
3097 | ||
3098 | mutex_lock(&dev->mode_config.mutex); | |
3099 | ||
1f6010a9 DF |
3100 | /* |
3101 | * 1. Update status of the drm connector | |
3102 | * 2. Send an event and let userspace tell us what to do | |
3103 | */ | |
4562236b | 3104 | if (sink) { |
1f6010a9 DF |
3105 | /* |
3106 | * TODO: check if we still need the S3 mode update workaround. | |
3107 | * If yes, put it here. | |
3108 | */ | |
c64b0d6b | 3109 | if (aconnector->dc_sink) { |
98e6436d | 3110 | amdgpu_dm_update_freesync_caps(connector, NULL); |
c64b0d6b VL |
3111 | dc_sink_release(aconnector->dc_sink); |
3112 | } | |
4562236b HW |
3113 | |
3114 | aconnector->dc_sink = sink; | |
dcd5fb82 | 3115 | dc_sink_retain(aconnector->dc_sink); |
900b3cb1 | 3116 | if (sink->dc_edid.length == 0) { |
4562236b | 3117 | aconnector->edid = NULL; |
e6142dd5 AP |
3118 | if (aconnector->dc_link->aux_mode) { |
3119 | drm_dp_cec_unset_edid( | |
3120 | &aconnector->dm_dp_aux.aux); | |
3121 | } | |
900b3cb1 | 3122 | } else { |
4562236b | 3123 | aconnector->edid = |
e6142dd5 | 3124 | (struct edid *)sink->dc_edid.raw_edid; |
4562236b | 3125 | |
e6142dd5 AP |
3126 | if (aconnector->dc_link->aux_mode) |
3127 | drm_dp_cec_set_edid(&aconnector->dm_dp_aux.aux, | |
3128 | aconnector->edid); | |
4562236b | 3129 | } |
e6142dd5 | 3130 | |
028c4ccf QZ |
3131 | aconnector->timing_requested = kzalloc(sizeof(struct dc_crtc_timing), GFP_KERNEL); |
3132 | if (!aconnector->timing_requested) | |
3133 | dm_error("%s: failed to create aconnector->requested_timing\n", __func__); | |
3134 | ||
20543be9 | 3135 | drm_connector_update_edid_property(connector, aconnector->edid); |
98e6436d | 3136 | amdgpu_dm_update_freesync_caps(connector, aconnector->edid); |
94562810 | 3137 | update_connector_ext_caps(aconnector); |
4562236b | 3138 | } else { |
e86e8947 | 3139 | drm_dp_cec_unset_edid(&aconnector->dm_dp_aux.aux); |
98e6436d | 3140 | amdgpu_dm_update_freesync_caps(connector, NULL); |
c555f023 | 3141 | drm_connector_update_edid_property(connector, NULL); |
4562236b | 3142 | aconnector->num_modes = 0; |
dcd5fb82 | 3143 | dc_sink_release(aconnector->dc_sink); |
4562236b | 3144 | aconnector->dc_sink = NULL; |
5326c452 | 3145 | aconnector->edid = NULL; |
028c4ccf QZ |
3146 | kfree(aconnector->timing_requested); |
3147 | aconnector->timing_requested = NULL; | |
0c8620d6 BL |
3148 | /* Set CP to DESIRED if it was ENABLED, so we can re-enable it again on hotplug */ |
3149 | if (connector->state->content_protection == DRM_MODE_CONTENT_PROTECTION_ENABLED) | |
3150 | connector->state->content_protection = DRM_MODE_CONTENT_PROTECTION_DESIRED; | |
4562236b HW |
3151 | } |
3152 | ||
3153 | mutex_unlock(&dev->mode_config.mutex); | |
dcd5fb82 | 3154 | |
0f877894 OV |
3155 | update_subconnector_property(aconnector); |
3156 | ||
dcd5fb82 MF |
3157 | if (sink) |
3158 | dc_sink_release(sink); | |
4562236b HW |
3159 | } |
3160 | ||
e27c41d5 | 3161 | static void handle_hpd_irq_helper(struct amdgpu_dm_connector *aconnector) |
4562236b | 3162 | { |
4562236b HW |
3163 | struct drm_connector *connector = &aconnector->base; |
3164 | struct drm_device *dev = connector->dev; | |
fbbdadf2 | 3165 | enum dc_connection_type new_connection_type = dc_connection_none; |
1348969a | 3166 | struct amdgpu_device *adev = drm_to_adev(dev); |
97f6c917 | 3167 | struct dm_connector_state *dm_con_state = to_dm_connector_state(connector->state); |
15c735e7 | 3168 | bool ret = false; |
4562236b | 3169 | |
b972b4f9 HW |
3170 | if (adev->dm.disable_hpd_irq) |
3171 | return; | |
3172 | ||
1f6010a9 DF |
3173 | /* |
3174 | * In case of failure or MST no need to update connector status or notify the OS | |
3175 | * since (for MST case) MST does this in its own context. | |
4562236b HW |
3176 | */ |
3177 | mutex_lock(&aconnector->hpd_lock); | |
2e0ac3d6 | 3178 | |
97f6c917 | 3179 | if (adev->dm.hdcp_workqueue) { |
96a3b32e | 3180 | hdcp_reset_display(adev->dm.hdcp_workqueue, aconnector->dc_link->link_index); |
97f6c917 BL |
3181 | dm_con_state->update_hdcp = true; |
3182 | } | |
2e0ac3d6 HW |
3183 | if (aconnector->fake_enable) |
3184 | aconnector->fake_enable = false; | |
3185 | ||
028c4ccf QZ |
3186 | aconnector->timing_changed = false; |
3187 | ||
54618888 | 3188 | if (!dc_link_detect_connection_type(aconnector->dc_link, &new_connection_type)) |
fbbdadf2 BL |
3189 | DRM_ERROR("KMS: Failed to detect connector\n"); |
3190 | ||
3191 | if (aconnector->base.force && new_connection_type == dc_connection_none) { | |
3192 | emulated_link_detect(aconnector->dc_link); | |
3193 | ||
fbbdadf2 BL |
3194 | drm_modeset_lock_all(dev); |
3195 | dm_restore_drm_connector_state(dev, connector); | |
3196 | drm_modeset_unlock_all(dev); | |
3197 | ||
3198 | if (aconnector->base.force == DRM_FORCE_UNSPECIFIED) | |
fc320a6f | 3199 | drm_kms_helper_connector_hotplug_event(connector); |
15c735e7 WL |
3200 | } else { |
3201 | mutex_lock(&adev->dm.dc_lock); | |
3202 | ret = dc_link_detect(aconnector->dc_link, DETECT_REASON_HPD); | |
3203 | mutex_unlock(&adev->dm.dc_lock); | |
3204 | if (ret) { | |
3205 | amdgpu_dm_update_connector_after_detect(aconnector); | |
fbbdadf2 | 3206 | |
15c735e7 WL |
3207 | drm_modeset_lock_all(dev); |
3208 | dm_restore_drm_connector_state(dev, connector); | |
3209 | drm_modeset_unlock_all(dev); | |
4562236b | 3210 | |
15c735e7 WL |
3211 | if (aconnector->base.force == DRM_FORCE_UNSPECIFIED) |
3212 | drm_kms_helper_connector_hotplug_event(connector); | |
3213 | } | |
4562236b HW |
3214 | } |
3215 | mutex_unlock(&aconnector->hpd_lock); | |
3216 | ||
3217 | } | |
3218 | ||
e27c41d5 JS |
3219 | static void handle_hpd_irq(void *param) |
3220 | { | |
3221 | struct amdgpu_dm_connector *aconnector = (struct amdgpu_dm_connector *)param; | |
3222 | ||
3223 | handle_hpd_irq_helper(aconnector); | |
3224 | ||
3225 | } | |
3226 | ||
8e794421 | 3227 | static void dm_handle_mst_sideband_msg(struct amdgpu_dm_connector *aconnector) |
4562236b | 3228 | { |
ae67558b SS |
3229 | u8 esi[DP_PSR_ERROR_STATUS - DP_SINK_COUNT_ESI] = { 0 }; |
3230 | u8 dret; | |
4562236b HW |
3231 | bool new_irq_handled = false; |
3232 | int dpcd_addr; | |
3233 | int dpcd_bytes_to_read; | |
3234 | ||
3235 | const int max_process_count = 30; | |
3236 | int process_count = 0; | |
3237 | ||
3238 | const struct dc_link_status *link_status = dc_link_get_status(aconnector->dc_link); | |
3239 | ||
3240 | if (link_status->dpcd_caps->dpcd_rev.raw < 0x12) { | |
3241 | dpcd_bytes_to_read = DP_LANE0_1_STATUS - DP_SINK_COUNT; | |
3242 | /* DPCD 0x200 - 0x201 for downstream IRQ */ | |
3243 | dpcd_addr = DP_SINK_COUNT; | |
3244 | } else { | |
3245 | dpcd_bytes_to_read = DP_PSR_ERROR_STATUS - DP_SINK_COUNT_ESI; | |
3246 | /* DPCD 0x2002 - 0x2005 for downstream IRQ */ | |
3247 | dpcd_addr = DP_SINK_COUNT_ESI; | |
3248 | } | |
3249 | ||
3250 | dret = drm_dp_dpcd_read( | |
3251 | &aconnector->dm_dp_aux.aux, | |
3252 | dpcd_addr, | |
3253 | esi, | |
3254 | dpcd_bytes_to_read); | |
3255 | ||
3256 | while (dret == dpcd_bytes_to_read && | |
3257 | process_count < max_process_count) { | |
ae67558b | 3258 | u8 retry; |
4562236b HW |
3259 | dret = 0; |
3260 | ||
3261 | process_count++; | |
3262 | ||
f1ad2f5e | 3263 | DRM_DEBUG_DRIVER("ESI %02x %02x %02x\n", esi[0], esi[1], esi[2]); |
4562236b HW |
3264 | /* handle HPD short pulse irq */ |
3265 | if (aconnector->mst_mgr.mst_state) | |
3266 | drm_dp_mst_hpd_irq( | |
3267 | &aconnector->mst_mgr, | |
3268 | esi, | |
3269 | &new_irq_handled); | |
4562236b HW |
3270 | |
3271 | if (new_irq_handled) { | |
3272 | /* ACK at DPCD to notify down stream */ | |
3273 | const int ack_dpcd_bytes_to_write = | |
3274 | dpcd_bytes_to_read - 1; | |
3275 | ||
3276 | for (retry = 0; retry < 3; retry++) { | |
ae67558b | 3277 | u8 wret; |
4562236b HW |
3278 | |
3279 | wret = drm_dp_dpcd_write( | |
3280 | &aconnector->dm_dp_aux.aux, | |
3281 | dpcd_addr + 1, | |
3282 | &esi[1], | |
3283 | ack_dpcd_bytes_to_write); | |
3284 | if (wret == ack_dpcd_bytes_to_write) | |
3285 | break; | |
3286 | } | |
3287 | ||
1f6010a9 | 3288 | /* check if there is new irq to be handled */ |
4562236b HW |
3289 | dret = drm_dp_dpcd_read( |
3290 | &aconnector->dm_dp_aux.aux, | |
3291 | dpcd_addr, | |
3292 | esi, | |
3293 | dpcd_bytes_to_read); | |
3294 | ||
3295 | new_irq_handled = false; | |
d4a6e8a9 | 3296 | } else { |
4562236b | 3297 | break; |
d4a6e8a9 | 3298 | } |
4562236b HW |
3299 | } |
3300 | ||
3301 | if (process_count == max_process_count) | |
f1ad2f5e | 3302 | DRM_DEBUG_DRIVER("Loop exceeded max iterations\n"); |
4562236b HW |
3303 | } |
3304 | ||
8e794421 WL |
3305 | static void schedule_hpd_rx_offload_work(struct hpd_rx_irq_offload_work_queue *offload_wq, |
3306 | union hpd_irq_data hpd_irq_data) | |
3307 | { | |
3308 | struct hpd_rx_irq_offload_work *offload_work = | |
3309 | kzalloc(sizeof(*offload_work), GFP_KERNEL); | |
3310 | ||
3311 | if (!offload_work) { | |
3312 | DRM_ERROR("Failed to allocate hpd_rx_irq_offload_work.\n"); | |
3313 | return; | |
3314 | } | |
3315 | ||
3316 | INIT_WORK(&offload_work->work, dm_handle_hpd_rx_offload_work); | |
3317 | offload_work->data = hpd_irq_data; | |
3318 | offload_work->offload_wq = offload_wq; | |
3319 | ||
3320 | queue_work(offload_wq->wq, &offload_work->work); | |
3321 | DRM_DEBUG_KMS("queue work to handle hpd_rx offload work"); | |
3322 | } | |
3323 | ||
4562236b HW |
3324 | static void handle_hpd_rx_irq(void *param) |
3325 | { | |
c84dec2f | 3326 | struct amdgpu_dm_connector *aconnector = (struct amdgpu_dm_connector *)param; |
4562236b HW |
3327 | struct drm_connector *connector = &aconnector->base; |
3328 | struct drm_device *dev = connector->dev; | |
53cbf65c | 3329 | struct dc_link *dc_link = aconnector->dc_link; |
4562236b | 3330 | bool is_mst_root_connector = aconnector->mst_mgr.mst_state; |
c8ea79a8 | 3331 | bool result = false; |
fbbdadf2 | 3332 | enum dc_connection_type new_connection_type = dc_connection_none; |
c8ea79a8 | 3333 | struct amdgpu_device *adev = drm_to_adev(dev); |
2a0f9270 | 3334 | union hpd_irq_data hpd_irq_data; |
8e794421 WL |
3335 | bool link_loss = false; |
3336 | bool has_left_work = false; | |
e322843e | 3337 | int idx = dc_link->link_index; |
8e794421 | 3338 | struct hpd_rx_irq_offload_work_queue *offload_wq = &adev->dm.hpd_rx_offload_wq[idx]; |
2a0f9270 BL |
3339 | |
3340 | memset(&hpd_irq_data, 0, sizeof(hpd_irq_data)); | |
4562236b | 3341 | |
b972b4f9 HW |
3342 | if (adev->dm.disable_hpd_irq) |
3343 | return; | |
3344 | ||
1f6010a9 DF |
3345 | /* |
3346 | * TODO:Temporary add mutex to protect hpd interrupt not have a gpio | |
4562236b HW |
3347 | * conflict, after implement i2c helper, this mutex should be |
3348 | * retired. | |
3349 | */ | |
b86e7eef | 3350 | mutex_lock(&aconnector->hpd_lock); |
4562236b | 3351 | |
8e794421 WL |
3352 | result = dc_link_handle_hpd_rx_irq(dc_link, &hpd_irq_data, |
3353 | &link_loss, true, &has_left_work); | |
3083a984 | 3354 | |
8e794421 WL |
3355 | if (!has_left_work) |
3356 | goto out; | |
3357 | ||
3358 | if (hpd_irq_data.bytes.device_service_irq.bits.AUTOMATED_TEST) { | |
3359 | schedule_hpd_rx_offload_work(offload_wq, hpd_irq_data); | |
3360 | goto out; | |
3361 | } | |
3362 | ||
3363 | if (dc_link_dp_allow_hpd_rx_irq(dc_link)) { | |
3364 | if (hpd_irq_data.bytes.device_service_irq.bits.UP_REQ_MSG_RDY || | |
3365 | hpd_irq_data.bytes.device_service_irq.bits.DOWN_REP_MSG_RDY) { | |
3366 | dm_handle_mst_sideband_msg(aconnector); | |
3083a984 QZ |
3367 | goto out; |
3368 | } | |
3083a984 | 3369 | |
8e794421 WL |
3370 | if (link_loss) { |
3371 | bool skip = false; | |
d2aa1356 | 3372 | |
8e794421 WL |
3373 | spin_lock(&offload_wq->offload_lock); |
3374 | skip = offload_wq->is_handling_link_loss; | |
3375 | ||
3376 | if (!skip) | |
3377 | offload_wq->is_handling_link_loss = true; | |
3378 | ||
3379 | spin_unlock(&offload_wq->offload_lock); | |
3380 | ||
3381 | if (!skip) | |
3382 | schedule_hpd_rx_offload_work(offload_wq, hpd_irq_data); | |
3383 | ||
3384 | goto out; | |
3385 | } | |
3386 | } | |
c8ea79a8 | 3387 | |
3083a984 | 3388 | out: |
c8ea79a8 | 3389 | if (result && !is_mst_root_connector) { |
4562236b | 3390 | /* Downstream Port status changed. */ |
54618888 | 3391 | if (!dc_link_detect_connection_type(dc_link, &new_connection_type)) |
fbbdadf2 BL |
3392 | DRM_ERROR("KMS: Failed to detect connector\n"); |
3393 | ||
3394 | if (aconnector->base.force && new_connection_type == dc_connection_none) { | |
3395 | emulated_link_detect(dc_link); | |
3396 | ||
3397 | if (aconnector->fake_enable) | |
3398 | aconnector->fake_enable = false; | |
3399 | ||
3400 | amdgpu_dm_update_connector_after_detect(aconnector); | |
3401 | ||
3402 | ||
3403 | drm_modeset_lock_all(dev); | |
3404 | dm_restore_drm_connector_state(dev, connector); | |
3405 | drm_modeset_unlock_all(dev); | |
3406 | ||
fc320a6f | 3407 | drm_kms_helper_connector_hotplug_event(connector); |
15c735e7 WL |
3408 | } else { |
3409 | bool ret = false; | |
88ac3dda | 3410 | |
15c735e7 WL |
3411 | mutex_lock(&adev->dm.dc_lock); |
3412 | ret = dc_link_detect(dc_link, DETECT_REASON_HPDRX); | |
3413 | mutex_unlock(&adev->dm.dc_lock); | |
88ac3dda | 3414 | |
15c735e7 WL |
3415 | if (ret) { |
3416 | if (aconnector->fake_enable) | |
3417 | aconnector->fake_enable = false; | |
4562236b | 3418 | |
15c735e7 | 3419 | amdgpu_dm_update_connector_after_detect(aconnector); |
4562236b | 3420 | |
15c735e7 WL |
3421 | drm_modeset_lock_all(dev); |
3422 | dm_restore_drm_connector_state(dev, connector); | |
3423 | drm_modeset_unlock_all(dev); | |
4562236b | 3424 | |
15c735e7 WL |
3425 | drm_kms_helper_connector_hotplug_event(connector); |
3426 | } | |
4562236b HW |
3427 | } |
3428 | } | |
95f247e7 DC |
3429 | if (hpd_irq_data.bytes.device_service_irq.bits.CP_IRQ) { |
3430 | if (adev->dm.hdcp_workqueue) | |
3431 | hdcp_handle_cpirq(adev->dm.hdcp_workqueue, aconnector->base.index); | |
3432 | } | |
4562236b | 3433 | |
b86e7eef | 3434 | if (dc_link->type != dc_connection_mst_branch) |
e86e8947 | 3435 | drm_dp_cec_irq(&aconnector->dm_dp_aux.aux); |
b86e7eef NC |
3436 | |
3437 | mutex_unlock(&aconnector->hpd_lock); | |
4562236b HW |
3438 | } |
3439 | ||
3440 | static void register_hpd_handlers(struct amdgpu_device *adev) | |
3441 | { | |
4a580877 | 3442 | struct drm_device *dev = adev_to_drm(adev); |
4562236b | 3443 | struct drm_connector *connector; |
c84dec2f | 3444 | struct amdgpu_dm_connector *aconnector; |
4562236b HW |
3445 | const struct dc_link *dc_link; |
3446 | struct dc_interrupt_params int_params = {0}; | |
3447 | ||
3448 | int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT; | |
3449 | int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT; | |
3450 | ||
3451 | list_for_each_entry(connector, | |
3452 | &dev->mode_config.connector_list, head) { | |
3453 | ||
c84dec2f | 3454 | aconnector = to_amdgpu_dm_connector(connector); |
4562236b HW |
3455 | dc_link = aconnector->dc_link; |
3456 | ||
3457 | if (DC_IRQ_SOURCE_INVALID != dc_link->irq_source_hpd) { | |
3458 | int_params.int_context = INTERRUPT_LOW_IRQ_CONTEXT; | |
3459 | int_params.irq_source = dc_link->irq_source_hpd; | |
3460 | ||
3461 | amdgpu_dm_irq_register_interrupt(adev, &int_params, | |
3462 | handle_hpd_irq, | |
3463 | (void *) aconnector); | |
3464 | } | |
3465 | ||
3466 | if (DC_IRQ_SOURCE_INVALID != dc_link->irq_source_hpd_rx) { | |
3467 | ||
3468 | /* Also register for DP short pulse (hpd_rx). */ | |
3469 | int_params.int_context = INTERRUPT_LOW_IRQ_CONTEXT; | |
3470 | int_params.irq_source = dc_link->irq_source_hpd_rx; | |
3471 | ||
3472 | amdgpu_dm_irq_register_interrupt(adev, &int_params, | |
3473 | handle_hpd_rx_irq, | |
3474 | (void *) aconnector); | |
8e794421 WL |
3475 | |
3476 | if (adev->dm.hpd_rx_offload_wq) | |
e322843e | 3477 | adev->dm.hpd_rx_offload_wq[dc_link->link_index].aconnector = |
8e794421 | 3478 | aconnector; |
4562236b HW |
3479 | } |
3480 | } | |
3481 | } | |
3482 | ||
55e56389 MR |
3483 | #if defined(CONFIG_DRM_AMD_DC_SI) |
3484 | /* Register IRQ sources and initialize IRQ callbacks */ | |
3485 | static int dce60_register_irq_handlers(struct amdgpu_device *adev) | |
3486 | { | |
3487 | struct dc *dc = adev->dm.dc; | |
3488 | struct common_irq_params *c_irq_params; | |
3489 | struct dc_interrupt_params int_params = {0}; | |
3490 | int r; | |
3491 | int i; | |
3492 | unsigned client_id = AMDGPU_IRQ_CLIENTID_LEGACY; | |
3493 | ||
3494 | int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT; | |
3495 | int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT; | |
3496 | ||
3497 | /* | |
3498 | * Actions of amdgpu_irq_add_id(): | |
3499 | * 1. Register a set() function with base driver. | |
3500 | * Base driver will call set() function to enable/disable an | |
3501 | * interrupt in DC hardware. | |
3502 | * 2. Register amdgpu_dm_irq_handler(). | |
3503 | * Base driver will call amdgpu_dm_irq_handler() for ALL interrupts | |
3504 | * coming from DC hardware. | |
3505 | * amdgpu_dm_irq_handler() will re-direct the interrupt to DC | |
3506 | * for acknowledging and handling. */ | |
3507 | ||
3508 | /* Use VBLANK interrupt */ | |
3509 | for (i = 0; i < adev->mode_info.num_crtc; i++) { | |
3510 | r = amdgpu_irq_add_id(adev, client_id, i+1 , &adev->crtc_irq); | |
3511 | if (r) { | |
3512 | DRM_ERROR("Failed to add crtc irq id!\n"); | |
3513 | return r; | |
3514 | } | |
3515 | ||
3516 | int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT; | |
3517 | int_params.irq_source = | |
3518 | dc_interrupt_to_irq_source(dc, i+1 , 0); | |
3519 | ||
3520 | c_irq_params = &adev->dm.vblank_params[int_params.irq_source - DC_IRQ_SOURCE_VBLANK1]; | |
3521 | ||
3522 | c_irq_params->adev = adev; | |
3523 | c_irq_params->irq_src = int_params.irq_source; | |
3524 | ||
3525 | amdgpu_dm_irq_register_interrupt(adev, &int_params, | |
3526 | dm_crtc_high_irq, c_irq_params); | |
3527 | } | |
3528 | ||
3529 | /* Use GRPH_PFLIP interrupt */ | |
3530 | for (i = VISLANDS30_IV_SRCID_D1_GRPH_PFLIP; | |
3531 | i <= VISLANDS30_IV_SRCID_D6_GRPH_PFLIP; i += 2) { | |
3532 | r = amdgpu_irq_add_id(adev, client_id, i, &adev->pageflip_irq); | |
3533 | if (r) { | |
3534 | DRM_ERROR("Failed to add page flip irq id!\n"); | |
3535 | return r; | |
3536 | } | |
3537 | ||
3538 | int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT; | |
3539 | int_params.irq_source = | |
3540 | dc_interrupt_to_irq_source(dc, i, 0); | |
3541 | ||
3542 | c_irq_params = &adev->dm.pflip_params[int_params.irq_source - DC_IRQ_SOURCE_PFLIP_FIRST]; | |
3543 | ||
3544 | c_irq_params->adev = adev; | |
3545 | c_irq_params->irq_src = int_params.irq_source; | |
3546 | ||
3547 | amdgpu_dm_irq_register_interrupt(adev, &int_params, | |
3548 | dm_pflip_high_irq, c_irq_params); | |
3549 | ||
3550 | } | |
3551 | ||
3552 | /* HPD */ | |
3553 | r = amdgpu_irq_add_id(adev, client_id, | |
3554 | VISLANDS30_IV_SRCID_HOTPLUG_DETECT_A, &adev->hpd_irq); | |
3555 | if (r) { | |
3556 | DRM_ERROR("Failed to add hpd irq id!\n"); | |
3557 | return r; | |
3558 | } | |
3559 | ||
3560 | register_hpd_handlers(adev); | |
3561 | ||
3562 | return 0; | |
3563 | } | |
3564 | #endif | |
3565 | ||
4562236b HW |
3566 | /* Register IRQ sources and initialize IRQ callbacks */ |
3567 | static int dce110_register_irq_handlers(struct amdgpu_device *adev) | |
3568 | { | |
3569 | struct dc *dc = adev->dm.dc; | |
3570 | struct common_irq_params *c_irq_params; | |
3571 | struct dc_interrupt_params int_params = {0}; | |
3572 | int r; | |
3573 | int i; | |
1ffdeca6 | 3574 | unsigned client_id = AMDGPU_IRQ_CLIENTID_LEGACY; |
2c8ad2d5 | 3575 | |
c08182f2 | 3576 | if (adev->family >= AMDGPU_FAMILY_AI) |
3760f76c | 3577 | client_id = SOC15_IH_CLIENTID_DCE; |
4562236b HW |
3578 | |
3579 | int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT; | |
3580 | int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT; | |
3581 | ||
1f6010a9 DF |
3582 | /* |
3583 | * Actions of amdgpu_irq_add_id(): | |
4562236b HW |
3584 | * 1. Register a set() function with base driver. |
3585 | * Base driver will call set() function to enable/disable an | |
3586 | * interrupt in DC hardware. | |
3587 | * 2. Register amdgpu_dm_irq_handler(). | |
3588 | * Base driver will call amdgpu_dm_irq_handler() for ALL interrupts | |
3589 | * coming from DC hardware. | |
3590 | * amdgpu_dm_irq_handler() will re-direct the interrupt to DC | |
3591 | * for acknowledging and handling. */ | |
3592 | ||
b57de80a | 3593 | /* Use VBLANK interrupt */ |
e9029155 | 3594 | for (i = VISLANDS30_IV_SRCID_D1_VERTICAL_INTERRUPT0; i <= VISLANDS30_IV_SRCID_D6_VERTICAL_INTERRUPT0; i++) { |
2c8ad2d5 | 3595 | r = amdgpu_irq_add_id(adev, client_id, i, &adev->crtc_irq); |
4562236b HW |
3596 | if (r) { |
3597 | DRM_ERROR("Failed to add crtc irq id!\n"); | |
3598 | return r; | |
3599 | } | |
3600 | ||
3601 | int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT; | |
3602 | int_params.irq_source = | |
3d761e79 | 3603 | dc_interrupt_to_irq_source(dc, i, 0); |
4562236b | 3604 | |
b57de80a | 3605 | c_irq_params = &adev->dm.vblank_params[int_params.irq_source - DC_IRQ_SOURCE_VBLANK1]; |
4562236b HW |
3606 | |
3607 | c_irq_params->adev = adev; | |
3608 | c_irq_params->irq_src = int_params.irq_source; | |
3609 | ||
3610 | amdgpu_dm_irq_register_interrupt(adev, &int_params, | |
3611 | dm_crtc_high_irq, c_irq_params); | |
3612 | } | |
3613 | ||
d2574c33 MK |
3614 | /* Use VUPDATE interrupt */ |
3615 | for (i = VISLANDS30_IV_SRCID_D1_V_UPDATE_INT; i <= VISLANDS30_IV_SRCID_D6_V_UPDATE_INT; i += 2) { | |
3616 | r = amdgpu_irq_add_id(adev, client_id, i, &adev->vupdate_irq); | |
3617 | if (r) { | |
3618 | DRM_ERROR("Failed to add vupdate irq id!\n"); | |
3619 | return r; | |
3620 | } | |
3621 | ||
3622 | int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT; | |
3623 | int_params.irq_source = | |
3624 | dc_interrupt_to_irq_source(dc, i, 0); | |
3625 | ||
3626 | c_irq_params = &adev->dm.vupdate_params[int_params.irq_source - DC_IRQ_SOURCE_VUPDATE1]; | |
3627 | ||
3628 | c_irq_params->adev = adev; | |
3629 | c_irq_params->irq_src = int_params.irq_source; | |
3630 | ||
3631 | amdgpu_dm_irq_register_interrupt(adev, &int_params, | |
3632 | dm_vupdate_high_irq, c_irq_params); | |
3633 | } | |
3634 | ||
3d761e79 | 3635 | /* Use GRPH_PFLIP interrupt */ |
4562236b HW |
3636 | for (i = VISLANDS30_IV_SRCID_D1_GRPH_PFLIP; |
3637 | i <= VISLANDS30_IV_SRCID_D6_GRPH_PFLIP; i += 2) { | |
2c8ad2d5 | 3638 | r = amdgpu_irq_add_id(adev, client_id, i, &adev->pageflip_irq); |
4562236b HW |
3639 | if (r) { |
3640 | DRM_ERROR("Failed to add page flip irq id!\n"); | |
3641 | return r; | |
3642 | } | |
3643 | ||
3644 | int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT; | |
3645 | int_params.irq_source = | |
3646 | dc_interrupt_to_irq_source(dc, i, 0); | |
3647 | ||
3648 | c_irq_params = &adev->dm.pflip_params[int_params.irq_source - DC_IRQ_SOURCE_PFLIP_FIRST]; | |
3649 | ||
3650 | c_irq_params->adev = adev; | |
3651 | c_irq_params->irq_src = int_params.irq_source; | |
3652 | ||
3653 | amdgpu_dm_irq_register_interrupt(adev, &int_params, | |
3654 | dm_pflip_high_irq, c_irq_params); | |
3655 | ||
3656 | } | |
3657 | ||
3658 | /* HPD */ | |
2c8ad2d5 AD |
3659 | r = amdgpu_irq_add_id(adev, client_id, |
3660 | VISLANDS30_IV_SRCID_HOTPLUG_DETECT_A, &adev->hpd_irq); | |
4562236b HW |
3661 | if (r) { |
3662 | DRM_ERROR("Failed to add hpd irq id!\n"); | |
3663 | return r; | |
3664 | } | |
3665 | ||
3666 | register_hpd_handlers(adev); | |
3667 | ||
3668 | return 0; | |
3669 | } | |
3670 | ||
ff5ef992 AD |
3671 | /* Register IRQ sources and initialize IRQ callbacks */ |
3672 | static int dcn10_register_irq_handlers(struct amdgpu_device *adev) | |
3673 | { | |
3674 | struct dc *dc = adev->dm.dc; | |
3675 | struct common_irq_params *c_irq_params; | |
3676 | struct dc_interrupt_params int_params = {0}; | |
3677 | int r; | |
3678 | int i; | |
660d5406 WL |
3679 | #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY) |
3680 | static const unsigned int vrtl_int_srcid[] = { | |
3681 | DCN_1_0__SRCID__OTG1_VERTICAL_INTERRUPT0_CONTROL, | |
3682 | DCN_1_0__SRCID__OTG2_VERTICAL_INTERRUPT0_CONTROL, | |
3683 | DCN_1_0__SRCID__OTG3_VERTICAL_INTERRUPT0_CONTROL, | |
3684 | DCN_1_0__SRCID__OTG4_VERTICAL_INTERRUPT0_CONTROL, | |
3685 | DCN_1_0__SRCID__OTG5_VERTICAL_INTERRUPT0_CONTROL, | |
3686 | DCN_1_0__SRCID__OTG6_VERTICAL_INTERRUPT0_CONTROL | |
3687 | }; | |
3688 | #endif | |
ff5ef992 AD |
3689 | |
3690 | int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT; | |
3691 | int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT; | |
3692 | ||
1f6010a9 DF |
3693 | /* |
3694 | * Actions of amdgpu_irq_add_id(): | |
ff5ef992 AD |
3695 | * 1. Register a set() function with base driver. |
3696 | * Base driver will call set() function to enable/disable an | |
3697 | * interrupt in DC hardware. | |
3698 | * 2. Register amdgpu_dm_irq_handler(). | |
3699 | * Base driver will call amdgpu_dm_irq_handler() for ALL interrupts | |
3700 | * coming from DC hardware. | |
3701 | * amdgpu_dm_irq_handler() will re-direct the interrupt to DC | |
3702 | * for acknowledging and handling. | |
1f6010a9 | 3703 | */ |
ff5ef992 AD |
3704 | |
3705 | /* Use VSTARTUP interrupt */ | |
3706 | for (i = DCN_1_0__SRCID__DC_D1_OTG_VSTARTUP; | |
3707 | i <= DCN_1_0__SRCID__DC_D1_OTG_VSTARTUP + adev->mode_info.num_crtc - 1; | |
3708 | i++) { | |
3760f76c | 3709 | r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, i, &adev->crtc_irq); |
ff5ef992 AD |
3710 | |
3711 | if (r) { | |
3712 | DRM_ERROR("Failed to add crtc irq id!\n"); | |
3713 | return r; | |
3714 | } | |
3715 | ||
3716 | int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT; | |
3717 | int_params.irq_source = | |
3718 | dc_interrupt_to_irq_source(dc, i, 0); | |
3719 | ||
3720 | c_irq_params = &adev->dm.vblank_params[int_params.irq_source - DC_IRQ_SOURCE_VBLANK1]; | |
3721 | ||
3722 | c_irq_params->adev = adev; | |
3723 | c_irq_params->irq_src = int_params.irq_source; | |
3724 | ||
2346ef47 NK |
3725 | amdgpu_dm_irq_register_interrupt( |
3726 | adev, &int_params, dm_crtc_high_irq, c_irq_params); | |
3727 | } | |
3728 | ||
86bc2219 WL |
3729 | /* Use otg vertical line interrupt */ |
3730 | #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY) | |
660d5406 WL |
3731 | for (i = 0; i <= adev->mode_info.num_crtc - 1; i++) { |
3732 | r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, | |
3733 | vrtl_int_srcid[i], &adev->vline0_irq); | |
86bc2219 WL |
3734 | |
3735 | if (r) { | |
3736 | DRM_ERROR("Failed to add vline0 irq id!\n"); | |
3737 | return r; | |
3738 | } | |
3739 | ||
3740 | int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT; | |
3741 | int_params.irq_source = | |
660d5406 WL |
3742 | dc_interrupt_to_irq_source(dc, vrtl_int_srcid[i], 0); |
3743 | ||
3744 | if (int_params.irq_source == DC_IRQ_SOURCE_INVALID) { | |
3745 | DRM_ERROR("Failed to register vline0 irq %d!\n", vrtl_int_srcid[i]); | |
3746 | break; | |
3747 | } | |
86bc2219 WL |
3748 | |
3749 | c_irq_params = &adev->dm.vline0_params[int_params.irq_source | |
3750 | - DC_IRQ_SOURCE_DC1_VLINE0]; | |
3751 | ||
3752 | c_irq_params->adev = adev; | |
3753 | c_irq_params->irq_src = int_params.irq_source; | |
3754 | ||
3755 | amdgpu_dm_irq_register_interrupt(adev, &int_params, | |
3756 | dm_dcn_vertical_interrupt0_high_irq, c_irq_params); | |
3757 | } | |
3758 | #endif | |
3759 | ||
2346ef47 NK |
3760 | /* Use VUPDATE_NO_LOCK interrupt on DCN, which seems to correspond to |
3761 | * the regular VUPDATE interrupt on DCE. We want DC_IRQ_SOURCE_VUPDATEx | |
3762 | * to trigger at end of each vblank, regardless of state of the lock, | |
3763 | * matching DCE behaviour. | |
3764 | */ | |
3765 | for (i = DCN_1_0__SRCID__OTG0_IHC_V_UPDATE_NO_LOCK_INTERRUPT; | |
3766 | i <= DCN_1_0__SRCID__OTG0_IHC_V_UPDATE_NO_LOCK_INTERRUPT + adev->mode_info.num_crtc - 1; | |
3767 | i++) { | |
3768 | r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, i, &adev->vupdate_irq); | |
3769 | ||
3770 | if (r) { | |
3771 | DRM_ERROR("Failed to add vupdate irq id!\n"); | |
3772 | return r; | |
3773 | } | |
3774 | ||
3775 | int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT; | |
3776 | int_params.irq_source = | |
3777 | dc_interrupt_to_irq_source(dc, i, 0); | |
3778 | ||
3779 | c_irq_params = &adev->dm.vupdate_params[int_params.irq_source - DC_IRQ_SOURCE_VUPDATE1]; | |
3780 | ||
3781 | c_irq_params->adev = adev; | |
3782 | c_irq_params->irq_src = int_params.irq_source; | |
3783 | ||
ff5ef992 | 3784 | amdgpu_dm_irq_register_interrupt(adev, &int_params, |
2346ef47 | 3785 | dm_vupdate_high_irq, c_irq_params); |
d2574c33 MK |
3786 | } |
3787 | ||
ff5ef992 AD |
3788 | /* Use GRPH_PFLIP interrupt */ |
3789 | for (i = DCN_1_0__SRCID__HUBP0_FLIP_INTERRUPT; | |
de95753c | 3790 | i <= DCN_1_0__SRCID__HUBP0_FLIP_INTERRUPT + dc->caps.max_otg_num - 1; |
ff5ef992 | 3791 | i++) { |
3760f76c | 3792 | r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, i, &adev->pageflip_irq); |
ff5ef992 AD |
3793 | if (r) { |
3794 | DRM_ERROR("Failed to add page flip irq id!\n"); | |
3795 | return r; | |
3796 | } | |
3797 | ||
3798 | int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT; | |
3799 | int_params.irq_source = | |
3800 | dc_interrupt_to_irq_source(dc, i, 0); | |
3801 | ||
3802 | c_irq_params = &adev->dm.pflip_params[int_params.irq_source - DC_IRQ_SOURCE_PFLIP_FIRST]; | |
3803 | ||
3804 | c_irq_params->adev = adev; | |
3805 | c_irq_params->irq_src = int_params.irq_source; | |
3806 | ||
3807 | amdgpu_dm_irq_register_interrupt(adev, &int_params, | |
3808 | dm_pflip_high_irq, c_irq_params); | |
3809 | ||
3810 | } | |
3811 | ||
81927e28 JS |
3812 | /* HPD */ |
3813 | r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, DCN_1_0__SRCID__DC_HPD1_INT, | |
3814 | &adev->hpd_irq); | |
3815 | if (r) { | |
3816 | DRM_ERROR("Failed to add hpd irq id!\n"); | |
3817 | return r; | |
3818 | } | |
a08f16cf | 3819 | |
81927e28 | 3820 | register_hpd_handlers(adev); |
a08f16cf | 3821 | |
81927e28 JS |
3822 | return 0; |
3823 | } | |
3824 | /* Register Outbox IRQ sources and initialize IRQ callbacks */ | |
3825 | static int register_outbox_irq_handlers(struct amdgpu_device *adev) | |
3826 | { | |
3827 | struct dc *dc = adev->dm.dc; | |
3828 | struct common_irq_params *c_irq_params; | |
3829 | struct dc_interrupt_params int_params = {0}; | |
3830 | int r, i; | |
3831 | ||
3832 | int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT; | |
3833 | int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT; | |
3834 | ||
3835 | r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, DCN_1_0__SRCID__DMCUB_OUTBOX_LOW_PRIORITY_READY_INT, | |
3836 | &adev->dmub_outbox_irq); | |
3837 | if (r) { | |
3838 | DRM_ERROR("Failed to add outbox irq id!\n"); | |
3839 | return r; | |
3840 | } | |
3841 | ||
3842 | if (dc->ctx->dmub_srv) { | |
3843 | i = DCN_1_0__SRCID__DMCUB_OUTBOX_LOW_PRIORITY_READY_INT; | |
3844 | int_params.int_context = INTERRUPT_LOW_IRQ_CONTEXT; | |
a08f16cf | 3845 | int_params.irq_source = |
81927e28 | 3846 | dc_interrupt_to_irq_source(dc, i, 0); |
a08f16cf | 3847 | |
81927e28 | 3848 | c_irq_params = &adev->dm.dmub_outbox_params[0]; |
a08f16cf LHM |
3849 | |
3850 | c_irq_params->adev = adev; | |
3851 | c_irq_params->irq_src = int_params.irq_source; | |
3852 | ||
3853 | amdgpu_dm_irq_register_interrupt(adev, &int_params, | |
81927e28 | 3854 | dm_dmub_outbox1_low_irq, c_irq_params); |
ff5ef992 AD |
3855 | } |
3856 | ||
ff5ef992 AD |
3857 | return 0; |
3858 | } | |
ff5ef992 | 3859 | |
eb3dc897 NK |
3860 | /* |
3861 | * Acquires the lock for the atomic state object and returns | |
3862 | * the new atomic state. | |
3863 | * | |
3864 | * This should only be called during atomic check. | |
3865 | */ | |
17ce8a69 RL |
3866 | int dm_atomic_get_state(struct drm_atomic_state *state, |
3867 | struct dm_atomic_state **dm_state) | |
eb3dc897 NK |
3868 | { |
3869 | struct drm_device *dev = state->dev; | |
1348969a | 3870 | struct amdgpu_device *adev = drm_to_adev(dev); |
eb3dc897 NK |
3871 | struct amdgpu_display_manager *dm = &adev->dm; |
3872 | struct drm_private_state *priv_state; | |
eb3dc897 NK |
3873 | |
3874 | if (*dm_state) | |
3875 | return 0; | |
3876 | ||
eb3dc897 NK |
3877 | priv_state = drm_atomic_get_private_obj_state(state, &dm->atomic_obj); |
3878 | if (IS_ERR(priv_state)) | |
3879 | return PTR_ERR(priv_state); | |
3880 | ||
3881 | *dm_state = to_dm_atomic_state(priv_state); | |
3882 | ||
3883 | return 0; | |
3884 | } | |
3885 | ||
dfd84d90 | 3886 | static struct dm_atomic_state * |
eb3dc897 NK |
3887 | dm_atomic_get_new_state(struct drm_atomic_state *state) |
3888 | { | |
3889 | struct drm_device *dev = state->dev; | |
1348969a | 3890 | struct amdgpu_device *adev = drm_to_adev(dev); |
eb3dc897 NK |
3891 | struct amdgpu_display_manager *dm = &adev->dm; |
3892 | struct drm_private_obj *obj; | |
3893 | struct drm_private_state *new_obj_state; | |
3894 | int i; | |
3895 | ||
3896 | for_each_new_private_obj_in_state(state, obj, new_obj_state, i) { | |
3897 | if (obj->funcs == dm->atomic_obj.funcs) | |
3898 | return to_dm_atomic_state(new_obj_state); | |
3899 | } | |
3900 | ||
3901 | return NULL; | |
3902 | } | |
3903 | ||
eb3dc897 NK |
3904 | static struct drm_private_state * |
3905 | dm_atomic_duplicate_state(struct drm_private_obj *obj) | |
3906 | { | |
3907 | struct dm_atomic_state *old_state, *new_state; | |
3908 | ||
3909 | new_state = kzalloc(sizeof(*new_state), GFP_KERNEL); | |
3910 | if (!new_state) | |
3911 | return NULL; | |
3912 | ||
3913 | __drm_atomic_helper_private_obj_duplicate_state(obj, &new_state->base); | |
3914 | ||
813d20dc AW |
3915 | old_state = to_dm_atomic_state(obj->state); |
3916 | ||
3917 | if (old_state && old_state->context) | |
3918 | new_state->context = dc_copy_state(old_state->context); | |
3919 | ||
eb3dc897 NK |
3920 | if (!new_state->context) { |
3921 | kfree(new_state); | |
3922 | return NULL; | |
3923 | } | |
3924 | ||
eb3dc897 NK |
3925 | return &new_state->base; |
3926 | } | |
3927 | ||
3928 | static void dm_atomic_destroy_state(struct drm_private_obj *obj, | |
3929 | struct drm_private_state *state) | |
3930 | { | |
3931 | struct dm_atomic_state *dm_state = to_dm_atomic_state(state); | |
3932 | ||
3933 | if (dm_state && dm_state->context) | |
3934 | dc_release_state(dm_state->context); | |
3935 | ||
3936 | kfree(dm_state); | |
3937 | } | |
3938 | ||
3939 | static struct drm_private_state_funcs dm_atomic_state_funcs = { | |
3940 | .atomic_duplicate_state = dm_atomic_duplicate_state, | |
3941 | .atomic_destroy_state = dm_atomic_destroy_state, | |
3942 | }; | |
3943 | ||
4562236b HW |
3944 | static int amdgpu_dm_mode_config_init(struct amdgpu_device *adev) |
3945 | { | |
eb3dc897 | 3946 | struct dm_atomic_state *state; |
4562236b HW |
3947 | int r; |
3948 | ||
3949 | adev->mode_info.mode_config_initialized = true; | |
3950 | ||
4a580877 LT |
3951 | adev_to_drm(adev)->mode_config.funcs = (void *)&amdgpu_dm_mode_funcs; |
3952 | adev_to_drm(adev)->mode_config.helper_private = &amdgpu_dm_mode_config_helperfuncs; | |
4562236b | 3953 | |
4a580877 LT |
3954 | adev_to_drm(adev)->mode_config.max_width = 16384; |
3955 | adev_to_drm(adev)->mode_config.max_height = 16384; | |
4562236b | 3956 | |
4a580877 | 3957 | adev_to_drm(adev)->mode_config.preferred_depth = 24; |
a6250bdb AD |
3958 | if (adev->asic_type == CHIP_HAWAII) |
3959 | /* disable prefer shadow for now due to hibernation issues */ | |
3960 | adev_to_drm(adev)->mode_config.prefer_shadow = 0; | |
3961 | else | |
3962 | adev_to_drm(adev)->mode_config.prefer_shadow = 1; | |
1f6010a9 | 3963 | /* indicates support for immediate flip */ |
4a580877 | 3964 | adev_to_drm(adev)->mode_config.async_page_flip = true; |
4562236b | 3965 | |
eb3dc897 NK |
3966 | state = kzalloc(sizeof(*state), GFP_KERNEL); |
3967 | if (!state) | |
3968 | return -ENOMEM; | |
3969 | ||
813d20dc | 3970 | state->context = dc_create_state(adev->dm.dc); |
eb3dc897 NK |
3971 | if (!state->context) { |
3972 | kfree(state); | |
3973 | return -ENOMEM; | |
3974 | } | |
3975 | ||
3976 | dc_resource_state_copy_construct_current(adev->dm.dc, state->context); | |
3977 | ||
4a580877 | 3978 | drm_atomic_private_obj_init(adev_to_drm(adev), |
8c1a765b | 3979 | &adev->dm.atomic_obj, |
eb3dc897 NK |
3980 | &state->base, |
3981 | &dm_atomic_state_funcs); | |
3982 | ||
3dc9b1ce | 3983 | r = amdgpu_display_modeset_create_props(adev); |
b67a468a DL |
3984 | if (r) { |
3985 | dc_release_state(state->context); | |
3986 | kfree(state); | |
4562236b | 3987 | return r; |
b67a468a | 3988 | } |
4562236b | 3989 | |
6ce8f316 | 3990 | r = amdgpu_dm_audio_init(adev); |
b67a468a DL |
3991 | if (r) { |
3992 | dc_release_state(state->context); | |
3993 | kfree(state); | |
6ce8f316 | 3994 | return r; |
b67a468a | 3995 | } |
6ce8f316 | 3996 | |
4562236b HW |
3997 | return 0; |
3998 | } | |
3999 | ||
206bbafe DF |
4000 | #define AMDGPU_DM_DEFAULT_MIN_BACKLIGHT 12 |
4001 | #define AMDGPU_DM_DEFAULT_MAX_BACKLIGHT 255 | |
94562810 | 4002 | #define AUX_BL_DEFAULT_TRANSITION_TIME_MS 50 |
206bbafe | 4003 | |
7fd13bae AD |
4004 | static void amdgpu_dm_update_backlight_caps(struct amdgpu_display_manager *dm, |
4005 | int bl_idx) | |
206bbafe DF |
4006 | { |
4007 | #if defined(CONFIG_ACPI) | |
4008 | struct amdgpu_dm_backlight_caps caps; | |
4009 | ||
58965855 FS |
4010 | memset(&caps, 0, sizeof(caps)); |
4011 | ||
7fd13bae | 4012 | if (dm->backlight_caps[bl_idx].caps_valid) |
206bbafe DF |
4013 | return; |
4014 | ||
f9b7f370 | 4015 | amdgpu_acpi_get_backlight_caps(&caps); |
206bbafe | 4016 | if (caps.caps_valid) { |
7fd13bae | 4017 | dm->backlight_caps[bl_idx].caps_valid = true; |
94562810 RS |
4018 | if (caps.aux_support) |
4019 | return; | |
7fd13bae AD |
4020 | dm->backlight_caps[bl_idx].min_input_signal = caps.min_input_signal; |
4021 | dm->backlight_caps[bl_idx].max_input_signal = caps.max_input_signal; | |
206bbafe | 4022 | } else { |
7fd13bae | 4023 | dm->backlight_caps[bl_idx].min_input_signal = |
206bbafe | 4024 | AMDGPU_DM_DEFAULT_MIN_BACKLIGHT; |
7fd13bae | 4025 | dm->backlight_caps[bl_idx].max_input_signal = |
206bbafe DF |
4026 | AMDGPU_DM_DEFAULT_MAX_BACKLIGHT; |
4027 | } | |
4028 | #else | |
7fd13bae | 4029 | if (dm->backlight_caps[bl_idx].aux_support) |
94562810 RS |
4030 | return; |
4031 | ||
7fd13bae AD |
4032 | dm->backlight_caps[bl_idx].min_input_signal = AMDGPU_DM_DEFAULT_MIN_BACKLIGHT; |
4033 | dm->backlight_caps[bl_idx].max_input_signal = AMDGPU_DM_DEFAULT_MAX_BACKLIGHT; | |
206bbafe DF |
4034 | #endif |
4035 | } | |
4036 | ||
69d9f427 AM |
4037 | static int get_brightness_range(const struct amdgpu_dm_backlight_caps *caps, |
4038 | unsigned *min, unsigned *max) | |
94562810 | 4039 | { |
94562810 | 4040 | if (!caps) |
69d9f427 | 4041 | return 0; |
94562810 | 4042 | |
69d9f427 AM |
4043 | if (caps->aux_support) { |
4044 | // Firmware limits are in nits, DC API wants millinits. | |
4045 | *max = 1000 * caps->aux_max_input_signal; | |
4046 | *min = 1000 * caps->aux_min_input_signal; | |
94562810 | 4047 | } else { |
69d9f427 AM |
4048 | // Firmware limits are 8-bit, PWM control is 16-bit. |
4049 | *max = 0x101 * caps->max_input_signal; | |
4050 | *min = 0x101 * caps->min_input_signal; | |
94562810 | 4051 | } |
69d9f427 AM |
4052 | return 1; |
4053 | } | |
94562810 | 4054 | |
69d9f427 AM |
4055 | static u32 convert_brightness_from_user(const struct amdgpu_dm_backlight_caps *caps, |
4056 | uint32_t brightness) | |
4057 | { | |
4058 | unsigned min, max; | |
94562810 | 4059 | |
69d9f427 AM |
4060 | if (!get_brightness_range(caps, &min, &max)) |
4061 | return brightness; | |
4062 | ||
4063 | // Rescale 0..255 to min..max | |
4064 | return min + DIV_ROUND_CLOSEST((max - min) * brightness, | |
4065 | AMDGPU_MAX_BL_LEVEL); | |
4066 | } | |
4067 | ||
4068 | static u32 convert_brightness_to_user(const struct amdgpu_dm_backlight_caps *caps, | |
4069 | uint32_t brightness) | |
4070 | { | |
4071 | unsigned min, max; | |
4072 | ||
4073 | if (!get_brightness_range(caps, &min, &max)) | |
4074 | return brightness; | |
4075 | ||
4076 | if (brightness < min) | |
4077 | return 0; | |
4078 | // Rescale min..max to 0..255 | |
4079 | return DIV_ROUND_CLOSEST(AMDGPU_MAX_BL_LEVEL * (brightness - min), | |
4080 | max - min); | |
94562810 RS |
4081 | } |
4082 | ||
4052287a | 4083 | static void amdgpu_dm_backlight_set_level(struct amdgpu_display_manager *dm, |
7fd13bae | 4084 | int bl_idx, |
3d6c9164 | 4085 | u32 user_brightness) |
4562236b | 4086 | { |
206bbafe | 4087 | struct amdgpu_dm_backlight_caps caps; |
7fd13bae AD |
4088 | struct dc_link *link; |
4089 | u32 brightness; | |
94562810 | 4090 | bool rc; |
4562236b | 4091 | |
7fd13bae AD |
4092 | amdgpu_dm_update_backlight_caps(dm, bl_idx); |
4093 | caps = dm->backlight_caps[bl_idx]; | |
94562810 | 4094 | |
7fd13bae | 4095 | dm->brightness[bl_idx] = user_brightness; |
1f579254 AD |
4096 | /* update scratch register */ |
4097 | if (bl_idx == 0) | |
4098 | amdgpu_atombios_scratch_regs_set_backlight_level(dm->adev, dm->brightness[bl_idx]); | |
7fd13bae AD |
4099 | brightness = convert_brightness_from_user(&caps, dm->brightness[bl_idx]); |
4100 | link = (struct dc_link *)dm->backlight_link[bl_idx]; | |
94562810 | 4101 | |
3d6c9164 | 4102 | /* Change brightness based on AUX property */ |
118b4627 | 4103 | if (caps.aux_support) { |
7fd13bae AD |
4104 | rc = dc_link_set_backlight_level_nits(link, true, brightness, |
4105 | AUX_BL_DEFAULT_TRANSITION_TIME_MS); | |
4106 | if (!rc) | |
4107 | DRM_DEBUG("DM: Failed to update backlight via AUX on eDP[%d]\n", bl_idx); | |
118b4627 | 4108 | } else { |
7fd13bae AD |
4109 | rc = dc_link_set_backlight_level(link, brightness, 0); |
4110 | if (!rc) | |
4111 | DRM_DEBUG("DM: Failed to update backlight on eDP[%d]\n", bl_idx); | |
118b4627 | 4112 | } |
94562810 | 4113 | |
4052287a S |
4114 | if (rc) |
4115 | dm->actual_brightness[bl_idx] = user_brightness; | |
4562236b HW |
4116 | } |
4117 | ||
3d6c9164 | 4118 | static int amdgpu_dm_backlight_update_status(struct backlight_device *bd) |
4562236b | 4119 | { |
620a0d27 | 4120 | struct amdgpu_display_manager *dm = bl_get_data(bd); |
7fd13bae | 4121 | int i; |
3d6c9164 | 4122 | |
7fd13bae AD |
4123 | for (i = 0; i < dm->num_of_edps; i++) { |
4124 | if (bd == dm->backlight_dev[i]) | |
4125 | break; | |
4126 | } | |
4127 | if (i >= AMDGPU_DM_MAX_NUM_EDP) | |
4128 | i = 0; | |
4129 | amdgpu_dm_backlight_set_level(dm, i, bd->props.brightness); | |
3d6c9164 AD |
4130 | |
4131 | return 0; | |
4132 | } | |
4133 | ||
7fd13bae AD |
4134 | static u32 amdgpu_dm_backlight_get_level(struct amdgpu_display_manager *dm, |
4135 | int bl_idx) | |
3d6c9164 | 4136 | { |
0ad3e64e | 4137 | struct amdgpu_dm_backlight_caps caps; |
7fd13bae | 4138 | struct dc_link *link = (struct dc_link *)dm->backlight_link[bl_idx]; |
0ad3e64e | 4139 | |
7fd13bae AD |
4140 | amdgpu_dm_update_backlight_caps(dm, bl_idx); |
4141 | caps = dm->backlight_caps[bl_idx]; | |
620a0d27 | 4142 | |
0ad3e64e | 4143 | if (caps.aux_support) { |
0ad3e64e AD |
4144 | u32 avg, peak; |
4145 | bool rc; | |
4146 | ||
4147 | rc = dc_link_get_backlight_level_nits(link, &avg, &peak); | |
4148 | if (!rc) | |
7fd13bae | 4149 | return dm->brightness[bl_idx]; |
0ad3e64e AD |
4150 | return convert_brightness_to_user(&caps, avg); |
4151 | } else { | |
7fd13bae | 4152 | int ret = dc_link_get_backlight_level(link); |
0ad3e64e AD |
4153 | |
4154 | if (ret == DC_ERROR_UNEXPECTED) | |
7fd13bae | 4155 | return dm->brightness[bl_idx]; |
0ad3e64e AD |
4156 | return convert_brightness_to_user(&caps, ret); |
4157 | } | |
4562236b HW |
4158 | } |
4159 | ||
3d6c9164 AD |
4160 | static int amdgpu_dm_backlight_get_brightness(struct backlight_device *bd) |
4161 | { | |
4162 | struct amdgpu_display_manager *dm = bl_get_data(bd); | |
7fd13bae | 4163 | int i; |
3d6c9164 | 4164 | |
7fd13bae AD |
4165 | for (i = 0; i < dm->num_of_edps; i++) { |
4166 | if (bd == dm->backlight_dev[i]) | |
4167 | break; | |
4168 | } | |
4169 | if (i >= AMDGPU_DM_MAX_NUM_EDP) | |
4170 | i = 0; | |
4171 | return amdgpu_dm_backlight_get_level(dm, i); | |
3d6c9164 AD |
4172 | } |
4173 | ||
4562236b | 4174 | static const struct backlight_ops amdgpu_dm_backlight_ops = { |
bb264220 | 4175 | .options = BL_CORE_SUSPENDRESUME, |
4562236b HW |
4176 | .get_brightness = amdgpu_dm_backlight_get_brightness, |
4177 | .update_status = amdgpu_dm_backlight_update_status, | |
4178 | }; | |
4179 | ||
7578ecda | 4180 | static void |
213eca2b | 4181 | amdgpu_dm_register_backlight_device(struct amdgpu_dm_connector *aconnector) |
4562236b | 4182 | { |
213eca2b HG |
4183 | struct drm_device *drm = aconnector->base.dev; |
4184 | struct amdgpu_display_manager *dm = &drm_to_adev(drm)->dm; | |
4562236b | 4185 | struct backlight_properties props = { 0 }; |
213eca2b | 4186 | char bl_name[16]; |
4562236b | 4187 | |
62f03dad HG |
4188 | if (aconnector->bl_idx == -1) |
4189 | return; | |
4190 | ||
da11ef83 | 4191 | if (!acpi_video_backlight_use_native()) { |
213eca2b | 4192 | drm_info(drm, "Skipping amdgpu DM backlight registration\n"); |
c0f50c5d HG |
4193 | /* Try registering an ACPI video backlight device instead. */ |
4194 | acpi_video_register_backlight(); | |
da11ef83 HG |
4195 | return; |
4196 | } | |
4197 | ||
4562236b | 4198 | props.max_brightness = AMDGPU_MAX_BL_LEVEL; |
53a53f86 | 4199 | props.brightness = AMDGPU_MAX_BL_LEVEL; |
4562236b HW |
4200 | props.type = BACKLIGHT_RAW; |
4201 | ||
4202 | snprintf(bl_name, sizeof(bl_name), "amdgpu_bl%d", | |
213eca2b | 4203 | drm->primary->index + aconnector->bl_idx); |
4562236b | 4204 | |
213eca2b | 4205 | dm->backlight_dev[aconnector->bl_idx] = |
62f03dad | 4206 | backlight_device_register(bl_name, aconnector->base.kdev, dm, |
213eca2b | 4207 | &amdgpu_dm_backlight_ops, &props); |
4562236b | 4208 | |
213eca2b | 4209 | if (IS_ERR(dm->backlight_dev[aconnector->bl_idx])) { |
4562236b | 4210 | DRM_ERROR("DM: Backlight registration failed!\n"); |
213eca2b | 4211 | dm->backlight_dev[aconnector->bl_idx] = NULL; |
4db231d7 | 4212 | } else |
f1ad2f5e | 4213 | DRM_DEBUG_DRIVER("DM: Registered Backlight device: %s\n", bl_name); |
4562236b | 4214 | } |
4562236b | 4215 | |
df534fff | 4216 | static int initialize_plane(struct amdgpu_display_manager *dm, |
b2fddb13 | 4217 | struct amdgpu_mode_info *mode_info, int plane_id, |
cc1fec57 NK |
4218 | enum drm_plane_type plane_type, |
4219 | const struct dc_plane_cap *plane_cap) | |
df534fff | 4220 | { |
f180b4bc | 4221 | struct drm_plane *plane; |
df534fff S |
4222 | unsigned long possible_crtcs; |
4223 | int ret = 0; | |
4224 | ||
f180b4bc | 4225 | plane = kzalloc(sizeof(struct drm_plane), GFP_KERNEL); |
df534fff S |
4226 | if (!plane) { |
4227 | DRM_ERROR("KMS: Failed to allocate plane\n"); | |
4228 | return -ENOMEM; | |
4229 | } | |
b2fddb13 | 4230 | plane->type = plane_type; |
df534fff S |
4231 | |
4232 | /* | |
b2fddb13 NK |
4233 | * HACK: IGT tests expect that the primary plane for a CRTC |
4234 | * can only have one possible CRTC. Only expose support for | |
4235 | * any CRTC if they're not going to be used as a primary plane | |
4236 | * for a CRTC - like overlay or underlay planes. | |
df534fff S |
4237 | */ |
4238 | possible_crtcs = 1 << plane_id; | |
4239 | if (plane_id >= dm->dc->caps.max_streams) | |
4240 | possible_crtcs = 0xff; | |
4241 | ||
cc1fec57 | 4242 | ret = amdgpu_dm_plane_init(dm, plane, possible_crtcs, plane_cap); |
df534fff S |
4243 | |
4244 | if (ret) { | |
4245 | DRM_ERROR("KMS: Failed to initialize plane\n"); | |
54087768 | 4246 | kfree(plane); |
df534fff S |
4247 | return ret; |
4248 | } | |
4249 | ||
54087768 NK |
4250 | if (mode_info) |
4251 | mode_info->planes[plane_id] = plane; | |
4252 | ||
df534fff S |
4253 | return ret; |
4254 | } | |
4255 | ||
89fc8d4e | 4256 | |
618e51cd HG |
4257 | static void setup_backlight_device(struct amdgpu_display_manager *dm, |
4258 | struct amdgpu_dm_connector *aconnector) | |
89fc8d4e | 4259 | { |
f196198c | 4260 | struct dc_link *link = aconnector->dc_link; |
ceb4a561 | 4261 | int bl_idx = dm->num_of_edps; |
89fc8d4e | 4262 | |
ceb4a561 HG |
4263 | if (!(link->connector_signal & (SIGNAL_TYPE_EDP | SIGNAL_TYPE_LVDS)) || |
4264 | link->type == dc_connection_none) | |
4265 | return; | |
4266 | ||
4267 | if (dm->num_of_edps >= AMDGPU_DM_MAX_NUM_EDP) { | |
4268 | drm_warn(adev_to_drm(dm->adev), "Too much eDP connections, skipping backlight setup for additional eDPs\n"); | |
4269 | return; | |
89fc8d4e | 4270 | } |
ceb4a561 | 4271 | |
f196198c HG |
4272 | aconnector->bl_idx = bl_idx; |
4273 | ||
618e51cd HG |
4274 | amdgpu_dm_update_backlight_caps(dm, bl_idx); |
4275 | dm->brightness[bl_idx] = AMDGPU_MAX_BL_LEVEL; | |
ceb4a561 HG |
4276 | dm->backlight_link[bl_idx] = link; |
4277 | dm->num_of_edps++; | |
618e51cd HG |
4278 | |
4279 | update_connector_ext_caps(aconnector); | |
89fc8d4e HW |
4280 | } |
4281 | ||
acc96ae0 | 4282 | static void amdgpu_set_panel_orientation(struct drm_connector *connector); |
89fc8d4e | 4283 | |
1f6010a9 DF |
4284 | /* |
4285 | * In this architecture, the association | |
4562236b HW |
4286 | * connector -> encoder -> crtc |
4287 | * id not really requried. The crtc and connector will hold the | |
4288 | * display_index as an abstraction to use with DAL component | |
4289 | * | |
4290 | * Returns 0 on success | |
4291 | */ | |
7578ecda | 4292 | static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev) |
4562236b HW |
4293 | { |
4294 | struct amdgpu_display_manager *dm = &adev->dm; | |
ae67558b | 4295 | s32 i; |
c84dec2f | 4296 | struct amdgpu_dm_connector *aconnector = NULL; |
f2a0f5e6 | 4297 | struct amdgpu_encoder *aencoder = NULL; |
d4e13b0d | 4298 | struct amdgpu_mode_info *mode_info = &adev->mode_info; |
ae67558b SS |
4299 | u32 link_cnt; |
4300 | s32 primary_planes; | |
fbbdadf2 | 4301 | enum dc_connection_type new_connection_type = dc_connection_none; |
cc1fec57 | 4302 | const struct dc_plane_cap *plane; |
9470620e | 4303 | bool psr_feature_enabled = false; |
35f33086 | 4304 | int max_overlay = dm->dc->caps.max_slave_planes; |
4562236b | 4305 | |
d58159de AD |
4306 | dm->display_indexes_num = dm->dc->caps.max_streams; |
4307 | /* Update the actual used number of crtc */ | |
4308 | adev->mode_info.num_crtc = adev->dm.display_indexes_num; | |
4309 | ||
60971b20 | 4310 | amdgpu_dm_set_irq_funcs(adev); |
4311 | ||
4562236b | 4312 | link_cnt = dm->dc->caps.max_links; |
4562236b HW |
4313 | if (amdgpu_dm_mode_config_init(dm->adev)) { |
4314 | DRM_ERROR("DM: Failed to initialize mode config\n"); | |
59d0f396 | 4315 | return -EINVAL; |
4562236b HW |
4316 | } |
4317 | ||
b2fddb13 NK |
4318 | /* There is one primary plane per CRTC */ |
4319 | primary_planes = dm->dc->caps.max_streams; | |
54087768 | 4320 | ASSERT(primary_planes <= AMDGPU_MAX_PLANES); |
efa6a8b7 | 4321 | |
b2fddb13 NK |
4322 | /* |
4323 | * Initialize primary planes, implicit planes for legacy IOCTLS. | |
4324 | * Order is reversed to match iteration order in atomic check. | |
4325 | */ | |
4326 | for (i = (primary_planes - 1); i >= 0; i--) { | |
cc1fec57 NK |
4327 | plane = &dm->dc->caps.planes[i]; |
4328 | ||
b2fddb13 | 4329 | if (initialize_plane(dm, mode_info, i, |
cc1fec57 | 4330 | DRM_PLANE_TYPE_PRIMARY, plane)) { |
df534fff | 4331 | DRM_ERROR("KMS: Failed to initialize primary plane\n"); |
cd8a2ae8 | 4332 | goto fail; |
d4e13b0d | 4333 | } |
df534fff | 4334 | } |
92f3ac40 | 4335 | |
0d579c7e NK |
4336 | /* |
4337 | * Initialize overlay planes, index starting after primary planes. | |
4338 | * These planes have a higher DRM index than the primary planes since | |
4339 | * they should be considered as having a higher z-order. | |
4340 | * Order is reversed to match iteration order in atomic check. | |
cc1fec57 NK |
4341 | * |
4342 | * Only support DCN for now, and only expose one so we don't encourage | |
4343 | * userspace to use up all the pipes. | |
0d579c7e | 4344 | */ |
cc1fec57 NK |
4345 | for (i = 0; i < dm->dc->caps.max_planes; ++i) { |
4346 | struct dc_plane_cap *plane = &dm->dc->caps.planes[i]; | |
4347 | ||
8813381a LL |
4348 | /* Do not create overlay if MPO disabled */ |
4349 | if (amdgpu_dc_debug_mask & DC_DISABLE_MPO) | |
4350 | break; | |
4351 | ||
cc1fec57 NK |
4352 | if (plane->type != DC_PLANE_TYPE_DCN_UNIVERSAL) |
4353 | continue; | |
4354 | ||
ea36ad34 | 4355 | if (!plane->pixel_format_support.argb8888) |
cc1fec57 NK |
4356 | continue; |
4357 | ||
35f33086 BL |
4358 | if (max_overlay-- == 0) |
4359 | break; | |
4360 | ||
54087768 | 4361 | if (initialize_plane(dm, NULL, primary_planes + i, |
cc1fec57 | 4362 | DRM_PLANE_TYPE_OVERLAY, plane)) { |
0d579c7e | 4363 | DRM_ERROR("KMS: Failed to initialize overlay plane\n"); |
cd8a2ae8 | 4364 | goto fail; |
d4e13b0d AD |
4365 | } |
4366 | } | |
4562236b | 4367 | |
d4e13b0d | 4368 | for (i = 0; i < dm->dc->caps.max_streams; i++) |
f180b4bc | 4369 | if (amdgpu_dm_crtc_init(dm, mode_info->planes[i], i)) { |
4562236b | 4370 | DRM_ERROR("KMS: Failed to initialize crtc\n"); |
cd8a2ae8 | 4371 | goto fail; |
4562236b | 4372 | } |
4562236b | 4373 | |
81927e28 | 4374 | /* Use Outbox interrupt */ |
1d789535 | 4375 | switch (adev->ip_versions[DCE_HWIP][0]) { |
c08182f2 AD |
4376 | case IP_VERSION(3, 0, 0): |
4377 | case IP_VERSION(3, 1, 2): | |
4378 | case IP_VERSION(3, 1, 3): | |
e850f6b1 | 4379 | case IP_VERSION(3, 1, 4): |
b5b8ed44 | 4380 | case IP_VERSION(3, 1, 5): |
de7cc1b4 | 4381 | case IP_VERSION(3, 1, 6): |
577359ca AP |
4382 | case IP_VERSION(3, 2, 0): |
4383 | case IP_VERSION(3, 2, 1): | |
c08182f2 | 4384 | case IP_VERSION(2, 1, 0): |
81927e28 JS |
4385 | if (register_outbox_irq_handlers(dm->adev)) { |
4386 | DRM_ERROR("DM: Failed to initialize IRQ\n"); | |
4387 | goto fail; | |
4388 | } | |
4389 | break; | |
4390 | default: | |
c08182f2 | 4391 | DRM_DEBUG_KMS("Unsupported DCN IP version for outbox: 0x%X\n", |
1d789535 | 4392 | adev->ip_versions[DCE_HWIP][0]); |
81927e28 | 4393 | } |
9470620e NK |
4394 | |
4395 | /* Determine whether to enable PSR support by default. */ | |
4396 | if (!(amdgpu_dc_debug_mask & DC_DISABLE_PSR)) { | |
4397 | switch (adev->ip_versions[DCE_HWIP][0]) { | |
4398 | case IP_VERSION(3, 1, 2): | |
4399 | case IP_VERSION(3, 1, 3): | |
e850f6b1 | 4400 | case IP_VERSION(3, 1, 4): |
b5b8ed44 | 4401 | case IP_VERSION(3, 1, 5): |
de7cc1b4 | 4402 | case IP_VERSION(3, 1, 6): |
577359ca AP |
4403 | case IP_VERSION(3, 2, 0): |
4404 | case IP_VERSION(3, 2, 1): | |
9470620e NK |
4405 | psr_feature_enabled = true; |
4406 | break; | |
4407 | default: | |
4408 | psr_feature_enabled = amdgpu_dc_feature_mask & DC_PSR_MASK; | |
4409 | break; | |
4410 | } | |
4411 | } | |
81927e28 | 4412 | |
4562236b HW |
4413 | /* loops over all connectors on the board */ |
4414 | for (i = 0; i < link_cnt; i++) { | |
89fc8d4e | 4415 | struct dc_link *link = NULL; |
4562236b HW |
4416 | |
4417 | if (i > AMDGPU_DM_MAX_DISPLAY_INDEX) { | |
4418 | DRM_ERROR( | |
4419 | "KMS: Cannot support more than %d display indexes\n", | |
4420 | AMDGPU_DM_MAX_DISPLAY_INDEX); | |
4421 | continue; | |
4422 | } | |
4423 | ||
4424 | aconnector = kzalloc(sizeof(*aconnector), GFP_KERNEL); | |
4425 | if (!aconnector) | |
cd8a2ae8 | 4426 | goto fail; |
4562236b HW |
4427 | |
4428 | aencoder = kzalloc(sizeof(*aencoder), GFP_KERNEL); | |
8440c304 | 4429 | if (!aencoder) |
cd8a2ae8 | 4430 | goto fail; |
4562236b HW |
4431 | |
4432 | if (amdgpu_dm_encoder_init(dm->ddev, aencoder, i)) { | |
4433 | DRM_ERROR("KMS: Failed to initialize encoder\n"); | |
cd8a2ae8 | 4434 | goto fail; |
4562236b HW |
4435 | } |
4436 | ||
4437 | if (amdgpu_dm_connector_init(dm, aconnector, i, aencoder)) { | |
4438 | DRM_ERROR("KMS: Failed to initialize connector\n"); | |
cd8a2ae8 | 4439 | goto fail; |
4562236b HW |
4440 | } |
4441 | ||
89fc8d4e HW |
4442 | link = dc_get_link_at_index(dm->dc, i); |
4443 | ||
54618888 | 4444 | if (!dc_link_detect_connection_type(link, &new_connection_type)) |
fbbdadf2 BL |
4445 | DRM_ERROR("KMS: Failed to detect connector\n"); |
4446 | ||
4447 | if (aconnector->base.force && new_connection_type == dc_connection_none) { | |
4448 | emulated_link_detect(link); | |
4449 | amdgpu_dm_update_connector_after_detect(aconnector); | |
15c735e7 WL |
4450 | } else { |
4451 | bool ret = false; | |
fbbdadf2 | 4452 | |
15c735e7 WL |
4453 | mutex_lock(&dm->dc_lock); |
4454 | ret = dc_link_detect(link, DETECT_REASON_BOOT); | |
4455 | mutex_unlock(&dm->dc_lock); | |
4456 | ||
4457 | if (ret) { | |
4458 | amdgpu_dm_update_connector_after_detect(aconnector); | |
618e51cd | 4459 | setup_backlight_device(dm, aconnector); |
89fc8d4e | 4460 | |
15c735e7 WL |
4461 | if (psr_feature_enabled) |
4462 | amdgpu_dm_set_psr_caps(link); | |
89fc8d4e | 4463 | |
15c735e7 WL |
4464 | /* TODO: Fix vblank control helpers to delay PSR entry to allow this when |
4465 | * PSR is also supported. | |
4466 | */ | |
4467 | if (link->psr_settings.psr_feature_enabled) | |
4468 | adev_to_drm(adev)->vblank_disable_immediate = false; | |
4469 | } | |
4470 | } | |
acc96ae0 | 4471 | amdgpu_set_panel_orientation(&aconnector->base); |
4562236b HW |
4472 | } |
4473 | ||
c573e240 ML |
4474 | /* If we didn't find a panel, notify the acpi video detection */ |
4475 | if (dm->adev->flags & AMD_IS_APU && dm->num_of_edps == 0) | |
4476 | acpi_video_report_nolcd(); | |
4477 | ||
4562236b HW |
4478 | /* Software is initialized. Now we can register interrupt handlers. */ |
4479 | switch (adev->asic_type) { | |
55e56389 MR |
4480 | #if defined(CONFIG_DRM_AMD_DC_SI) |
4481 | case CHIP_TAHITI: | |
4482 | case CHIP_PITCAIRN: | |
4483 | case CHIP_VERDE: | |
4484 | case CHIP_OLAND: | |
4485 | if (dce60_register_irq_handlers(dm->adev)) { | |
4486 | DRM_ERROR("DM: Failed to initialize IRQ\n"); | |
4487 | goto fail; | |
4488 | } | |
4489 | break; | |
4490 | #endif | |
4562236b HW |
4491 | case CHIP_BONAIRE: |
4492 | case CHIP_HAWAII: | |
cd4b356f AD |
4493 | case CHIP_KAVERI: |
4494 | case CHIP_KABINI: | |
4495 | case CHIP_MULLINS: | |
4562236b HW |
4496 | case CHIP_TONGA: |
4497 | case CHIP_FIJI: | |
4498 | case CHIP_CARRIZO: | |
4499 | case CHIP_STONEY: | |
4500 | case CHIP_POLARIS11: | |
4501 | case CHIP_POLARIS10: | |
b264d345 | 4502 | case CHIP_POLARIS12: |
7737de91 | 4503 | case CHIP_VEGAM: |
2c8ad2d5 | 4504 | case CHIP_VEGA10: |
2325ff30 | 4505 | case CHIP_VEGA12: |
1fe6bf2f | 4506 | case CHIP_VEGA20: |
4562236b HW |
4507 | if (dce110_register_irq_handlers(dm->adev)) { |
4508 | DRM_ERROR("DM: Failed to initialize IRQ\n"); | |
cd8a2ae8 | 4509 | goto fail; |
4562236b HW |
4510 | } |
4511 | break; | |
4512 | default: | |
1d789535 | 4513 | switch (adev->ip_versions[DCE_HWIP][0]) { |
559f591d AD |
4514 | case IP_VERSION(1, 0, 0): |
4515 | case IP_VERSION(1, 0, 1): | |
c08182f2 AD |
4516 | case IP_VERSION(2, 0, 2): |
4517 | case IP_VERSION(2, 0, 3): | |
4518 | case IP_VERSION(2, 0, 0): | |
4519 | case IP_VERSION(2, 1, 0): | |
4520 | case IP_VERSION(3, 0, 0): | |
4521 | case IP_VERSION(3, 0, 2): | |
4522 | case IP_VERSION(3, 0, 3): | |
4523 | case IP_VERSION(3, 0, 1): | |
4524 | case IP_VERSION(3, 1, 2): | |
4525 | case IP_VERSION(3, 1, 3): | |
e850f6b1 | 4526 | case IP_VERSION(3, 1, 4): |
b5b8ed44 | 4527 | case IP_VERSION(3, 1, 5): |
de7cc1b4 | 4528 | case IP_VERSION(3, 1, 6): |
577359ca AP |
4529 | case IP_VERSION(3, 2, 0): |
4530 | case IP_VERSION(3, 2, 1): | |
c08182f2 AD |
4531 | if (dcn10_register_irq_handlers(dm->adev)) { |
4532 | DRM_ERROR("DM: Failed to initialize IRQ\n"); | |
4533 | goto fail; | |
4534 | } | |
4535 | break; | |
4536 | default: | |
2cbc6f42 | 4537 | DRM_ERROR("Unsupported DCE IP versions: 0x%X\n", |
1d789535 | 4538 | adev->ip_versions[DCE_HWIP][0]); |
2cbc6f42 | 4539 | goto fail; |
c08182f2 | 4540 | } |
2cbc6f42 | 4541 | break; |
4562236b HW |
4542 | } |
4543 | ||
4562236b | 4544 | return 0; |
cd8a2ae8 | 4545 | fail: |
4562236b | 4546 | kfree(aencoder); |
4562236b | 4547 | kfree(aconnector); |
54087768 | 4548 | |
59d0f396 | 4549 | return -EINVAL; |
4562236b HW |
4550 | } |
4551 | ||
7578ecda | 4552 | static void amdgpu_dm_destroy_drm_device(struct amdgpu_display_manager *dm) |
4562236b | 4553 | { |
eb3dc897 | 4554 | drm_atomic_private_obj_fini(&dm->atomic_obj); |
4562236b HW |
4555 | return; |
4556 | } | |
4557 | ||
4558 | /****************************************************************************** | |
4559 | * amdgpu_display_funcs functions | |
4560 | *****************************************************************************/ | |
4561 | ||
1f6010a9 | 4562 | /* |
4562236b HW |
4563 | * dm_bandwidth_update - program display watermarks |
4564 | * | |
4565 | * @adev: amdgpu_device pointer | |
4566 | * | |
4567 | * Calculate and program the display watermarks and line buffer allocation. | |
4568 | */ | |
4569 | static void dm_bandwidth_update(struct amdgpu_device *adev) | |
4570 | { | |
49c07a99 | 4571 | /* TODO: implement later */ |
4562236b HW |
4572 | } |
4573 | ||
39cc5be2 | 4574 | static const struct amdgpu_display_funcs dm_display_funcs = { |
4562236b HW |
4575 | .bandwidth_update = dm_bandwidth_update, /* called unconditionally */ |
4576 | .vblank_get_counter = dm_vblank_get_counter,/* called unconditionally */ | |
7b42573b HW |
4577 | .backlight_set_level = NULL, /* never called for DC */ |
4578 | .backlight_get_level = NULL, /* never called for DC */ | |
4562236b HW |
4579 | .hpd_sense = NULL,/* called unconditionally */ |
4580 | .hpd_set_polarity = NULL, /* called unconditionally */ | |
4581 | .hpd_get_gpio_reg = NULL, /* VBIOS parsing. DAL does it. */ | |
4562236b HW |
4582 | .page_flip_get_scanoutpos = |
4583 | dm_crtc_get_scanoutpos,/* called unconditionally */ | |
4584 | .add_encoder = NULL, /* VBIOS parsing. DAL does it. */ | |
4585 | .add_connector = NULL, /* VBIOS parsing. DAL does it. */ | |
4562236b HW |
4586 | }; |
4587 | ||
4588 | #if defined(CONFIG_DEBUG_KERNEL_DC) | |
4589 | ||
3ee6b26b AD |
4590 | static ssize_t s3_debug_store(struct device *device, |
4591 | struct device_attribute *attr, | |
4592 | const char *buf, | |
4593 | size_t count) | |
4562236b HW |
4594 | { |
4595 | int ret; | |
4596 | int s3_state; | |
ef1de361 | 4597 | struct drm_device *drm_dev = dev_get_drvdata(device); |
1348969a | 4598 | struct amdgpu_device *adev = drm_to_adev(drm_dev); |
4562236b HW |
4599 | |
4600 | ret = kstrtoint(buf, 0, &s3_state); | |
4601 | ||
4602 | if (ret == 0) { | |
4603 | if (s3_state) { | |
4604 | dm_resume(adev); | |
4a580877 | 4605 | drm_kms_helper_hotplug_event(adev_to_drm(adev)); |
4562236b HW |
4606 | } else |
4607 | dm_suspend(adev); | |
4608 | } | |
4609 | ||
4610 | return ret == 0 ? count : 0; | |
4611 | } | |
4612 | ||
4613 | DEVICE_ATTR_WO(s3_debug); | |
4614 | ||
4615 | #endif | |
4616 | ||
a7ab3451 ML |
4617 | static int dm_init_microcode(struct amdgpu_device *adev) |
4618 | { | |
4619 | char *fw_name_dmub; | |
4620 | int r; | |
4621 | ||
4622 | switch (adev->ip_versions[DCE_HWIP][0]) { | |
4623 | case IP_VERSION(2, 1, 0): | |
4624 | fw_name_dmub = FIRMWARE_RENOIR_DMUB; | |
4625 | if (ASICREV_IS_GREEN_SARDINE(adev->external_rev_id)) | |
4626 | fw_name_dmub = FIRMWARE_GREEN_SARDINE_DMUB; | |
4627 | break; | |
4628 | case IP_VERSION(3, 0, 0): | |
4629 | if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 3, 0)) | |
4630 | fw_name_dmub = FIRMWARE_SIENNA_CICHLID_DMUB; | |
4631 | else | |
4632 | fw_name_dmub = FIRMWARE_NAVY_FLOUNDER_DMUB; | |
4633 | break; | |
4634 | case IP_VERSION(3, 0, 1): | |
4635 | fw_name_dmub = FIRMWARE_VANGOGH_DMUB; | |
4636 | break; | |
4637 | case IP_VERSION(3, 0, 2): | |
4638 | fw_name_dmub = FIRMWARE_DIMGREY_CAVEFISH_DMUB; | |
4639 | break; | |
4640 | case IP_VERSION(3, 0, 3): | |
4641 | fw_name_dmub = FIRMWARE_BEIGE_GOBY_DMUB; | |
4642 | break; | |
4643 | case IP_VERSION(3, 1, 2): | |
4644 | case IP_VERSION(3, 1, 3): | |
4645 | fw_name_dmub = FIRMWARE_YELLOW_CARP_DMUB; | |
4646 | break; | |
4647 | case IP_VERSION(3, 1, 4): | |
4648 | fw_name_dmub = FIRMWARE_DCN_314_DMUB; | |
4649 | break; | |
4650 | case IP_VERSION(3, 1, 5): | |
4651 | fw_name_dmub = FIRMWARE_DCN_315_DMUB; | |
4652 | break; | |
4653 | case IP_VERSION(3, 1, 6): | |
4654 | fw_name_dmub = FIRMWARE_DCN316_DMUB; | |
4655 | break; | |
4656 | case IP_VERSION(3, 2, 0): | |
4657 | fw_name_dmub = FIRMWARE_DCN_V3_2_0_DMCUB; | |
4658 | break; | |
4659 | case IP_VERSION(3, 2, 1): | |
4660 | fw_name_dmub = FIRMWARE_DCN_V3_2_1_DMCUB; | |
4661 | break; | |
4662 | default: | |
4663 | /* ASIC doesn't support DMUB. */ | |
4664 | return 0; | |
4665 | } | |
4666 | r = amdgpu_ucode_request(adev, &adev->dm.dmub_fw, fw_name_dmub); | |
4667 | if (r) | |
4668 | DRM_ERROR("DMUB firmware loading failed: %d\n", r); | |
4669 | return r; | |
4670 | } | |
4671 | ||
4562236b HW |
4672 | static int dm_early_init(void *handle) |
4673 | { | |
4674 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; | |
44900af0 AD |
4675 | struct amdgpu_mode_info *mode_info = &adev->mode_info; |
4676 | struct atom_context *ctx = mode_info->atom_context; | |
4677 | int index = GetIndexIntoMasterTable(DATA, Object_Header); | |
4678 | u16 data_offset; | |
4679 | ||
4680 | /* if there is no object header, skip DM */ | |
4681 | if (!amdgpu_atom_parse_data_header(ctx, index, NULL, NULL, NULL, &data_offset)) { | |
4682 | adev->harvest_ip_mask |= AMD_HARVEST_IP_DMU_MASK; | |
4683 | dev_info(adev->dev, "No object header, skipping DM\n"); | |
4684 | return -ENOENT; | |
4685 | } | |
4562236b | 4686 | |
4562236b | 4687 | switch (adev->asic_type) { |
55e56389 MR |
4688 | #if defined(CONFIG_DRM_AMD_DC_SI) |
4689 | case CHIP_TAHITI: | |
4690 | case CHIP_PITCAIRN: | |
4691 | case CHIP_VERDE: | |
4692 | adev->mode_info.num_crtc = 6; | |
4693 | adev->mode_info.num_hpd = 6; | |
4694 | adev->mode_info.num_dig = 6; | |
4695 | break; | |
4696 | case CHIP_OLAND: | |
4697 | adev->mode_info.num_crtc = 2; | |
4698 | adev->mode_info.num_hpd = 2; | |
4699 | adev->mode_info.num_dig = 2; | |
4700 | break; | |
4701 | #endif | |
4562236b HW |
4702 | case CHIP_BONAIRE: |
4703 | case CHIP_HAWAII: | |
4704 | adev->mode_info.num_crtc = 6; | |
4705 | adev->mode_info.num_hpd = 6; | |
4706 | adev->mode_info.num_dig = 6; | |
4562236b | 4707 | break; |
cd4b356f AD |
4708 | case CHIP_KAVERI: |
4709 | adev->mode_info.num_crtc = 4; | |
4710 | adev->mode_info.num_hpd = 6; | |
4711 | adev->mode_info.num_dig = 7; | |
cd4b356f AD |
4712 | break; |
4713 | case CHIP_KABINI: | |
4714 | case CHIP_MULLINS: | |
4715 | adev->mode_info.num_crtc = 2; | |
4716 | adev->mode_info.num_hpd = 6; | |
4717 | adev->mode_info.num_dig = 6; | |
cd4b356f | 4718 | break; |
4562236b HW |
4719 | case CHIP_FIJI: |
4720 | case CHIP_TONGA: | |
4721 | adev->mode_info.num_crtc = 6; | |
4722 | adev->mode_info.num_hpd = 6; | |
4723 | adev->mode_info.num_dig = 7; | |
4562236b HW |
4724 | break; |
4725 | case CHIP_CARRIZO: | |
4726 | adev->mode_info.num_crtc = 3; | |
4727 | adev->mode_info.num_hpd = 6; | |
4728 | adev->mode_info.num_dig = 9; | |
4562236b HW |
4729 | break; |
4730 | case CHIP_STONEY: | |
4731 | adev->mode_info.num_crtc = 2; | |
4732 | adev->mode_info.num_hpd = 6; | |
4733 | adev->mode_info.num_dig = 9; | |
4562236b HW |
4734 | break; |
4735 | case CHIP_POLARIS11: | |
b264d345 | 4736 | case CHIP_POLARIS12: |
4562236b HW |
4737 | adev->mode_info.num_crtc = 5; |
4738 | adev->mode_info.num_hpd = 5; | |
4739 | adev->mode_info.num_dig = 5; | |
4562236b HW |
4740 | break; |
4741 | case CHIP_POLARIS10: | |
7737de91 | 4742 | case CHIP_VEGAM: |
4562236b HW |
4743 | adev->mode_info.num_crtc = 6; |
4744 | adev->mode_info.num_hpd = 6; | |
4745 | adev->mode_info.num_dig = 6; | |
4562236b | 4746 | break; |
2c8ad2d5 | 4747 | case CHIP_VEGA10: |
2325ff30 | 4748 | case CHIP_VEGA12: |
1fe6bf2f | 4749 | case CHIP_VEGA20: |
2c8ad2d5 AD |
4750 | adev->mode_info.num_crtc = 6; |
4751 | adev->mode_info.num_hpd = 6; | |
4752 | adev->mode_info.num_dig = 6; | |
4753 | break; | |
4562236b | 4754 | default: |
cae5c1ab | 4755 | |
1d789535 | 4756 | switch (adev->ip_versions[DCE_HWIP][0]) { |
c08182f2 AD |
4757 | case IP_VERSION(2, 0, 2): |
4758 | case IP_VERSION(3, 0, 0): | |
4759 | adev->mode_info.num_crtc = 6; | |
4760 | adev->mode_info.num_hpd = 6; | |
4761 | adev->mode_info.num_dig = 6; | |
4762 | break; | |
4763 | case IP_VERSION(2, 0, 0): | |
4764 | case IP_VERSION(3, 0, 2): | |
4765 | adev->mode_info.num_crtc = 5; | |
4766 | adev->mode_info.num_hpd = 5; | |
4767 | adev->mode_info.num_dig = 5; | |
4768 | break; | |
4769 | case IP_VERSION(2, 0, 3): | |
4770 | case IP_VERSION(3, 0, 3): | |
4771 | adev->mode_info.num_crtc = 2; | |
4772 | adev->mode_info.num_hpd = 2; | |
4773 | adev->mode_info.num_dig = 2; | |
4774 | break; | |
559f591d AD |
4775 | case IP_VERSION(1, 0, 0): |
4776 | case IP_VERSION(1, 0, 1): | |
c08182f2 AD |
4777 | case IP_VERSION(3, 0, 1): |
4778 | case IP_VERSION(2, 1, 0): | |
4779 | case IP_VERSION(3, 1, 2): | |
4780 | case IP_VERSION(3, 1, 3): | |
e850f6b1 | 4781 | case IP_VERSION(3, 1, 4): |
b5b8ed44 | 4782 | case IP_VERSION(3, 1, 5): |
de7cc1b4 | 4783 | case IP_VERSION(3, 1, 6): |
577359ca AP |
4784 | case IP_VERSION(3, 2, 0): |
4785 | case IP_VERSION(3, 2, 1): | |
c08182f2 AD |
4786 | adev->mode_info.num_crtc = 4; |
4787 | adev->mode_info.num_hpd = 4; | |
4788 | adev->mode_info.num_dig = 4; | |
4789 | break; | |
4790 | default: | |
2cbc6f42 | 4791 | DRM_ERROR("Unsupported DCE IP versions: 0x%x\n", |
1d789535 | 4792 | adev->ip_versions[DCE_HWIP][0]); |
2cbc6f42 | 4793 | return -EINVAL; |
c08182f2 | 4794 | } |
2cbc6f42 | 4795 | break; |
4562236b HW |
4796 | } |
4797 | ||
39cc5be2 AD |
4798 | if (adev->mode_info.funcs == NULL) |
4799 | adev->mode_info.funcs = &dm_display_funcs; | |
4800 | ||
1f6010a9 DF |
4801 | /* |
4802 | * Note: Do NOT change adev->audio_endpt_rreg and | |
4562236b | 4803 | * adev->audio_endpt_wreg because they are initialised in |
1f6010a9 DF |
4804 | * amdgpu_device_init() |
4805 | */ | |
4562236b HW |
4806 | #if defined(CONFIG_DEBUG_KERNEL_DC) |
4807 | device_create_file( | |
4a580877 | 4808 | adev_to_drm(adev)->dev, |
4562236b HW |
4809 | &dev_attr_s3_debug); |
4810 | #endif | |
d09ef243 | 4811 | adev->dc_enabled = true; |
4562236b | 4812 | |
a7ab3451 | 4813 | return dm_init_microcode(adev); |
4562236b HW |
4814 | } |
4815 | ||
e7b07cee HW |
4816 | static bool modereset_required(struct drm_crtc_state *crtc_state) |
4817 | { | |
2afda735 | 4818 | return !crtc_state->active && drm_atomic_crtc_needs_modeset(crtc_state); |
e7b07cee HW |
4819 | } |
4820 | ||
7578ecda | 4821 | static void amdgpu_dm_encoder_destroy(struct drm_encoder *encoder) |
e7b07cee HW |
4822 | { |
4823 | drm_encoder_cleanup(encoder); | |
4824 | kfree(encoder); | |
4825 | } | |
4826 | ||
4827 | static const struct drm_encoder_funcs amdgpu_dm_encoder_funcs = { | |
4828 | .destroy = amdgpu_dm_encoder_destroy, | |
4829 | }; | |
4830 | ||
5d945cbc RS |
4831 | static int |
4832 | fill_plane_color_attributes(const struct drm_plane_state *plane_state, | |
4833 | const enum surface_pixel_format format, | |
4834 | enum dc_color_space *color_space) | |
6300b3bd | 4835 | { |
5d945cbc | 4836 | bool full_range; |
6300b3bd | 4837 | |
5d945cbc RS |
4838 | *color_space = COLOR_SPACE_SRGB; |
4839 | ||
4840 | /* DRM color properties only affect non-RGB formats. */ | |
4841 | if (format < SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) | |
4842 | return 0; | |
4843 | ||
4844 | full_range = (plane_state->color_range == DRM_COLOR_YCBCR_FULL_RANGE); | |
4845 | ||
4846 | switch (plane_state->color_encoding) { | |
4847 | case DRM_COLOR_YCBCR_BT601: | |
4848 | if (full_range) | |
4849 | *color_space = COLOR_SPACE_YCBCR601; | |
4850 | else | |
4851 | *color_space = COLOR_SPACE_YCBCR601_LIMITED; | |
6300b3bd MK |
4852 | break; |
4853 | ||
5d945cbc RS |
4854 | case DRM_COLOR_YCBCR_BT709: |
4855 | if (full_range) | |
4856 | *color_space = COLOR_SPACE_YCBCR709; | |
4857 | else | |
4858 | *color_space = COLOR_SPACE_YCBCR709_LIMITED; | |
6300b3bd MK |
4859 | break; |
4860 | ||
5d945cbc RS |
4861 | case DRM_COLOR_YCBCR_BT2020: |
4862 | if (full_range) | |
4863 | *color_space = COLOR_SPACE_2020_YCBCR; | |
4864 | else | |
4865 | return -EINVAL; | |
6300b3bd | 4866 | break; |
6300b3bd | 4867 | |
5d945cbc RS |
4868 | default: |
4869 | return -EINVAL; | |
4870 | } | |
6300b3bd | 4871 | |
5d945cbc | 4872 | return 0; |
6300b3bd MK |
4873 | } |
4874 | ||
5d945cbc RS |
4875 | static int |
4876 | fill_dc_plane_info_and_addr(struct amdgpu_device *adev, | |
4877 | const struct drm_plane_state *plane_state, | |
ae67558b | 4878 | const u64 tiling_flags, |
5d945cbc RS |
4879 | struct dc_plane_info *plane_info, |
4880 | struct dc_plane_address *address, | |
4881 | bool tmz_surface, | |
4882 | bool force_disable_dcc) | |
e7b07cee | 4883 | { |
5d945cbc RS |
4884 | const struct drm_framebuffer *fb = plane_state->fb; |
4885 | const struct amdgpu_framebuffer *afb = | |
4886 | to_amdgpu_framebuffer(plane_state->fb); | |
4887 | int ret; | |
e7b07cee | 4888 | |
5d945cbc | 4889 | memset(plane_info, 0, sizeof(*plane_info)); |
e7b07cee | 4890 | |
5d945cbc RS |
4891 | switch (fb->format->format) { |
4892 | case DRM_FORMAT_C8: | |
4893 | plane_info->format = | |
4894 | SURFACE_PIXEL_FORMAT_GRPH_PALETA_256_COLORS; | |
4895 | break; | |
4896 | case DRM_FORMAT_RGB565: | |
4897 | plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_RGB565; | |
4898 | break; | |
4899 | case DRM_FORMAT_XRGB8888: | |
4900 | case DRM_FORMAT_ARGB8888: | |
4901 | plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB8888; | |
4902 | break; | |
4903 | case DRM_FORMAT_XRGB2101010: | |
4904 | case DRM_FORMAT_ARGB2101010: | |
4905 | plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010; | |
4906 | break; | |
4907 | case DRM_FORMAT_XBGR2101010: | |
4908 | case DRM_FORMAT_ABGR2101010: | |
4909 | plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010; | |
4910 | break; | |
4911 | case DRM_FORMAT_XBGR8888: | |
4912 | case DRM_FORMAT_ABGR8888: | |
4913 | plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ABGR8888; | |
4914 | break; | |
4915 | case DRM_FORMAT_NV21: | |
4916 | plane_info->format = SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr; | |
4917 | break; | |
4918 | case DRM_FORMAT_NV12: | |
4919 | plane_info->format = SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb; | |
4920 | break; | |
4921 | case DRM_FORMAT_P010: | |
4922 | plane_info->format = SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCrCb; | |
4923 | break; | |
4924 | case DRM_FORMAT_XRGB16161616F: | |
4925 | case DRM_FORMAT_ARGB16161616F: | |
4926 | plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F; | |
4927 | break; | |
4928 | case DRM_FORMAT_XBGR16161616F: | |
4929 | case DRM_FORMAT_ABGR16161616F: | |
4930 | plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F; | |
4931 | break; | |
4932 | case DRM_FORMAT_XRGB16161616: | |
4933 | case DRM_FORMAT_ARGB16161616: | |
4934 | plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616; | |
4935 | break; | |
4936 | case DRM_FORMAT_XBGR16161616: | |
4937 | case DRM_FORMAT_ABGR16161616: | |
4938 | plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616; | |
4939 | break; | |
4940 | default: | |
4941 | DRM_ERROR( | |
4942 | "Unsupported screen format %p4cc\n", | |
4943 | &fb->format->format); | |
d89f6048 | 4944 | return -EINVAL; |
5d945cbc | 4945 | } |
d89f6048 | 4946 | |
5d945cbc RS |
4947 | switch (plane_state->rotation & DRM_MODE_ROTATE_MASK) { |
4948 | case DRM_MODE_ROTATE_0: | |
4949 | plane_info->rotation = ROTATION_ANGLE_0; | |
4950 | break; | |
4951 | case DRM_MODE_ROTATE_90: | |
4952 | plane_info->rotation = ROTATION_ANGLE_90; | |
4953 | break; | |
4954 | case DRM_MODE_ROTATE_180: | |
4955 | plane_info->rotation = ROTATION_ANGLE_180; | |
4956 | break; | |
4957 | case DRM_MODE_ROTATE_270: | |
4958 | plane_info->rotation = ROTATION_ANGLE_270; | |
4959 | break; | |
4960 | default: | |
4961 | plane_info->rotation = ROTATION_ANGLE_0; | |
4962 | break; | |
4963 | } | |
695af5f9 | 4964 | |
695af5f9 | 4965 | |
5d945cbc RS |
4966 | plane_info->visible = true; |
4967 | plane_info->stereo_format = PLANE_STEREO_FORMAT_NONE; | |
e7b07cee | 4968 | |
22c42b0e | 4969 | plane_info->layer_index = plane_state->normalized_zpos; |
e7b07cee | 4970 | |
5d945cbc RS |
4971 | ret = fill_plane_color_attributes(plane_state, plane_info->format, |
4972 | &plane_info->color_space); | |
4973 | if (ret) | |
4974 | return ret; | |
e7b07cee | 4975 | |
8bf0d9cd | 4976 | ret = amdgpu_dm_plane_fill_plane_buffer_attributes(adev, afb, plane_info->format, |
5d945cbc RS |
4977 | plane_info->rotation, tiling_flags, |
4978 | &plane_info->tiling_info, | |
4979 | &plane_info->plane_size, | |
4980 | &plane_info->dcc, address, | |
4981 | tmz_surface, force_disable_dcc); | |
4982 | if (ret) | |
4983 | return ret; | |
e7b07cee | 4984 | |
8bf0d9cd | 4985 | amdgpu_dm_plane_fill_blending_from_plane_state( |
5d945cbc RS |
4986 | plane_state, &plane_info->per_pixel_alpha, &plane_info->pre_multiplied_alpha, |
4987 | &plane_info->global_alpha, &plane_info->global_alpha_value); | |
e7b07cee | 4988 | |
5d945cbc RS |
4989 | return 0; |
4990 | } | |
e7b07cee | 4991 | |
5d945cbc RS |
4992 | static int fill_dc_plane_attributes(struct amdgpu_device *adev, |
4993 | struct dc_plane_state *dc_plane_state, | |
4994 | struct drm_plane_state *plane_state, | |
4995 | struct drm_crtc_state *crtc_state) | |
4996 | { | |
4997 | struct dm_crtc_state *dm_crtc_state = to_dm_crtc_state(crtc_state); | |
4998 | struct amdgpu_framebuffer *afb = (struct amdgpu_framebuffer *)plane_state->fb; | |
4999 | struct dc_scaling_info scaling_info; | |
5000 | struct dc_plane_info plane_info; | |
5001 | int ret; | |
5002 | bool force_disable_dcc = false; | |
6300b3bd | 5003 | |
8bf0d9cd | 5004 | ret = amdgpu_dm_plane_fill_dc_scaling_info(adev, plane_state, &scaling_info); |
5d945cbc RS |
5005 | if (ret) |
5006 | return ret; | |
e7b07cee | 5007 | |
5d945cbc RS |
5008 | dc_plane_state->src_rect = scaling_info.src_rect; |
5009 | dc_plane_state->dst_rect = scaling_info.dst_rect; | |
5010 | dc_plane_state->clip_rect = scaling_info.clip_rect; | |
5011 | dc_plane_state->scaling_quality = scaling_info.scaling_quality; | |
6491f0c0 | 5012 | |
5d945cbc RS |
5013 | force_disable_dcc = adev->asic_type == CHIP_RAVEN && adev->in_suspend; |
5014 | ret = fill_dc_plane_info_and_addr(adev, plane_state, | |
5015 | afb->tiling_flags, | |
5016 | &plane_info, | |
5017 | &dc_plane_state->address, | |
5018 | afb->tmz_surface, | |
5019 | force_disable_dcc); | |
5020 | if (ret) | |
5021 | return ret; | |
6491f0c0 | 5022 | |
5d945cbc RS |
5023 | dc_plane_state->format = plane_info.format; |
5024 | dc_plane_state->color_space = plane_info.color_space; | |
5025 | dc_plane_state->format = plane_info.format; | |
5026 | dc_plane_state->plane_size = plane_info.plane_size; | |
5027 | dc_plane_state->rotation = plane_info.rotation; | |
5028 | dc_plane_state->horizontal_mirror = plane_info.horizontal_mirror; | |
5029 | dc_plane_state->stereo_format = plane_info.stereo_format; | |
5030 | dc_plane_state->tiling_info = plane_info.tiling_info; | |
5031 | dc_plane_state->visible = plane_info.visible; | |
5032 | dc_plane_state->per_pixel_alpha = plane_info.per_pixel_alpha; | |
5033 | dc_plane_state->pre_multiplied_alpha = plane_info.pre_multiplied_alpha; | |
5034 | dc_plane_state->global_alpha = plane_info.global_alpha; | |
5035 | dc_plane_state->global_alpha_value = plane_info.global_alpha_value; | |
5036 | dc_plane_state->dcc = plane_info.dcc; | |
22c42b0e | 5037 | dc_plane_state->layer_index = plane_info.layer_index; |
5d945cbc | 5038 | dc_plane_state->flip_int_enabled = true; |
6491f0c0 | 5039 | |
695af5f9 | 5040 | /* |
5d945cbc RS |
5041 | * Always set input transfer function, since plane state is refreshed |
5042 | * every time. | |
695af5f9 | 5043 | */ |
5d945cbc RS |
5044 | ret = amdgpu_dm_update_plane_color_mgmt(dm_crtc_state, dc_plane_state); |
5045 | if (ret) | |
5046 | return ret; | |
e7b07cee | 5047 | |
695af5f9 | 5048 | return 0; |
4562236b | 5049 | } |
695af5f9 | 5050 | |
30ebe415 HM |
5051 | static inline void fill_dc_dirty_rect(struct drm_plane *plane, |
5052 | struct rect *dirty_rect, int32_t x, | |
ae67558b | 5053 | s32 y, s32 width, s32 height, |
30ebe415 HM |
5054 | int *i, bool ffu) |
5055 | { | |
5056 | if (*i > DC_MAX_DIRTY_RECTS) | |
5057 | return; | |
5058 | ||
5059 | if (*i == DC_MAX_DIRTY_RECTS) | |
5060 | goto out; | |
5061 | ||
5062 | dirty_rect->x = x; | |
5063 | dirty_rect->y = y; | |
5064 | dirty_rect->width = width; | |
5065 | dirty_rect->height = height; | |
5066 | ||
5067 | if (ffu) | |
5068 | drm_dbg(plane->dev, | |
5069 | "[PLANE:%d] PSR FFU dirty rect size (%d, %d)\n", | |
5070 | plane->base.id, width, height); | |
5071 | else | |
5072 | drm_dbg(plane->dev, | |
5073 | "[PLANE:%d] PSR SU dirty rect at (%d, %d) size (%d, %d)", | |
5074 | plane->base.id, x, y, width, height); | |
5075 | ||
5076 | out: | |
5077 | (*i)++; | |
5078 | } | |
5079 | ||
5d945cbc RS |
5080 | /** |
5081 | * fill_dc_dirty_rects() - Fill DC dirty regions for PSR selective updates | |
5082 | * | |
5083 | * @plane: DRM plane containing dirty regions that need to be flushed to the eDP | |
5084 | * remote fb | |
5085 | * @old_plane_state: Old state of @plane | |
5086 | * @new_plane_state: New state of @plane | |
5087 | * @crtc_state: New state of CRTC connected to the @plane | |
5088 | * @flip_addrs: DC flip tracking struct, which also tracts dirty rects | |
d6ed6d0d | 5089 | * @dirty_regions_changed: dirty regions changed |
5d945cbc RS |
5090 | * |
5091 | * For PSR SU, DC informs the DMUB uController of dirty rectangle regions | |
5092 | * (referred to as "damage clips" in DRM nomenclature) that require updating on | |
5093 | * the eDP remote buffer. The responsibility of specifying the dirty regions is | |
5094 | * amdgpu_dm's. | |
5095 | * | |
5096 | * A damage-aware DRM client should fill the FB_DAMAGE_CLIPS property on the | |
5097 | * plane with regions that require flushing to the eDP remote buffer. In | |
5098 | * addition, certain use cases - such as cursor and multi-plane overlay (MPO) - | |
5099 | * implicitly provide damage clips without any client support via the plane | |
5100 | * bounds. | |
5d945cbc RS |
5101 | */ |
5102 | static void fill_dc_dirty_rects(struct drm_plane *plane, | |
5103 | struct drm_plane_state *old_plane_state, | |
5104 | struct drm_plane_state *new_plane_state, | |
5105 | struct drm_crtc_state *crtc_state, | |
d6ed6d0d TC |
5106 | struct dc_flip_addrs *flip_addrs, |
5107 | bool *dirty_regions_changed) | |
5d945cbc RS |
5108 | { |
5109 | struct dm_crtc_state *dm_crtc_state = to_dm_crtc_state(crtc_state); | |
5110 | struct rect *dirty_rects = flip_addrs->dirty_rects; | |
ae67558b | 5111 | u32 num_clips; |
30ebe415 | 5112 | struct drm_mode_rect *clips; |
5d945cbc RS |
5113 | bool bb_changed; |
5114 | bool fb_changed; | |
ae67558b | 5115 | u32 i = 0; |
d6ed6d0d | 5116 | *dirty_regions_changed = false; |
e7b07cee | 5117 | |
7cc191ee LL |
5118 | /* |
5119 | * Cursor plane has it's own dirty rect update interface. See | |
5120 | * dcn10_dmub_update_cursor_data and dmub_cmd_update_cursor_info_data | |
5121 | */ | |
5122 | if (plane->type == DRM_PLANE_TYPE_CURSOR) | |
5123 | return; | |
5124 | ||
30ebe415 HM |
5125 | num_clips = drm_plane_get_damage_clips_count(new_plane_state); |
5126 | clips = drm_plane_get_damage_clips(new_plane_state); | |
5127 | ||
7cc191ee | 5128 | if (!dm_crtc_state->mpo_requested) { |
30ebe415 HM |
5129 | if (!num_clips || num_clips > DC_MAX_DIRTY_RECTS) |
5130 | goto ffu; | |
5131 | ||
5132 | for (; flip_addrs->dirty_rect_count < num_clips; clips++) | |
5133 | fill_dc_dirty_rect(new_plane_state->plane, | |
566b6577 BC |
5134 | &dirty_rects[flip_addrs->dirty_rect_count], |
5135 | clips->x1, clips->y1, | |
5136 | clips->x2 - clips->x1, clips->y2 - clips->y1, | |
30ebe415 HM |
5137 | &flip_addrs->dirty_rect_count, |
5138 | false); | |
7cc191ee LL |
5139 | return; |
5140 | } | |
5141 | ||
5142 | /* | |
5143 | * MPO is requested. Add entire plane bounding box to dirty rects if | |
5144 | * flipped to or damaged. | |
5145 | * | |
5146 | * If plane is moved or resized, also add old bounding box to dirty | |
5147 | * rects. | |
5148 | */ | |
7cc191ee LL |
5149 | fb_changed = old_plane_state->fb->base.id != |
5150 | new_plane_state->fb->base.id; | |
5151 | bb_changed = (old_plane_state->crtc_x != new_plane_state->crtc_x || | |
5152 | old_plane_state->crtc_y != new_plane_state->crtc_y || | |
5153 | old_plane_state->crtc_w != new_plane_state->crtc_w || | |
5154 | old_plane_state->crtc_h != new_plane_state->crtc_h); | |
5155 | ||
30ebe415 HM |
5156 | drm_dbg(plane->dev, |
5157 | "[PLANE:%d] PSR bb_changed:%d fb_changed:%d num_clips:%d\n", | |
5158 | new_plane_state->plane->base.id, | |
5159 | bb_changed, fb_changed, num_clips); | |
7cc191ee | 5160 | |
d6ed6d0d TC |
5161 | *dirty_regions_changed = bb_changed; |
5162 | ||
7cc191ee | 5163 | if (bb_changed) { |
30ebe415 HM |
5164 | fill_dc_dirty_rect(new_plane_state->plane, &dirty_rects[i], |
5165 | new_plane_state->crtc_x, | |
5166 | new_plane_state->crtc_y, | |
5167 | new_plane_state->crtc_w, | |
5168 | new_plane_state->crtc_h, &i, false); | |
5169 | ||
5170 | /* Add old plane bounding-box if plane is moved or resized */ | |
5171 | fill_dc_dirty_rect(new_plane_state->plane, &dirty_rects[i], | |
5172 | old_plane_state->crtc_x, | |
5173 | old_plane_state->crtc_y, | |
5174 | old_plane_state->crtc_w, | |
5175 | old_plane_state->crtc_h, &i, false); | |
5176 | } | |
5177 | ||
5178 | if (num_clips) { | |
5179 | for (; i < num_clips; clips++) | |
5180 | fill_dc_dirty_rect(new_plane_state->plane, | |
5181 | &dirty_rects[i], clips->x1, | |
5182 | clips->y1, clips->x2 - clips->x1, | |
5183 | clips->y2 - clips->y1, &i, false); | |
5184 | } else if (fb_changed && !bb_changed) { | |
5185 | fill_dc_dirty_rect(new_plane_state->plane, &dirty_rects[i], | |
5186 | new_plane_state->crtc_x, | |
5187 | new_plane_state->crtc_y, | |
5188 | new_plane_state->crtc_w, | |
5189 | new_plane_state->crtc_h, &i, false); | |
5190 | } | |
5191 | ||
5192 | if (i > DC_MAX_DIRTY_RECTS) | |
5193 | goto ffu; | |
7cc191ee LL |
5194 | |
5195 | flip_addrs->dirty_rect_count = i; | |
30ebe415 HM |
5196 | return; |
5197 | ||
5198 | ffu: | |
5199 | fill_dc_dirty_rect(new_plane_state->plane, &dirty_rects[0], 0, 0, | |
5200 | dm_crtc_state->base.mode.crtc_hdisplay, | |
5201 | dm_crtc_state->base.mode.crtc_vdisplay, | |
5202 | &flip_addrs->dirty_rect_count, true); | |
7cc191ee LL |
5203 | } |
5204 | ||
3ee6b26b AD |
5205 | static void update_stream_scaling_settings(const struct drm_display_mode *mode, |
5206 | const struct dm_connector_state *dm_state, | |
5207 | struct dc_stream_state *stream) | |
e7b07cee HW |
5208 | { |
5209 | enum amdgpu_rmx_type rmx_type; | |
5210 | ||
5211 | struct rect src = { 0 }; /* viewport in composition space*/ | |
5212 | struct rect dst = { 0 }; /* stream addressable area */ | |
5213 | ||
5214 | /* no mode. nothing to be done */ | |
5215 | if (!mode) | |
5216 | return; | |
5217 | ||
5218 | /* Full screen scaling by default */ | |
5219 | src.width = mode->hdisplay; | |
5220 | src.height = mode->vdisplay; | |
5221 | dst.width = stream->timing.h_addressable; | |
5222 | dst.height = stream->timing.v_addressable; | |
5223 | ||
f4791779 HW |
5224 | if (dm_state) { |
5225 | rmx_type = dm_state->scaling; | |
5226 | if (rmx_type == RMX_ASPECT || rmx_type == RMX_OFF) { | |
5227 | if (src.width * dst.height < | |
5228 | src.height * dst.width) { | |
5229 | /* height needs less upscaling/more downscaling */ | |
5230 | dst.width = src.width * | |
5231 | dst.height / src.height; | |
5232 | } else { | |
5233 | /* width needs less upscaling/more downscaling */ | |
5234 | dst.height = src.height * | |
5235 | dst.width / src.width; | |
5236 | } | |
5237 | } else if (rmx_type == RMX_CENTER) { | |
5238 | dst = src; | |
e7b07cee | 5239 | } |
e7b07cee | 5240 | |
f4791779 HW |
5241 | dst.x = (stream->timing.h_addressable - dst.width) / 2; |
5242 | dst.y = (stream->timing.v_addressable - dst.height) / 2; | |
e7b07cee | 5243 | |
f4791779 HW |
5244 | if (dm_state->underscan_enable) { |
5245 | dst.x += dm_state->underscan_hborder / 2; | |
5246 | dst.y += dm_state->underscan_vborder / 2; | |
5247 | dst.width -= dm_state->underscan_hborder; | |
5248 | dst.height -= dm_state->underscan_vborder; | |
5249 | } | |
e7b07cee HW |
5250 | } |
5251 | ||
5252 | stream->src = src; | |
5253 | stream->dst = dst; | |
5254 | ||
4711c033 LT |
5255 | DRM_DEBUG_KMS("Destination Rectangle x:%d y:%d width:%d height:%d\n", |
5256 | dst.x, dst.y, dst.width, dst.height); | |
e7b07cee HW |
5257 | |
5258 | } | |
5259 | ||
3ee6b26b | 5260 | static enum dc_color_depth |
42ba01fc | 5261 | convert_color_depth_from_display_info(const struct drm_connector *connector, |
cbd14ae7 | 5262 | bool is_y420, int requested_bpc) |
e7b07cee | 5263 | { |
ae67558b | 5264 | u8 bpc; |
01c22997 | 5265 | |
1bc22f20 SW |
5266 | if (is_y420) { |
5267 | bpc = 8; | |
5268 | ||
5269 | /* Cap display bpc based on HDMI 2.0 HF-VSDB */ | |
5270 | if (connector->display_info.hdmi.y420_dc_modes & DRM_EDID_YCBCR420_DC_48) | |
5271 | bpc = 16; | |
5272 | else if (connector->display_info.hdmi.y420_dc_modes & DRM_EDID_YCBCR420_DC_36) | |
5273 | bpc = 12; | |
5274 | else if (connector->display_info.hdmi.y420_dc_modes & DRM_EDID_YCBCR420_DC_30) | |
5275 | bpc = 10; | |
5276 | } else { | |
5277 | bpc = (uint8_t)connector->display_info.bpc; | |
5278 | /* Assume 8 bpc by default if no bpc is specified. */ | |
5279 | bpc = bpc ? bpc : 8; | |
5280 | } | |
e7b07cee | 5281 | |
cbd14ae7 | 5282 | if (requested_bpc > 0) { |
01c22997 NK |
5283 | /* |
5284 | * Cap display bpc based on the user requested value. | |
5285 | * | |
5286 | * The value for state->max_bpc may not correctly updated | |
5287 | * depending on when the connector gets added to the state | |
5288 | * or if this was called outside of atomic check, so it | |
5289 | * can't be used directly. | |
5290 | */ | |
cbd14ae7 | 5291 | bpc = min_t(u8, bpc, requested_bpc); |
01c22997 | 5292 | |
1825fd34 NK |
5293 | /* Round down to the nearest even number. */ |
5294 | bpc = bpc - (bpc & 1); | |
5295 | } | |
07e3a1cf | 5296 | |
e7b07cee HW |
5297 | switch (bpc) { |
5298 | case 0: | |
1f6010a9 DF |
5299 | /* |
5300 | * Temporary Work around, DRM doesn't parse color depth for | |
e7b07cee HW |
5301 | * EDID revision before 1.4 |
5302 | * TODO: Fix edid parsing | |
5303 | */ | |
5304 | return COLOR_DEPTH_888; | |
5305 | case 6: | |
5306 | return COLOR_DEPTH_666; | |
5307 | case 8: | |
5308 | return COLOR_DEPTH_888; | |
5309 | case 10: | |
5310 | return COLOR_DEPTH_101010; | |
5311 | case 12: | |
5312 | return COLOR_DEPTH_121212; | |
5313 | case 14: | |
5314 | return COLOR_DEPTH_141414; | |
5315 | case 16: | |
5316 | return COLOR_DEPTH_161616; | |
5317 | default: | |
5318 | return COLOR_DEPTH_UNDEFINED; | |
5319 | } | |
5320 | } | |
5321 | ||
3ee6b26b AD |
5322 | static enum dc_aspect_ratio |
5323 | get_aspect_ratio(const struct drm_display_mode *mode_in) | |
e7b07cee | 5324 | { |
e11d4147 LSL |
5325 | /* 1-1 mapping, since both enums follow the HDMI spec. */ |
5326 | return (enum dc_aspect_ratio) mode_in->picture_aspect_ratio; | |
e7b07cee HW |
5327 | } |
5328 | ||
3ee6b26b AD |
5329 | static enum dc_color_space |
5330 | get_output_color_space(const struct dc_crtc_timing *dc_crtc_timing) | |
e7b07cee HW |
5331 | { |
5332 | enum dc_color_space color_space = COLOR_SPACE_SRGB; | |
5333 | ||
5334 | switch (dc_crtc_timing->pixel_encoding) { | |
5335 | case PIXEL_ENCODING_YCBCR422: | |
5336 | case PIXEL_ENCODING_YCBCR444: | |
5337 | case PIXEL_ENCODING_YCBCR420: | |
5338 | { | |
5339 | /* | |
5340 | * 27030khz is the separation point between HDTV and SDTV | |
5341 | * according to HDMI spec, we use YCbCr709 and YCbCr601 | |
5342 | * respectively | |
5343 | */ | |
380604e2 | 5344 | if (dc_crtc_timing->pix_clk_100hz > 270300) { |
e7b07cee HW |
5345 | if (dc_crtc_timing->flags.Y_ONLY) |
5346 | color_space = | |
5347 | COLOR_SPACE_YCBCR709_LIMITED; | |
5348 | else | |
5349 | color_space = COLOR_SPACE_YCBCR709; | |
5350 | } else { | |
5351 | if (dc_crtc_timing->flags.Y_ONLY) | |
5352 | color_space = | |
5353 | COLOR_SPACE_YCBCR601_LIMITED; | |
5354 | else | |
5355 | color_space = COLOR_SPACE_YCBCR601; | |
5356 | } | |
5357 | ||
5358 | } | |
5359 | break; | |
5360 | case PIXEL_ENCODING_RGB: | |
5361 | color_space = COLOR_SPACE_SRGB; | |
5362 | break; | |
5363 | ||
5364 | default: | |
5365 | WARN_ON(1); | |
5366 | break; | |
5367 | } | |
5368 | ||
5369 | return color_space; | |
5370 | } | |
5371 | ||
ea117312 TA |
5372 | static bool adjust_colour_depth_from_display_info( |
5373 | struct dc_crtc_timing *timing_out, | |
5374 | const struct drm_display_info *info) | |
400443e8 | 5375 | { |
ea117312 | 5376 | enum dc_color_depth depth = timing_out->display_color_depth; |
400443e8 | 5377 | int normalized_clk; |
400443e8 | 5378 | do { |
380604e2 | 5379 | normalized_clk = timing_out->pix_clk_100hz / 10; |
400443e8 ML |
5380 | /* YCbCr 4:2:0 requires additional adjustment of 1/2 */ |
5381 | if (timing_out->pixel_encoding == PIXEL_ENCODING_YCBCR420) | |
5382 | normalized_clk /= 2; | |
5383 | /* Adjusting pix clock following on HDMI spec based on colour depth */ | |
ea117312 TA |
5384 | switch (depth) { |
5385 | case COLOR_DEPTH_888: | |
5386 | break; | |
400443e8 ML |
5387 | case COLOR_DEPTH_101010: |
5388 | normalized_clk = (normalized_clk * 30) / 24; | |
5389 | break; | |
5390 | case COLOR_DEPTH_121212: | |
5391 | normalized_clk = (normalized_clk * 36) / 24; | |
5392 | break; | |
5393 | case COLOR_DEPTH_161616: | |
5394 | normalized_clk = (normalized_clk * 48) / 24; | |
5395 | break; | |
5396 | default: | |
ea117312 TA |
5397 | /* The above depths are the only ones valid for HDMI. */ |
5398 | return false; | |
400443e8 | 5399 | } |
ea117312 TA |
5400 | if (normalized_clk <= info->max_tmds_clock) { |
5401 | timing_out->display_color_depth = depth; | |
5402 | return true; | |
5403 | } | |
5404 | } while (--depth > COLOR_DEPTH_666); | |
5405 | return false; | |
400443e8 | 5406 | } |
e7b07cee | 5407 | |
42ba01fc NK |
5408 | static void fill_stream_properties_from_drm_display_mode( |
5409 | struct dc_stream_state *stream, | |
5410 | const struct drm_display_mode *mode_in, | |
5411 | const struct drm_connector *connector, | |
5412 | const struct drm_connector_state *connector_state, | |
cbd14ae7 SW |
5413 | const struct dc_stream_state *old_stream, |
5414 | int requested_bpc) | |
e7b07cee HW |
5415 | { |
5416 | struct dc_crtc_timing *timing_out = &stream->timing; | |
fe61a2f1 | 5417 | const struct drm_display_info *info = &connector->display_info; |
d4252eee | 5418 | struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); |
1cb1d477 WL |
5419 | struct hdmi_vendor_infoframe hv_frame; |
5420 | struct hdmi_avi_infoframe avi_frame; | |
e7b07cee | 5421 | |
acf83f86 WL |
5422 | memset(&hv_frame, 0, sizeof(hv_frame)); |
5423 | memset(&avi_frame, 0, sizeof(avi_frame)); | |
5424 | ||
e7b07cee HW |
5425 | timing_out->h_border_left = 0; |
5426 | timing_out->h_border_right = 0; | |
5427 | timing_out->v_border_top = 0; | |
5428 | timing_out->v_border_bottom = 0; | |
5429 | /* TODO: un-hardcode */ | |
fe61a2f1 | 5430 | if (drm_mode_is_420_only(info, mode_in) |
ceb3dbb4 | 5431 | && stream->signal == SIGNAL_TYPE_HDMI_TYPE_A) |
fe61a2f1 | 5432 | timing_out->pixel_encoding = PIXEL_ENCODING_YCBCR420; |
d4252eee SW |
5433 | else if (drm_mode_is_420_also(info, mode_in) |
5434 | && aconnector->force_yuv420_output) | |
5435 | timing_out->pixel_encoding = PIXEL_ENCODING_YCBCR420; | |
c03d0b52 | 5436 | else if ((connector->display_info.color_formats & DRM_COLOR_FORMAT_YCBCR444) |
ceb3dbb4 | 5437 | && stream->signal == SIGNAL_TYPE_HDMI_TYPE_A) |
e7b07cee HW |
5438 | timing_out->pixel_encoding = PIXEL_ENCODING_YCBCR444; |
5439 | else | |
5440 | timing_out->pixel_encoding = PIXEL_ENCODING_RGB; | |
5441 | ||
5442 | timing_out->timing_3d_format = TIMING_3D_FORMAT_NONE; | |
5443 | timing_out->display_color_depth = convert_color_depth_from_display_info( | |
cbd14ae7 SW |
5444 | connector, |
5445 | (timing_out->pixel_encoding == PIXEL_ENCODING_YCBCR420), | |
5446 | requested_bpc); | |
e7b07cee HW |
5447 | timing_out->scan_type = SCANNING_TYPE_NODATA; |
5448 | timing_out->hdmi_vic = 0; | |
b333730d | 5449 | |
5d945cbc | 5450 | if (old_stream) { |
b333730d BL |
5451 | timing_out->vic = old_stream->timing.vic; |
5452 | timing_out->flags.HSYNC_POSITIVE_POLARITY = old_stream->timing.flags.HSYNC_POSITIVE_POLARITY; | |
5453 | timing_out->flags.VSYNC_POSITIVE_POLARITY = old_stream->timing.flags.VSYNC_POSITIVE_POLARITY; | |
5454 | } else { | |
5455 | timing_out->vic = drm_match_cea_mode(mode_in); | |
5456 | if (mode_in->flags & DRM_MODE_FLAG_PHSYNC) | |
5457 | timing_out->flags.HSYNC_POSITIVE_POLARITY = 1; | |
5458 | if (mode_in->flags & DRM_MODE_FLAG_PVSYNC) | |
5459 | timing_out->flags.VSYNC_POSITIVE_POLARITY = 1; | |
5460 | } | |
e7b07cee | 5461 | |
1cb1d477 WL |
5462 | if (stream->signal == SIGNAL_TYPE_HDMI_TYPE_A) { |
5463 | drm_hdmi_avi_infoframe_from_display_mode(&avi_frame, (struct drm_connector *)connector, mode_in); | |
5464 | timing_out->vic = avi_frame.video_code; | |
5465 | drm_hdmi_vendor_infoframe_from_display_mode(&hv_frame, (struct drm_connector *)connector, mode_in); | |
5466 | timing_out->hdmi_vic = hv_frame.vic; | |
5467 | } | |
5468 | ||
fe8858bb NC |
5469 | if (is_freesync_video_mode(mode_in, aconnector)) { |
5470 | timing_out->h_addressable = mode_in->hdisplay; | |
5471 | timing_out->h_total = mode_in->htotal; | |
5472 | timing_out->h_sync_width = mode_in->hsync_end - mode_in->hsync_start; | |
5473 | timing_out->h_front_porch = mode_in->hsync_start - mode_in->hdisplay; | |
5474 | timing_out->v_total = mode_in->vtotal; | |
5475 | timing_out->v_addressable = mode_in->vdisplay; | |
5476 | timing_out->v_front_porch = mode_in->vsync_start - mode_in->vdisplay; | |
5477 | timing_out->v_sync_width = mode_in->vsync_end - mode_in->vsync_start; | |
5478 | timing_out->pix_clk_100hz = mode_in->clock * 10; | |
5479 | } else { | |
5480 | timing_out->h_addressable = mode_in->crtc_hdisplay; | |
5481 | timing_out->h_total = mode_in->crtc_htotal; | |
5482 | timing_out->h_sync_width = mode_in->crtc_hsync_end - mode_in->crtc_hsync_start; | |
5483 | timing_out->h_front_porch = mode_in->crtc_hsync_start - mode_in->crtc_hdisplay; | |
5484 | timing_out->v_total = mode_in->crtc_vtotal; | |
5485 | timing_out->v_addressable = mode_in->crtc_vdisplay; | |
5486 | timing_out->v_front_porch = mode_in->crtc_vsync_start - mode_in->crtc_vdisplay; | |
5487 | timing_out->v_sync_width = mode_in->crtc_vsync_end - mode_in->crtc_vsync_start; | |
5488 | timing_out->pix_clk_100hz = mode_in->crtc_clock * 10; | |
5489 | } | |
a85ba005 | 5490 | |
e7b07cee | 5491 | timing_out->aspect_ratio = get_aspect_ratio(mode_in); |
e7b07cee | 5492 | |
e43a432c AK |
5493 | stream->out_transfer_func->type = TF_TYPE_PREDEFINED; |
5494 | stream->out_transfer_func->tf = TRANSFER_FUNCTION_SRGB; | |
ea117312 TA |
5495 | if (stream->signal == SIGNAL_TYPE_HDMI_TYPE_A) { |
5496 | if (!adjust_colour_depth_from_display_info(timing_out, info) && | |
5497 | drm_mode_is_420_also(info, mode_in) && | |
5498 | timing_out->pixel_encoding != PIXEL_ENCODING_YCBCR420) { | |
5499 | timing_out->pixel_encoding = PIXEL_ENCODING_YCBCR420; | |
5500 | adjust_colour_depth_from_display_info(timing_out, info); | |
5501 | } | |
5502 | } | |
766f1792 JA |
5503 | |
5504 | stream->output_color_space = get_output_color_space(timing_out); | |
e7b07cee HW |
5505 | } |
5506 | ||
3ee6b26b AD |
5507 | static void fill_audio_info(struct audio_info *audio_info, |
5508 | const struct drm_connector *drm_connector, | |
5509 | const struct dc_sink *dc_sink) | |
e7b07cee HW |
5510 | { |
5511 | int i = 0; | |
5512 | int cea_revision = 0; | |
5513 | const struct dc_edid_caps *edid_caps = &dc_sink->edid_caps; | |
5514 | ||
5515 | audio_info->manufacture_id = edid_caps->manufacturer_id; | |
5516 | audio_info->product_id = edid_caps->product_id; | |
5517 | ||
5518 | cea_revision = drm_connector->display_info.cea_rev; | |
5519 | ||
090afc1e | 5520 | strscpy(audio_info->display_name, |
d2b2562c | 5521 | edid_caps->display_name, |
090afc1e | 5522 | AUDIO_INFO_DISPLAY_NAME_SIZE_IN_CHARS); |
e7b07cee | 5523 | |
b830ebc9 | 5524 | if (cea_revision >= 3) { |
e7b07cee HW |
5525 | audio_info->mode_count = edid_caps->audio_mode_count; |
5526 | ||
5527 | for (i = 0; i < audio_info->mode_count; ++i) { | |
5528 | audio_info->modes[i].format_code = | |
5529 | (enum audio_format_code) | |
5530 | (edid_caps->audio_modes[i].format_code); | |
5531 | audio_info->modes[i].channel_count = | |
5532 | edid_caps->audio_modes[i].channel_count; | |
5533 | audio_info->modes[i].sample_rates.all = | |
5534 | edid_caps->audio_modes[i].sample_rate; | |
5535 | audio_info->modes[i].sample_size = | |
5536 | edid_caps->audio_modes[i].sample_size; | |
5537 | } | |
5538 | } | |
5539 | ||
5540 | audio_info->flags.all = edid_caps->speaker_flags; | |
5541 | ||
5542 | /* TODO: We only check for the progressive mode, check for interlace mode too */ | |
b830ebc9 | 5543 | if (drm_connector->latency_present[0]) { |
e7b07cee HW |
5544 | audio_info->video_latency = drm_connector->video_latency[0]; |
5545 | audio_info->audio_latency = drm_connector->audio_latency[0]; | |
5546 | } | |
5547 | ||
5548 | /* TODO: For DP, video and audio latency should be calculated from DPCD caps */ | |
5549 | ||
5550 | } | |
5551 | ||
3ee6b26b AD |
5552 | static void |
5553 | copy_crtc_timing_for_drm_display_mode(const struct drm_display_mode *src_mode, | |
5554 | struct drm_display_mode *dst_mode) | |
e7b07cee HW |
5555 | { |
5556 | dst_mode->crtc_hdisplay = src_mode->crtc_hdisplay; | |
5557 | dst_mode->crtc_vdisplay = src_mode->crtc_vdisplay; | |
5558 | dst_mode->crtc_clock = src_mode->crtc_clock; | |
5559 | dst_mode->crtc_hblank_start = src_mode->crtc_hblank_start; | |
5560 | dst_mode->crtc_hblank_end = src_mode->crtc_hblank_end; | |
b830ebc9 | 5561 | dst_mode->crtc_hsync_start = src_mode->crtc_hsync_start; |
e7b07cee HW |
5562 | dst_mode->crtc_hsync_end = src_mode->crtc_hsync_end; |
5563 | dst_mode->crtc_htotal = src_mode->crtc_htotal; | |
5564 | dst_mode->crtc_hskew = src_mode->crtc_hskew; | |
5565 | dst_mode->crtc_vblank_start = src_mode->crtc_vblank_start; | |
5566 | dst_mode->crtc_vblank_end = src_mode->crtc_vblank_end; | |
5567 | dst_mode->crtc_vsync_start = src_mode->crtc_vsync_start; | |
5568 | dst_mode->crtc_vsync_end = src_mode->crtc_vsync_end; | |
5569 | dst_mode->crtc_vtotal = src_mode->crtc_vtotal; | |
5570 | } | |
5571 | ||
3ee6b26b AD |
5572 | static void |
5573 | decide_crtc_timing_for_drm_display_mode(struct drm_display_mode *drm_mode, | |
5574 | const struct drm_display_mode *native_mode, | |
5575 | bool scale_enabled) | |
e7b07cee HW |
5576 | { |
5577 | if (scale_enabled) { | |
5578 | copy_crtc_timing_for_drm_display_mode(native_mode, drm_mode); | |
5579 | } else if (native_mode->clock == drm_mode->clock && | |
5580 | native_mode->htotal == drm_mode->htotal && | |
5581 | native_mode->vtotal == drm_mode->vtotal) { | |
5582 | copy_crtc_timing_for_drm_display_mode(native_mode, drm_mode); | |
5583 | } else { | |
5584 | /* no scaling nor amdgpu inserted, no need to patch */ | |
5585 | } | |
5586 | } | |
5587 | ||
aed15309 ML |
5588 | static struct dc_sink * |
5589 | create_fake_sink(struct amdgpu_dm_connector *aconnector) | |
2e0ac3d6 | 5590 | { |
2e0ac3d6 | 5591 | struct dc_sink_init_data sink_init_data = { 0 }; |
aed15309 | 5592 | struct dc_sink *sink = NULL; |
2e0ac3d6 HW |
5593 | sink_init_data.link = aconnector->dc_link; |
5594 | sink_init_data.sink_signal = aconnector->dc_link->connector_signal; | |
5595 | ||
5596 | sink = dc_sink_create(&sink_init_data); | |
423788c7 | 5597 | if (!sink) { |
2e0ac3d6 | 5598 | DRM_ERROR("Failed to create sink!\n"); |
aed15309 | 5599 | return NULL; |
423788c7 | 5600 | } |
2e0ac3d6 | 5601 | sink->sink_signal = SIGNAL_TYPE_VIRTUAL; |
423788c7 | 5602 | |
aed15309 | 5603 | return sink; |
2e0ac3d6 HW |
5604 | } |
5605 | ||
fa2123db ML |
5606 | static void set_multisync_trigger_params( |
5607 | struct dc_stream_state *stream) | |
5608 | { | |
ec372186 ML |
5609 | struct dc_stream_state *master = NULL; |
5610 | ||
fa2123db | 5611 | if (stream->triggered_crtc_reset.enabled) { |
ec372186 ML |
5612 | master = stream->triggered_crtc_reset.event_source; |
5613 | stream->triggered_crtc_reset.event = | |
5614 | master->timing.flags.VSYNC_POSITIVE_POLARITY ? | |
5615 | CRTC_EVENT_VSYNC_RISING : CRTC_EVENT_VSYNC_FALLING; | |
5616 | stream->triggered_crtc_reset.delay = TRIGGER_DELAY_NEXT_PIXEL; | |
fa2123db ML |
5617 | } |
5618 | } | |
5619 | ||
5620 | static void set_master_stream(struct dc_stream_state *stream_set[], | |
5621 | int stream_count) | |
5622 | { | |
5623 | int j, highest_rfr = 0, master_stream = 0; | |
5624 | ||
5625 | for (j = 0; j < stream_count; j++) { | |
5626 | if (stream_set[j] && stream_set[j]->triggered_crtc_reset.enabled) { | |
5627 | int refresh_rate = 0; | |
5628 | ||
380604e2 | 5629 | refresh_rate = (stream_set[j]->timing.pix_clk_100hz*100)/ |
fa2123db ML |
5630 | (stream_set[j]->timing.h_total*stream_set[j]->timing.v_total); |
5631 | if (refresh_rate > highest_rfr) { | |
5632 | highest_rfr = refresh_rate; | |
5633 | master_stream = j; | |
5634 | } | |
5635 | } | |
5636 | } | |
5637 | for (j = 0; j < stream_count; j++) { | |
03736f4c | 5638 | if (stream_set[j]) |
fa2123db ML |
5639 | stream_set[j]->triggered_crtc_reset.event_source = stream_set[master_stream]; |
5640 | } | |
5641 | } | |
5642 | ||
5643 | static void dm_enable_per_frame_crtc_master_sync(struct dc_state *context) | |
5644 | { | |
5645 | int i = 0; | |
ec372186 | 5646 | struct dc_stream_state *stream; |
fa2123db ML |
5647 | |
5648 | if (context->stream_count < 2) | |
5649 | return; | |
5650 | for (i = 0; i < context->stream_count ; i++) { | |
5651 | if (!context->streams[i]) | |
5652 | continue; | |
1f6010a9 DF |
5653 | /* |
5654 | * TODO: add a function to read AMD VSDB bits and set | |
fa2123db | 5655 | * crtc_sync_master.multi_sync_enabled flag |
1f6010a9 | 5656 | * For now it's set to false |
fa2123db | 5657 | */ |
fa2123db | 5658 | } |
ec372186 | 5659 | |
fa2123db | 5660 | set_master_stream(context->streams, context->stream_count); |
ec372186 ML |
5661 | |
5662 | for (i = 0; i < context->stream_count ; i++) { | |
5663 | stream = context->streams[i]; | |
5664 | ||
5665 | if (!stream) | |
5666 | continue; | |
5667 | ||
5668 | set_multisync_trigger_params(stream); | |
5669 | } | |
fa2123db ML |
5670 | } |
5671 | ||
5d945cbc RS |
5672 | /** |
5673 | * DOC: FreeSync Video | |
5674 | * | |
5675 | * When a userspace application wants to play a video, the content follows a | |
5676 | * standard format definition that usually specifies the FPS for that format. | |
5677 | * The below list illustrates some video format and the expected FPS, | |
5678 | * respectively: | |
5679 | * | |
5680 | * - TV/NTSC (23.976 FPS) | |
5681 | * - Cinema (24 FPS) | |
5682 | * - TV/PAL (25 FPS) | |
5683 | * - TV/NTSC (29.97 FPS) | |
5684 | * - TV/NTSC (30 FPS) | |
5685 | * - Cinema HFR (48 FPS) | |
5686 | * - TV/PAL (50 FPS) | |
5687 | * - Commonly used (60 FPS) | |
5688 | * - Multiples of 24 (48,72,96 FPS) | |
5689 | * | |
5690 | * The list of standards video format is not huge and can be added to the | |
5691 | * connector modeset list beforehand. With that, userspace can leverage | |
5692 | * FreeSync to extends the front porch in order to attain the target refresh | |
5693 | * rate. Such a switch will happen seamlessly, without screen blanking or | |
5694 | * reprogramming of the output in any other way. If the userspace requests a | |
5695 | * modesetting change compatible with FreeSync modes that only differ in the | |
5696 | * refresh rate, DC will skip the full update and avoid blink during the | |
5697 | * transition. For example, the video player can change the modesetting from | |
5698 | * 60Hz to 30Hz for playing TV/NTSC content when it goes full screen without | |
5699 | * causing any display blink. This same concept can be applied to a mode | |
5700 | * setting change. | |
5701 | */ | |
5702 | static struct drm_display_mode * | |
5703 | get_highest_refresh_rate_mode(struct amdgpu_dm_connector *aconnector, | |
5704 | bool use_probed_modes) | |
5705 | { | |
5706 | struct drm_display_mode *m, *m_pref = NULL; | |
5707 | u16 current_refresh, highest_refresh; | |
5708 | struct list_head *list_head = use_probed_modes ? | |
5709 | &aconnector->base.probed_modes : | |
5710 | &aconnector->base.modes; | |
5711 | ||
5712 | if (aconnector->freesync_vid_base.clock != 0) | |
5713 | return &aconnector->freesync_vid_base; | |
5714 | ||
5715 | /* Find the preferred mode */ | |
5716 | list_for_each_entry (m, list_head, head) { | |
5717 | if (m->type & DRM_MODE_TYPE_PREFERRED) { | |
5718 | m_pref = m; | |
5719 | break; | |
5720 | } | |
5721 | } | |
5722 | ||
5723 | if (!m_pref) { | |
5724 | /* Probably an EDID with no preferred mode. Fallback to first entry */ | |
5725 | m_pref = list_first_entry_or_null( | |
5726 | &aconnector->base.modes, struct drm_display_mode, head); | |
5727 | if (!m_pref) { | |
5728 | DRM_DEBUG_DRIVER("No preferred mode found in EDID\n"); | |
5729 | return NULL; | |
5730 | } | |
5731 | } | |
5732 | ||
5733 | highest_refresh = drm_mode_vrefresh(m_pref); | |
5734 | ||
5735 | /* | |
5736 | * Find the mode with highest refresh rate with same resolution. | |
5737 | * For some monitors, preferred mode is not the mode with highest | |
5738 | * supported refresh rate. | |
5739 | */ | |
5740 | list_for_each_entry (m, list_head, head) { | |
5741 | current_refresh = drm_mode_vrefresh(m); | |
5742 | ||
5743 | if (m->hdisplay == m_pref->hdisplay && | |
5744 | m->vdisplay == m_pref->vdisplay && | |
5745 | highest_refresh < current_refresh) { | |
5746 | highest_refresh = current_refresh; | |
5747 | m_pref = m; | |
5748 | } | |
5749 | } | |
5750 | ||
5751 | drm_mode_copy(&aconnector->freesync_vid_base, m_pref); | |
5752 | return m_pref; | |
5753 | } | |
5754 | ||
5755 | static bool is_freesync_video_mode(const struct drm_display_mode *mode, | |
5756 | struct amdgpu_dm_connector *aconnector) | |
5757 | { | |
5758 | struct drm_display_mode *high_mode; | |
5759 | int timing_diff; | |
5760 | ||
5761 | high_mode = get_highest_refresh_rate_mode(aconnector, false); | |
5762 | if (!high_mode || !mode) | |
5763 | return false; | |
5764 | ||
5765 | timing_diff = high_mode->vtotal - mode->vtotal; | |
5766 | ||
5767 | if (high_mode->clock == 0 || high_mode->clock != mode->clock || | |
5768 | high_mode->hdisplay != mode->hdisplay || | |
5769 | high_mode->vdisplay != mode->vdisplay || | |
5770 | high_mode->hsync_start != mode->hsync_start || | |
5771 | high_mode->hsync_end != mode->hsync_end || | |
5772 | high_mode->htotal != mode->htotal || | |
5773 | high_mode->hskew != mode->hskew || | |
5774 | high_mode->vscan != mode->vscan || | |
5775 | high_mode->vsync_start - mode->vsync_start != timing_diff || | |
5776 | high_mode->vsync_end - mode->vsync_end != timing_diff) | |
5777 | return false; | |
5778 | else | |
5779 | return true; | |
5780 | } | |
5781 | ||
998b7ad2 | 5782 | static void update_dsc_caps(struct amdgpu_dm_connector *aconnector, |
5d945cbc RS |
5783 | struct dc_sink *sink, struct dc_stream_state *stream, |
5784 | struct dsc_dec_dpcd_caps *dsc_caps) | |
998b7ad2 FZ |
5785 | { |
5786 | stream->timing.flags.DSC = 0; | |
63ad5371 | 5787 | dsc_caps->is_dsc_supported = false; |
998b7ad2 | 5788 | |
2665f63a | 5789 | if (aconnector->dc_link && (sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT || |
5d945cbc | 5790 | sink->sink_signal == SIGNAL_TYPE_EDP)) { |
50b1f44e FZ |
5791 | if (sink->link->dpcd_caps.dongle_type == DISPLAY_DONGLE_NONE || |
5792 | sink->link->dpcd_caps.dongle_type == DISPLAY_DONGLE_DP_HDMI_CONVERTER) | |
5793 | dc_dsc_parse_dsc_dpcd(aconnector->dc_link->ctx->dc, | |
5794 | aconnector->dc_link->dpcd_caps.dsc_caps.dsc_basic_caps.raw, | |
5795 | aconnector->dc_link->dpcd_caps.dsc_caps.dsc_branch_decoder_caps.raw, | |
5796 | dsc_caps); | |
998b7ad2 FZ |
5797 | } |
5798 | } | |
5799 | ||
5d945cbc | 5800 | |
2665f63a ML |
5801 | static void apply_dsc_policy_for_edp(struct amdgpu_dm_connector *aconnector, |
5802 | struct dc_sink *sink, struct dc_stream_state *stream, | |
5803 | struct dsc_dec_dpcd_caps *dsc_caps, | |
5804 | uint32_t max_dsc_target_bpp_limit_override) | |
5805 | { | |
5806 | const struct dc_link_settings *verified_link_cap = NULL; | |
ae67558b SS |
5807 | u32 link_bw_in_kbps; |
5808 | u32 edp_min_bpp_x16, edp_max_bpp_x16; | |
2665f63a ML |
5809 | struct dc *dc = sink->ctx->dc; |
5810 | struct dc_dsc_bw_range bw_range = {0}; | |
5811 | struct dc_dsc_config dsc_cfg = {0}; | |
de534c1c MH |
5812 | struct dc_dsc_config_options dsc_options = {0}; |
5813 | ||
5814 | dc_dsc_get_default_config_option(dc, &dsc_options); | |
5815 | dsc_options.max_target_bpp_limit_override_x16 = max_dsc_target_bpp_limit_override * 16; | |
2665f63a ML |
5816 | |
5817 | verified_link_cap = dc_link_get_link_cap(stream->link); | |
5818 | link_bw_in_kbps = dc_link_bandwidth_kbps(stream->link, verified_link_cap); | |
5819 | edp_min_bpp_x16 = 8 * 16; | |
5820 | edp_max_bpp_x16 = 8 * 16; | |
5821 | ||
5822 | if (edp_max_bpp_x16 > dsc_caps->edp_max_bits_per_pixel) | |
5823 | edp_max_bpp_x16 = dsc_caps->edp_max_bits_per_pixel; | |
5824 | ||
5825 | if (edp_max_bpp_x16 < edp_min_bpp_x16) | |
5826 | edp_min_bpp_x16 = edp_max_bpp_x16; | |
5827 | ||
5828 | if (dc_dsc_compute_bandwidth_range(dc->res_pool->dscs[0], | |
5829 | dc->debug.dsc_min_slice_height_override, | |
5830 | edp_min_bpp_x16, edp_max_bpp_x16, | |
5831 | dsc_caps, | |
5832 | &stream->timing, | |
5833 | &bw_range)) { | |
5834 | ||
5835 | if (bw_range.max_kbps < link_bw_in_kbps) { | |
5836 | if (dc_dsc_compute_config(dc->res_pool->dscs[0], | |
5837 | dsc_caps, | |
de534c1c | 5838 | &dsc_options, |
2665f63a ML |
5839 | 0, |
5840 | &stream->timing, | |
5841 | &dsc_cfg)) { | |
5842 | stream->timing.dsc_cfg = dsc_cfg; | |
5843 | stream->timing.flags.DSC = 1; | |
5844 | stream->timing.dsc_cfg.bits_per_pixel = edp_max_bpp_x16; | |
5845 | } | |
5846 | return; | |
5847 | } | |
5848 | } | |
5849 | ||
5850 | if (dc_dsc_compute_config(dc->res_pool->dscs[0], | |
5851 | dsc_caps, | |
de534c1c | 5852 | &dsc_options, |
2665f63a ML |
5853 | link_bw_in_kbps, |
5854 | &stream->timing, | |
5855 | &dsc_cfg)) { | |
5856 | stream->timing.dsc_cfg = dsc_cfg; | |
5857 | stream->timing.flags.DSC = 1; | |
5858 | } | |
5859 | } | |
5860 | ||
5d945cbc | 5861 | |
998b7ad2 | 5862 | static void apply_dsc_policy_for_stream(struct amdgpu_dm_connector *aconnector, |
5d945cbc RS |
5863 | struct dc_sink *sink, struct dc_stream_state *stream, |
5864 | struct dsc_dec_dpcd_caps *dsc_caps) | |
998b7ad2 FZ |
5865 | { |
5866 | struct drm_connector *drm_connector = &aconnector->base; | |
ae67558b | 5867 | u32 link_bandwidth_kbps; |
2665f63a | 5868 | struct dc *dc = sink->ctx->dc; |
ae67558b SS |
5869 | u32 max_supported_bw_in_kbps, timing_bw_in_kbps; |
5870 | u32 dsc_max_supported_bw_in_kbps; | |
5871 | u32 max_dsc_target_bpp_limit_override = | |
6e5abe94 | 5872 | drm_connector->display_info.max_dsc_bpp; |
de534c1c MH |
5873 | struct dc_dsc_config_options dsc_options = {0}; |
5874 | ||
5875 | dc_dsc_get_default_config_option(dc, &dsc_options); | |
5876 | dsc_options.max_target_bpp_limit_override_x16 = max_dsc_target_bpp_limit_override * 16; | |
998b7ad2 FZ |
5877 | |
5878 | link_bandwidth_kbps = dc_link_bandwidth_kbps(aconnector->dc_link, | |
5879 | dc_link_get_link_cap(aconnector->dc_link)); | |
de7cc1b4 | 5880 | |
998b7ad2 FZ |
5881 | /* Set DSC policy according to dsc_clock_en */ |
5882 | dc_dsc_policy_set_enable_dsc_when_not_needed( | |
5883 | aconnector->dsc_settings.dsc_force_enable == DSC_CLK_FORCE_ENABLE); | |
5884 | ||
c17a34e0 IC |
5885 | if (aconnector->dc_link && sink->sink_signal == SIGNAL_TYPE_EDP && |
5886 | !aconnector->dc_link->panel_config.dsc.disable_dsc_edp && | |
2665f63a ML |
5887 | dc->caps.edp_dsc_support && aconnector->dsc_settings.dsc_force_enable != DSC_CLK_FORCE_DISABLE) { |
5888 | ||
5889 | apply_dsc_policy_for_edp(aconnector, sink, stream, dsc_caps, max_dsc_target_bpp_limit_override); | |
5890 | ||
5891 | } else if (aconnector->dc_link && sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT) { | |
50b1f44e FZ |
5892 | if (sink->link->dpcd_caps.dongle_type == DISPLAY_DONGLE_NONE) { |
5893 | if (dc_dsc_compute_config(aconnector->dc_link->ctx->dc->res_pool->dscs[0], | |
998b7ad2 | 5894 | dsc_caps, |
de534c1c | 5895 | &dsc_options, |
998b7ad2 FZ |
5896 | link_bandwidth_kbps, |
5897 | &stream->timing, | |
5898 | &stream->timing.dsc_cfg)) { | |
50b1f44e | 5899 | stream->timing.flags.DSC = 1; |
5d945cbc | 5900 | DRM_DEBUG_DRIVER("%s: [%s] DSC is selected from SST RX\n", __func__, drm_connector->name); |
50b1f44e FZ |
5901 | } |
5902 | } else if (sink->link->dpcd_caps.dongle_type == DISPLAY_DONGLE_DP_HDMI_CONVERTER) { | |
5903 | timing_bw_in_kbps = dc_bandwidth_in_kbps_from_timing(&stream->timing); | |
5904 | max_supported_bw_in_kbps = link_bandwidth_kbps; | |
5905 | dsc_max_supported_bw_in_kbps = link_bandwidth_kbps; | |
5906 | ||
5907 | if (timing_bw_in_kbps > max_supported_bw_in_kbps && | |
5908 | max_supported_bw_in_kbps > 0 && | |
5909 | dsc_max_supported_bw_in_kbps > 0) | |
5910 | if (dc_dsc_compute_config(aconnector->dc_link->ctx->dc->res_pool->dscs[0], | |
5911 | dsc_caps, | |
de534c1c | 5912 | &dsc_options, |
50b1f44e FZ |
5913 | dsc_max_supported_bw_in_kbps, |
5914 | &stream->timing, | |
5915 | &stream->timing.dsc_cfg)) { | |
5916 | stream->timing.flags.DSC = 1; | |
5917 | DRM_DEBUG_DRIVER("%s: [%s] DSC is selected from DP-HDMI PCON\n", | |
5918 | __func__, drm_connector->name); | |
5919 | } | |
998b7ad2 FZ |
5920 | } |
5921 | } | |
5922 | ||
5923 | /* Overwrite the stream flag if DSC is enabled through debugfs */ | |
5924 | if (aconnector->dsc_settings.dsc_force_enable == DSC_CLK_FORCE_ENABLE) | |
5925 | stream->timing.flags.DSC = 1; | |
5926 | ||
5d945cbc RS |
5927 | if (stream->timing.flags.DSC && aconnector->dsc_settings.dsc_num_slices_h) |
5928 | stream->timing.dsc_cfg.num_slices_h = aconnector->dsc_settings.dsc_num_slices_h; | |
a85ba005 | 5929 | |
5d945cbc RS |
5930 | if (stream->timing.flags.DSC && aconnector->dsc_settings.dsc_num_slices_v) |
5931 | stream->timing.dsc_cfg.num_slices_v = aconnector->dsc_settings.dsc_num_slices_v; | |
a85ba005 | 5932 | |
5d945cbc RS |
5933 | if (stream->timing.flags.DSC && aconnector->dsc_settings.dsc_bits_per_pixel) |
5934 | stream->timing.dsc_cfg.bits_per_pixel = aconnector->dsc_settings.dsc_bits_per_pixel; | |
a85ba005 NC |
5935 | } |
5936 | ||
f11d9373 | 5937 | static struct dc_stream_state * |
3ee6b26b AD |
5938 | create_stream_for_sink(struct amdgpu_dm_connector *aconnector, |
5939 | const struct drm_display_mode *drm_mode, | |
b333730d | 5940 | const struct dm_connector_state *dm_state, |
cbd14ae7 SW |
5941 | const struct dc_stream_state *old_stream, |
5942 | int requested_bpc) | |
e7b07cee HW |
5943 | { |
5944 | struct drm_display_mode *preferred_mode = NULL; | |
391ef035 | 5945 | struct drm_connector *drm_connector; |
42ba01fc NK |
5946 | const struct drm_connector_state *con_state = |
5947 | dm_state ? &dm_state->base : NULL; | |
0971c40e | 5948 | struct dc_stream_state *stream = NULL; |
0a204ce0 | 5949 | struct drm_display_mode mode; |
a85ba005 NC |
5950 | struct drm_display_mode saved_mode; |
5951 | struct drm_display_mode *freesync_mode = NULL; | |
e7b07cee | 5952 | bool native_mode_found = false; |
b0781603 NK |
5953 | bool recalculate_timing = false; |
5954 | bool scale = dm_state ? (dm_state->scaling != RMX_OFF) : false; | |
b333730d | 5955 | int mode_refresh; |
58124bf8 | 5956 | int preferred_refresh = 0; |
b1a98cf8 | 5957 | enum color_transfer_func tf = TRANSFER_FUNC_UNKNOWN; |
df2f1015 | 5958 | struct dsc_dec_dpcd_caps dsc_caps; |
5d945cbc | 5959 | |
aed15309 | 5960 | struct dc_sink *sink = NULL; |
a85ba005 | 5961 | |
0a204ce0 | 5962 | drm_mode_init(&mode, drm_mode); |
a85ba005 NC |
5963 | memset(&saved_mode, 0, sizeof(saved_mode)); |
5964 | ||
b830ebc9 | 5965 | if (aconnector == NULL) { |
e7b07cee | 5966 | DRM_ERROR("aconnector is NULL!\n"); |
64245fa7 | 5967 | return stream; |
e7b07cee HW |
5968 | } |
5969 | ||
e7b07cee | 5970 | drm_connector = &aconnector->base; |
2e0ac3d6 | 5971 | |
f4ac176e | 5972 | if (!aconnector->dc_sink) { |
e3fa5c4c JFZ |
5973 | sink = create_fake_sink(aconnector); |
5974 | if (!sink) | |
5975 | return stream; | |
aed15309 ML |
5976 | } else { |
5977 | sink = aconnector->dc_sink; | |
dcd5fb82 | 5978 | dc_sink_retain(sink); |
f4ac176e | 5979 | } |
2e0ac3d6 | 5980 | |
aed15309 | 5981 | stream = dc_create_stream_for_sink(sink); |
4562236b | 5982 | |
b830ebc9 | 5983 | if (stream == NULL) { |
e7b07cee | 5984 | DRM_ERROR("Failed to create stream for sink!\n"); |
aed15309 | 5985 | goto finish; |
e7b07cee HW |
5986 | } |
5987 | ||
ceb3dbb4 JL |
5988 | stream->dm_stream_context = aconnector; |
5989 | ||
4a36fcba WL |
5990 | stream->timing.flags.LTE_340MCSC_SCRAMBLE = |
5991 | drm_connector->display_info.hdmi.scdc.scrambling.low_rates; | |
5992 | ||
e7b07cee HW |
5993 | list_for_each_entry(preferred_mode, &aconnector->base.modes, head) { |
5994 | /* Search for preferred mode */ | |
5995 | if (preferred_mode->type & DRM_MODE_TYPE_PREFERRED) { | |
5996 | native_mode_found = true; | |
5997 | break; | |
5998 | } | |
5999 | } | |
6000 | if (!native_mode_found) | |
6001 | preferred_mode = list_first_entry_or_null( | |
6002 | &aconnector->base.modes, | |
6003 | struct drm_display_mode, | |
6004 | head); | |
6005 | ||
b333730d BL |
6006 | mode_refresh = drm_mode_vrefresh(&mode); |
6007 | ||
b830ebc9 | 6008 | if (preferred_mode == NULL) { |
1f6010a9 DF |
6009 | /* |
6010 | * This may not be an error, the use case is when we have no | |
e7b07cee HW |
6011 | * usermode calls to reset and set mode upon hotplug. In this |
6012 | * case, we call set mode ourselves to restore the previous mode | |
6013 | * and the modelist may not be filled in in time. | |
6014 | */ | |
f1ad2f5e | 6015 | DRM_DEBUG_DRIVER("No preferred mode found\n"); |
e7b07cee | 6016 | } else { |
4243c84a MD |
6017 | recalculate_timing = amdgpu_freesync_vid_mode && |
6018 | is_freesync_video_mode(&mode, aconnector); | |
a85ba005 NC |
6019 | if (recalculate_timing) { |
6020 | freesync_mode = get_highest_refresh_rate_mode(aconnector, false); | |
426c89aa VS |
6021 | drm_mode_copy(&saved_mode, &mode); |
6022 | drm_mode_copy(&mode, freesync_mode); | |
a85ba005 NC |
6023 | } else { |
6024 | decide_crtc_timing_for_drm_display_mode( | |
5d945cbc | 6025 | &mode, preferred_mode, scale); |
a85ba005 | 6026 | |
b0781603 NK |
6027 | preferred_refresh = drm_mode_vrefresh(preferred_mode); |
6028 | } | |
e7b07cee HW |
6029 | } |
6030 | ||
a85ba005 NC |
6031 | if (recalculate_timing) |
6032 | drm_mode_set_crtcinfo(&saved_mode, 0); | |
fe8858bb | 6033 | else if (!dm_state) |
f783577c JFZ |
6034 | drm_mode_set_crtcinfo(&mode, 0); |
6035 | ||
5d945cbc | 6036 | /* |
b333730d BL |
6037 | * If scaling is enabled and refresh rate didn't change |
6038 | * we copy the vic and polarities of the old timings | |
6039 | */ | |
b0781603 | 6040 | if (!scale || mode_refresh != preferred_refresh) |
a85ba005 NC |
6041 | fill_stream_properties_from_drm_display_mode( |
6042 | stream, &mode, &aconnector->base, con_state, NULL, | |
6043 | requested_bpc); | |
b333730d | 6044 | else |
a85ba005 NC |
6045 | fill_stream_properties_from_drm_display_mode( |
6046 | stream, &mode, &aconnector->base, con_state, old_stream, | |
6047 | requested_bpc); | |
b333730d | 6048 | |
028c4ccf QZ |
6049 | if (aconnector->timing_changed) { |
6050 | DC_LOG_DEBUG("%s: overriding timing for automated test, bpc %d, changing to %d\n", | |
6051 | __func__, | |
6052 | stream->timing.display_color_depth, | |
6053 | aconnector->timing_requested->display_color_depth); | |
6054 | stream->timing = *aconnector->timing_requested; | |
6055 | } | |
6056 | ||
998b7ad2 FZ |
6057 | /* SST DSC determination policy */ |
6058 | update_dsc_caps(aconnector, sink, stream, &dsc_caps); | |
6059 | if (aconnector->dsc_settings.dsc_force_enable != DSC_CLK_FORCE_DISABLE && dsc_caps.is_dsc_supported) | |
6060 | apply_dsc_policy_for_stream(aconnector, sink, stream, &dsc_caps); | |
39a4eb85 | 6061 | |
e7b07cee HW |
6062 | update_stream_scaling_settings(&mode, dm_state, stream); |
6063 | ||
6064 | fill_audio_info( | |
6065 | &stream->audio_info, | |
6066 | drm_connector, | |
aed15309 | 6067 | sink); |
e7b07cee | 6068 | |
ceb3dbb4 | 6069 | update_stream_signal(stream, sink); |
9182b4cb | 6070 | |
d832fc3b | 6071 | if (stream->signal == SIGNAL_TYPE_HDMI_TYPE_A) |
75f77aaf WL |
6072 | mod_build_hf_vsif_infopacket(stream, &stream->vsp_infopacket); |
6073 | ||
8a488f5d RL |
6074 | if (stream->link->psr_settings.psr_feature_enabled) { |
6075 | // | |
6076 | // should decide stream support vsc sdp colorimetry capability | |
6077 | // before building vsc info packet | |
6078 | // | |
6079 | stream->use_vsc_sdp_for_colorimetry = false; | |
6080 | if (aconnector->dc_sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT_MST) { | |
6081 | stream->use_vsc_sdp_for_colorimetry = | |
6082 | aconnector->dc_sink->is_vsc_sdp_colorimetry_supported; | |
6083 | } else { | |
6084 | if (stream->link->dpcd_caps.dprx_feature.bits.VSC_SDP_COLORIMETRY_SUPPORTED) | |
6085 | stream->use_vsc_sdp_for_colorimetry = true; | |
8c322309 | 6086 | } |
b1a98cf8 MH |
6087 | if (stream->out_transfer_func->tf == TRANSFER_FUNCTION_GAMMA22) |
6088 | tf = TRANSFER_FUNC_GAMMA_22; | |
6089 | mod_build_vsc_infopacket(stream, &stream->vsc_infopacket, stream->output_color_space, tf); | |
1a365683 RL |
6090 | aconnector->psr_skip_count = AMDGPU_DM_PSR_ENTRY_DELAY; |
6091 | ||
8c322309 | 6092 | } |
aed15309 | 6093 | finish: |
dcd5fb82 | 6094 | dc_sink_release(sink); |
9e3efe3e | 6095 | |
e7b07cee HW |
6096 | return stream; |
6097 | } | |
6098 | ||
e7b07cee HW |
6099 | static enum drm_connector_status |
6100 | amdgpu_dm_connector_detect(struct drm_connector *connector, bool force) | |
6101 | { | |
6102 | bool connected; | |
c84dec2f | 6103 | struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); |
e7b07cee | 6104 | |
1f6010a9 DF |
6105 | /* |
6106 | * Notes: | |
e7b07cee HW |
6107 | * 1. This interface is NOT called in context of HPD irq. |
6108 | * 2. This interface *is called* in context of user-mode ioctl. Which | |
1f6010a9 DF |
6109 | * makes it a bad place for *any* MST-related activity. |
6110 | */ | |
e7b07cee | 6111 | |
8580d60b HW |
6112 | if (aconnector->base.force == DRM_FORCE_UNSPECIFIED && |
6113 | !aconnector->fake_enable) | |
e7b07cee HW |
6114 | connected = (aconnector->dc_sink != NULL); |
6115 | else | |
5d945cbc RS |
6116 | connected = (aconnector->base.force == DRM_FORCE_ON || |
6117 | aconnector->base.force == DRM_FORCE_ON_DIGITAL); | |
e7b07cee | 6118 | |
0f877894 OV |
6119 | update_subconnector_property(aconnector); |
6120 | ||
e7b07cee HW |
6121 | return (connected ? connector_status_connected : |
6122 | connector_status_disconnected); | |
6123 | } | |
6124 | ||
3ee6b26b AD |
6125 | int amdgpu_dm_connector_atomic_set_property(struct drm_connector *connector, |
6126 | struct drm_connector_state *connector_state, | |
6127 | struct drm_property *property, | |
6128 | uint64_t val) | |
e7b07cee HW |
6129 | { |
6130 | struct drm_device *dev = connector->dev; | |
1348969a | 6131 | struct amdgpu_device *adev = drm_to_adev(dev); |
e7b07cee HW |
6132 | struct dm_connector_state *dm_old_state = |
6133 | to_dm_connector_state(connector->state); | |
6134 | struct dm_connector_state *dm_new_state = | |
6135 | to_dm_connector_state(connector_state); | |
6136 | ||
6137 | int ret = -EINVAL; | |
6138 | ||
6139 | if (property == dev->mode_config.scaling_mode_property) { | |
6140 | enum amdgpu_rmx_type rmx_type; | |
6141 | ||
6142 | switch (val) { | |
6143 | case DRM_MODE_SCALE_CENTER: | |
6144 | rmx_type = RMX_CENTER; | |
6145 | break; | |
6146 | case DRM_MODE_SCALE_ASPECT: | |
6147 | rmx_type = RMX_ASPECT; | |
6148 | break; | |
6149 | case DRM_MODE_SCALE_FULLSCREEN: | |
6150 | rmx_type = RMX_FULL; | |
6151 | break; | |
6152 | case DRM_MODE_SCALE_NONE: | |
6153 | default: | |
6154 | rmx_type = RMX_OFF; | |
6155 | break; | |
6156 | } | |
6157 | ||
6158 | if (dm_old_state->scaling == rmx_type) | |
6159 | return 0; | |
6160 | ||
6161 | dm_new_state->scaling = rmx_type; | |
6162 | ret = 0; | |
6163 | } else if (property == adev->mode_info.underscan_hborder_property) { | |
6164 | dm_new_state->underscan_hborder = val; | |
6165 | ret = 0; | |
6166 | } else if (property == adev->mode_info.underscan_vborder_property) { | |
6167 | dm_new_state->underscan_vborder = val; | |
6168 | ret = 0; | |
6169 | } else if (property == adev->mode_info.underscan_property) { | |
6170 | dm_new_state->underscan_enable = val; | |
6171 | ret = 0; | |
c1ee92f9 DF |
6172 | } else if (property == adev->mode_info.abm_level_property) { |
6173 | dm_new_state->abm_level = val; | |
6174 | ret = 0; | |
e7b07cee HW |
6175 | } |
6176 | ||
6177 | return ret; | |
6178 | } | |
6179 | ||
3ee6b26b AD |
6180 | int amdgpu_dm_connector_atomic_get_property(struct drm_connector *connector, |
6181 | const struct drm_connector_state *state, | |
6182 | struct drm_property *property, | |
6183 | uint64_t *val) | |
e7b07cee HW |
6184 | { |
6185 | struct drm_device *dev = connector->dev; | |
1348969a | 6186 | struct amdgpu_device *adev = drm_to_adev(dev); |
e7b07cee HW |
6187 | struct dm_connector_state *dm_state = |
6188 | to_dm_connector_state(state); | |
6189 | int ret = -EINVAL; | |
6190 | ||
6191 | if (property == dev->mode_config.scaling_mode_property) { | |
6192 | switch (dm_state->scaling) { | |
6193 | case RMX_CENTER: | |
6194 | *val = DRM_MODE_SCALE_CENTER; | |
6195 | break; | |
6196 | case RMX_ASPECT: | |
6197 | *val = DRM_MODE_SCALE_ASPECT; | |
6198 | break; | |
6199 | case RMX_FULL: | |
6200 | *val = DRM_MODE_SCALE_FULLSCREEN; | |
6201 | break; | |
6202 | case RMX_OFF: | |
6203 | default: | |
6204 | *val = DRM_MODE_SCALE_NONE; | |
6205 | break; | |
6206 | } | |
6207 | ret = 0; | |
6208 | } else if (property == adev->mode_info.underscan_hborder_property) { | |
6209 | *val = dm_state->underscan_hborder; | |
6210 | ret = 0; | |
6211 | } else if (property == adev->mode_info.underscan_vborder_property) { | |
6212 | *val = dm_state->underscan_vborder; | |
6213 | ret = 0; | |
6214 | } else if (property == adev->mode_info.underscan_property) { | |
6215 | *val = dm_state->underscan_enable; | |
6216 | ret = 0; | |
c1ee92f9 DF |
6217 | } else if (property == adev->mode_info.abm_level_property) { |
6218 | *val = dm_state->abm_level; | |
6219 | ret = 0; | |
e7b07cee | 6220 | } |
c1ee92f9 | 6221 | |
e7b07cee HW |
6222 | return ret; |
6223 | } | |
6224 | ||
526c654a ED |
6225 | static void amdgpu_dm_connector_unregister(struct drm_connector *connector) |
6226 | { | |
6227 | struct amdgpu_dm_connector *amdgpu_dm_connector = to_amdgpu_dm_connector(connector); | |
6228 | ||
6229 | drm_dp_aux_unregister(&amdgpu_dm_connector->dm_dp_aux.aux); | |
6230 | } | |
6231 | ||
7578ecda | 6232 | static void amdgpu_dm_connector_destroy(struct drm_connector *connector) |
e7b07cee | 6233 | { |
c84dec2f | 6234 | struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); |
1348969a | 6235 | struct amdgpu_device *adev = drm_to_adev(connector->dev); |
e7b07cee | 6236 | struct amdgpu_display_manager *dm = &adev->dm; |
ada8ce15 | 6237 | |
5dff80bd | 6238 | /* |
5d945cbc | 6239 | * Call only if mst_mgr was initialized before since it's not done |
5dff80bd AG |
6240 | * for all connector types. |
6241 | */ | |
6242 | if (aconnector->mst_mgr.dev) | |
6243 | drm_dp_mst_topology_mgr_destroy(&aconnector->mst_mgr); | |
6244 | ||
f196198c HG |
6245 | if (aconnector->bl_idx != -1) { |
6246 | backlight_device_unregister(dm->backlight_dev[aconnector->bl_idx]); | |
6247 | dm->backlight_dev[aconnector->bl_idx] = NULL; | |
e7b07cee | 6248 | } |
dcd5fb82 MF |
6249 | |
6250 | if (aconnector->dc_em_sink) | |
6251 | dc_sink_release(aconnector->dc_em_sink); | |
6252 | aconnector->dc_em_sink = NULL; | |
6253 | if (aconnector->dc_sink) | |
6254 | dc_sink_release(aconnector->dc_sink); | |
6255 | aconnector->dc_sink = NULL; | |
6256 | ||
e86e8947 | 6257 | drm_dp_cec_unregister_connector(&aconnector->dm_dp_aux.aux); |
e7b07cee HW |
6258 | drm_connector_unregister(connector); |
6259 | drm_connector_cleanup(connector); | |
526c654a ED |
6260 | if (aconnector->i2c) { |
6261 | i2c_del_adapter(&aconnector->i2c->base); | |
6262 | kfree(aconnector->i2c); | |
6263 | } | |
7daec99f | 6264 | kfree(aconnector->dm_dp_aux.aux.name); |
526c654a | 6265 | |
e7b07cee HW |
6266 | kfree(connector); |
6267 | } | |
6268 | ||
6269 | void amdgpu_dm_connector_funcs_reset(struct drm_connector *connector) | |
6270 | { | |
6271 | struct dm_connector_state *state = | |
6272 | to_dm_connector_state(connector->state); | |
6273 | ||
df099b9b LSL |
6274 | if (connector->state) |
6275 | __drm_atomic_helper_connector_destroy_state(connector->state); | |
6276 | ||
e7b07cee HW |
6277 | kfree(state); |
6278 | ||
6279 | state = kzalloc(sizeof(*state), GFP_KERNEL); | |
6280 | ||
6281 | if (state) { | |
6282 | state->scaling = RMX_OFF; | |
6283 | state->underscan_enable = false; | |
6284 | state->underscan_hborder = 0; | |
6285 | state->underscan_vborder = 0; | |
01933ba4 | 6286 | state->base.max_requested_bpc = 8; |
3261e013 ML |
6287 | state->vcpi_slots = 0; |
6288 | state->pbn = 0; | |
5d945cbc | 6289 | |
c3e50f89 NK |
6290 | if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) |
6291 | state->abm_level = amdgpu_dm_abm_level; | |
6292 | ||
df099b9b | 6293 | __drm_atomic_helper_connector_reset(connector, &state->base); |
e7b07cee HW |
6294 | } |
6295 | } | |
6296 | ||
3ee6b26b AD |
6297 | struct drm_connector_state * |
6298 | amdgpu_dm_connector_atomic_duplicate_state(struct drm_connector *connector) | |
e7b07cee HW |
6299 | { |
6300 | struct dm_connector_state *state = | |
6301 | to_dm_connector_state(connector->state); | |
6302 | ||
6303 | struct dm_connector_state *new_state = | |
6304 | kmemdup(state, sizeof(*state), GFP_KERNEL); | |
6305 | ||
98e6436d AK |
6306 | if (!new_state) |
6307 | return NULL; | |
e7b07cee | 6308 | |
98e6436d AK |
6309 | __drm_atomic_helper_connector_duplicate_state(connector, &new_state->base); |
6310 | ||
6311 | new_state->freesync_capable = state->freesync_capable; | |
c1ee92f9 | 6312 | new_state->abm_level = state->abm_level; |
922454c2 NK |
6313 | new_state->scaling = state->scaling; |
6314 | new_state->underscan_enable = state->underscan_enable; | |
6315 | new_state->underscan_hborder = state->underscan_hborder; | |
6316 | new_state->underscan_vborder = state->underscan_vborder; | |
3261e013 ML |
6317 | new_state->vcpi_slots = state->vcpi_slots; |
6318 | new_state->pbn = state->pbn; | |
98e6436d | 6319 | return &new_state->base; |
e7b07cee HW |
6320 | } |
6321 | ||
14f04fa4 AD |
6322 | static int |
6323 | amdgpu_dm_connector_late_register(struct drm_connector *connector) | |
6324 | { | |
6325 | struct amdgpu_dm_connector *amdgpu_dm_connector = | |
6326 | to_amdgpu_dm_connector(connector); | |
00a8037e | 6327 | int r; |
14f04fa4 | 6328 | |
62f03dad HG |
6329 | amdgpu_dm_register_backlight_device(amdgpu_dm_connector); |
6330 | ||
00a8037e AD |
6331 | if ((connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort) || |
6332 | (connector->connector_type == DRM_MODE_CONNECTOR_eDP)) { | |
6333 | amdgpu_dm_connector->dm_dp_aux.aux.dev = connector->kdev; | |
6334 | r = drm_dp_aux_register(&amdgpu_dm_connector->dm_dp_aux.aux); | |
6335 | if (r) | |
6336 | return r; | |
6337 | } | |
6338 | ||
6339 | #if defined(CONFIG_DEBUG_FS) | |
14f04fa4 AD |
6340 | connector_debugfs_init(amdgpu_dm_connector); |
6341 | #endif | |
6342 | ||
6343 | return 0; | |
6344 | } | |
6345 | ||
e7b07cee HW |
6346 | static const struct drm_connector_funcs amdgpu_dm_connector_funcs = { |
6347 | .reset = amdgpu_dm_connector_funcs_reset, | |
6348 | .detect = amdgpu_dm_connector_detect, | |
6349 | .fill_modes = drm_helper_probe_single_connector_modes, | |
6350 | .destroy = amdgpu_dm_connector_destroy, | |
6351 | .atomic_duplicate_state = amdgpu_dm_connector_atomic_duplicate_state, | |
6352 | .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, | |
6353 | .atomic_set_property = amdgpu_dm_connector_atomic_set_property, | |
526c654a | 6354 | .atomic_get_property = amdgpu_dm_connector_atomic_get_property, |
14f04fa4 | 6355 | .late_register = amdgpu_dm_connector_late_register, |
526c654a | 6356 | .early_unregister = amdgpu_dm_connector_unregister |
e7b07cee HW |
6357 | }; |
6358 | ||
e7b07cee HW |
6359 | static int get_modes(struct drm_connector *connector) |
6360 | { | |
6361 | return amdgpu_dm_connector_get_modes(connector); | |
6362 | } | |
6363 | ||
c84dec2f | 6364 | static void create_eml_sink(struct amdgpu_dm_connector *aconnector) |
e7b07cee HW |
6365 | { |
6366 | struct dc_sink_init_data init_params = { | |
6367 | .link = aconnector->dc_link, | |
6368 | .sink_signal = SIGNAL_TYPE_VIRTUAL | |
6369 | }; | |
70e8ffc5 | 6370 | struct edid *edid; |
e7b07cee | 6371 | |
a89ff457 | 6372 | if (!aconnector->base.edid_blob_ptr) { |
e7b07cee HW |
6373 | DRM_ERROR("No EDID firmware found on connector: %s ,forcing to OFF!\n", |
6374 | aconnector->base.name); | |
6375 | ||
6376 | aconnector->base.force = DRM_FORCE_OFF; | |
e7b07cee HW |
6377 | return; |
6378 | } | |
6379 | ||
70e8ffc5 HW |
6380 | edid = (struct edid *) aconnector->base.edid_blob_ptr->data; |
6381 | ||
e7b07cee HW |
6382 | aconnector->edid = edid; |
6383 | ||
6384 | aconnector->dc_em_sink = dc_link_add_remote_sink( | |
6385 | aconnector->dc_link, | |
6386 | (uint8_t *)edid, | |
6387 | (edid->extensions + 1) * EDID_LENGTH, | |
6388 | &init_params); | |
6389 | ||
dcd5fb82 | 6390 | if (aconnector->base.force == DRM_FORCE_ON) { |
e7b07cee HW |
6391 | aconnector->dc_sink = aconnector->dc_link->local_sink ? |
6392 | aconnector->dc_link->local_sink : | |
6393 | aconnector->dc_em_sink; | |
dcd5fb82 MF |
6394 | dc_sink_retain(aconnector->dc_sink); |
6395 | } | |
e7b07cee HW |
6396 | } |
6397 | ||
c84dec2f | 6398 | static void handle_edid_mgmt(struct amdgpu_dm_connector *aconnector) |
e7b07cee HW |
6399 | { |
6400 | struct dc_link *link = (struct dc_link *)aconnector->dc_link; | |
6401 | ||
1f6010a9 DF |
6402 | /* |
6403 | * In case of headless boot with force on for DP managed connector | |
e7b07cee HW |
6404 | * Those settings have to be != 0 to get initial modeset |
6405 | */ | |
6406 | if (link->connector_signal == SIGNAL_TYPE_DISPLAY_PORT) { | |
6407 | link->verified_link_cap.lane_count = LANE_COUNT_FOUR; | |
6408 | link->verified_link_cap.link_rate = LINK_RATE_HIGH2; | |
6409 | } | |
6410 | ||
e7b07cee HW |
6411 | create_eml_sink(aconnector); |
6412 | } | |
6413 | ||
5468c36d FZ |
6414 | static enum dc_status dm_validate_stream_and_context(struct dc *dc, |
6415 | struct dc_stream_state *stream) | |
6416 | { | |
6417 | enum dc_status dc_result = DC_ERROR_UNEXPECTED; | |
6418 | struct dc_plane_state *dc_plane_state = NULL; | |
6419 | struct dc_state *dc_state = NULL; | |
6420 | ||
6421 | if (!stream) | |
6422 | goto cleanup; | |
6423 | ||
6424 | dc_plane_state = dc_create_plane_state(dc); | |
6425 | if (!dc_plane_state) | |
6426 | goto cleanup; | |
6427 | ||
6428 | dc_state = dc_create_state(dc); | |
6429 | if (!dc_state) | |
6430 | goto cleanup; | |
6431 | ||
6432 | /* populate stream to plane */ | |
6433 | dc_plane_state->src_rect.height = stream->src.height; | |
6434 | dc_plane_state->src_rect.width = stream->src.width; | |
6435 | dc_plane_state->dst_rect.height = stream->src.height; | |
6436 | dc_plane_state->dst_rect.width = stream->src.width; | |
6437 | dc_plane_state->clip_rect.height = stream->src.height; | |
6438 | dc_plane_state->clip_rect.width = stream->src.width; | |
6439 | dc_plane_state->plane_size.surface_pitch = ((stream->src.width + 255) / 256) * 256; | |
6440 | dc_plane_state->plane_size.surface_size.height = stream->src.height; | |
6441 | dc_plane_state->plane_size.surface_size.width = stream->src.width; | |
6442 | dc_plane_state->plane_size.chroma_size.height = stream->src.height; | |
6443 | dc_plane_state->plane_size.chroma_size.width = stream->src.width; | |
5468c36d FZ |
6444 | dc_plane_state->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB8888; |
6445 | dc_plane_state->tiling_info.gfx9.swizzle = DC_SW_UNKNOWN; | |
6446 | dc_plane_state->rotation = ROTATION_ANGLE_0; | |
6447 | dc_plane_state->is_tiling_rotated = false; | |
6448 | dc_plane_state->tiling_info.gfx8.array_mode = DC_ARRAY_LINEAR_GENERAL; | |
6449 | ||
6450 | dc_result = dc_validate_stream(dc, stream); | |
6451 | if (dc_result == DC_OK) | |
6452 | dc_result = dc_validate_plane(dc, dc_plane_state); | |
6453 | ||
6454 | if (dc_result == DC_OK) | |
6455 | dc_result = dc_add_stream_to_ctx(dc, dc_state, stream); | |
6456 | ||
6457 | if (dc_result == DC_OK && !dc_add_plane_to_context( | |
6458 | dc, | |
6459 | stream, | |
6460 | dc_plane_state, | |
6461 | dc_state)) | |
6462 | dc_result = DC_FAIL_ATTACH_SURFACES; | |
6463 | ||
6464 | if (dc_result == DC_OK) | |
6465 | dc_result = dc_validate_global_state(dc, dc_state, true); | |
6466 | ||
6467 | cleanup: | |
6468 | if (dc_state) | |
6469 | dc_release_state(dc_state); | |
6470 | ||
6471 | if (dc_plane_state) | |
6472 | dc_plane_state_release(dc_plane_state); | |
6473 | ||
6474 | return dc_result; | |
6475 | } | |
6476 | ||
17ce8a69 | 6477 | struct dc_stream_state * |
cbd14ae7 SW |
6478 | create_validate_stream_for_sink(struct amdgpu_dm_connector *aconnector, |
6479 | const struct drm_display_mode *drm_mode, | |
6480 | const struct dm_connector_state *dm_state, | |
6481 | const struct dc_stream_state *old_stream) | |
6482 | { | |
6483 | struct drm_connector *connector = &aconnector->base; | |
1348969a | 6484 | struct amdgpu_device *adev = drm_to_adev(connector->dev); |
cbd14ae7 | 6485 | struct dc_stream_state *stream; |
4b7da34b SW |
6486 | const struct drm_connector_state *drm_state = dm_state ? &dm_state->base : NULL; |
6487 | int requested_bpc = drm_state ? drm_state->max_requested_bpc : 8; | |
cbd14ae7 SW |
6488 | enum dc_status dc_result = DC_OK; |
6489 | ||
6490 | do { | |
6491 | stream = create_stream_for_sink(aconnector, drm_mode, | |
6492 | dm_state, old_stream, | |
6493 | requested_bpc); | |
6494 | if (stream == NULL) { | |
6495 | DRM_ERROR("Failed to create stream for sink!\n"); | |
6496 | break; | |
6497 | } | |
6498 | ||
e9a7d236 RS |
6499 | dc_result = dc_validate_stream(adev->dm.dc, stream); |
6500 | if (dc_result == DC_OK && stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST) | |
f04d275d | 6501 | dc_result = dm_dp_mst_is_port_support_mode(aconnector, stream); |
6502 | ||
5468c36d FZ |
6503 | if (dc_result == DC_OK) |
6504 | dc_result = dm_validate_stream_and_context(adev->dm.dc, stream); | |
6505 | ||
cbd14ae7 | 6506 | if (dc_result != DC_OK) { |
74a16675 | 6507 | DRM_DEBUG_KMS("Mode %dx%d (clk %d) failed DC validation with error %d (%s)\n", |
cbd14ae7 SW |
6508 | drm_mode->hdisplay, |
6509 | drm_mode->vdisplay, | |
6510 | drm_mode->clock, | |
74a16675 RS |
6511 | dc_result, |
6512 | dc_status_to_str(dc_result)); | |
cbd14ae7 SW |
6513 | |
6514 | dc_stream_release(stream); | |
6515 | stream = NULL; | |
6516 | requested_bpc -= 2; /* lower bpc to retry validation */ | |
6517 | } | |
6518 | ||
6519 | } while (stream == NULL && requested_bpc >= 6); | |
6520 | ||
68eb3ae3 WS |
6521 | if (dc_result == DC_FAIL_ENC_VALIDATE && !aconnector->force_yuv420_output) { |
6522 | DRM_DEBUG_KMS("Retry forcing YCbCr420 encoding\n"); | |
6523 | ||
6524 | aconnector->force_yuv420_output = true; | |
6525 | stream = create_validate_stream_for_sink(aconnector, drm_mode, | |
6526 | dm_state, old_stream); | |
6527 | aconnector->force_yuv420_output = false; | |
6528 | } | |
6529 | ||
cbd14ae7 SW |
6530 | return stream; |
6531 | } | |
6532 | ||
ba9ca088 | 6533 | enum drm_mode_status amdgpu_dm_connector_mode_valid(struct drm_connector *connector, |
3ee6b26b | 6534 | struct drm_display_mode *mode) |
e7b07cee HW |
6535 | { |
6536 | int result = MODE_ERROR; | |
6537 | struct dc_sink *dc_sink; | |
e7b07cee | 6538 | /* TODO: Unhardcode stream count */ |
0971c40e | 6539 | struct dc_stream_state *stream; |
c84dec2f | 6540 | struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); |
e7b07cee HW |
6541 | |
6542 | if ((mode->flags & DRM_MODE_FLAG_INTERLACE) || | |
6543 | (mode->flags & DRM_MODE_FLAG_DBLSCAN)) | |
6544 | return result; | |
6545 | ||
1f6010a9 DF |
6546 | /* |
6547 | * Only run this the first time mode_valid is called to initilialize | |
e7b07cee HW |
6548 | * EDID mgmt |
6549 | */ | |
6550 | if (aconnector->base.force != DRM_FORCE_UNSPECIFIED && | |
6551 | !aconnector->dc_em_sink) | |
6552 | handle_edid_mgmt(aconnector); | |
6553 | ||
c84dec2f | 6554 | dc_sink = to_amdgpu_dm_connector(connector)->dc_sink; |
e7b07cee | 6555 | |
ad975f44 VL |
6556 | if (dc_sink == NULL && aconnector->base.force != DRM_FORCE_ON_DIGITAL && |
6557 | aconnector->base.force != DRM_FORCE_ON) { | |
e7b07cee HW |
6558 | DRM_ERROR("dc_sink is NULL!\n"); |
6559 | goto fail; | |
6560 | } | |
6561 | ||
cbd14ae7 SW |
6562 | stream = create_validate_stream_for_sink(aconnector, mode, NULL, NULL); |
6563 | if (stream) { | |
6564 | dc_stream_release(stream); | |
e7b07cee | 6565 | result = MODE_OK; |
cbd14ae7 | 6566 | } |
e7b07cee HW |
6567 | |
6568 | fail: | |
6569 | /* TODO: error handling*/ | |
6570 | return result; | |
6571 | } | |
6572 | ||
88694af9 NK |
6573 | static int fill_hdr_info_packet(const struct drm_connector_state *state, |
6574 | struct dc_info_packet *out) | |
6575 | { | |
6576 | struct hdmi_drm_infoframe frame; | |
6577 | unsigned char buf[30]; /* 26 + 4 */ | |
6578 | ssize_t len; | |
6579 | int ret, i; | |
6580 | ||
6581 | memset(out, 0, sizeof(*out)); | |
6582 | ||
6583 | if (!state->hdr_output_metadata) | |
6584 | return 0; | |
6585 | ||
6586 | ret = drm_hdmi_infoframe_set_hdr_metadata(&frame, state); | |
6587 | if (ret) | |
6588 | return ret; | |
6589 | ||
6590 | len = hdmi_drm_infoframe_pack_only(&frame, buf, sizeof(buf)); | |
6591 | if (len < 0) | |
6592 | return (int)len; | |
6593 | ||
6594 | /* Static metadata is a fixed 26 bytes + 4 byte header. */ | |
6595 | if (len != 30) | |
6596 | return -EINVAL; | |
6597 | ||
6598 | /* Prepare the infopacket for DC. */ | |
6599 | switch (state->connector->connector_type) { | |
6600 | case DRM_MODE_CONNECTOR_HDMIA: | |
6601 | out->hb0 = 0x87; /* type */ | |
6602 | out->hb1 = 0x01; /* version */ | |
6603 | out->hb2 = 0x1A; /* length */ | |
6604 | out->sb[0] = buf[3]; /* checksum */ | |
6605 | i = 1; | |
6606 | break; | |
6607 | ||
6608 | case DRM_MODE_CONNECTOR_DisplayPort: | |
6609 | case DRM_MODE_CONNECTOR_eDP: | |
6610 | out->hb0 = 0x00; /* sdp id, zero */ | |
6611 | out->hb1 = 0x87; /* type */ | |
6612 | out->hb2 = 0x1D; /* payload len - 1 */ | |
6613 | out->hb3 = (0x13 << 2); /* sdp version */ | |
6614 | out->sb[0] = 0x01; /* version */ | |
6615 | out->sb[1] = 0x1A; /* length */ | |
6616 | i = 2; | |
6617 | break; | |
6618 | ||
6619 | default: | |
6620 | return -EINVAL; | |
6621 | } | |
6622 | ||
6623 | memcpy(&out->sb[i], &buf[4], 26); | |
6624 | out->valid = true; | |
6625 | ||
6626 | print_hex_dump(KERN_DEBUG, "HDR SB:", DUMP_PREFIX_NONE, 16, 1, out->sb, | |
6627 | sizeof(out->sb), false); | |
6628 | ||
6629 | return 0; | |
6630 | } | |
6631 | ||
88694af9 NK |
6632 | static int |
6633 | amdgpu_dm_connector_atomic_check(struct drm_connector *conn, | |
51e857af | 6634 | struct drm_atomic_state *state) |
88694af9 | 6635 | { |
51e857af SP |
6636 | struct drm_connector_state *new_con_state = |
6637 | drm_atomic_get_new_connector_state(state, conn); | |
88694af9 NK |
6638 | struct drm_connector_state *old_con_state = |
6639 | drm_atomic_get_old_connector_state(state, conn); | |
6640 | struct drm_crtc *crtc = new_con_state->crtc; | |
6641 | struct drm_crtc_state *new_crtc_state; | |
a76eb429 | 6642 | struct amdgpu_dm_connector *aconn = to_amdgpu_dm_connector(conn); |
88694af9 NK |
6643 | int ret; |
6644 | ||
e8a98235 RS |
6645 | trace_amdgpu_dm_connector_atomic_check(new_con_state); |
6646 | ||
a76eb429 LP |
6647 | if (conn->connector_type == DRM_MODE_CONNECTOR_DisplayPort) { |
6648 | ret = drm_dp_mst_root_conn_atomic_check(new_con_state, &aconn->mst_mgr); | |
6649 | if (ret < 0) | |
6650 | return ret; | |
6651 | } | |
6652 | ||
88694af9 NK |
6653 | if (!crtc) |
6654 | return 0; | |
6655 | ||
72921cdf | 6656 | if (!drm_connector_atomic_hdr_metadata_equal(old_con_state, new_con_state)) { |
88694af9 NK |
6657 | struct dc_info_packet hdr_infopacket; |
6658 | ||
6659 | ret = fill_hdr_info_packet(new_con_state, &hdr_infopacket); | |
6660 | if (ret) | |
6661 | return ret; | |
6662 | ||
6663 | new_crtc_state = drm_atomic_get_crtc_state(state, crtc); | |
6664 | if (IS_ERR(new_crtc_state)) | |
6665 | return PTR_ERR(new_crtc_state); | |
6666 | ||
6667 | /* | |
6668 | * DC considers the stream backends changed if the | |
6669 | * static metadata changes. Forcing the modeset also | |
6670 | * gives a simple way for userspace to switch from | |
b232d4ed NK |
6671 | * 8bpc to 10bpc when setting the metadata to enter |
6672 | * or exit HDR. | |
6673 | * | |
6674 | * Changing the static metadata after it's been | |
6675 | * set is permissible, however. So only force a | |
6676 | * modeset if we're entering or exiting HDR. | |
88694af9 | 6677 | */ |
b232d4ed NK |
6678 | new_crtc_state->mode_changed = |
6679 | !old_con_state->hdr_output_metadata || | |
6680 | !new_con_state->hdr_output_metadata; | |
88694af9 NK |
6681 | } |
6682 | ||
6683 | return 0; | |
6684 | } | |
6685 | ||
e7b07cee HW |
6686 | static const struct drm_connector_helper_funcs |
6687 | amdgpu_dm_connector_helper_funcs = { | |
6688 | /* | |
1f6010a9 | 6689 | * If hotplugging a second bigger display in FB Con mode, bigger resolution |
b830ebc9 | 6690 | * modes will be filtered by drm_mode_validate_size(), and those modes |
1f6010a9 | 6691 | * are missing after user start lightdm. So we need to renew modes list. |
b830ebc9 HW |
6692 | * in get_modes call back, not just return the modes count |
6693 | */ | |
e7b07cee HW |
6694 | .get_modes = get_modes, |
6695 | .mode_valid = amdgpu_dm_connector_mode_valid, | |
88694af9 | 6696 | .atomic_check = amdgpu_dm_connector_atomic_check, |
e7b07cee HW |
6697 | }; |
6698 | ||
e7b07cee HW |
6699 | static void dm_encoder_helper_disable(struct drm_encoder *encoder) |
6700 | { | |
6701 | ||
6702 | } | |
6703 | ||
f04d275d | 6704 | int convert_dc_color_depth_into_bpc(enum dc_color_depth display_color_depth) |
3261e013 ML |
6705 | { |
6706 | switch (display_color_depth) { | |
5d945cbc RS |
6707 | case COLOR_DEPTH_666: |
6708 | return 6; | |
6709 | case COLOR_DEPTH_888: | |
6710 | return 8; | |
6711 | case COLOR_DEPTH_101010: | |
6712 | return 10; | |
6713 | case COLOR_DEPTH_121212: | |
6714 | return 12; | |
6715 | case COLOR_DEPTH_141414: | |
6716 | return 14; | |
6717 | case COLOR_DEPTH_161616: | |
6718 | return 16; | |
6719 | default: | |
6720 | break; | |
6721 | } | |
3261e013 ML |
6722 | return 0; |
6723 | } | |
6724 | ||
3ee6b26b AD |
6725 | static int dm_encoder_helper_atomic_check(struct drm_encoder *encoder, |
6726 | struct drm_crtc_state *crtc_state, | |
6727 | struct drm_connector_state *conn_state) | |
e7b07cee | 6728 | { |
3261e013 ML |
6729 | struct drm_atomic_state *state = crtc_state->state; |
6730 | struct drm_connector *connector = conn_state->connector; | |
6731 | struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); | |
6732 | struct dm_connector_state *dm_new_connector_state = to_dm_connector_state(conn_state); | |
6733 | const struct drm_display_mode *adjusted_mode = &crtc_state->adjusted_mode; | |
6734 | struct drm_dp_mst_topology_mgr *mst_mgr; | |
6735 | struct drm_dp_mst_port *mst_port; | |
4d07b0bc | 6736 | struct drm_dp_mst_topology_state *mst_state; |
3261e013 ML |
6737 | enum dc_color_depth color_depth; |
6738 | int clock, bpp = 0; | |
1bc22f20 | 6739 | bool is_y420 = false; |
3261e013 | 6740 | |
f0127cb1 | 6741 | if (!aconnector->mst_output_port || !aconnector->dc_sink) |
3261e013 ML |
6742 | return 0; |
6743 | ||
f0127cb1 WL |
6744 | mst_port = aconnector->mst_output_port; |
6745 | mst_mgr = &aconnector->mst_root->mst_mgr; | |
3261e013 ML |
6746 | |
6747 | if (!crtc_state->connectors_changed && !crtc_state->mode_changed) | |
6748 | return 0; | |
6749 | ||
4d07b0bc LP |
6750 | mst_state = drm_atomic_get_mst_topology_state(state, mst_mgr); |
6751 | if (IS_ERR(mst_state)) | |
6752 | return PTR_ERR(mst_state); | |
6753 | ||
6754 | if (!mst_state->pbn_div) | |
f0127cb1 | 6755 | mst_state->pbn_div = dm_mst_get_pbn_divider(aconnector->mst_root->dc_link); |
4d07b0bc | 6756 | |
3261e013 | 6757 | if (!state->duplicated) { |
cbd14ae7 | 6758 | int max_bpc = conn_state->max_requested_bpc; |
1bc22f20 | 6759 | is_y420 = drm_mode_is_420_also(&connector->display_info, adjusted_mode) && |
5d945cbc | 6760 | aconnector->force_yuv420_output; |
cbd14ae7 SW |
6761 | color_depth = convert_color_depth_from_display_info(connector, |
6762 | is_y420, | |
6763 | max_bpc); | |
3261e013 ML |
6764 | bpp = convert_dc_color_depth_into_bpc(color_depth) * 3; |
6765 | clock = adjusted_mode->clock; | |
dc48529f | 6766 | dm_new_connector_state->pbn = drm_dp_calc_pbn_mode(clock, bpp, false); |
3261e013 | 6767 | } |
4d07b0bc LP |
6768 | |
6769 | dm_new_connector_state->vcpi_slots = | |
6770 | drm_dp_atomic_find_time_slots(state, mst_mgr, mst_port, | |
6771 | dm_new_connector_state->pbn); | |
3261e013 ML |
6772 | if (dm_new_connector_state->vcpi_slots < 0) { |
6773 | DRM_DEBUG_ATOMIC("failed finding vcpi slots: %d\n", (int)dm_new_connector_state->vcpi_slots); | |
6774 | return dm_new_connector_state->vcpi_slots; | |
6775 | } | |
e7b07cee HW |
6776 | return 0; |
6777 | } | |
6778 | ||
6779 | const struct drm_encoder_helper_funcs amdgpu_dm_encoder_helper_funcs = { | |
6780 | .disable = dm_encoder_helper_disable, | |
6781 | .atomic_check = dm_encoder_helper_atomic_check | |
6782 | }; | |
6783 | ||
29b9ba74 | 6784 | static int dm_update_mst_vcpi_slots_for_dsc(struct drm_atomic_state *state, |
6513104b HW |
6785 | struct dc_state *dc_state, |
6786 | struct dsc_mst_fairness_vars *vars) | |
29b9ba74 ML |
6787 | { |
6788 | struct dc_stream_state *stream = NULL; | |
6789 | struct drm_connector *connector; | |
5760dcb9 | 6790 | struct drm_connector_state *new_con_state; |
29b9ba74 ML |
6791 | struct amdgpu_dm_connector *aconnector; |
6792 | struct dm_connector_state *dm_conn_state; | |
7cce4cd6 | 6793 | int i, j, ret; |
a550bb16 | 6794 | int vcpi, pbn_div, pbn, slot_num = 0; |
29b9ba74 | 6795 | |
5760dcb9 | 6796 | for_each_new_connector_in_state(state, connector, new_con_state, i) { |
29b9ba74 ML |
6797 | |
6798 | aconnector = to_amdgpu_dm_connector(connector); | |
6799 | ||
f0127cb1 | 6800 | if (!aconnector->mst_output_port) |
29b9ba74 ML |
6801 | continue; |
6802 | ||
6803 | if (!new_con_state || !new_con_state->crtc) | |
6804 | continue; | |
6805 | ||
6806 | dm_conn_state = to_dm_connector_state(new_con_state); | |
6807 | ||
6808 | for (j = 0; j < dc_state->stream_count; j++) { | |
6809 | stream = dc_state->streams[j]; | |
6810 | if (!stream) | |
6811 | continue; | |
6812 | ||
5d945cbc | 6813 | if ((struct amdgpu_dm_connector *)stream->dm_stream_context == aconnector) |
29b9ba74 ML |
6814 | break; |
6815 | ||
6816 | stream = NULL; | |
6817 | } | |
6818 | ||
6819 | if (!stream) | |
6820 | continue; | |
6821 | ||
29b9ba74 | 6822 | pbn_div = dm_mst_get_pbn_divider(stream->link); |
6513104b HW |
6823 | /* pbn is calculated by compute_mst_dsc_configs_for_state*/ |
6824 | for (j = 0; j < dc_state->stream_count; j++) { | |
6825 | if (vars[j].aconnector == aconnector) { | |
6826 | pbn = vars[j].pbn; | |
6827 | break; | |
6828 | } | |
6829 | } | |
6830 | ||
a550bb16 HW |
6831 | if (j == dc_state->stream_count) |
6832 | continue; | |
6833 | ||
6834 | slot_num = DIV_ROUND_UP(pbn, pbn_div); | |
6835 | ||
6836 | if (stream->timing.flags.DSC != 1) { | |
6837 | dm_conn_state->pbn = pbn; | |
6838 | dm_conn_state->vcpi_slots = slot_num; | |
6839 | ||
f0127cb1 | 6840 | ret = drm_dp_mst_atomic_enable_dsc(state, aconnector->mst_output_port, |
7cce4cd6 LP |
6841 | dm_conn_state->pbn, false); |
6842 | if (ret < 0) | |
6843 | return ret; | |
6844 | ||
a550bb16 HW |
6845 | continue; |
6846 | } | |
6847 | ||
f0127cb1 | 6848 | vcpi = drm_dp_mst_atomic_enable_dsc(state, aconnector->mst_output_port, pbn, true); |
29b9ba74 ML |
6849 | if (vcpi < 0) |
6850 | return vcpi; | |
6851 | ||
6852 | dm_conn_state->pbn = pbn; | |
6853 | dm_conn_state->vcpi_slots = vcpi; | |
6854 | } | |
6855 | return 0; | |
6856 | } | |
6857 | ||
e7b07cee HW |
6858 | static int to_drm_connector_type(enum signal_type st) |
6859 | { | |
6860 | switch (st) { | |
6861 | case SIGNAL_TYPE_HDMI_TYPE_A: | |
6862 | return DRM_MODE_CONNECTOR_HDMIA; | |
6863 | case SIGNAL_TYPE_EDP: | |
6864 | return DRM_MODE_CONNECTOR_eDP; | |
11c3ee48 AD |
6865 | case SIGNAL_TYPE_LVDS: |
6866 | return DRM_MODE_CONNECTOR_LVDS; | |
e7b07cee HW |
6867 | case SIGNAL_TYPE_RGB: |
6868 | return DRM_MODE_CONNECTOR_VGA; | |
6869 | case SIGNAL_TYPE_DISPLAY_PORT: | |
6870 | case SIGNAL_TYPE_DISPLAY_PORT_MST: | |
6871 | return DRM_MODE_CONNECTOR_DisplayPort; | |
6872 | case SIGNAL_TYPE_DVI_DUAL_LINK: | |
6873 | case SIGNAL_TYPE_DVI_SINGLE_LINK: | |
6874 | return DRM_MODE_CONNECTOR_DVID; | |
6875 | case SIGNAL_TYPE_VIRTUAL: | |
6876 | return DRM_MODE_CONNECTOR_VIRTUAL; | |
6877 | ||
6878 | default: | |
6879 | return DRM_MODE_CONNECTOR_Unknown; | |
6880 | } | |
6881 | } | |
6882 | ||
2b4c1c05 DV |
6883 | static struct drm_encoder *amdgpu_dm_connector_to_encoder(struct drm_connector *connector) |
6884 | { | |
62afb4ad JRS |
6885 | struct drm_encoder *encoder; |
6886 | ||
6887 | /* There is only one encoder per connector */ | |
6888 | drm_connector_for_each_possible_encoder(connector, encoder) | |
6889 | return encoder; | |
6890 | ||
6891 | return NULL; | |
2b4c1c05 DV |
6892 | } |
6893 | ||
e7b07cee HW |
6894 | static void amdgpu_dm_get_native_mode(struct drm_connector *connector) |
6895 | { | |
e7b07cee HW |
6896 | struct drm_encoder *encoder; |
6897 | struct amdgpu_encoder *amdgpu_encoder; | |
6898 | ||
2b4c1c05 | 6899 | encoder = amdgpu_dm_connector_to_encoder(connector); |
e7b07cee HW |
6900 | |
6901 | if (encoder == NULL) | |
6902 | return; | |
6903 | ||
6904 | amdgpu_encoder = to_amdgpu_encoder(encoder); | |
6905 | ||
6906 | amdgpu_encoder->native_mode.clock = 0; | |
6907 | ||
6908 | if (!list_empty(&connector->probed_modes)) { | |
6909 | struct drm_display_mode *preferred_mode = NULL; | |
b830ebc9 | 6910 | |
e7b07cee | 6911 | list_for_each_entry(preferred_mode, |
b830ebc9 HW |
6912 | &connector->probed_modes, |
6913 | head) { | |
6914 | if (preferred_mode->type & DRM_MODE_TYPE_PREFERRED) | |
6915 | amdgpu_encoder->native_mode = *preferred_mode; | |
6916 | ||
e7b07cee HW |
6917 | break; |
6918 | } | |
6919 | ||
6920 | } | |
6921 | } | |
6922 | ||
3ee6b26b AD |
6923 | static struct drm_display_mode * |
6924 | amdgpu_dm_create_common_mode(struct drm_encoder *encoder, | |
6925 | char *name, | |
6926 | int hdisplay, int vdisplay) | |
e7b07cee HW |
6927 | { |
6928 | struct drm_device *dev = encoder->dev; | |
6929 | struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); | |
6930 | struct drm_display_mode *mode = NULL; | |
6931 | struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode; | |
6932 | ||
6933 | mode = drm_mode_duplicate(dev, native_mode); | |
6934 | ||
b830ebc9 | 6935 | if (mode == NULL) |
e7b07cee HW |
6936 | return NULL; |
6937 | ||
6938 | mode->hdisplay = hdisplay; | |
6939 | mode->vdisplay = vdisplay; | |
6940 | mode->type &= ~DRM_MODE_TYPE_PREFERRED; | |
090afc1e | 6941 | strscpy(mode->name, name, DRM_DISPLAY_MODE_LEN); |
e7b07cee HW |
6942 | |
6943 | return mode; | |
6944 | ||
6945 | } | |
6946 | ||
6947 | static void amdgpu_dm_connector_add_common_modes(struct drm_encoder *encoder, | |
3ee6b26b | 6948 | struct drm_connector *connector) |
e7b07cee HW |
6949 | { |
6950 | struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); | |
6951 | struct drm_display_mode *mode = NULL; | |
6952 | struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode; | |
c84dec2f HW |
6953 | struct amdgpu_dm_connector *amdgpu_dm_connector = |
6954 | to_amdgpu_dm_connector(connector); | |
e7b07cee HW |
6955 | int i; |
6956 | int n; | |
6957 | struct mode_size { | |
6958 | char name[DRM_DISPLAY_MODE_LEN]; | |
6959 | int w; | |
6960 | int h; | |
b830ebc9 | 6961 | } common_modes[] = { |
e7b07cee HW |
6962 | { "640x480", 640, 480}, |
6963 | { "800x600", 800, 600}, | |
6964 | { "1024x768", 1024, 768}, | |
6965 | { "1280x720", 1280, 720}, | |
6966 | { "1280x800", 1280, 800}, | |
6967 | {"1280x1024", 1280, 1024}, | |
6968 | { "1440x900", 1440, 900}, | |
6969 | {"1680x1050", 1680, 1050}, | |
6970 | {"1600x1200", 1600, 1200}, | |
6971 | {"1920x1080", 1920, 1080}, | |
6972 | {"1920x1200", 1920, 1200} | |
6973 | }; | |
6974 | ||
b830ebc9 | 6975 | n = ARRAY_SIZE(common_modes); |
e7b07cee HW |
6976 | |
6977 | for (i = 0; i < n; i++) { | |
6978 | struct drm_display_mode *curmode = NULL; | |
6979 | bool mode_existed = false; | |
6980 | ||
6981 | if (common_modes[i].w > native_mode->hdisplay || | |
b830ebc9 HW |
6982 | common_modes[i].h > native_mode->vdisplay || |
6983 | (common_modes[i].w == native_mode->hdisplay && | |
6984 | common_modes[i].h == native_mode->vdisplay)) | |
6985 | continue; | |
e7b07cee HW |
6986 | |
6987 | list_for_each_entry(curmode, &connector->probed_modes, head) { | |
6988 | if (common_modes[i].w == curmode->hdisplay && | |
b830ebc9 | 6989 | common_modes[i].h == curmode->vdisplay) { |
e7b07cee HW |
6990 | mode_existed = true; |
6991 | break; | |
6992 | } | |
6993 | } | |
6994 | ||
6995 | if (mode_existed) | |
6996 | continue; | |
6997 | ||
6998 | mode = amdgpu_dm_create_common_mode(encoder, | |
6999 | common_modes[i].name, common_modes[i].w, | |
7000 | common_modes[i].h); | |
588a7017 ZQ |
7001 | if (!mode) |
7002 | continue; | |
7003 | ||
e7b07cee | 7004 | drm_mode_probed_add(connector, mode); |
c84dec2f | 7005 | amdgpu_dm_connector->num_modes++; |
e7b07cee HW |
7006 | } |
7007 | } | |
7008 | ||
d77de788 SS |
7009 | static void amdgpu_set_panel_orientation(struct drm_connector *connector) |
7010 | { | |
7011 | struct drm_encoder *encoder; | |
7012 | struct amdgpu_encoder *amdgpu_encoder; | |
7013 | const struct drm_display_mode *native_mode; | |
7014 | ||
7015 | if (connector->connector_type != DRM_MODE_CONNECTOR_eDP && | |
7016 | connector->connector_type != DRM_MODE_CONNECTOR_LVDS) | |
7017 | return; | |
7018 | ||
acc96ae0 MW |
7019 | mutex_lock(&connector->dev->mode_config.mutex); |
7020 | amdgpu_dm_connector_get_modes(connector); | |
7021 | mutex_unlock(&connector->dev->mode_config.mutex); | |
7022 | ||
d77de788 SS |
7023 | encoder = amdgpu_dm_connector_to_encoder(connector); |
7024 | if (!encoder) | |
7025 | return; | |
7026 | ||
7027 | amdgpu_encoder = to_amdgpu_encoder(encoder); | |
7028 | ||
7029 | native_mode = &amdgpu_encoder->native_mode; | |
7030 | if (native_mode->hdisplay == 0 || native_mode->vdisplay == 0) | |
7031 | return; | |
7032 | ||
7033 | drm_connector_set_panel_orientation_with_quirk(connector, | |
7034 | DRM_MODE_PANEL_ORIENTATION_UNKNOWN, | |
7035 | native_mode->hdisplay, | |
7036 | native_mode->vdisplay); | |
7037 | } | |
7038 | ||
3ee6b26b AD |
7039 | static void amdgpu_dm_connector_ddc_get_modes(struct drm_connector *connector, |
7040 | struct edid *edid) | |
e7b07cee | 7041 | { |
c84dec2f HW |
7042 | struct amdgpu_dm_connector *amdgpu_dm_connector = |
7043 | to_amdgpu_dm_connector(connector); | |
e7b07cee HW |
7044 | |
7045 | if (edid) { | |
7046 | /* empty probed_modes */ | |
7047 | INIT_LIST_HEAD(&connector->probed_modes); | |
c84dec2f | 7048 | amdgpu_dm_connector->num_modes = |
e7b07cee HW |
7049 | drm_add_edid_modes(connector, edid); |
7050 | ||
f1e5e913 YMM |
7051 | /* sorting the probed modes before calling function |
7052 | * amdgpu_dm_get_native_mode() since EDID can have | |
7053 | * more than one preferred mode. The modes that are | |
7054 | * later in the probed mode list could be of higher | |
7055 | * and preferred resolution. For example, 3840x2160 | |
7056 | * resolution in base EDID preferred timing and 4096x2160 | |
7057 | * preferred resolution in DID extension block later. | |
7058 | */ | |
7059 | drm_mode_sort(&connector->probed_modes); | |
e7b07cee | 7060 | amdgpu_dm_get_native_mode(connector); |
f9b4f20c SW |
7061 | |
7062 | /* Freesync capabilities are reset by calling | |
7063 | * drm_add_edid_modes() and need to be | |
7064 | * restored here. | |
7065 | */ | |
7066 | amdgpu_dm_update_freesync_caps(connector, edid); | |
a8d8d3dc | 7067 | } else { |
c84dec2f | 7068 | amdgpu_dm_connector->num_modes = 0; |
a8d8d3dc | 7069 | } |
e7b07cee HW |
7070 | } |
7071 | ||
a85ba005 NC |
7072 | static bool is_duplicate_mode(struct amdgpu_dm_connector *aconnector, |
7073 | struct drm_display_mode *mode) | |
7074 | { | |
7075 | struct drm_display_mode *m; | |
7076 | ||
7077 | list_for_each_entry (m, &aconnector->base.probed_modes, head) { | |
7078 | if (drm_mode_equal(m, mode)) | |
7079 | return true; | |
7080 | } | |
7081 | ||
7082 | return false; | |
7083 | } | |
7084 | ||
7085 | static uint add_fs_modes(struct amdgpu_dm_connector *aconnector) | |
7086 | { | |
7087 | const struct drm_display_mode *m; | |
7088 | struct drm_display_mode *new_mode; | |
7089 | uint i; | |
ae67558b | 7090 | u32 new_modes_count = 0; |
a85ba005 NC |
7091 | |
7092 | /* Standard FPS values | |
7093 | * | |
12cdff6b | 7094 | * 23.976 - TV/NTSC |
3335a135 UKK |
7095 | * 24 - Cinema |
7096 | * 25 - TV/PAL | |
12cdff6b | 7097 | * 29.97 - TV/NTSC |
3335a135 UKK |
7098 | * 30 - TV/NTSC |
7099 | * 48 - Cinema HFR | |
7100 | * 50 - TV/PAL | |
7101 | * 60 - Commonly used | |
12cdff6b | 7102 | * 48,72,96,120 - Multiples of 24 |
a85ba005 | 7103 | */ |
ae67558b | 7104 | static const u32 common_rates[] = { |
9ce5ed6e | 7105 | 23976, 24000, 25000, 29970, 30000, |
12cdff6b | 7106 | 48000, 50000, 60000, 72000, 96000, 120000 |
9ce5ed6e | 7107 | }; |
a85ba005 NC |
7108 | |
7109 | /* | |
7110 | * Find mode with highest refresh rate with the same resolution | |
7111 | * as the preferred mode. Some monitors report a preferred mode | |
7112 | * with lower resolution than the highest refresh rate supported. | |
7113 | */ | |
7114 | ||
7115 | m = get_highest_refresh_rate_mode(aconnector, true); | |
7116 | if (!m) | |
7117 | return 0; | |
7118 | ||
7119 | for (i = 0; i < ARRAY_SIZE(common_rates); i++) { | |
ae67558b SS |
7120 | u64 target_vtotal, target_vtotal_diff; |
7121 | u64 num, den; | |
a85ba005 NC |
7122 | |
7123 | if (drm_mode_vrefresh(m) * 1000 < common_rates[i]) | |
7124 | continue; | |
7125 | ||
7126 | if (common_rates[i] < aconnector->min_vfreq * 1000 || | |
7127 | common_rates[i] > aconnector->max_vfreq * 1000) | |
7128 | continue; | |
7129 | ||
7130 | num = (unsigned long long)m->clock * 1000 * 1000; | |
7131 | den = common_rates[i] * (unsigned long long)m->htotal; | |
7132 | target_vtotal = div_u64(num, den); | |
7133 | target_vtotal_diff = target_vtotal - m->vtotal; | |
7134 | ||
7135 | /* Check for illegal modes */ | |
7136 | if (m->vsync_start + target_vtotal_diff < m->vdisplay || | |
7137 | m->vsync_end + target_vtotal_diff < m->vsync_start || | |
7138 | m->vtotal + target_vtotal_diff < m->vsync_end) | |
7139 | continue; | |
7140 | ||
7141 | new_mode = drm_mode_duplicate(aconnector->base.dev, m); | |
7142 | if (!new_mode) | |
7143 | goto out; | |
7144 | ||
7145 | new_mode->vtotal += (u16)target_vtotal_diff; | |
7146 | new_mode->vsync_start += (u16)target_vtotal_diff; | |
7147 | new_mode->vsync_end += (u16)target_vtotal_diff; | |
7148 | new_mode->type &= ~DRM_MODE_TYPE_PREFERRED; | |
7149 | new_mode->type |= DRM_MODE_TYPE_DRIVER; | |
7150 | ||
7151 | if (!is_duplicate_mode(aconnector, new_mode)) { | |
7152 | drm_mode_probed_add(&aconnector->base, new_mode); | |
7153 | new_modes_count += 1; | |
7154 | } else | |
7155 | drm_mode_destroy(aconnector->base.dev, new_mode); | |
7156 | } | |
7157 | out: | |
7158 | return new_modes_count; | |
7159 | } | |
7160 | ||
7161 | static void amdgpu_dm_connector_add_freesync_modes(struct drm_connector *connector, | |
7162 | struct edid *edid) | |
7163 | { | |
7164 | struct amdgpu_dm_connector *amdgpu_dm_connector = | |
7165 | to_amdgpu_dm_connector(connector); | |
7166 | ||
4243c84a | 7167 | if (!(amdgpu_freesync_vid_mode && edid)) |
a85ba005 | 7168 | return; |
fe8858bb | 7169 | |
a85ba005 NC |
7170 | if (amdgpu_dm_connector->max_vfreq - amdgpu_dm_connector->min_vfreq > 10) |
7171 | amdgpu_dm_connector->num_modes += | |
7172 | add_fs_modes(amdgpu_dm_connector); | |
7173 | } | |
7174 | ||
7578ecda | 7175 | static int amdgpu_dm_connector_get_modes(struct drm_connector *connector) |
e7b07cee | 7176 | { |
c84dec2f HW |
7177 | struct amdgpu_dm_connector *amdgpu_dm_connector = |
7178 | to_amdgpu_dm_connector(connector); | |
e7b07cee | 7179 | struct drm_encoder *encoder; |
c84dec2f | 7180 | struct edid *edid = amdgpu_dm_connector->edid; |
c32699ca JD |
7181 | struct dc_link_settings *verified_link_cap = |
7182 | &amdgpu_dm_connector->dc_link->verified_link_cap; | |
98ce7d32 | 7183 | const struct dc *dc = amdgpu_dm_connector->dc_link->dc; |
e7b07cee | 7184 | |
2b4c1c05 | 7185 | encoder = amdgpu_dm_connector_to_encoder(connector); |
3e332d3a | 7186 | |
5c0e6840 | 7187 | if (!drm_edid_is_valid(edid)) { |
1b369d3c ML |
7188 | amdgpu_dm_connector->num_modes = |
7189 | drm_add_modes_noedid(connector, 640, 480); | |
98ce7d32 | 7190 | if (dc->link_srv->dp_get_encoding_format(verified_link_cap) == DP_128b_132b_ENCODING) |
c32699ca JD |
7191 | amdgpu_dm_connector->num_modes += |
7192 | drm_add_modes_noedid(connector, 1920, 1080); | |
85ee15d6 ML |
7193 | } else { |
7194 | amdgpu_dm_connector_ddc_get_modes(connector, edid); | |
7195 | amdgpu_dm_connector_add_common_modes(encoder, connector); | |
a85ba005 | 7196 | amdgpu_dm_connector_add_freesync_modes(connector, edid); |
85ee15d6 | 7197 | } |
3e332d3a | 7198 | amdgpu_dm_fbc_init(connector); |
5099114b | 7199 | |
c84dec2f | 7200 | return amdgpu_dm_connector->num_modes; |
e7b07cee HW |
7201 | } |
7202 | ||
3ee6b26b AD |
7203 | void amdgpu_dm_connector_init_helper(struct amdgpu_display_manager *dm, |
7204 | struct amdgpu_dm_connector *aconnector, | |
7205 | int connector_type, | |
7206 | struct dc_link *link, | |
7207 | int link_index) | |
e7b07cee | 7208 | { |
1348969a | 7209 | struct amdgpu_device *adev = drm_to_adev(dm->ddev); |
e7b07cee | 7210 | |
f04bee34 NK |
7211 | /* |
7212 | * Some of the properties below require access to state, like bpc. | |
7213 | * Allocate some default initial connector state with our reset helper. | |
7214 | */ | |
7215 | if (aconnector->base.funcs->reset) | |
7216 | aconnector->base.funcs->reset(&aconnector->base); | |
7217 | ||
e7b07cee | 7218 | aconnector->connector_id = link_index; |
f196198c | 7219 | aconnector->bl_idx = -1; |
e7b07cee HW |
7220 | aconnector->dc_link = link; |
7221 | aconnector->base.interlace_allowed = false; | |
7222 | aconnector->base.doublescan_allowed = false; | |
7223 | aconnector->base.stereo_allowed = false; | |
7224 | aconnector->base.dpms = DRM_MODE_DPMS_OFF; | |
7225 | aconnector->hpd.hpd = AMDGPU_HPD_NONE; /* not used */ | |
6ce8f316 | 7226 | aconnector->audio_inst = -1; |
5b49da02 SJK |
7227 | aconnector->pack_sdp_v1_3 = false; |
7228 | aconnector->as_type = ADAPTIVE_SYNC_TYPE_NONE; | |
7229 | memset(&aconnector->vsdb_info, 0, sizeof(aconnector->vsdb_info)); | |
e7b07cee HW |
7230 | mutex_init(&aconnector->hpd_lock); |
7231 | ||
1f6010a9 DF |
7232 | /* |
7233 | * configure support HPD hot plug connector_>polled default value is 0 | |
b830ebc9 HW |
7234 | * which means HPD hot plug not supported |
7235 | */ | |
e7b07cee HW |
7236 | switch (connector_type) { |
7237 | case DRM_MODE_CONNECTOR_HDMIA: | |
7238 | aconnector->base.polled = DRM_CONNECTOR_POLL_HPD; | |
e7baae1c | 7239 | aconnector->base.ycbcr_420_allowed = |
9ea59d5a | 7240 | link->link_enc->features.hdmi_ycbcr420_supported ? true : false; |
e7b07cee HW |
7241 | break; |
7242 | case DRM_MODE_CONNECTOR_DisplayPort: | |
7243 | aconnector->base.polled = DRM_CONNECTOR_POLL_HPD; | |
d715c9a2 | 7244 | link->link_enc = link_enc_cfg_get_link_enc(link); |
7b201d53 | 7245 | ASSERT(link->link_enc); |
f6e03f80 JS |
7246 | if (link->link_enc) |
7247 | aconnector->base.ycbcr_420_allowed = | |
9ea59d5a | 7248 | link->link_enc->features.dp_ycbcr420_supported ? true : false; |
e7b07cee HW |
7249 | break; |
7250 | case DRM_MODE_CONNECTOR_DVID: | |
7251 | aconnector->base.polled = DRM_CONNECTOR_POLL_HPD; | |
7252 | break; | |
7253 | default: | |
7254 | break; | |
7255 | } | |
7256 | ||
7257 | drm_object_attach_property(&aconnector->base.base, | |
7258 | dm->ddev->mode_config.scaling_mode_property, | |
7259 | DRM_MODE_SCALE_NONE); | |
7260 | ||
7261 | drm_object_attach_property(&aconnector->base.base, | |
7262 | adev->mode_info.underscan_property, | |
7263 | UNDERSCAN_OFF); | |
7264 | drm_object_attach_property(&aconnector->base.base, | |
7265 | adev->mode_info.underscan_hborder_property, | |
7266 | 0); | |
7267 | drm_object_attach_property(&aconnector->base.base, | |
7268 | adev->mode_info.underscan_vborder_property, | |
7269 | 0); | |
1825fd34 | 7270 | |
f0127cb1 | 7271 | if (!aconnector->mst_root) |
8c61b31e | 7272 | drm_connector_attach_max_bpc_property(&aconnector->base, 8, 16); |
1825fd34 | 7273 | |
e47f1691 | 7274 | aconnector->base.state->max_bpc = 16; |
4a8ca46b | 7275 | aconnector->base.state->max_requested_bpc = aconnector->base.state->max_bpc; |
e7b07cee | 7276 | |
c1ee92f9 | 7277 | if (connector_type == DRM_MODE_CONNECTOR_eDP && |
5cb32419 | 7278 | (dc_is_dmcu_initialized(adev->dm.dc) || adev->dm.dc->ctx->dmub_srv)) { |
c1ee92f9 DF |
7279 | drm_object_attach_property(&aconnector->base.base, |
7280 | adev->mode_info.abm_level_property, 0); | |
7281 | } | |
bb47de73 NK |
7282 | |
7283 | if (connector_type == DRM_MODE_CONNECTOR_HDMIA || | |
7fad8da1 NK |
7284 | connector_type == DRM_MODE_CONNECTOR_DisplayPort || |
7285 | connector_type == DRM_MODE_CONNECTOR_eDP) { | |
e057b52c | 7286 | drm_connector_attach_hdr_output_metadata_property(&aconnector->base); |
88694af9 | 7287 | |
f0127cb1 | 7288 | if (!aconnector->mst_root) |
8c61b31e JFZ |
7289 | drm_connector_attach_vrr_capable_property(&aconnector->base); |
7290 | ||
e22bb562 | 7291 | if (adev->dm.hdcp_workqueue) |
53e108aa | 7292 | drm_connector_attach_content_protection_property(&aconnector->base, true); |
bb47de73 | 7293 | } |
e7b07cee HW |
7294 | } |
7295 | ||
7578ecda AD |
7296 | static int amdgpu_dm_i2c_xfer(struct i2c_adapter *i2c_adap, |
7297 | struct i2c_msg *msgs, int num) | |
e7b07cee HW |
7298 | { |
7299 | struct amdgpu_i2c_adapter *i2c = i2c_get_adapdata(i2c_adap); | |
7300 | struct ddc_service *ddc_service = i2c->ddc_service; | |
7301 | struct i2c_command cmd; | |
7302 | int i; | |
7303 | int result = -EIO; | |
7304 | ||
b830ebc9 | 7305 | cmd.payloads = kcalloc(num, sizeof(struct i2c_payload), GFP_KERNEL); |
e7b07cee HW |
7306 | |
7307 | if (!cmd.payloads) | |
7308 | return result; | |
7309 | ||
7310 | cmd.number_of_payloads = num; | |
7311 | cmd.engine = I2C_COMMAND_ENGINE_DEFAULT; | |
7312 | cmd.speed = 100; | |
7313 | ||
7314 | for (i = 0; i < num; i++) { | |
7315 | cmd.payloads[i].write = !(msgs[i].flags & I2C_M_RD); | |
7316 | cmd.payloads[i].address = msgs[i].addr; | |
7317 | cmd.payloads[i].length = msgs[i].len; | |
7318 | cmd.payloads[i].data = msgs[i].buf; | |
7319 | } | |
7320 | ||
c85e6e54 DF |
7321 | if (dc_submit_i2c( |
7322 | ddc_service->ctx->dc, | |
22676bc5 | 7323 | ddc_service->link->link_index, |
e7b07cee HW |
7324 | &cmd)) |
7325 | result = num; | |
7326 | ||
7327 | kfree(cmd.payloads); | |
7328 | return result; | |
7329 | } | |
7330 | ||
7578ecda | 7331 | static u32 amdgpu_dm_i2c_func(struct i2c_adapter *adap) |
e7b07cee HW |
7332 | { |
7333 | return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL; | |
7334 | } | |
7335 | ||
7336 | static const struct i2c_algorithm amdgpu_dm_i2c_algo = { | |
7337 | .master_xfer = amdgpu_dm_i2c_xfer, | |
7338 | .functionality = amdgpu_dm_i2c_func, | |
7339 | }; | |
7340 | ||
3ee6b26b AD |
7341 | static struct amdgpu_i2c_adapter * |
7342 | create_i2c(struct ddc_service *ddc_service, | |
7343 | int link_index, | |
7344 | int *res) | |
e7b07cee HW |
7345 | { |
7346 | struct amdgpu_device *adev = ddc_service->ctx->driver_context; | |
7347 | struct amdgpu_i2c_adapter *i2c; | |
7348 | ||
b830ebc9 | 7349 | i2c = kzalloc(sizeof(struct amdgpu_i2c_adapter), GFP_KERNEL); |
2a55f096 ES |
7350 | if (!i2c) |
7351 | return NULL; | |
e7b07cee HW |
7352 | i2c->base.owner = THIS_MODULE; |
7353 | i2c->base.class = I2C_CLASS_DDC; | |
7354 | i2c->base.dev.parent = &adev->pdev->dev; | |
7355 | i2c->base.algo = &amdgpu_dm_i2c_algo; | |
b830ebc9 | 7356 | snprintf(i2c->base.name, sizeof(i2c->base.name), "AMDGPU DM i2c hw bus %d", link_index); |
e7b07cee HW |
7357 | i2c_set_adapdata(&i2c->base, i2c); |
7358 | i2c->ddc_service = ddc_service; | |
7359 | ||
7360 | return i2c; | |
7361 | } | |
7362 | ||
89fc8d4e | 7363 | |
1f6010a9 DF |
7364 | /* |
7365 | * Note: this function assumes that dc_link_detect() was called for the | |
b830ebc9 HW |
7366 | * dc_link which will be represented by this aconnector. |
7367 | */ | |
7578ecda AD |
7368 | static int amdgpu_dm_connector_init(struct amdgpu_display_manager *dm, |
7369 | struct amdgpu_dm_connector *aconnector, | |
ae67558b | 7370 | u32 link_index, |
7578ecda | 7371 | struct amdgpu_encoder *aencoder) |
e7b07cee HW |
7372 | { |
7373 | int res = 0; | |
7374 | int connector_type; | |
7375 | struct dc *dc = dm->dc; | |
7376 | struct dc_link *link = dc_get_link_at_index(dc, link_index); | |
7377 | struct amdgpu_i2c_adapter *i2c; | |
9a227d26 TSD |
7378 | |
7379 | link->priv = aconnector; | |
e7b07cee | 7380 | |
f1ad2f5e | 7381 | DRM_DEBUG_DRIVER("%s()\n", __func__); |
e7b07cee HW |
7382 | |
7383 | i2c = create_i2c(link->ddc, link->link_index, &res); | |
2a55f096 ES |
7384 | if (!i2c) { |
7385 | DRM_ERROR("Failed to create i2c adapter data\n"); | |
7386 | return -ENOMEM; | |
7387 | } | |
7388 | ||
e7b07cee HW |
7389 | aconnector->i2c = i2c; |
7390 | res = i2c_add_adapter(&i2c->base); | |
7391 | ||
7392 | if (res) { | |
7393 | DRM_ERROR("Failed to register hw i2c %d\n", link->link_index); | |
7394 | goto out_free; | |
7395 | } | |
7396 | ||
7397 | connector_type = to_drm_connector_type(link->connector_signal); | |
7398 | ||
17165de2 | 7399 | res = drm_connector_init_with_ddc( |
e7b07cee HW |
7400 | dm->ddev, |
7401 | &aconnector->base, | |
7402 | &amdgpu_dm_connector_funcs, | |
17165de2 AP |
7403 | connector_type, |
7404 | &i2c->base); | |
e7b07cee HW |
7405 | |
7406 | if (res) { | |
7407 | DRM_ERROR("connector_init failed\n"); | |
7408 | aconnector->connector_id = -1; | |
7409 | goto out_free; | |
7410 | } | |
7411 | ||
7412 | drm_connector_helper_add( | |
7413 | &aconnector->base, | |
7414 | &amdgpu_dm_connector_helper_funcs); | |
7415 | ||
7416 | amdgpu_dm_connector_init_helper( | |
7417 | dm, | |
7418 | aconnector, | |
7419 | connector_type, | |
7420 | link, | |
7421 | link_index); | |
7422 | ||
cde4c44d | 7423 | drm_connector_attach_encoder( |
e7b07cee HW |
7424 | &aconnector->base, &aencoder->base); |
7425 | ||
e7b07cee HW |
7426 | if (connector_type == DRM_MODE_CONNECTOR_DisplayPort |
7427 | || connector_type == DRM_MODE_CONNECTOR_eDP) | |
7daec99f | 7428 | amdgpu_dm_initialize_dp_connector(dm, aconnector, link->link_index); |
e7b07cee | 7429 | |
e7b07cee HW |
7430 | out_free: |
7431 | if (res) { | |
7432 | kfree(i2c); | |
7433 | aconnector->i2c = NULL; | |
7434 | } | |
7435 | return res; | |
7436 | } | |
7437 | ||
7438 | int amdgpu_dm_get_encoder_crtc_mask(struct amdgpu_device *adev) | |
7439 | { | |
7440 | switch (adev->mode_info.num_crtc) { | |
7441 | case 1: | |
7442 | return 0x1; | |
7443 | case 2: | |
7444 | return 0x3; | |
7445 | case 3: | |
7446 | return 0x7; | |
7447 | case 4: | |
7448 | return 0xf; | |
7449 | case 5: | |
7450 | return 0x1f; | |
7451 | case 6: | |
7452 | default: | |
7453 | return 0x3f; | |
7454 | } | |
7455 | } | |
7456 | ||
7578ecda AD |
7457 | static int amdgpu_dm_encoder_init(struct drm_device *dev, |
7458 | struct amdgpu_encoder *aencoder, | |
7459 | uint32_t link_index) | |
e7b07cee | 7460 | { |
1348969a | 7461 | struct amdgpu_device *adev = drm_to_adev(dev); |
e7b07cee HW |
7462 | |
7463 | int res = drm_encoder_init(dev, | |
7464 | &aencoder->base, | |
7465 | &amdgpu_dm_encoder_funcs, | |
7466 | DRM_MODE_ENCODER_TMDS, | |
7467 | NULL); | |
7468 | ||
7469 | aencoder->base.possible_crtcs = amdgpu_dm_get_encoder_crtc_mask(adev); | |
7470 | ||
7471 | if (!res) | |
7472 | aencoder->encoder_id = link_index; | |
7473 | else | |
7474 | aencoder->encoder_id = -1; | |
7475 | ||
7476 | drm_encoder_helper_add(&aencoder->base, &amdgpu_dm_encoder_helper_funcs); | |
7477 | ||
7478 | return res; | |
7479 | } | |
7480 | ||
3ee6b26b AD |
7481 | static void manage_dm_interrupts(struct amdgpu_device *adev, |
7482 | struct amdgpu_crtc *acrtc, | |
7483 | bool enable) | |
e7b07cee HW |
7484 | { |
7485 | /* | |
8fe684e9 NK |
7486 | * We have no guarantee that the frontend index maps to the same |
7487 | * backend index - some even map to more than one. | |
7488 | * | |
7489 | * TODO: Use a different interrupt or check DC itself for the mapping. | |
e7b07cee HW |
7490 | */ |
7491 | int irq_type = | |
734dd01d | 7492 | amdgpu_display_crtc_idx_to_irq_type( |
e7b07cee HW |
7493 | adev, |
7494 | acrtc->crtc_id); | |
7495 | ||
7496 | if (enable) { | |
7497 | drm_crtc_vblank_on(&acrtc->base); | |
7498 | amdgpu_irq_get( | |
7499 | adev, | |
7500 | &adev->pageflip_irq, | |
7501 | irq_type); | |
86bc2219 WL |
7502 | #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY) |
7503 | amdgpu_irq_get( | |
7504 | adev, | |
7505 | &adev->vline0_irq, | |
7506 | irq_type); | |
7507 | #endif | |
e7b07cee | 7508 | } else { |
86bc2219 WL |
7509 | #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY) |
7510 | amdgpu_irq_put( | |
7511 | adev, | |
7512 | &adev->vline0_irq, | |
7513 | irq_type); | |
7514 | #endif | |
e7b07cee HW |
7515 | amdgpu_irq_put( |
7516 | adev, | |
7517 | &adev->pageflip_irq, | |
7518 | irq_type); | |
7519 | drm_crtc_vblank_off(&acrtc->base); | |
7520 | } | |
7521 | } | |
7522 | ||
8fe684e9 NK |
7523 | static void dm_update_pflip_irq_state(struct amdgpu_device *adev, |
7524 | struct amdgpu_crtc *acrtc) | |
7525 | { | |
7526 | int irq_type = | |
7527 | amdgpu_display_crtc_idx_to_irq_type(adev, acrtc->crtc_id); | |
7528 | ||
7529 | /** | |
7530 | * This reads the current state for the IRQ and force reapplies | |
7531 | * the setting to hardware. | |
7532 | */ | |
7533 | amdgpu_irq_update(adev, &adev->pageflip_irq, irq_type); | |
7534 | } | |
7535 | ||
3ee6b26b AD |
7536 | static bool |
7537 | is_scaling_state_different(const struct dm_connector_state *dm_state, | |
7538 | const struct dm_connector_state *old_dm_state) | |
e7b07cee HW |
7539 | { |
7540 | if (dm_state->scaling != old_dm_state->scaling) | |
7541 | return true; | |
7542 | if (!dm_state->underscan_enable && old_dm_state->underscan_enable) { | |
7543 | if (old_dm_state->underscan_hborder != 0 && old_dm_state->underscan_vborder != 0) | |
7544 | return true; | |
7545 | } else if (dm_state->underscan_enable && !old_dm_state->underscan_enable) { | |
7546 | if (dm_state->underscan_hborder != 0 && dm_state->underscan_vborder != 0) | |
7547 | return true; | |
b830ebc9 HW |
7548 | } else if (dm_state->underscan_hborder != old_dm_state->underscan_hborder || |
7549 | dm_state->underscan_vborder != old_dm_state->underscan_vborder) | |
7550 | return true; | |
e7b07cee HW |
7551 | return false; |
7552 | } | |
7553 | ||
e8fd3eeb | 7554 | static bool is_content_protection_different(struct drm_crtc_state *new_crtc_state, |
7555 | struct drm_crtc_state *old_crtc_state, | |
7556 | struct drm_connector_state *new_conn_state, | |
7557 | struct drm_connector_state *old_conn_state, | |
7558 | const struct drm_connector *connector, | |
7559 | struct hdcp_workqueue *hdcp_w) | |
0c8620d6 BL |
7560 | { |
7561 | struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); | |
97f6c917 | 7562 | struct dm_connector_state *dm_con_state = to_dm_connector_state(connector->state); |
0c8620d6 | 7563 | |
e8fd3eeb | 7564 | pr_debug("[HDCP_DM] connector->index: %x connect_status: %x dpms: %x\n", |
7565 | connector->index, connector->status, connector->dpms); | |
7566 | pr_debug("[HDCP_DM] state protection old: %x new: %x\n", | |
7567 | old_conn_state->content_protection, new_conn_state->content_protection); | |
7568 | ||
7569 | if (old_crtc_state) | |
7570 | pr_debug("[HDCP_DM] old crtc en: %x a: %x m: %x a-chg: %x c-chg: %x\n", | |
7571 | old_crtc_state->enable, | |
7572 | old_crtc_state->active, | |
7573 | old_crtc_state->mode_changed, | |
7574 | old_crtc_state->active_changed, | |
7575 | old_crtc_state->connectors_changed); | |
7576 | ||
7577 | if (new_crtc_state) | |
7578 | pr_debug("[HDCP_DM] NEW crtc en: %x a: %x m: %x a-chg: %x c-chg: %x\n", | |
7579 | new_crtc_state->enable, | |
7580 | new_crtc_state->active, | |
7581 | new_crtc_state->mode_changed, | |
7582 | new_crtc_state->active_changed, | |
7583 | new_crtc_state->connectors_changed); | |
7584 | ||
7585 | /* hdcp content type change */ | |
7586 | if (old_conn_state->hdcp_content_type != new_conn_state->hdcp_content_type && | |
7587 | new_conn_state->content_protection != DRM_MODE_CONTENT_PROTECTION_UNDESIRED) { | |
7588 | new_conn_state->content_protection = DRM_MODE_CONTENT_PROTECTION_DESIRED; | |
7589 | pr_debug("[HDCP_DM] Type0/1 change %s :true\n", __func__); | |
53e108aa BL |
7590 | return true; |
7591 | } | |
7592 | ||
e8fd3eeb | 7593 | /* CP is being re enabled, ignore this */ |
7594 | if (old_conn_state->content_protection == DRM_MODE_CONTENT_PROTECTION_ENABLED && | |
7595 | new_conn_state->content_protection == DRM_MODE_CONTENT_PROTECTION_DESIRED) { | |
7596 | if (new_crtc_state && new_crtc_state->mode_changed) { | |
7597 | new_conn_state->content_protection = DRM_MODE_CONTENT_PROTECTION_DESIRED; | |
7598 | pr_debug("[HDCP_DM] ENABLED->DESIRED & mode_changed %s :true\n", __func__); | |
7599 | return true; | |
0b8f42ab | 7600 | } |
e8fd3eeb | 7601 | new_conn_state->content_protection = DRM_MODE_CONTENT_PROTECTION_ENABLED; |
7602 | pr_debug("[HDCP_DM] ENABLED -> DESIRED %s :false\n", __func__); | |
0c8620d6 BL |
7603 | return false; |
7604 | } | |
7605 | ||
31c0ed90 BL |
7606 | /* S3 resume case, since old state will always be 0 (UNDESIRED) and the restored state will be ENABLED |
7607 | * | |
7608 | * Handles: UNDESIRED -> ENABLED | |
7609 | */ | |
e8fd3eeb | 7610 | if (old_conn_state->content_protection == DRM_MODE_CONTENT_PROTECTION_UNDESIRED && |
7611 | new_conn_state->content_protection == DRM_MODE_CONTENT_PROTECTION_ENABLED) | |
7612 | new_conn_state->content_protection = DRM_MODE_CONTENT_PROTECTION_DESIRED; | |
0c8620d6 | 7613 | |
0d9a947b QZ |
7614 | /* Stream removed and re-enabled |
7615 | * | |
7616 | * Can sometimes overlap with the HPD case, | |
7617 | * thus set update_hdcp to false to avoid | |
7618 | * setting HDCP multiple times. | |
7619 | * | |
7620 | * Handles: DESIRED -> DESIRED (Special case) | |
7621 | */ | |
e8fd3eeb | 7622 | if (!(old_conn_state->crtc && old_conn_state->crtc->enabled) && |
7623 | new_conn_state->crtc && new_conn_state->crtc->enabled && | |
0d9a947b QZ |
7624 | connector->state->content_protection == DRM_MODE_CONTENT_PROTECTION_DESIRED) { |
7625 | dm_con_state->update_hdcp = false; | |
e8fd3eeb | 7626 | pr_debug("[HDCP_DM] DESIRED->DESIRED (Stream removed and re-enabled) %s :true\n", |
7627 | __func__); | |
0d9a947b QZ |
7628 | return true; |
7629 | } | |
7630 | ||
7631 | /* Hot-plug, headless s3, dpms | |
7632 | * | |
7633 | * Only start HDCP if the display is connected/enabled. | |
7634 | * update_hdcp flag will be set to false until the next | |
7635 | * HPD comes in. | |
31c0ed90 BL |
7636 | * |
7637 | * Handles: DESIRED -> DESIRED (Special case) | |
0c8620d6 | 7638 | */ |
e8fd3eeb | 7639 | if (dm_con_state->update_hdcp && |
7640 | new_conn_state->content_protection == DRM_MODE_CONTENT_PROTECTION_DESIRED && | |
7641 | connector->dpms == DRM_MODE_DPMS_ON && aconnector->dc_sink != NULL) { | |
97f6c917 | 7642 | dm_con_state->update_hdcp = false; |
e8fd3eeb | 7643 | pr_debug("[HDCP_DM] DESIRED->DESIRED (Hot-plug, headless s3, dpms) %s :true\n", |
7644 | __func__); | |
0c8620d6 | 7645 | return true; |
97f6c917 | 7646 | } |
0c8620d6 | 7647 | |
e8fd3eeb | 7648 | if (old_conn_state->content_protection == new_conn_state->content_protection) { |
7649 | if (new_conn_state->content_protection >= DRM_MODE_CONTENT_PROTECTION_DESIRED) { | |
7650 | if (new_crtc_state && new_crtc_state->mode_changed) { | |
7651 | pr_debug("[HDCP_DM] DESIRED->DESIRED or ENABLE->ENABLE mode_change %s :true\n", | |
7652 | __func__); | |
7653 | return true; | |
0b8f42ab | 7654 | } |
e8fd3eeb | 7655 | pr_debug("[HDCP_DM] DESIRED->DESIRED & ENABLE->ENABLE %s :false\n", |
7656 | __func__); | |
7657 | return false; | |
0b8f42ab | 7658 | } |
e8fd3eeb | 7659 | |
7660 | pr_debug("[HDCP_DM] UNDESIRED->UNDESIRED %s :false\n", __func__); | |
0c8620d6 | 7661 | return false; |
e8fd3eeb | 7662 | } |
0c8620d6 | 7663 | |
e8fd3eeb | 7664 | if (new_conn_state->content_protection != DRM_MODE_CONTENT_PROTECTION_ENABLED) { |
7665 | pr_debug("[HDCP_DM] UNDESIRED->DESIRED or DESIRED->UNDESIRED or ENABLED->UNDESIRED %s :true\n", | |
7666 | __func__); | |
0c8620d6 | 7667 | return true; |
e8fd3eeb | 7668 | } |
0c8620d6 | 7669 | |
e8fd3eeb | 7670 | pr_debug("[HDCP_DM] DESIRED->ENABLED %s :false\n", __func__); |
0c8620d6 BL |
7671 | return false; |
7672 | } | |
e8fd3eeb | 7673 | |
3ee6b26b AD |
7674 | static void remove_stream(struct amdgpu_device *adev, |
7675 | struct amdgpu_crtc *acrtc, | |
7676 | struct dc_stream_state *stream) | |
e7b07cee HW |
7677 | { |
7678 | /* this is the update mode case */ | |
e7b07cee HW |
7679 | |
7680 | acrtc->otg_inst = -1; | |
7681 | acrtc->enabled = false; | |
7682 | } | |
7683 | ||
e7b07cee HW |
7684 | static void prepare_flip_isr(struct amdgpu_crtc *acrtc) |
7685 | { | |
7686 | ||
7687 | assert_spin_locked(&acrtc->base.dev->event_lock); | |
7688 | WARN_ON(acrtc->event); | |
7689 | ||
7690 | acrtc->event = acrtc->base.state->event; | |
7691 | ||
7692 | /* Set the flip status */ | |
7693 | acrtc->pflip_status = AMDGPU_FLIP_SUBMITTED; | |
7694 | ||
7695 | /* Mark this event as consumed */ | |
7696 | acrtc->base.state->event = NULL; | |
7697 | ||
cb2318b7 VL |
7698 | DC_LOG_PFLIP("crtc:%d, pflip_stat:AMDGPU_FLIP_SUBMITTED\n", |
7699 | acrtc->crtc_id); | |
e7b07cee HW |
7700 | } |
7701 | ||
bb47de73 NK |
7702 | static void update_freesync_state_on_stream( |
7703 | struct amdgpu_display_manager *dm, | |
7704 | struct dm_crtc_state *new_crtc_state, | |
180db303 NK |
7705 | struct dc_stream_state *new_stream, |
7706 | struct dc_plane_state *surface, | |
7707 | u32 flip_timestamp_in_us) | |
bb47de73 | 7708 | { |
09aef2c4 | 7709 | struct mod_vrr_params vrr_params; |
bb47de73 | 7710 | struct dc_info_packet vrr_infopacket = {0}; |
09aef2c4 | 7711 | struct amdgpu_device *adev = dm->adev; |
585d450c | 7712 | struct amdgpu_crtc *acrtc = to_amdgpu_crtc(new_crtc_state->base.crtc); |
09aef2c4 | 7713 | unsigned long flags; |
4cda3243 | 7714 | bool pack_sdp_v1_3 = false; |
5b49da02 SJK |
7715 | struct amdgpu_dm_connector *aconn; |
7716 | enum vrr_packet_type packet_type = PACKET_TYPE_VRR; | |
bb47de73 NK |
7717 | |
7718 | if (!new_stream) | |
7719 | return; | |
7720 | ||
7721 | /* | |
7722 | * TODO: Determine why min/max totals and vrefresh can be 0 here. | |
7723 | * For now it's sufficient to just guard against these conditions. | |
7724 | */ | |
7725 | ||
7726 | if (!new_stream->timing.h_total || !new_stream->timing.v_total) | |
7727 | return; | |
7728 | ||
4a580877 | 7729 | spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags); |
3335a135 | 7730 | vrr_params = acrtc->dm_irq_params.vrr_params; |
09aef2c4 | 7731 | |
180db303 NK |
7732 | if (surface) { |
7733 | mod_freesync_handle_preflip( | |
7734 | dm->freesync_module, | |
7735 | surface, | |
7736 | new_stream, | |
7737 | flip_timestamp_in_us, | |
7738 | &vrr_params); | |
09aef2c4 MK |
7739 | |
7740 | if (adev->family < AMDGPU_FAMILY_AI && | |
6c5e25a0 | 7741 | amdgpu_dm_crtc_vrr_active(new_crtc_state)) { |
09aef2c4 MK |
7742 | mod_freesync_handle_v_update(dm->freesync_module, |
7743 | new_stream, &vrr_params); | |
e63e2491 EB |
7744 | |
7745 | /* Need to call this before the frame ends. */ | |
7746 | dc_stream_adjust_vmin_vmax(dm->dc, | |
7747 | new_crtc_state->stream, | |
7748 | &vrr_params.adjust); | |
09aef2c4 | 7749 | } |
180db303 | 7750 | } |
bb47de73 | 7751 | |
5b49da02 SJK |
7752 | aconn = (struct amdgpu_dm_connector *)new_stream->dm_stream_context; |
7753 | ||
7754 | if (aconn && aconn->as_type == FREESYNC_TYPE_PCON_IN_WHITELIST) { | |
7755 | pack_sdp_v1_3 = aconn->pack_sdp_v1_3; | |
7756 | ||
7757 | if (aconn->vsdb_info.amd_vsdb_version == 1) | |
7758 | packet_type = PACKET_TYPE_FS_V1; | |
7759 | else if (aconn->vsdb_info.amd_vsdb_version == 2) | |
7760 | packet_type = PACKET_TYPE_FS_V2; | |
7761 | else if (aconn->vsdb_info.amd_vsdb_version == 3) | |
7762 | packet_type = PACKET_TYPE_FS_V3; | |
7763 | ||
7764 | mod_build_adaptive_sync_infopacket(new_stream, aconn->as_type, NULL, | |
7765 | &new_stream->adaptive_sync_infopacket); | |
7766 | } | |
7767 | ||
bb47de73 NK |
7768 | mod_freesync_build_vrr_infopacket( |
7769 | dm->freesync_module, | |
7770 | new_stream, | |
180db303 | 7771 | &vrr_params, |
5b49da02 | 7772 | packet_type, |
ecd0136b | 7773 | TRANSFER_FUNC_UNKNOWN, |
4cda3243 MT |
7774 | &vrr_infopacket, |
7775 | pack_sdp_v1_3); | |
bb47de73 | 7776 | |
8a48b44c | 7777 | new_crtc_state->freesync_vrr_info_changed |= |
bb47de73 NK |
7778 | (memcmp(&new_crtc_state->vrr_infopacket, |
7779 | &vrr_infopacket, | |
7780 | sizeof(vrr_infopacket)) != 0); | |
7781 | ||
585d450c | 7782 | acrtc->dm_irq_params.vrr_params = vrr_params; |
bb47de73 NK |
7783 | new_crtc_state->vrr_infopacket = vrr_infopacket; |
7784 | ||
bb47de73 | 7785 | new_stream->vrr_infopacket = vrr_infopacket; |
7eaef116 | 7786 | new_stream->allow_freesync = mod_freesync_get_freesync_enabled(&vrr_params); |
bb47de73 NK |
7787 | |
7788 | if (new_crtc_state->freesync_vrr_info_changed) | |
7789 | DRM_DEBUG_KMS("VRR packet update: crtc=%u enabled=%d state=%d", | |
7790 | new_crtc_state->base.crtc->base.id, | |
7791 | (int)new_crtc_state->base.vrr_enabled, | |
180db303 | 7792 | (int)vrr_params.state); |
09aef2c4 | 7793 | |
4a580877 | 7794 | spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags); |
bb47de73 NK |
7795 | } |
7796 | ||
585d450c | 7797 | static void update_stream_irq_parameters( |
e854194c MK |
7798 | struct amdgpu_display_manager *dm, |
7799 | struct dm_crtc_state *new_crtc_state) | |
7800 | { | |
7801 | struct dc_stream_state *new_stream = new_crtc_state->stream; | |
09aef2c4 | 7802 | struct mod_vrr_params vrr_params; |
e854194c | 7803 | struct mod_freesync_config config = new_crtc_state->freesync_config; |
09aef2c4 | 7804 | struct amdgpu_device *adev = dm->adev; |
585d450c | 7805 | struct amdgpu_crtc *acrtc = to_amdgpu_crtc(new_crtc_state->base.crtc); |
09aef2c4 | 7806 | unsigned long flags; |
e854194c MK |
7807 | |
7808 | if (!new_stream) | |
7809 | return; | |
7810 | ||
7811 | /* | |
7812 | * TODO: Determine why min/max totals and vrefresh can be 0 here. | |
7813 | * For now it's sufficient to just guard against these conditions. | |
7814 | */ | |
7815 | if (!new_stream->timing.h_total || !new_stream->timing.v_total) | |
7816 | return; | |
7817 | ||
4a580877 | 7818 | spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags); |
585d450c | 7819 | vrr_params = acrtc->dm_irq_params.vrr_params; |
09aef2c4 | 7820 | |
e854194c MK |
7821 | if (new_crtc_state->vrr_supported && |
7822 | config.min_refresh_in_uhz && | |
7823 | config.max_refresh_in_uhz) { | |
a85ba005 NC |
7824 | /* |
7825 | * if freesync compatible mode was set, config.state will be set | |
7826 | * in atomic check | |
7827 | */ | |
7828 | if (config.state == VRR_STATE_ACTIVE_FIXED && config.fixed_refresh_in_uhz && | |
7829 | (!drm_atomic_crtc_needs_modeset(&new_crtc_state->base) || | |
7830 | new_crtc_state->freesync_config.state == VRR_STATE_ACTIVE_FIXED)) { | |
7831 | vrr_params.max_refresh_in_uhz = config.max_refresh_in_uhz; | |
7832 | vrr_params.min_refresh_in_uhz = config.min_refresh_in_uhz; | |
7833 | vrr_params.fixed_refresh_in_uhz = config.fixed_refresh_in_uhz; | |
7834 | vrr_params.state = VRR_STATE_ACTIVE_FIXED; | |
7835 | } else { | |
7836 | config.state = new_crtc_state->base.vrr_enabled ? | |
7837 | VRR_STATE_ACTIVE_VARIABLE : | |
7838 | VRR_STATE_INACTIVE; | |
7839 | } | |
e854194c MK |
7840 | } else { |
7841 | config.state = VRR_STATE_UNSUPPORTED; | |
7842 | } | |
7843 | ||
7844 | mod_freesync_build_vrr_params(dm->freesync_module, | |
7845 | new_stream, | |
7846 | &config, &vrr_params); | |
7847 | ||
585d450c AP |
7848 | new_crtc_state->freesync_config = config; |
7849 | /* Copy state for access from DM IRQ handler */ | |
7850 | acrtc->dm_irq_params.freesync_config = config; | |
7851 | acrtc->dm_irq_params.active_planes = new_crtc_state->active_planes; | |
7852 | acrtc->dm_irq_params.vrr_params = vrr_params; | |
4a580877 | 7853 | spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags); |
e854194c MK |
7854 | } |
7855 | ||
66b0c973 MK |
7856 | static void amdgpu_dm_handle_vrr_transition(struct dm_crtc_state *old_state, |
7857 | struct dm_crtc_state *new_state) | |
7858 | { | |
6c5e25a0 DT |
7859 | bool old_vrr_active = amdgpu_dm_crtc_vrr_active(old_state); |
7860 | bool new_vrr_active = amdgpu_dm_crtc_vrr_active(new_state); | |
66b0c973 MK |
7861 | |
7862 | if (!old_vrr_active && new_vrr_active) { | |
7863 | /* Transition VRR inactive -> active: | |
7864 | * While VRR is active, we must not disable vblank irq, as a | |
7865 | * reenable after disable would compute bogus vblank/pflip | |
7866 | * timestamps if it likely happened inside display front-porch. | |
d2574c33 MK |
7867 | * |
7868 | * We also need vupdate irq for the actual core vblank handling | |
7869 | * at end of vblank. | |
66b0c973 | 7870 | */ |
6c5e25a0 | 7871 | WARN_ON(amdgpu_dm_crtc_set_vupdate_irq(new_state->base.crtc, true) != 0); |
8799c0be | 7872 | WARN_ON(drm_crtc_vblank_get(new_state->base.crtc) != 0); |
66b0c973 MK |
7873 | DRM_DEBUG_DRIVER("%s: crtc=%u VRR off->on: Get vblank ref\n", |
7874 | __func__, new_state->base.crtc->base.id); | |
7875 | } else if (old_vrr_active && !new_vrr_active) { | |
7876 | /* Transition VRR active -> inactive: | |
7877 | * Allow vblank irq disable again for fixed refresh rate. | |
7878 | */ | |
6c5e25a0 | 7879 | WARN_ON(amdgpu_dm_crtc_set_vupdate_irq(new_state->base.crtc, false) != 0); |
66b0c973 MK |
7880 | drm_crtc_vblank_put(new_state->base.crtc); |
7881 | DRM_DEBUG_DRIVER("%s: crtc=%u VRR on->off: Drop vblank ref\n", | |
7882 | __func__, new_state->base.crtc->base.id); | |
7883 | } | |
7884 | } | |
7885 | ||
8ad27806 NK |
7886 | static void amdgpu_dm_commit_cursors(struct drm_atomic_state *state) |
7887 | { | |
7888 | struct drm_plane *plane; | |
5760dcb9 | 7889 | struct drm_plane_state *old_plane_state; |
8ad27806 NK |
7890 | int i; |
7891 | ||
7892 | /* | |
7893 | * TODO: Make this per-stream so we don't issue redundant updates for | |
7894 | * commits with multiple streams. | |
7895 | */ | |
5760dcb9 | 7896 | for_each_old_plane_in_state(state, plane, old_plane_state, i) |
8ad27806 | 7897 | if (plane->type == DRM_PLANE_TYPE_CURSOR) |
8bf0d9cd | 7898 | amdgpu_dm_plane_handle_cursor_update(plane, old_plane_state); |
8ad27806 NK |
7899 | } |
7900 | ||
3be5262e | 7901 | static void amdgpu_dm_commit_planes(struct drm_atomic_state *state, |
eb3dc897 | 7902 | struct dc_state *dc_state, |
3ee6b26b AD |
7903 | struct drm_device *dev, |
7904 | struct amdgpu_display_manager *dm, | |
7905 | struct drm_crtc *pcrtc, | |
420cd472 | 7906 | bool wait_for_vblank) |
e7b07cee | 7907 | { |
ae67558b | 7908 | u32 i; |
d6ed6d0d | 7909 | u64 timestamp_ns = ktime_get_ns(); |
e7b07cee | 7910 | struct drm_plane *plane; |
0bc9706d | 7911 | struct drm_plane_state *old_plane_state, *new_plane_state; |
e7b07cee | 7912 | struct amdgpu_crtc *acrtc_attach = to_amdgpu_crtc(pcrtc); |
0bc9706d LSL |
7913 | struct drm_crtc_state *new_pcrtc_state = |
7914 | drm_atomic_get_new_crtc_state(state, pcrtc); | |
7915 | struct dm_crtc_state *acrtc_state = to_dm_crtc_state(new_pcrtc_state); | |
44d09c6a HW |
7916 | struct dm_crtc_state *dm_old_crtc_state = |
7917 | to_dm_crtc_state(drm_atomic_get_old_crtc_state(state, pcrtc)); | |
74aa7bd4 | 7918 | int planes_count = 0, vpos, hpos; |
e7b07cee | 7919 | unsigned long flags; |
ae67558b | 7920 | u32 target_vblank, last_flip_vblank; |
6c5e25a0 | 7921 | bool vrr_active = amdgpu_dm_crtc_vrr_active(acrtc_state); |
cc79950b | 7922 | bool cursor_update = false; |
74aa7bd4 | 7923 | bool pflip_present = false; |
d6ed6d0d | 7924 | bool dirty_rects_changed = false; |
bc7f670e DF |
7925 | struct { |
7926 | struct dc_surface_update surface_updates[MAX_SURFACES]; | |
7927 | struct dc_plane_info plane_infos[MAX_SURFACES]; | |
7928 | struct dc_scaling_info scaling_infos[MAX_SURFACES]; | |
74aa7bd4 | 7929 | struct dc_flip_addrs flip_addrs[MAX_SURFACES]; |
bc7f670e | 7930 | struct dc_stream_update stream_update; |
74aa7bd4 | 7931 | } *bundle; |
bc7f670e | 7932 | |
74aa7bd4 | 7933 | bundle = kzalloc(sizeof(*bundle), GFP_KERNEL); |
8a48b44c | 7934 | |
74aa7bd4 DF |
7935 | if (!bundle) { |
7936 | dm_error("Failed to allocate update bundle\n"); | |
4b510503 NK |
7937 | goto cleanup; |
7938 | } | |
e7b07cee | 7939 | |
8ad27806 NK |
7940 | /* |
7941 | * Disable the cursor first if we're disabling all the planes. | |
7942 | * It'll remain on the screen after the planes are re-enabled | |
7943 | * if we don't. | |
7944 | */ | |
7945 | if (acrtc_state->active_planes == 0) | |
7946 | amdgpu_dm_commit_cursors(state); | |
7947 | ||
e7b07cee | 7948 | /* update planes when needed */ |
efc8278e | 7949 | for_each_oldnew_plane_in_state(state, plane, old_plane_state, new_plane_state, i) { |
0bc9706d | 7950 | struct drm_crtc *crtc = new_plane_state->crtc; |
f5ba60fe | 7951 | struct drm_crtc_state *new_crtc_state; |
0bc9706d | 7952 | struct drm_framebuffer *fb = new_plane_state->fb; |
6eed95b0 | 7953 | struct amdgpu_framebuffer *afb = (struct amdgpu_framebuffer *)fb; |
34bafd27 | 7954 | bool plane_needs_flip; |
c7af5f77 | 7955 | struct dc_plane_state *dc_plane; |
54d76575 | 7956 | struct dm_plane_state *dm_new_plane_state = to_dm_plane_state(new_plane_state); |
e7b07cee | 7957 | |
80c218d5 | 7958 | /* Cursor plane is handled after stream updates */ |
cc79950b MD |
7959 | if (plane->type == DRM_PLANE_TYPE_CURSOR) { |
7960 | if ((fb && crtc == pcrtc) || | |
7961 | (old_plane_state->fb && old_plane_state->crtc == pcrtc)) | |
7962 | cursor_update = true; | |
7963 | ||
e7b07cee | 7964 | continue; |
cc79950b | 7965 | } |
e7b07cee | 7966 | |
f5ba60fe DD |
7967 | if (!fb || !crtc || pcrtc != crtc) |
7968 | continue; | |
7969 | ||
7970 | new_crtc_state = drm_atomic_get_new_crtc_state(state, crtc); | |
7971 | if (!new_crtc_state->active) | |
e7b07cee HW |
7972 | continue; |
7973 | ||
bc7f670e | 7974 | dc_plane = dm_new_plane_state->dc_state; |
da5e1490 AP |
7975 | if (!dc_plane) |
7976 | continue; | |
e7b07cee | 7977 | |
74aa7bd4 | 7978 | bundle->surface_updates[planes_count].surface = dc_plane; |
bc7f670e | 7979 | if (new_pcrtc_state->color_mgmt_changed) { |
74aa7bd4 DF |
7980 | bundle->surface_updates[planes_count].gamma = dc_plane->gamma_correction; |
7981 | bundle->surface_updates[planes_count].in_transfer_func = dc_plane->in_transfer_func; | |
44efb784 | 7982 | bundle->surface_updates[planes_count].gamut_remap_matrix = &dc_plane->gamut_remap_matrix; |
bc7f670e | 7983 | } |
8a48b44c | 7984 | |
8bf0d9cd | 7985 | amdgpu_dm_plane_fill_dc_scaling_info(dm->adev, new_plane_state, |
695af5f9 | 7986 | &bundle->scaling_infos[planes_count]); |
8a48b44c | 7987 | |
695af5f9 NK |
7988 | bundle->surface_updates[planes_count].scaling_info = |
7989 | &bundle->scaling_infos[planes_count]; | |
8a48b44c | 7990 | |
f5031000 | 7991 | plane_needs_flip = old_plane_state->fb && new_plane_state->fb; |
8a48b44c | 7992 | |
f5031000 | 7993 | pflip_present = pflip_present || plane_needs_flip; |
8a48b44c | 7994 | |
f5031000 DF |
7995 | if (!plane_needs_flip) { |
7996 | planes_count += 1; | |
7997 | continue; | |
7998 | } | |
8a48b44c | 7999 | |
695af5f9 | 8000 | fill_dc_plane_info_and_addr( |
8ce5d842 | 8001 | dm->adev, new_plane_state, |
6eed95b0 | 8002 | afb->tiling_flags, |
695af5f9 | 8003 | &bundle->plane_infos[planes_count], |
87b7ebc2 | 8004 | &bundle->flip_addrs[planes_count].address, |
6eed95b0 | 8005 | afb->tmz_surface, false); |
87b7ebc2 | 8006 | |
9f07550b | 8007 | drm_dbg_state(state->dev, "plane: id=%d dcc_en=%d\n", |
87b7ebc2 RS |
8008 | new_plane_state->plane->index, |
8009 | bundle->plane_infos[planes_count].dcc.enable); | |
695af5f9 NK |
8010 | |
8011 | bundle->surface_updates[planes_count].plane_info = | |
8012 | &bundle->plane_infos[planes_count]; | |
8a48b44c | 8013 | |
d6ed6d0d | 8014 | if (acrtc_state->stream->link->psr_settings.psr_feature_enabled) { |
d852871c HM |
8015 | fill_dc_dirty_rects(plane, old_plane_state, |
8016 | new_plane_state, new_crtc_state, | |
d6ed6d0d TC |
8017 | &bundle->flip_addrs[planes_count], |
8018 | &dirty_rects_changed); | |
8019 | ||
8020 | /* | |
8021 | * If the dirty regions changed, PSR-SU need to be disabled temporarily | |
8022 | * and enabled it again after dirty regions are stable to avoid video glitch. | |
8023 | * PSR-SU will be enabled in vblank_control_worker() if user pause the video | |
8024 | * during the PSR-SU was disabled. | |
8025 | */ | |
8026 | if (acrtc_state->stream->link->psr_settings.psr_version >= DC_PSR_VERSION_SU_1 && | |
8027 | acrtc_attach->dm_irq_params.allow_psr_entry && | |
8028 | #ifdef CONFIG_DRM_AMD_SECURE_DISPLAY | |
8029 | !amdgpu_dm_crc_window_is_activated(acrtc_state->base.crtc) && | |
8030 | #endif | |
8031 | dirty_rects_changed) { | |
8032 | mutex_lock(&dm->dc_lock); | |
8033 | acrtc_state->stream->link->psr_settings.psr_dirty_rects_change_timestamp_ns = | |
8034 | timestamp_ns; | |
8035 | if (acrtc_state->stream->link->psr_settings.psr_allow_active) | |
8036 | amdgpu_dm_psr_disable(acrtc_state->stream); | |
8037 | mutex_unlock(&dm->dc_lock); | |
8038 | } | |
8039 | } | |
7cc191ee | 8040 | |
caff0e66 NK |
8041 | /* |
8042 | * Only allow immediate flips for fast updates that don't | |
8043 | * change FB pitch, DCC state, rotation or mirroing. | |
8044 | */ | |
f5031000 | 8045 | bundle->flip_addrs[planes_count].flip_immediate = |
4d85f45c | 8046 | crtc->state->async_flip && |
caff0e66 | 8047 | acrtc_state->update_type == UPDATE_TYPE_FAST; |
8a48b44c | 8048 | |
f5031000 DF |
8049 | timestamp_ns = ktime_get_ns(); |
8050 | bundle->flip_addrs[planes_count].flip_timestamp_in_us = div_u64(timestamp_ns, 1000); | |
8051 | bundle->surface_updates[planes_count].flip_addr = &bundle->flip_addrs[planes_count]; | |
8052 | bundle->surface_updates[planes_count].surface = dc_plane; | |
8a48b44c | 8053 | |
f5031000 DF |
8054 | if (!bundle->surface_updates[planes_count].surface) { |
8055 | DRM_ERROR("No surface for CRTC: id=%d\n", | |
8056 | acrtc_attach->crtc_id); | |
8057 | continue; | |
bc7f670e DF |
8058 | } |
8059 | ||
f5031000 DF |
8060 | if (plane == pcrtc->primary) |
8061 | update_freesync_state_on_stream( | |
8062 | dm, | |
8063 | acrtc_state, | |
8064 | acrtc_state->stream, | |
8065 | dc_plane, | |
8066 | bundle->flip_addrs[planes_count].flip_timestamp_in_us); | |
bc7f670e | 8067 | |
9f07550b | 8068 | drm_dbg_state(state->dev, "%s Flipping to hi: 0x%x, low: 0x%x\n", |
f5031000 DF |
8069 | __func__, |
8070 | bundle->flip_addrs[planes_count].address.grph.addr.high_part, | |
8071 | bundle->flip_addrs[planes_count].address.grph.addr.low_part); | |
bc7f670e DF |
8072 | |
8073 | planes_count += 1; | |
8074 | ||
8a48b44c DF |
8075 | } |
8076 | ||
74aa7bd4 | 8077 | if (pflip_present) { |
634092b1 MK |
8078 | if (!vrr_active) { |
8079 | /* Use old throttling in non-vrr fixed refresh rate mode | |
8080 | * to keep flip scheduling based on target vblank counts | |
8081 | * working in a backwards compatible way, e.g., for | |
8082 | * clients using the GLX_OML_sync_control extension or | |
8083 | * DRI3/Present extension with defined target_msc. | |
8084 | */ | |
e3eff4b5 | 8085 | last_flip_vblank = amdgpu_get_vblank_counter_kms(pcrtc); |
634092b1 MK |
8086 | } |
8087 | else { | |
8088 | /* For variable refresh rate mode only: | |
8089 | * Get vblank of last completed flip to avoid > 1 vrr | |
8090 | * flips per video frame by use of throttling, but allow | |
8091 | * flip programming anywhere in the possibly large | |
8092 | * variable vrr vblank interval for fine-grained flip | |
8093 | * timing control and more opportunity to avoid stutter | |
8094 | * on late submission of flips. | |
8095 | */ | |
8096 | spin_lock_irqsave(&pcrtc->dev->event_lock, flags); | |
5d1c59c4 | 8097 | last_flip_vblank = acrtc_attach->dm_irq_params.last_flip_vblank; |
634092b1 MK |
8098 | spin_unlock_irqrestore(&pcrtc->dev->event_lock, flags); |
8099 | } | |
8100 | ||
fdd1fe57 | 8101 | target_vblank = last_flip_vblank + wait_for_vblank; |
8a48b44c DF |
8102 | |
8103 | /* | |
8104 | * Wait until we're out of the vertical blank period before the one | |
8105 | * targeted by the flip | |
8106 | */ | |
8107 | while ((acrtc_attach->enabled && | |
8108 | (amdgpu_display_get_crtc_scanoutpos(dm->ddev, acrtc_attach->crtc_id, | |
8109 | 0, &vpos, &hpos, NULL, | |
8110 | NULL, &pcrtc->hwmode) | |
8111 | & (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_IN_VBLANK)) == | |
8112 | (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_IN_VBLANK) && | |
8113 | (int)(target_vblank - | |
e3eff4b5 | 8114 | amdgpu_get_vblank_counter_kms(pcrtc)) > 0)) { |
8a48b44c DF |
8115 | usleep_range(1000, 1100); |
8116 | } | |
8117 | ||
8fe684e9 NK |
8118 | /** |
8119 | * Prepare the flip event for the pageflip interrupt to handle. | |
8120 | * | |
8121 | * This only works in the case where we've already turned on the | |
8122 | * appropriate hardware blocks (eg. HUBP) so in the transition case | |
8123 | * from 0 -> n planes we have to skip a hardware generated event | |
8124 | * and rely on sending it from software. | |
8125 | */ | |
8126 | if (acrtc_attach->base.state->event && | |
10a36226 | 8127 | acrtc_state->active_planes > 0) { |
8a48b44c DF |
8128 | drm_crtc_vblank_get(pcrtc); |
8129 | ||
8130 | spin_lock_irqsave(&pcrtc->dev->event_lock, flags); | |
8131 | ||
8132 | WARN_ON(acrtc_attach->pflip_status != AMDGPU_FLIP_NONE); | |
8133 | prepare_flip_isr(acrtc_attach); | |
8134 | ||
8135 | spin_unlock_irqrestore(&pcrtc->dev->event_lock, flags); | |
8136 | } | |
8137 | ||
8138 | if (acrtc_state->stream) { | |
8a48b44c | 8139 | if (acrtc_state->freesync_vrr_info_changed) |
74aa7bd4 | 8140 | bundle->stream_update.vrr_infopacket = |
8a48b44c | 8141 | &acrtc_state->stream->vrr_infopacket; |
e7b07cee | 8142 | } |
cc79950b MD |
8143 | } else if (cursor_update && acrtc_state->active_planes > 0 && |
8144 | acrtc_attach->base.state->event) { | |
8145 | drm_crtc_vblank_get(pcrtc); | |
8146 | ||
8147 | spin_lock_irqsave(&pcrtc->dev->event_lock, flags); | |
8148 | ||
8149 | acrtc_attach->event = acrtc_attach->base.state->event; | |
8150 | acrtc_attach->base.state->event = NULL; | |
8151 | ||
8152 | spin_unlock_irqrestore(&pcrtc->dev->event_lock, flags); | |
e7b07cee HW |
8153 | } |
8154 | ||
bc92c065 | 8155 | /* Update the planes if changed or disable if we don't have any. */ |
ed9656fb ES |
8156 | if ((planes_count || acrtc_state->active_planes == 0) && |
8157 | acrtc_state->stream) { | |
58aa1c50 NK |
8158 | /* |
8159 | * If PSR or idle optimizations are enabled then flush out | |
8160 | * any pending work before hardware programming. | |
8161 | */ | |
06dd1888 NK |
8162 | if (dm->vblank_control_workqueue) |
8163 | flush_workqueue(dm->vblank_control_workqueue); | |
58aa1c50 | 8164 | |
b6e881c9 | 8165 | bundle->stream_update.stream = acrtc_state->stream; |
bc7f670e | 8166 | if (new_pcrtc_state->mode_changed) { |
74aa7bd4 DF |
8167 | bundle->stream_update.src = acrtc_state->stream->src; |
8168 | bundle->stream_update.dst = acrtc_state->stream->dst; | |
e7b07cee HW |
8169 | } |
8170 | ||
cf020d49 NK |
8171 | if (new_pcrtc_state->color_mgmt_changed) { |
8172 | /* | |
8173 | * TODO: This isn't fully correct since we've actually | |
8174 | * already modified the stream in place. | |
8175 | */ | |
8176 | bundle->stream_update.gamut_remap = | |
8177 | &acrtc_state->stream->gamut_remap_matrix; | |
8178 | bundle->stream_update.output_csc_transform = | |
8179 | &acrtc_state->stream->csc_color_matrix; | |
8180 | bundle->stream_update.out_transfer_func = | |
8181 | acrtc_state->stream->out_transfer_func; | |
8182 | } | |
bc7f670e | 8183 | |
8a48b44c | 8184 | acrtc_state->stream->abm_level = acrtc_state->abm_level; |
bc7f670e | 8185 | if (acrtc_state->abm_level != dm_old_crtc_state->abm_level) |
74aa7bd4 | 8186 | bundle->stream_update.abm_level = &acrtc_state->abm_level; |
44d09c6a | 8187 | |
e63e2491 EB |
8188 | /* |
8189 | * If FreeSync state on the stream has changed then we need to | |
8190 | * re-adjust the min/max bounds now that DC doesn't handle this | |
8191 | * as part of commit. | |
8192 | */ | |
a85ba005 | 8193 | if (is_dc_timing_adjust_needed(dm_old_crtc_state, acrtc_state)) { |
e63e2491 EB |
8194 | spin_lock_irqsave(&pcrtc->dev->event_lock, flags); |
8195 | dc_stream_adjust_vmin_vmax( | |
8196 | dm->dc, acrtc_state->stream, | |
585d450c | 8197 | &acrtc_attach->dm_irq_params.vrr_params.adjust); |
e63e2491 EB |
8198 | spin_unlock_irqrestore(&pcrtc->dev->event_lock, flags); |
8199 | } | |
bc7f670e | 8200 | mutex_lock(&dm->dc_lock); |
8c322309 | 8201 | if ((acrtc_state->update_type > UPDATE_TYPE_FAST) && |
d1ebfdd8 | 8202 | acrtc_state->stream->link->psr_settings.psr_allow_active) |
8c322309 RL |
8203 | amdgpu_dm_psr_disable(acrtc_state->stream); |
8204 | ||
81f743a0 RS |
8205 | update_planes_and_stream_adapter(dm->dc, |
8206 | acrtc_state->update_type, | |
8207 | planes_count, | |
8208 | acrtc_state->stream, | |
8209 | &bundle->stream_update, | |
8210 | bundle->surface_updates); | |
8c322309 | 8211 | |
8fe684e9 NK |
8212 | /** |
8213 | * Enable or disable the interrupts on the backend. | |
8214 | * | |
8215 | * Most pipes are put into power gating when unused. | |
8216 | * | |
8217 | * When power gating is enabled on a pipe we lose the | |
8218 | * interrupt enablement state when power gating is disabled. | |
8219 | * | |
8220 | * So we need to update the IRQ control state in hardware | |
8221 | * whenever the pipe turns on (since it could be previously | |
8222 | * power gated) or off (since some pipes can't be power gated | |
8223 | * on some ASICs). | |
8224 | */ | |
8225 | if (dm_old_crtc_state->active_planes != acrtc_state->active_planes) | |
1348969a LT |
8226 | dm_update_pflip_irq_state(drm_to_adev(dev), |
8227 | acrtc_attach); | |
8fe684e9 | 8228 | |
8c322309 | 8229 | if ((acrtc_state->update_type > UPDATE_TYPE_FAST) && |
1cfbbdde | 8230 | acrtc_state->stream->link->psr_settings.psr_version != DC_PSR_VERSION_UNSUPPORTED && |
d1ebfdd8 | 8231 | !acrtc_state->stream->link->psr_settings.psr_feature_enabled) |
8c322309 | 8232 | amdgpu_dm_link_setup_psr(acrtc_state->stream); |
58aa1c50 NK |
8233 | |
8234 | /* Decrement skip count when PSR is enabled and we're doing fast updates. */ | |
8235 | if (acrtc_state->update_type == UPDATE_TYPE_FAST && | |
8236 | acrtc_state->stream->link->psr_settings.psr_feature_enabled) { | |
8237 | struct amdgpu_dm_connector *aconn = | |
8238 | (struct amdgpu_dm_connector *)acrtc_state->stream->dm_stream_context; | |
1a365683 RL |
8239 | |
8240 | if (aconn->psr_skip_count > 0) | |
8241 | aconn->psr_skip_count--; | |
58aa1c50 NK |
8242 | |
8243 | /* Allow PSR when skip count is 0. */ | |
8244 | acrtc_attach->dm_irq_params.allow_psr_entry = !aconn->psr_skip_count; | |
7cc191ee LL |
8245 | |
8246 | /* | |
8247 | * If sink supports PSR SU, there is no need to rely on | |
8248 | * a vblank event disable request to enable PSR. PSR SU | |
8249 | * can be enabled immediately once OS demonstrates an | |
8250 | * adequate number of fast atomic commits to notify KMD | |
8251 | * of update events. See `vblank_control_worker()`. | |
8252 | */ | |
8253 | if (acrtc_state->stream->link->psr_settings.psr_version >= DC_PSR_VERSION_SU_1 && | |
8254 | acrtc_attach->dm_irq_params.allow_psr_entry && | |
c0459bdd AL |
8255 | #ifdef CONFIG_DRM_AMD_SECURE_DISPLAY |
8256 | !amdgpu_dm_crc_window_is_activated(acrtc_state->base.crtc) && | |
8257 | #endif | |
d6ed6d0d TC |
8258 | !acrtc_state->stream->link->psr_settings.psr_allow_active && |
8259 | (timestamp_ns - | |
8260 | acrtc_state->stream->link->psr_settings.psr_dirty_rects_change_timestamp_ns) > | |
8261 | 500000000) | |
7cc191ee | 8262 | amdgpu_dm_psr_enable(acrtc_state->stream); |
58aa1c50 NK |
8263 | } else { |
8264 | acrtc_attach->dm_irq_params.allow_psr_entry = false; | |
8c322309 RL |
8265 | } |
8266 | ||
bc7f670e | 8267 | mutex_unlock(&dm->dc_lock); |
e7b07cee | 8268 | } |
4b510503 | 8269 | |
8ad27806 NK |
8270 | /* |
8271 | * Update cursor state *after* programming all the planes. | |
8272 | * This avoids redundant programming in the case where we're going | |
8273 | * to be disabling a single plane - those pipes are being disabled. | |
8274 | */ | |
8275 | if (acrtc_state->active_planes) | |
8276 | amdgpu_dm_commit_cursors(state); | |
80c218d5 | 8277 | |
4b510503 | 8278 | cleanup: |
74aa7bd4 | 8279 | kfree(bundle); |
e7b07cee HW |
8280 | } |
8281 | ||
6ce8f316 NK |
8282 | static void amdgpu_dm_commit_audio(struct drm_device *dev, |
8283 | struct drm_atomic_state *state) | |
8284 | { | |
1348969a | 8285 | struct amdgpu_device *adev = drm_to_adev(dev); |
6ce8f316 NK |
8286 | struct amdgpu_dm_connector *aconnector; |
8287 | struct drm_connector *connector; | |
8288 | struct drm_connector_state *old_con_state, *new_con_state; | |
8289 | struct drm_crtc_state *new_crtc_state; | |
8290 | struct dm_crtc_state *new_dm_crtc_state; | |
8291 | const struct dc_stream_status *status; | |
8292 | int i, inst; | |
8293 | ||
8294 | /* Notify device removals. */ | |
8295 | for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) { | |
8296 | if (old_con_state->crtc != new_con_state->crtc) { | |
8297 | /* CRTC changes require notification. */ | |
8298 | goto notify; | |
8299 | } | |
8300 | ||
8301 | if (!new_con_state->crtc) | |
8302 | continue; | |
8303 | ||
8304 | new_crtc_state = drm_atomic_get_new_crtc_state( | |
8305 | state, new_con_state->crtc); | |
8306 | ||
8307 | if (!new_crtc_state) | |
8308 | continue; | |
8309 | ||
8310 | if (!drm_atomic_crtc_needs_modeset(new_crtc_state)) | |
8311 | continue; | |
8312 | ||
3335a135 | 8313 | notify: |
6ce8f316 NK |
8314 | aconnector = to_amdgpu_dm_connector(connector); |
8315 | ||
8316 | mutex_lock(&adev->dm.audio_lock); | |
8317 | inst = aconnector->audio_inst; | |
8318 | aconnector->audio_inst = -1; | |
8319 | mutex_unlock(&adev->dm.audio_lock); | |
8320 | ||
8321 | amdgpu_dm_audio_eld_notify(adev, inst); | |
8322 | } | |
8323 | ||
8324 | /* Notify audio device additions. */ | |
8325 | for_each_new_connector_in_state(state, connector, new_con_state, i) { | |
8326 | if (!new_con_state->crtc) | |
8327 | continue; | |
8328 | ||
8329 | new_crtc_state = drm_atomic_get_new_crtc_state( | |
8330 | state, new_con_state->crtc); | |
8331 | ||
8332 | if (!new_crtc_state) | |
8333 | continue; | |
8334 | ||
8335 | if (!drm_atomic_crtc_needs_modeset(new_crtc_state)) | |
8336 | continue; | |
8337 | ||
8338 | new_dm_crtc_state = to_dm_crtc_state(new_crtc_state); | |
8339 | if (!new_dm_crtc_state->stream) | |
8340 | continue; | |
8341 | ||
8342 | status = dc_stream_get_status(new_dm_crtc_state->stream); | |
8343 | if (!status) | |
8344 | continue; | |
8345 | ||
8346 | aconnector = to_amdgpu_dm_connector(connector); | |
8347 | ||
8348 | mutex_lock(&adev->dm.audio_lock); | |
8349 | inst = status->audio_inst; | |
8350 | aconnector->audio_inst = inst; | |
8351 | mutex_unlock(&adev->dm.audio_lock); | |
8352 | ||
8353 | amdgpu_dm_audio_eld_notify(adev, inst); | |
8354 | } | |
8355 | } | |
8356 | ||
1f6010a9 | 8357 | /* |
27b3f4fc LSL |
8358 | * amdgpu_dm_crtc_copy_transient_flags - copy mirrored flags from DRM to DC |
8359 | * @crtc_state: the DRM CRTC state | |
8360 | * @stream_state: the DC stream state. | |
8361 | * | |
8362 | * Copy the mirrored transient state flags from DRM, to DC. It is used to bring | |
8363 | * a dc_stream_state's flags in sync with a drm_crtc_state's flags. | |
8364 | */ | |
8365 | static void amdgpu_dm_crtc_copy_transient_flags(struct drm_crtc_state *crtc_state, | |
8366 | struct dc_stream_state *stream_state) | |
8367 | { | |
b9952f93 | 8368 | stream_state->mode_changed = drm_atomic_crtc_needs_modeset(crtc_state); |
27b3f4fc | 8369 | } |
e7b07cee | 8370 | |
b8592b48 LL |
8371 | /** |
8372 | * amdgpu_dm_atomic_commit_tail() - AMDgpu DM's commit tail implementation. | |
8373 | * @state: The atomic state to commit | |
8374 | * | |
8375 | * This will tell DC to commit the constructed DC state from atomic_check, | |
8376 | * programming the hardware. Any failures here implies a hardware failure, since | |
8377 | * atomic check should have filtered anything non-kosher. | |
8378 | */ | |
7578ecda | 8379 | static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state) |
e7b07cee HW |
8380 | { |
8381 | struct drm_device *dev = state->dev; | |
1348969a | 8382 | struct amdgpu_device *adev = drm_to_adev(dev); |
e7b07cee HW |
8383 | struct amdgpu_display_manager *dm = &adev->dm; |
8384 | struct dm_atomic_state *dm_state; | |
eb3dc897 | 8385 | struct dc_state *dc_state = NULL, *dc_state_temp = NULL; |
ae67558b | 8386 | u32 i, j; |
5cc6dcbd | 8387 | struct drm_crtc *crtc; |
0bc9706d | 8388 | struct drm_crtc_state *old_crtc_state, *new_crtc_state; |
e7b07cee HW |
8389 | unsigned long flags; |
8390 | bool wait_for_vblank = true; | |
8391 | struct drm_connector *connector; | |
c2cea706 | 8392 | struct drm_connector_state *old_con_state, *new_con_state; |
54d76575 | 8393 | struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state; |
fe2a1965 | 8394 | int crtc_disable_count = 0; |
6ee90e88 | 8395 | bool mode_set_reset_required = false; |
047de3f1 | 8396 | int r; |
e7b07cee | 8397 | |
e8a98235 RS |
8398 | trace_amdgpu_dm_atomic_commit_tail_begin(state); |
8399 | ||
047de3f1 CK |
8400 | r = drm_atomic_helper_wait_for_fences(dev, state, false); |
8401 | if (unlikely(r)) | |
8402 | DRM_ERROR("Waiting for fences timed out!"); | |
8403 | ||
e7b07cee | 8404 | drm_atomic_helper_update_legacy_modeset_state(dev, state); |
a5c2c0d1 | 8405 | drm_dp_mst_atomic_wait_for_dependencies(state); |
e7b07cee | 8406 | |
eb3dc897 NK |
8407 | dm_state = dm_atomic_get_new_state(state); |
8408 | if (dm_state && dm_state->context) { | |
8409 | dc_state = dm_state->context; | |
8410 | } else { | |
8411 | /* No state changes, retain current state. */ | |
813d20dc | 8412 | dc_state_temp = dc_create_state(dm->dc); |
eb3dc897 NK |
8413 | ASSERT(dc_state_temp); |
8414 | dc_state = dc_state_temp; | |
8415 | dc_resource_state_copy_construct_current(dm->dc, dc_state); | |
8416 | } | |
e7b07cee | 8417 | |
6d90a208 AP |
8418 | for_each_oldnew_crtc_in_state (state, crtc, old_crtc_state, |
8419 | new_crtc_state, i) { | |
8420 | struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); | |
8421 | ||
8422 | dm_old_crtc_state = to_dm_crtc_state(old_crtc_state); | |
8423 | ||
8424 | if (old_crtc_state->active && | |
8425 | (!new_crtc_state->active || | |
8426 | drm_atomic_crtc_needs_modeset(new_crtc_state))) { | |
8427 | manage_dm_interrupts(adev, acrtc, false); | |
8428 | dc_stream_release(dm_old_crtc_state->stream); | |
8429 | } | |
8430 | } | |
8431 | ||
8976f73b RS |
8432 | drm_atomic_helper_calc_timestamping_constants(state); |
8433 | ||
e7b07cee | 8434 | /* update changed items */ |
0bc9706d | 8435 | for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { |
e7b07cee | 8436 | struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); |
b830ebc9 | 8437 | |
54d76575 LSL |
8438 | dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); |
8439 | dm_old_crtc_state = to_dm_crtc_state(old_crtc_state); | |
e7b07cee | 8440 | |
9f07550b | 8441 | drm_dbg_state(state->dev, |
e7b07cee HW |
8442 | "amdgpu_crtc id:%d crtc_state_flags: enable:%d, active:%d, " |
8443 | "planes_changed:%d, mode_changed:%d,active_changed:%d," | |
8444 | "connectors_changed:%d\n", | |
8445 | acrtc->crtc_id, | |
0bc9706d LSL |
8446 | new_crtc_state->enable, |
8447 | new_crtc_state->active, | |
8448 | new_crtc_state->planes_changed, | |
8449 | new_crtc_state->mode_changed, | |
8450 | new_crtc_state->active_changed, | |
8451 | new_crtc_state->connectors_changed); | |
e7b07cee | 8452 | |
5c68c652 VL |
8453 | /* Disable cursor if disabling crtc */ |
8454 | if (old_crtc_state->active && !new_crtc_state->active) { | |
8455 | struct dc_cursor_position position; | |
8456 | ||
8457 | memset(&position, 0, sizeof(position)); | |
8458 | mutex_lock(&dm->dc_lock); | |
8459 | dc_stream_set_cursor_position(dm_old_crtc_state->stream, &position); | |
8460 | mutex_unlock(&dm->dc_lock); | |
8461 | } | |
8462 | ||
27b3f4fc LSL |
8463 | /* Copy all transient state flags into dc state */ |
8464 | if (dm_new_crtc_state->stream) { | |
8465 | amdgpu_dm_crtc_copy_transient_flags(&dm_new_crtc_state->base, | |
8466 | dm_new_crtc_state->stream); | |
8467 | } | |
8468 | ||
e7b07cee HW |
8469 | /* handles headless hotplug case, updating new_state and |
8470 | * aconnector as needed | |
8471 | */ | |
8472 | ||
6c5e25a0 | 8473 | if (amdgpu_dm_crtc_modeset_required(new_crtc_state, dm_new_crtc_state->stream, dm_old_crtc_state->stream)) { |
e7b07cee | 8474 | |
4711c033 | 8475 | DRM_DEBUG_ATOMIC("Atomic commit: SET crtc id %d: [%p]\n", acrtc->crtc_id, acrtc); |
e7b07cee | 8476 | |
54d76575 | 8477 | if (!dm_new_crtc_state->stream) { |
e7b07cee | 8478 | /* |
b830ebc9 HW |
8479 | * this could happen because of issues with |
8480 | * userspace notifications delivery. | |
8481 | * In this case userspace tries to set mode on | |
1f6010a9 DF |
8482 | * display which is disconnected in fact. |
8483 | * dc_sink is NULL in this case on aconnector. | |
b830ebc9 HW |
8484 | * We expect reset mode will come soon. |
8485 | * | |
8486 | * This can also happen when unplug is done | |
8487 | * during resume sequence ended | |
8488 | * | |
8489 | * In this case, we want to pretend we still | |
8490 | * have a sink to keep the pipe running so that | |
8491 | * hw state is consistent with the sw state | |
8492 | */ | |
f1ad2f5e | 8493 | DRM_DEBUG_DRIVER("%s: Failed to create new stream for crtc %d\n", |
e7b07cee HW |
8494 | __func__, acrtc->base.base.id); |
8495 | continue; | |
8496 | } | |
8497 | ||
54d76575 LSL |
8498 | if (dm_old_crtc_state->stream) |
8499 | remove_stream(adev, acrtc, dm_old_crtc_state->stream); | |
e7b07cee | 8500 | |
97028037 LP |
8501 | pm_runtime_get_noresume(dev->dev); |
8502 | ||
e7b07cee | 8503 | acrtc->enabled = true; |
0bc9706d LSL |
8504 | acrtc->hw_mode = new_crtc_state->mode; |
8505 | crtc->hwmode = new_crtc_state->mode; | |
6ee90e88 | 8506 | mode_set_reset_required = true; |
0bc9706d | 8507 | } else if (modereset_required(new_crtc_state)) { |
4711c033 | 8508 | DRM_DEBUG_ATOMIC("Atomic commit: RESET. crtc id %d:[%p]\n", acrtc->crtc_id, acrtc); |
e7b07cee | 8509 | /* i.e. reset mode */ |
6ee90e88 | 8510 | if (dm_old_crtc_state->stream) |
54d76575 | 8511 | remove_stream(adev, acrtc, dm_old_crtc_state->stream); |
a85ba005 | 8512 | |
6ee90e88 | 8513 | mode_set_reset_required = true; |
e7b07cee HW |
8514 | } |
8515 | } /* for_each_crtc_in_state() */ | |
8516 | ||
eb3dc897 | 8517 | if (dc_state) { |
6ee90e88 | 8518 | /* if there mode set or reset, disable eDP PSR */ |
58aa1c50 | 8519 | if (mode_set_reset_required) { |
06dd1888 NK |
8520 | if (dm->vblank_control_workqueue) |
8521 | flush_workqueue(dm->vblank_control_workqueue); | |
cae5c1ab | 8522 | |
6ee90e88 | 8523 | amdgpu_dm_psr_disable_all(dm); |
58aa1c50 | 8524 | } |
6ee90e88 | 8525 | |
eb3dc897 | 8526 | dm_enable_per_frame_crtc_master_sync(dc_state); |
674e78ac | 8527 | mutex_lock(&dm->dc_lock); |
b8272241 | 8528 | WARN_ON(!dc_commit_streams(dm->dc, dc_state->streams, dc_state->stream_count)); |
f3106c94 JC |
8529 | |
8530 | /* Allow idle optimization when vblank count is 0 for display off */ | |
8531 | if (dm->active_vblank_irq_count == 0) | |
8532 | dc_allow_idle_optimizations(dm->dc, true); | |
674e78ac | 8533 | mutex_unlock(&dm->dc_lock); |
fa2123db | 8534 | } |
fe8858bb | 8535 | |
0bc9706d | 8536 | for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) { |
e7b07cee | 8537 | struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); |
b830ebc9 | 8538 | |
54d76575 | 8539 | dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); |
e7b07cee | 8540 | |
54d76575 | 8541 | if (dm_new_crtc_state->stream != NULL) { |
e7b07cee | 8542 | const struct dc_stream_status *status = |
54d76575 | 8543 | dc_stream_get_status(dm_new_crtc_state->stream); |
e7b07cee | 8544 | |
eb3dc897 | 8545 | if (!status) |
09f609c3 LL |
8546 | status = dc_stream_get_status_from_state(dc_state, |
8547 | dm_new_crtc_state->stream); | |
e7b07cee | 8548 | if (!status) |
54d76575 | 8549 | DC_ERR("got no status for stream %p on acrtc%p\n", dm_new_crtc_state->stream, acrtc); |
e7b07cee HW |
8550 | else |
8551 | acrtc->otg_inst = status->primary_otg_inst; | |
8552 | } | |
8553 | } | |
0c8620d6 BL |
8554 | for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) { |
8555 | struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state); | |
8556 | struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc); | |
8557 | struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); | |
8558 | ||
e8fd3eeb | 8559 | pr_debug("[HDCP_DM] -------------- i : %x ----------\n", i); |
8560 | ||
8561 | if (!connector) | |
8562 | continue; | |
8563 | ||
8564 | pr_debug("[HDCP_DM] connector->index: %x connect_status: %x dpms: %x\n", | |
8565 | connector->index, connector->status, connector->dpms); | |
8566 | pr_debug("[HDCP_DM] state protection old: %x new: %x\n", | |
8567 | old_con_state->content_protection, new_con_state->content_protection); | |
8568 | ||
8569 | if (aconnector->dc_sink) { | |
8570 | if (aconnector->dc_sink->sink_signal != SIGNAL_TYPE_VIRTUAL && | |
8571 | aconnector->dc_sink->sink_signal != SIGNAL_TYPE_NONE) { | |
8572 | pr_debug("[HDCP_DM] pipe_ctx dispname=%s\n", | |
8573 | aconnector->dc_sink->edid_caps.display_name); | |
8574 | } | |
8575 | } | |
8576 | ||
0c8620d6 | 8577 | new_crtc_state = NULL; |
e8fd3eeb | 8578 | old_crtc_state = NULL; |
0c8620d6 | 8579 | |
e8fd3eeb | 8580 | if (acrtc) { |
0c8620d6 | 8581 | new_crtc_state = drm_atomic_get_new_crtc_state(state, &acrtc->base); |
e8fd3eeb | 8582 | old_crtc_state = drm_atomic_get_old_crtc_state(state, &acrtc->base); |
8583 | } | |
8584 | ||
8585 | if (old_crtc_state) | |
8586 | pr_debug("old crtc en: %x a: %x m: %x a-chg: %x c-chg: %x\n", | |
8587 | old_crtc_state->enable, | |
8588 | old_crtc_state->active, | |
8589 | old_crtc_state->mode_changed, | |
8590 | old_crtc_state->active_changed, | |
8591 | old_crtc_state->connectors_changed); | |
8592 | ||
8593 | if (new_crtc_state) | |
8594 | pr_debug("NEW crtc en: %x a: %x m: %x a-chg: %x c-chg: %x\n", | |
8595 | new_crtc_state->enable, | |
8596 | new_crtc_state->active, | |
8597 | new_crtc_state->mode_changed, | |
8598 | new_crtc_state->active_changed, | |
8599 | new_crtc_state->connectors_changed); | |
8600 | } | |
8601 | ||
8602 | for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) { | |
8603 | struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state); | |
8604 | struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc); | |
8605 | struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); | |
8606 | ||
8607 | new_crtc_state = NULL; | |
8608 | old_crtc_state = NULL; | |
8609 | ||
8610 | if (acrtc) { | |
8611 | new_crtc_state = drm_atomic_get_new_crtc_state(state, &acrtc->base); | |
8612 | old_crtc_state = drm_atomic_get_old_crtc_state(state, &acrtc->base); | |
8613 | } | |
0c8620d6 BL |
8614 | |
8615 | dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); | |
8616 | ||
8617 | if (dm_new_crtc_state && dm_new_crtc_state->stream == NULL && | |
8618 | connector->state->content_protection == DRM_MODE_CONTENT_PROTECTION_ENABLED) { | |
8619 | hdcp_reset_display(adev->dm.hdcp_workqueue, aconnector->dc_link->link_index); | |
8620 | new_con_state->content_protection = DRM_MODE_CONTENT_PROTECTION_DESIRED; | |
97f6c917 | 8621 | dm_new_con_state->update_hdcp = true; |
0c8620d6 BL |
8622 | continue; |
8623 | } | |
8624 | ||
e8fd3eeb | 8625 | if (is_content_protection_different(new_crtc_state, old_crtc_state, new_con_state, |
8626 | old_con_state, connector, adev->dm.hdcp_workqueue)) { | |
82986fd6 | 8627 | /* when display is unplugged from mst hub, connctor will |
8628 | * be destroyed within dm_dp_mst_connector_destroy. connector | |
8629 | * hdcp perperties, like type, undesired, desired, enabled, | |
8630 | * will be lost. So, save hdcp properties into hdcp_work within | |
8631 | * amdgpu_dm_atomic_commit_tail. if the same display is | |
8632 | * plugged back with same display index, its hdcp properties | |
8633 | * will be retrieved from hdcp_work within dm_dp_mst_get_modes | |
8634 | */ | |
8635 | ||
e8fd3eeb | 8636 | bool enable_encryption = false; |
8637 | ||
8638 | if (new_con_state->content_protection == DRM_MODE_CONTENT_PROTECTION_DESIRED) | |
8639 | enable_encryption = true; | |
8640 | ||
82986fd6 | 8641 | if (aconnector->dc_link && aconnector->dc_sink && |
8642 | aconnector->dc_link->type == dc_connection_mst_branch) { | |
8643 | struct hdcp_workqueue *hdcp_work = adev->dm.hdcp_workqueue; | |
8644 | struct hdcp_workqueue *hdcp_w = | |
8645 | &hdcp_work[aconnector->dc_link->link_index]; | |
8646 | ||
8647 | hdcp_w->hdcp_content_type[connector->index] = | |
8648 | new_con_state->hdcp_content_type; | |
8649 | hdcp_w->content_protection[connector->index] = | |
8650 | new_con_state->content_protection; | |
8651 | } | |
8652 | ||
e8fd3eeb | 8653 | if (new_crtc_state && new_crtc_state->mode_changed && |
8654 | new_con_state->content_protection >= DRM_MODE_CONTENT_PROTECTION_DESIRED) | |
8655 | enable_encryption = true; | |
8656 | ||
8657 | DRM_INFO("[HDCP_DM] hdcp_update_display enable_encryption = %x\n", enable_encryption); | |
8658 | ||
b1abe558 BL |
8659 | hdcp_update_display( |
8660 | adev->dm.hdcp_workqueue, aconnector->dc_link->link_index, aconnector, | |
e8fd3eeb | 8661 | new_con_state->hdcp_content_type, enable_encryption); |
8662 | } | |
0c8620d6 | 8663 | } |
e7b07cee | 8664 | |
02d6a6fc | 8665 | /* Handle connector state changes */ |
c2cea706 | 8666 | for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) { |
54d76575 LSL |
8667 | struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state); |
8668 | struct dm_connector_state *dm_old_con_state = to_dm_connector_state(old_con_state); | |
8669 | struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc); | |
efc8278e | 8670 | struct dc_surface_update dummy_updates[MAX_SURFACES]; |
19afd799 | 8671 | struct dc_stream_update stream_update; |
b232d4ed | 8672 | struct dc_info_packet hdr_packet; |
e7b07cee | 8673 | struct dc_stream_status *status = NULL; |
b232d4ed | 8674 | bool abm_changed, hdr_changed, scaling_changed; |
e7b07cee | 8675 | |
efc8278e | 8676 | memset(&dummy_updates, 0, sizeof(dummy_updates)); |
19afd799 NC |
8677 | memset(&stream_update, 0, sizeof(stream_update)); |
8678 | ||
44d09c6a | 8679 | if (acrtc) { |
0bc9706d | 8680 | new_crtc_state = drm_atomic_get_new_crtc_state(state, &acrtc->base); |
44d09c6a HW |
8681 | old_crtc_state = drm_atomic_get_old_crtc_state(state, &acrtc->base); |
8682 | } | |
0bc9706d | 8683 | |
e7b07cee | 8684 | /* Skip any modesets/resets */ |
0bc9706d | 8685 | if (!acrtc || drm_atomic_crtc_needs_modeset(new_crtc_state)) |
e7b07cee HW |
8686 | continue; |
8687 | ||
54d76575 | 8688 | dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); |
c1ee92f9 DF |
8689 | dm_old_crtc_state = to_dm_crtc_state(old_crtc_state); |
8690 | ||
b232d4ed NK |
8691 | scaling_changed = is_scaling_state_different(dm_new_con_state, |
8692 | dm_old_con_state); | |
8693 | ||
8694 | abm_changed = dm_new_crtc_state->abm_level != | |
8695 | dm_old_crtc_state->abm_level; | |
8696 | ||
8697 | hdr_changed = | |
72921cdf | 8698 | !drm_connector_atomic_hdr_metadata_equal(old_con_state, new_con_state); |
b232d4ed NK |
8699 | |
8700 | if (!scaling_changed && !abm_changed && !hdr_changed) | |
c1ee92f9 | 8701 | continue; |
e7b07cee | 8702 | |
b6e881c9 | 8703 | stream_update.stream = dm_new_crtc_state->stream; |
b232d4ed | 8704 | if (scaling_changed) { |
02d6a6fc | 8705 | update_stream_scaling_settings(&dm_new_con_state->base.crtc->mode, |
b6e881c9 | 8706 | dm_new_con_state, dm_new_crtc_state->stream); |
e7b07cee | 8707 | |
02d6a6fc DF |
8708 | stream_update.src = dm_new_crtc_state->stream->src; |
8709 | stream_update.dst = dm_new_crtc_state->stream->dst; | |
8710 | } | |
8711 | ||
b232d4ed | 8712 | if (abm_changed) { |
02d6a6fc DF |
8713 | dm_new_crtc_state->stream->abm_level = dm_new_crtc_state->abm_level; |
8714 | ||
8715 | stream_update.abm_level = &dm_new_crtc_state->abm_level; | |
8716 | } | |
70e8ffc5 | 8717 | |
b232d4ed NK |
8718 | if (hdr_changed) { |
8719 | fill_hdr_info_packet(new_con_state, &hdr_packet); | |
8720 | stream_update.hdr_static_metadata = &hdr_packet; | |
8721 | } | |
8722 | ||
54d76575 | 8723 | status = dc_stream_get_status(dm_new_crtc_state->stream); |
57738ae4 ND |
8724 | |
8725 | if (WARN_ON(!status)) | |
8726 | continue; | |
8727 | ||
3be5262e | 8728 | WARN_ON(!status->plane_count); |
e7b07cee | 8729 | |
02d6a6fc DF |
8730 | /* |
8731 | * TODO: DC refuses to perform stream updates without a dc_surface_update. | |
8732 | * Here we create an empty update on each plane. | |
8733 | * To fix this, DC should permit updating only stream properties. | |
8734 | */ | |
8735 | for (j = 0; j < status->plane_count; j++) | |
efc8278e | 8736 | dummy_updates[j].surface = status->plane_states[0]; |
02d6a6fc DF |
8737 | |
8738 | ||
8739 | mutex_lock(&dm->dc_lock); | |
f7511289 RS |
8740 | dc_update_planes_and_stream(dm->dc, |
8741 | dummy_updates, | |
8742 | status->plane_count, | |
8743 | dm_new_crtc_state->stream, | |
8744 | &stream_update); | |
02d6a6fc | 8745 | mutex_unlock(&dm->dc_lock); |
e7b07cee HW |
8746 | } |
8747 | ||
8fe684e9 NK |
8748 | /** |
8749 | * Enable interrupts for CRTCs that are newly enabled or went through | |
8750 | * a modeset. It was intentionally deferred until after the front end | |
8751 | * state was modified to wait until the OTG was on and so the IRQ | |
8752 | * handlers didn't access stale or invalid state. | |
8753 | */ | |
8754 | for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { | |
8755 | struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); | |
8e7b6fee WL |
8756 | #ifdef CONFIG_DEBUG_FS |
8757 | enum amdgpu_dm_pipe_crc_source cur_crc_src; | |
8799c0be YL |
8758 | #endif |
8759 | /* Count number of newly disabled CRTCs for dropping PM refs later. */ | |
8760 | if (old_crtc_state->active && !new_crtc_state->active) | |
8761 | crtc_disable_count++; | |
8762 | ||
8763 | dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); | |
8764 | dm_old_crtc_state = to_dm_crtc_state(old_crtc_state); | |
8765 | ||
8766 | /* For freesync config update on crtc state and params for irq */ | |
8767 | update_stream_irq_parameters(dm, dm_new_crtc_state); | |
8768 | ||
8769 | #ifdef CONFIG_DEBUG_FS | |
d98af272 WL |
8770 | spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags); |
8771 | cur_crc_src = acrtc->dm_irq_params.crc_src; | |
8772 | spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags); | |
8e7b6fee | 8773 | #endif |
585d450c | 8774 | |
8fe684e9 NK |
8775 | if (new_crtc_state->active && |
8776 | (!old_crtc_state->active || | |
8777 | drm_atomic_crtc_needs_modeset(new_crtc_state))) { | |
585d450c AP |
8778 | dc_stream_retain(dm_new_crtc_state->stream); |
8779 | acrtc->dm_irq_params.stream = dm_new_crtc_state->stream; | |
8fe684e9 | 8780 | manage_dm_interrupts(adev, acrtc, true); |
8799c0be YL |
8781 | } |
8782 | /* Handle vrr on->off / off->on transitions */ | |
8783 | amdgpu_dm_handle_vrr_transition(dm_old_crtc_state, dm_new_crtc_state); | |
e2881d6d | 8784 | |
24eb9374 | 8785 | #ifdef CONFIG_DEBUG_FS |
8799c0be YL |
8786 | if (new_crtc_state->active && |
8787 | (!old_crtc_state->active || | |
8788 | drm_atomic_crtc_needs_modeset(new_crtc_state))) { | |
8fe684e9 NK |
8789 | /** |
8790 | * Frontend may have changed so reapply the CRC capture | |
8791 | * settings for the stream. | |
8792 | */ | |
8e7b6fee | 8793 | if (amdgpu_dm_is_valid_crc_source(cur_crc_src)) { |
86bc2219 | 8794 | #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY) |
d98af272 WL |
8795 | if (amdgpu_dm_crc_window_is_activated(crtc)) { |
8796 | spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags); | |
c0459bdd | 8797 | acrtc->dm_irq_params.window_param.update_win = true; |
1b11ff76 AL |
8798 | |
8799 | /** | |
8800 | * It takes 2 frames for HW to stably generate CRC when | |
8801 | * resuming from suspend, so we set skip_frame_cnt 2. | |
8802 | */ | |
c0459bdd | 8803 | acrtc->dm_irq_params.window_param.skip_frame_cnt = 2; |
d98af272 WL |
8804 | spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags); |
8805 | } | |
86bc2219 | 8806 | #endif |
bbc49fc0 WL |
8807 | if (amdgpu_dm_crtc_configure_crc_source( |
8808 | crtc, dm_new_crtc_state, cur_crc_src)) | |
8809 | DRM_DEBUG_DRIVER("Failed to configure crc source"); | |
8799c0be | 8810 | } |
8fe684e9 | 8811 | } |
2130b87b | 8812 | #endif |
8fe684e9 | 8813 | } |
e7b07cee | 8814 | |
420cd472 | 8815 | for_each_new_crtc_in_state(state, crtc, new_crtc_state, j) |
4d85f45c | 8816 | if (new_crtc_state->async_flip) |
420cd472 DF |
8817 | wait_for_vblank = false; |
8818 | ||
e7b07cee | 8819 | /* update planes when needed per crtc*/ |
5cc6dcbd | 8820 | for_each_new_crtc_in_state(state, crtc, new_crtc_state, j) { |
54d76575 | 8821 | dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); |
e7b07cee | 8822 | |
54d76575 | 8823 | if (dm_new_crtc_state->stream) |
eb3dc897 | 8824 | amdgpu_dm_commit_planes(state, dc_state, dev, |
420cd472 | 8825 | dm, crtc, wait_for_vblank); |
e7b07cee HW |
8826 | } |
8827 | ||
6ce8f316 NK |
8828 | /* Update audio instances for each connector. */ |
8829 | amdgpu_dm_commit_audio(dev, state); | |
8830 | ||
7230362c | 8831 | /* restore the backlight level */ |
7fd13bae AD |
8832 | for (i = 0; i < dm->num_of_edps; i++) { |
8833 | if (dm->backlight_dev[i] && | |
4052287a | 8834 | (dm->actual_brightness[i] != dm->brightness[i])) |
7fd13bae AD |
8835 | amdgpu_dm_backlight_set_level(dm, i, dm->brightness[i]); |
8836 | } | |
83a3439d | 8837 | |
e7b07cee HW |
8838 | /* |
8839 | * send vblank event on all events not handled in flip and | |
8840 | * mark consumed event for drm_atomic_helper_commit_hw_done | |
8841 | */ | |
4a580877 | 8842 | spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags); |
0bc9706d | 8843 | for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) { |
e7b07cee | 8844 | |
0bc9706d LSL |
8845 | if (new_crtc_state->event) |
8846 | drm_send_event_locked(dev, &new_crtc_state->event->base); | |
e7b07cee | 8847 | |
0bc9706d | 8848 | new_crtc_state->event = NULL; |
e7b07cee | 8849 | } |
4a580877 | 8850 | spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags); |
e7b07cee | 8851 | |
29c8f234 LL |
8852 | /* Signal HW programming completion */ |
8853 | drm_atomic_helper_commit_hw_done(state); | |
e7b07cee HW |
8854 | |
8855 | if (wait_for_vblank) | |
320a1274 | 8856 | drm_atomic_helper_wait_for_flip_done(dev, state); |
e7b07cee HW |
8857 | |
8858 | drm_atomic_helper_cleanup_planes(dev, state); | |
97028037 | 8859 | |
5f6fab24 AD |
8860 | /* return the stolen vga memory back to VRAM */ |
8861 | if (!adev->mman.keep_stolen_vga_memory) | |
8862 | amdgpu_bo_free_kernel(&adev->mman.stolen_vga_memory, NULL, NULL); | |
8863 | amdgpu_bo_free_kernel(&adev->mman.stolen_extended_memory, NULL, NULL); | |
8864 | ||
1f6010a9 DF |
8865 | /* |
8866 | * Finally, drop a runtime PM reference for each newly disabled CRTC, | |
97028037 LP |
8867 | * so we can put the GPU into runtime suspend if we're not driving any |
8868 | * displays anymore | |
8869 | */ | |
fe2a1965 LP |
8870 | for (i = 0; i < crtc_disable_count; i++) |
8871 | pm_runtime_put_autosuspend(dev->dev); | |
97028037 | 8872 | pm_runtime_mark_last_busy(dev->dev); |
eb3dc897 NK |
8873 | |
8874 | if (dc_state_temp) | |
8875 | dc_release_state(dc_state_temp); | |
e7b07cee HW |
8876 | } |
8877 | ||
e7b07cee HW |
8878 | static int dm_force_atomic_commit(struct drm_connector *connector) |
8879 | { | |
8880 | int ret = 0; | |
8881 | struct drm_device *ddev = connector->dev; | |
8882 | struct drm_atomic_state *state = drm_atomic_state_alloc(ddev); | |
8883 | struct amdgpu_crtc *disconnected_acrtc = to_amdgpu_crtc(connector->encoder->crtc); | |
8884 | struct drm_plane *plane = disconnected_acrtc->base.primary; | |
8885 | struct drm_connector_state *conn_state; | |
8886 | struct drm_crtc_state *crtc_state; | |
8887 | struct drm_plane_state *plane_state; | |
8888 | ||
8889 | if (!state) | |
8890 | return -ENOMEM; | |
8891 | ||
8892 | state->acquire_ctx = ddev->mode_config.acquire_ctx; | |
8893 | ||
8894 | /* Construct an atomic state to restore previous display setting */ | |
8895 | ||
8896 | /* | |
8897 | * Attach connectors to drm_atomic_state | |
8898 | */ | |
8899 | conn_state = drm_atomic_get_connector_state(state, connector); | |
8900 | ||
8901 | ret = PTR_ERR_OR_ZERO(conn_state); | |
8902 | if (ret) | |
2dc39051 | 8903 | goto out; |
e7b07cee HW |
8904 | |
8905 | /* Attach crtc to drm_atomic_state*/ | |
8906 | crtc_state = drm_atomic_get_crtc_state(state, &disconnected_acrtc->base); | |
8907 | ||
8908 | ret = PTR_ERR_OR_ZERO(crtc_state); | |
8909 | if (ret) | |
2dc39051 | 8910 | goto out; |
e7b07cee HW |
8911 | |
8912 | /* force a restore */ | |
8913 | crtc_state->mode_changed = true; | |
8914 | ||
8915 | /* Attach plane to drm_atomic_state */ | |
8916 | plane_state = drm_atomic_get_plane_state(state, plane); | |
8917 | ||
8918 | ret = PTR_ERR_OR_ZERO(plane_state); | |
8919 | if (ret) | |
2dc39051 | 8920 | goto out; |
e7b07cee HW |
8921 | |
8922 | /* Call commit internally with the state we just constructed */ | |
8923 | ret = drm_atomic_commit(state); | |
e7b07cee | 8924 | |
2dc39051 | 8925 | out: |
e7b07cee | 8926 | drm_atomic_state_put(state); |
2dc39051 VL |
8927 | if (ret) |
8928 | DRM_ERROR("Restoring old state failed with %i\n", ret); | |
e7b07cee HW |
8929 | |
8930 | return ret; | |
8931 | } | |
8932 | ||
8933 | /* | |
1f6010a9 DF |
8934 | * This function handles all cases when set mode does not come upon hotplug. |
8935 | * This includes when a display is unplugged then plugged back into the | |
8936 | * same port and when running without usermode desktop manager supprot | |
e7b07cee | 8937 | */ |
3ee6b26b AD |
8938 | void dm_restore_drm_connector_state(struct drm_device *dev, |
8939 | struct drm_connector *connector) | |
e7b07cee | 8940 | { |
c84dec2f | 8941 | struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); |
e7b07cee HW |
8942 | struct amdgpu_crtc *disconnected_acrtc; |
8943 | struct dm_crtc_state *acrtc_state; | |
8944 | ||
8945 | if (!aconnector->dc_sink || !connector->state || !connector->encoder) | |
8946 | return; | |
8947 | ||
8948 | disconnected_acrtc = to_amdgpu_crtc(connector->encoder->crtc); | |
70e8ffc5 HW |
8949 | if (!disconnected_acrtc) |
8950 | return; | |
e7b07cee | 8951 | |
70e8ffc5 HW |
8952 | acrtc_state = to_dm_crtc_state(disconnected_acrtc->base.state); |
8953 | if (!acrtc_state->stream) | |
e7b07cee HW |
8954 | return; |
8955 | ||
8956 | /* | |
8957 | * If the previous sink is not released and different from the current, | |
8958 | * we deduce we are in a state where we can not rely on usermode call | |
8959 | * to turn on the display, so we do it here | |
8960 | */ | |
8961 | if (acrtc_state->stream->sink != aconnector->dc_sink) | |
8962 | dm_force_atomic_commit(&aconnector->base); | |
8963 | } | |
8964 | ||
1f6010a9 | 8965 | /* |
e7b07cee HW |
8966 | * Grabs all modesetting locks to serialize against any blocking commits, |
8967 | * Waits for completion of all non blocking commits. | |
8968 | */ | |
3ee6b26b AD |
8969 | static int do_aquire_global_lock(struct drm_device *dev, |
8970 | struct drm_atomic_state *state) | |
e7b07cee HW |
8971 | { |
8972 | struct drm_crtc *crtc; | |
8973 | struct drm_crtc_commit *commit; | |
8974 | long ret; | |
8975 | ||
1f6010a9 DF |
8976 | /* |
8977 | * Adding all modeset locks to aquire_ctx will | |
e7b07cee HW |
8978 | * ensure that when the framework release it the |
8979 | * extra locks we are locking here will get released to | |
8980 | */ | |
8981 | ret = drm_modeset_lock_all_ctx(dev, state->acquire_ctx); | |
8982 | if (ret) | |
8983 | return ret; | |
8984 | ||
8985 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { | |
8986 | spin_lock(&crtc->commit_lock); | |
8987 | commit = list_first_entry_or_null(&crtc->commit_list, | |
8988 | struct drm_crtc_commit, commit_entry); | |
8989 | if (commit) | |
8990 | drm_crtc_commit_get(commit); | |
8991 | spin_unlock(&crtc->commit_lock); | |
8992 | ||
8993 | if (!commit) | |
8994 | continue; | |
8995 | ||
1f6010a9 DF |
8996 | /* |
8997 | * Make sure all pending HW programming completed and | |
e7b07cee HW |
8998 | * page flips done |
8999 | */ | |
9000 | ret = wait_for_completion_interruptible_timeout(&commit->hw_done, 10*HZ); | |
9001 | ||
9002 | if (ret > 0) | |
9003 | ret = wait_for_completion_interruptible_timeout( | |
9004 | &commit->flip_done, 10*HZ); | |
9005 | ||
9006 | if (ret == 0) | |
9007 | DRM_ERROR("[CRTC:%d:%s] hw_done or flip_done " | |
b830ebc9 | 9008 | "timed out\n", crtc->base.id, crtc->name); |
e7b07cee HW |
9009 | |
9010 | drm_crtc_commit_put(commit); | |
9011 | } | |
9012 | ||
9013 | return ret < 0 ? ret : 0; | |
9014 | } | |
9015 | ||
bb47de73 NK |
9016 | static void get_freesync_config_for_crtc( |
9017 | struct dm_crtc_state *new_crtc_state, | |
9018 | struct dm_connector_state *new_con_state) | |
98e6436d AK |
9019 | { |
9020 | struct mod_freesync_config config = {0}; | |
98e6436d AK |
9021 | struct amdgpu_dm_connector *aconnector = |
9022 | to_amdgpu_dm_connector(new_con_state->base.connector); | |
a057ec46 | 9023 | struct drm_display_mode *mode = &new_crtc_state->base.mode; |
0ab925d3 | 9024 | int vrefresh = drm_mode_vrefresh(mode); |
a85ba005 | 9025 | bool fs_vid_mode = false; |
98e6436d | 9026 | |
a057ec46 | 9027 | new_crtc_state->vrr_supported = new_con_state->freesync_capable && |
0ab925d3 NK |
9028 | vrefresh >= aconnector->min_vfreq && |
9029 | vrefresh <= aconnector->max_vfreq; | |
bb47de73 | 9030 | |
6ffa6799 | 9031 | if (new_crtc_state->vrr_supported) { |
7e5098ab | 9032 | new_crtc_state->stream->ignore_msa_timing_param = true; |
6ffa6799 | 9033 | fs_vid_mode = new_crtc_state->freesync_config.state == VRR_STATE_ACTIVE_FIXED; |
7e5098ab | 9034 | |
a85ba005 NC |
9035 | config.min_refresh_in_uhz = aconnector->min_vfreq * 1000000; |
9036 | config.max_refresh_in_uhz = aconnector->max_vfreq * 1000000; | |
69ff8845 | 9037 | config.vsif_supported = true; |
180db303 | 9038 | config.btr = true; |
98e6436d | 9039 | |
a85ba005 NC |
9040 | if (fs_vid_mode) { |
9041 | config.state = VRR_STATE_ACTIVE_FIXED; | |
9042 | config.fixed_refresh_in_uhz = new_crtc_state->freesync_config.fixed_refresh_in_uhz; | |
9043 | goto out; | |
9044 | } else if (new_crtc_state->base.vrr_enabled) { | |
9045 | config.state = VRR_STATE_ACTIVE_VARIABLE; | |
9046 | } else { | |
9047 | config.state = VRR_STATE_INACTIVE; | |
9048 | } | |
9049 | } | |
9050 | out: | |
bb47de73 NK |
9051 | new_crtc_state->freesync_config = config; |
9052 | } | |
98e6436d | 9053 | |
bb47de73 NK |
9054 | static void reset_freesync_config_for_crtc( |
9055 | struct dm_crtc_state *new_crtc_state) | |
9056 | { | |
9057 | new_crtc_state->vrr_supported = false; | |
98e6436d | 9058 | |
bb47de73 NK |
9059 | memset(&new_crtc_state->vrr_infopacket, 0, |
9060 | sizeof(new_crtc_state->vrr_infopacket)); | |
98e6436d AK |
9061 | } |
9062 | ||
a85ba005 NC |
9063 | static bool |
9064 | is_timing_unchanged_for_freesync(struct drm_crtc_state *old_crtc_state, | |
9065 | struct drm_crtc_state *new_crtc_state) | |
9066 | { | |
1cbd7887 | 9067 | const struct drm_display_mode *old_mode, *new_mode; |
a85ba005 NC |
9068 | |
9069 | if (!old_crtc_state || !new_crtc_state) | |
9070 | return false; | |
9071 | ||
1cbd7887 VS |
9072 | old_mode = &old_crtc_state->mode; |
9073 | new_mode = &new_crtc_state->mode; | |
9074 | ||
9075 | if (old_mode->clock == new_mode->clock && | |
9076 | old_mode->hdisplay == new_mode->hdisplay && | |
9077 | old_mode->vdisplay == new_mode->vdisplay && | |
9078 | old_mode->htotal == new_mode->htotal && | |
9079 | old_mode->vtotal != new_mode->vtotal && | |
9080 | old_mode->hsync_start == new_mode->hsync_start && | |
9081 | old_mode->vsync_start != new_mode->vsync_start && | |
9082 | old_mode->hsync_end == new_mode->hsync_end && | |
9083 | old_mode->vsync_end != new_mode->vsync_end && | |
9084 | old_mode->hskew == new_mode->hskew && | |
9085 | old_mode->vscan == new_mode->vscan && | |
9086 | (old_mode->vsync_end - old_mode->vsync_start) == | |
9087 | (new_mode->vsync_end - new_mode->vsync_start)) | |
a85ba005 NC |
9088 | return true; |
9089 | ||
9090 | return false; | |
9091 | } | |
9092 | ||
9093 | static void set_freesync_fixed_config(struct dm_crtc_state *dm_new_crtc_state) { | |
ae67558b | 9094 | u64 num, den, res; |
a85ba005 NC |
9095 | struct drm_crtc_state *new_crtc_state = &dm_new_crtc_state->base; |
9096 | ||
9097 | dm_new_crtc_state->freesync_config.state = VRR_STATE_ACTIVE_FIXED; | |
9098 | ||
9099 | num = (unsigned long long)new_crtc_state->mode.clock * 1000 * 1000000; | |
9100 | den = (unsigned long long)new_crtc_state->mode.htotal * | |
9101 | (unsigned long long)new_crtc_state->mode.vtotal; | |
9102 | ||
9103 | res = div_u64(num, den); | |
9104 | dm_new_crtc_state->freesync_config.fixed_refresh_in_uhz = res; | |
9105 | } | |
9106 | ||
f11d9373 | 9107 | static int dm_update_crtc_state(struct amdgpu_display_manager *dm, |
17ce8a69 RL |
9108 | struct drm_atomic_state *state, |
9109 | struct drm_crtc *crtc, | |
9110 | struct drm_crtc_state *old_crtc_state, | |
9111 | struct drm_crtc_state *new_crtc_state, | |
9112 | bool enable, | |
9113 | bool *lock_and_validation_needed) | |
e7b07cee | 9114 | { |
eb3dc897 | 9115 | struct dm_atomic_state *dm_state = NULL; |
54d76575 | 9116 | struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state; |
9635b754 | 9117 | struct dc_stream_state *new_stream; |
62f55537 | 9118 | int ret = 0; |
d4d4a645 | 9119 | |
1f6010a9 DF |
9120 | /* |
9121 | * TODO Move this code into dm_crtc_atomic_check once we get rid of dc_validation_set | |
9122 | * update changed items | |
9123 | */ | |
4b9674e5 LL |
9124 | struct amdgpu_crtc *acrtc = NULL; |
9125 | struct amdgpu_dm_connector *aconnector = NULL; | |
9126 | struct drm_connector_state *drm_new_conn_state = NULL, *drm_old_conn_state = NULL; | |
9127 | struct dm_connector_state *dm_new_conn_state = NULL, *dm_old_conn_state = NULL; | |
e7b07cee | 9128 | |
4b9674e5 | 9129 | new_stream = NULL; |
9635b754 | 9130 | |
4b9674e5 LL |
9131 | dm_old_crtc_state = to_dm_crtc_state(old_crtc_state); |
9132 | dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); | |
9133 | acrtc = to_amdgpu_crtc(crtc); | |
4b9674e5 | 9134 | aconnector = amdgpu_dm_find_first_crtc_matching_connector(state, crtc); |
19f89e23 | 9135 | |
4b9674e5 LL |
9136 | /* TODO This hack should go away */ |
9137 | if (aconnector && enable) { | |
9138 | /* Make sure fake sink is created in plug-in scenario */ | |
9139 | drm_new_conn_state = drm_atomic_get_new_connector_state(state, | |
9140 | &aconnector->base); | |
9141 | drm_old_conn_state = drm_atomic_get_old_connector_state(state, | |
9142 | &aconnector->base); | |
19f89e23 | 9143 | |
4b9674e5 LL |
9144 | if (IS_ERR(drm_new_conn_state)) { |
9145 | ret = PTR_ERR_OR_ZERO(drm_new_conn_state); | |
9146 | goto fail; | |
9147 | } | |
19f89e23 | 9148 | |
4b9674e5 LL |
9149 | dm_new_conn_state = to_dm_connector_state(drm_new_conn_state); |
9150 | dm_old_conn_state = to_dm_connector_state(drm_old_conn_state); | |
19f89e23 | 9151 | |
02d35a67 JFZ |
9152 | if (!drm_atomic_crtc_needs_modeset(new_crtc_state)) |
9153 | goto skip_modeset; | |
9154 | ||
cbd14ae7 SW |
9155 | new_stream = create_validate_stream_for_sink(aconnector, |
9156 | &new_crtc_state->mode, | |
9157 | dm_new_conn_state, | |
9158 | dm_old_crtc_state->stream); | |
19f89e23 | 9159 | |
4b9674e5 LL |
9160 | /* |
9161 | * we can have no stream on ACTION_SET if a display | |
9162 | * was disconnected during S3, in this case it is not an | |
9163 | * error, the OS will be updated after detection, and | |
9164 | * will do the right thing on next atomic commit | |
9165 | */ | |
19f89e23 | 9166 | |
4b9674e5 LL |
9167 | if (!new_stream) { |
9168 | DRM_DEBUG_DRIVER("%s: Failed to create new stream for crtc %d\n", | |
9169 | __func__, acrtc->base.base.id); | |
9170 | ret = -ENOMEM; | |
9171 | goto fail; | |
9172 | } | |
e7b07cee | 9173 | |
3d4e52d0 VL |
9174 | /* |
9175 | * TODO: Check VSDB bits to decide whether this should | |
9176 | * be enabled or not. | |
9177 | */ | |
9178 | new_stream->triggered_crtc_reset.enabled = | |
9179 | dm->force_timing_sync; | |
9180 | ||
4b9674e5 | 9181 | dm_new_crtc_state->abm_level = dm_new_conn_state->abm_level; |
98e6436d | 9182 | |
88694af9 NK |
9183 | ret = fill_hdr_info_packet(drm_new_conn_state, |
9184 | &new_stream->hdr_static_metadata); | |
9185 | if (ret) | |
9186 | goto fail; | |
9187 | ||
7e930949 NK |
9188 | /* |
9189 | * If we already removed the old stream from the context | |
9190 | * (and set the new stream to NULL) then we can't reuse | |
9191 | * the old stream even if the stream and scaling are unchanged. | |
9192 | * We'll hit the BUG_ON and black screen. | |
9193 | * | |
9194 | * TODO: Refactor this function to allow this check to work | |
9195 | * in all conditions. | |
9196 | */ | |
4243c84a MD |
9197 | if (amdgpu_freesync_vid_mode && |
9198 | dm_new_crtc_state->stream && | |
a85ba005 NC |
9199 | is_timing_unchanged_for_freesync(new_crtc_state, old_crtc_state)) |
9200 | goto skip_modeset; | |
9201 | ||
7e930949 NK |
9202 | if (dm_new_crtc_state->stream && |
9203 | dc_is_stream_unchanged(new_stream, dm_old_crtc_state->stream) && | |
4b9674e5 LL |
9204 | dc_is_stream_scaling_unchanged(new_stream, dm_old_crtc_state->stream)) { |
9205 | new_crtc_state->mode_changed = false; | |
9206 | DRM_DEBUG_DRIVER("Mode change not required, setting mode_changed to %d", | |
9207 | new_crtc_state->mode_changed); | |
62f55537 | 9208 | } |
4b9674e5 | 9209 | } |
b830ebc9 | 9210 | |
02d35a67 | 9211 | /* mode_changed flag may get updated above, need to check again */ |
4b9674e5 LL |
9212 | if (!drm_atomic_crtc_needs_modeset(new_crtc_state)) |
9213 | goto skip_modeset; | |
e7b07cee | 9214 | |
9f07550b | 9215 | drm_dbg_state(state->dev, |
4b9674e5 LL |
9216 | "amdgpu_crtc id:%d crtc_state_flags: enable:%d, active:%d, " |
9217 | "planes_changed:%d, mode_changed:%d,active_changed:%d," | |
9218 | "connectors_changed:%d\n", | |
9219 | acrtc->crtc_id, | |
9220 | new_crtc_state->enable, | |
9221 | new_crtc_state->active, | |
9222 | new_crtc_state->planes_changed, | |
9223 | new_crtc_state->mode_changed, | |
9224 | new_crtc_state->active_changed, | |
9225 | new_crtc_state->connectors_changed); | |
62f55537 | 9226 | |
4b9674e5 LL |
9227 | /* Remove stream for any changed/disabled CRTC */ |
9228 | if (!enable) { | |
62f55537 | 9229 | |
4b9674e5 LL |
9230 | if (!dm_old_crtc_state->stream) |
9231 | goto skip_modeset; | |
eb3dc897 | 9232 | |
0f5f1ee4 AP |
9233 | /* Unset freesync video if it was active before */ |
9234 | if (dm_old_crtc_state->freesync_config.state == VRR_STATE_ACTIVE_FIXED) { | |
9235 | dm_new_crtc_state->freesync_config.state = VRR_STATE_INACTIVE; | |
9236 | dm_new_crtc_state->freesync_config.fixed_refresh_in_uhz = 0; | |
9237 | } | |
9238 | ||
9239 | /* Now check if we should set freesync video mode */ | |
4243c84a | 9240 | if (amdgpu_freesync_vid_mode && dm_new_crtc_state->stream && |
a85ba005 NC |
9241 | is_timing_unchanged_for_freesync(new_crtc_state, |
9242 | old_crtc_state)) { | |
9243 | new_crtc_state->mode_changed = false; | |
9244 | DRM_DEBUG_DRIVER( | |
9245 | "Mode change not required for front porch change, " | |
9246 | "setting mode_changed to %d", | |
9247 | new_crtc_state->mode_changed); | |
9248 | ||
9249 | set_freesync_fixed_config(dm_new_crtc_state); | |
9250 | ||
9251 | goto skip_modeset; | |
4243c84a | 9252 | } else if (amdgpu_freesync_vid_mode && aconnector && |
a85ba005 NC |
9253 | is_freesync_video_mode(&new_crtc_state->mode, |
9254 | aconnector)) { | |
e88ebd83 SC |
9255 | struct drm_display_mode *high_mode; |
9256 | ||
9257 | high_mode = get_highest_refresh_rate_mode(aconnector, false); | |
9258 | if (!drm_mode_equal(&new_crtc_state->mode, high_mode)) { | |
9259 | set_freesync_fixed_config(dm_new_crtc_state); | |
9260 | } | |
a85ba005 NC |
9261 | } |
9262 | ||
4b9674e5 LL |
9263 | ret = dm_atomic_get_state(state, &dm_state); |
9264 | if (ret) | |
9265 | goto fail; | |
e7b07cee | 9266 | |
4b9674e5 LL |
9267 | DRM_DEBUG_DRIVER("Disabling DRM crtc: %d\n", |
9268 | crtc->base.id); | |
62f55537 | 9269 | |
4b9674e5 LL |
9270 | /* i.e. reset mode */ |
9271 | if (dc_remove_stream_from_ctx( | |
9272 | dm->dc, | |
9273 | dm_state->context, | |
9274 | dm_old_crtc_state->stream) != DC_OK) { | |
9275 | ret = -EINVAL; | |
9276 | goto fail; | |
9277 | } | |
62f55537 | 9278 | |
4b9674e5 LL |
9279 | dc_stream_release(dm_old_crtc_state->stream); |
9280 | dm_new_crtc_state->stream = NULL; | |
bb47de73 | 9281 | |
4b9674e5 | 9282 | reset_freesync_config_for_crtc(dm_new_crtc_state); |
62f55537 | 9283 | |
4b9674e5 | 9284 | *lock_and_validation_needed = true; |
62f55537 | 9285 | |
4b9674e5 LL |
9286 | } else {/* Add stream for any updated/enabled CRTC */ |
9287 | /* | |
9288 | * Quick fix to prevent NULL pointer on new_stream when | |
9289 | * added MST connectors not found in existing crtc_state in the chained mode | |
9290 | * TODO: need to dig out the root cause of that | |
9291 | */ | |
84a8b390 | 9292 | if (!aconnector) |
4b9674e5 | 9293 | goto skip_modeset; |
62f55537 | 9294 | |
4b9674e5 LL |
9295 | if (modereset_required(new_crtc_state)) |
9296 | goto skip_modeset; | |
62f55537 | 9297 | |
6c5e25a0 | 9298 | if (amdgpu_dm_crtc_modeset_required(new_crtc_state, new_stream, |
4b9674e5 | 9299 | dm_old_crtc_state->stream)) { |
62f55537 | 9300 | |
4b9674e5 | 9301 | WARN_ON(dm_new_crtc_state->stream); |
eb3dc897 | 9302 | |
4b9674e5 LL |
9303 | ret = dm_atomic_get_state(state, &dm_state); |
9304 | if (ret) | |
9305 | goto fail; | |
27b3f4fc | 9306 | |
4b9674e5 | 9307 | dm_new_crtc_state->stream = new_stream; |
62f55537 | 9308 | |
4b9674e5 | 9309 | dc_stream_retain(new_stream); |
1dc90497 | 9310 | |
4711c033 LT |
9311 | DRM_DEBUG_ATOMIC("Enabling DRM crtc: %d\n", |
9312 | crtc->base.id); | |
1dc90497 | 9313 | |
4b9674e5 LL |
9314 | if (dc_add_stream_to_ctx( |
9315 | dm->dc, | |
9316 | dm_state->context, | |
9317 | dm_new_crtc_state->stream) != DC_OK) { | |
9318 | ret = -EINVAL; | |
9319 | goto fail; | |
9b690ef3 BL |
9320 | } |
9321 | ||
4b9674e5 LL |
9322 | *lock_and_validation_needed = true; |
9323 | } | |
9324 | } | |
e277adc5 | 9325 | |
4b9674e5 LL |
9326 | skip_modeset: |
9327 | /* Release extra reference */ | |
9328 | if (new_stream) | |
3335a135 | 9329 | dc_stream_release(new_stream); |
e277adc5 | 9330 | |
4b9674e5 LL |
9331 | /* |
9332 | * We want to do dc stream updates that do not require a | |
9333 | * full modeset below. | |
9334 | */ | |
2afda735 | 9335 | if (!(enable && aconnector && new_crtc_state->active)) |
4b9674e5 LL |
9336 | return 0; |
9337 | /* | |
9338 | * Given above conditions, the dc state cannot be NULL because: | |
9339 | * 1. We're in the process of enabling CRTCs (just been added | |
9340 | * to the dc context, or already is on the context) | |
9341 | * 2. Has a valid connector attached, and | |
9342 | * 3. Is currently active and enabled. | |
9343 | * => The dc stream state currently exists. | |
9344 | */ | |
9345 | BUG_ON(dm_new_crtc_state->stream == NULL); | |
a9e8d275 | 9346 | |
4b9674e5 | 9347 | /* Scaling or underscan settings */ |
c521fc31 RL |
9348 | if (is_scaling_state_different(dm_old_conn_state, dm_new_conn_state) || |
9349 | drm_atomic_crtc_needs_modeset(new_crtc_state)) | |
4b9674e5 LL |
9350 | update_stream_scaling_settings( |
9351 | &new_crtc_state->mode, dm_new_conn_state, dm_new_crtc_state->stream); | |
98e6436d | 9352 | |
b05e2c5e DF |
9353 | /* ABM settings */ |
9354 | dm_new_crtc_state->abm_level = dm_new_conn_state->abm_level; | |
9355 | ||
4b9674e5 LL |
9356 | /* |
9357 | * Color management settings. We also update color properties | |
9358 | * when a modeset is needed, to ensure it gets reprogrammed. | |
9359 | */ | |
9360 | if (dm_new_crtc_state->base.color_mgmt_changed || | |
9361 | drm_atomic_crtc_needs_modeset(new_crtc_state)) { | |
cf020d49 | 9362 | ret = amdgpu_dm_update_crtc_color_mgmt(dm_new_crtc_state); |
4b9674e5 LL |
9363 | if (ret) |
9364 | goto fail; | |
62f55537 | 9365 | } |
e7b07cee | 9366 | |
4b9674e5 LL |
9367 | /* Update Freesync settings. */ |
9368 | get_freesync_config_for_crtc(dm_new_crtc_state, | |
9369 | dm_new_conn_state); | |
9370 | ||
62f55537 | 9371 | return ret; |
9635b754 DS |
9372 | |
9373 | fail: | |
9374 | if (new_stream) | |
9375 | dc_stream_release(new_stream); | |
9376 | return ret; | |
62f55537 | 9377 | } |
9b690ef3 | 9378 | |
f6ff2a08 NK |
9379 | static bool should_reset_plane(struct drm_atomic_state *state, |
9380 | struct drm_plane *plane, | |
9381 | struct drm_plane_state *old_plane_state, | |
9382 | struct drm_plane_state *new_plane_state) | |
9383 | { | |
9384 | struct drm_plane *other; | |
9385 | struct drm_plane_state *old_other_state, *new_other_state; | |
9386 | struct drm_crtc_state *new_crtc_state; | |
9387 | int i; | |
9388 | ||
70a1efac NK |
9389 | /* |
9390 | * TODO: Remove this hack once the checks below are sufficient | |
9391 | * enough to determine when we need to reset all the planes on | |
9392 | * the stream. | |
9393 | */ | |
9394 | if (state->allow_modeset) | |
9395 | return true; | |
9396 | ||
f6ff2a08 NK |
9397 | /* Exit early if we know that we're adding or removing the plane. */ |
9398 | if (old_plane_state->crtc != new_plane_state->crtc) | |
9399 | return true; | |
9400 | ||
9401 | /* old crtc == new_crtc == NULL, plane not in context. */ | |
9402 | if (!new_plane_state->crtc) | |
9403 | return false; | |
9404 | ||
9405 | new_crtc_state = | |
9406 | drm_atomic_get_new_crtc_state(state, new_plane_state->crtc); | |
9407 | ||
9408 | if (!new_crtc_state) | |
9409 | return true; | |
9410 | ||
7316c4ad NK |
9411 | /* CRTC Degamma changes currently require us to recreate planes. */ |
9412 | if (new_crtc_state->color_mgmt_changed) | |
9413 | return true; | |
9414 | ||
f6ff2a08 NK |
9415 | if (drm_atomic_crtc_needs_modeset(new_crtc_state)) |
9416 | return true; | |
9417 | ||
9418 | /* | |
9419 | * If there are any new primary or overlay planes being added or | |
9420 | * removed then the z-order can potentially change. To ensure | |
9421 | * correct z-order and pipe acquisition the current DC architecture | |
9422 | * requires us to remove and recreate all existing planes. | |
9423 | * | |
9424 | * TODO: Come up with a more elegant solution for this. | |
9425 | */ | |
9426 | for_each_oldnew_plane_in_state(state, other, old_other_state, new_other_state, i) { | |
6eed95b0 | 9427 | struct amdgpu_framebuffer *old_afb, *new_afb; |
f6ff2a08 NK |
9428 | if (other->type == DRM_PLANE_TYPE_CURSOR) |
9429 | continue; | |
9430 | ||
9431 | if (old_other_state->crtc != new_plane_state->crtc && | |
9432 | new_other_state->crtc != new_plane_state->crtc) | |
9433 | continue; | |
9434 | ||
9435 | if (old_other_state->crtc != new_other_state->crtc) | |
9436 | return true; | |
9437 | ||
dc4cb30d NK |
9438 | /* Src/dst size and scaling updates. */ |
9439 | if (old_other_state->src_w != new_other_state->src_w || | |
9440 | old_other_state->src_h != new_other_state->src_h || | |
9441 | old_other_state->crtc_w != new_other_state->crtc_w || | |
9442 | old_other_state->crtc_h != new_other_state->crtc_h) | |
9443 | return true; | |
9444 | ||
9445 | /* Rotation / mirroring updates. */ | |
9446 | if (old_other_state->rotation != new_other_state->rotation) | |
9447 | return true; | |
9448 | ||
9449 | /* Blending updates. */ | |
9450 | if (old_other_state->pixel_blend_mode != | |
9451 | new_other_state->pixel_blend_mode) | |
9452 | return true; | |
9453 | ||
9454 | /* Alpha updates. */ | |
9455 | if (old_other_state->alpha != new_other_state->alpha) | |
9456 | return true; | |
9457 | ||
9458 | /* Colorspace changes. */ | |
9459 | if (old_other_state->color_range != new_other_state->color_range || | |
9460 | old_other_state->color_encoding != new_other_state->color_encoding) | |
9461 | return true; | |
9462 | ||
9a81cc60 NK |
9463 | /* Framebuffer checks fall at the end. */ |
9464 | if (!old_other_state->fb || !new_other_state->fb) | |
9465 | continue; | |
9466 | ||
9467 | /* Pixel format changes can require bandwidth updates. */ | |
9468 | if (old_other_state->fb->format != new_other_state->fb->format) | |
9469 | return true; | |
9470 | ||
6eed95b0 BN |
9471 | old_afb = (struct amdgpu_framebuffer *)old_other_state->fb; |
9472 | new_afb = (struct amdgpu_framebuffer *)new_other_state->fb; | |
9a81cc60 NK |
9473 | |
9474 | /* Tiling and DCC changes also require bandwidth updates. */ | |
37384b3f BN |
9475 | if (old_afb->tiling_flags != new_afb->tiling_flags || |
9476 | old_afb->base.modifier != new_afb->base.modifier) | |
f6ff2a08 NK |
9477 | return true; |
9478 | } | |
9479 | ||
9480 | return false; | |
9481 | } | |
9482 | ||
b0455fda SS |
9483 | static int dm_check_cursor_fb(struct amdgpu_crtc *new_acrtc, |
9484 | struct drm_plane_state *new_plane_state, | |
9485 | struct drm_framebuffer *fb) | |
9486 | { | |
e72868c4 SS |
9487 | struct amdgpu_device *adev = drm_to_adev(new_acrtc->base.dev); |
9488 | struct amdgpu_framebuffer *afb = to_amdgpu_framebuffer(fb); | |
b0455fda | 9489 | unsigned int pitch; |
e72868c4 | 9490 | bool linear; |
b0455fda SS |
9491 | |
9492 | if (fb->width > new_acrtc->max_cursor_width || | |
9493 | fb->height > new_acrtc->max_cursor_height) { | |
9494 | DRM_DEBUG_ATOMIC("Bad cursor FB size %dx%d\n", | |
9495 | new_plane_state->fb->width, | |
9496 | new_plane_state->fb->height); | |
9497 | return -EINVAL; | |
9498 | } | |
9499 | if (new_plane_state->src_w != fb->width << 16 || | |
9500 | new_plane_state->src_h != fb->height << 16) { | |
9501 | DRM_DEBUG_ATOMIC("Cropping not supported for cursor plane\n"); | |
9502 | return -EINVAL; | |
9503 | } | |
9504 | ||
9505 | /* Pitch in pixels */ | |
9506 | pitch = fb->pitches[0] / fb->format->cpp[0]; | |
9507 | ||
9508 | if (fb->width != pitch) { | |
9509 | DRM_DEBUG_ATOMIC("Cursor FB width %d doesn't match pitch %d", | |
9510 | fb->width, pitch); | |
9511 | return -EINVAL; | |
9512 | } | |
9513 | ||
9514 | switch (pitch) { | |
9515 | case 64: | |
9516 | case 128: | |
9517 | case 256: | |
9518 | /* FB pitch is supported by cursor plane */ | |
9519 | break; | |
9520 | default: | |
9521 | DRM_DEBUG_ATOMIC("Bad cursor FB pitch %d px\n", pitch); | |
9522 | return -EINVAL; | |
9523 | } | |
9524 | ||
e72868c4 SS |
9525 | /* Core DRM takes care of checking FB modifiers, so we only need to |
9526 | * check tiling flags when the FB doesn't have a modifier. */ | |
9527 | if (!(fb->flags & DRM_MODE_FB_MODIFIERS)) { | |
9528 | if (adev->family < AMDGPU_FAMILY_AI) { | |
9529 | linear = AMDGPU_TILING_GET(afb->tiling_flags, ARRAY_MODE) != DC_ARRAY_2D_TILED_THIN1 && | |
9530 | AMDGPU_TILING_GET(afb->tiling_flags, ARRAY_MODE) != DC_ARRAY_1D_TILED_THIN1 && | |
9531 | AMDGPU_TILING_GET(afb->tiling_flags, MICRO_TILE_MODE) == 0; | |
9532 | } else { | |
9533 | linear = AMDGPU_TILING_GET(afb->tiling_flags, SWIZZLE_MODE) == 0; | |
9534 | } | |
9535 | if (!linear) { | |
9536 | DRM_DEBUG_ATOMIC("Cursor FB not linear"); | |
9537 | return -EINVAL; | |
9538 | } | |
9539 | } | |
9540 | ||
b0455fda SS |
9541 | return 0; |
9542 | } | |
9543 | ||
9e869063 LL |
9544 | static int dm_update_plane_state(struct dc *dc, |
9545 | struct drm_atomic_state *state, | |
9546 | struct drm_plane *plane, | |
9547 | struct drm_plane_state *old_plane_state, | |
9548 | struct drm_plane_state *new_plane_state, | |
9549 | bool enable, | |
35f33086 BL |
9550 | bool *lock_and_validation_needed, |
9551 | bool *is_top_most_overlay) | |
62f55537 | 9552 | { |
eb3dc897 NK |
9553 | |
9554 | struct dm_atomic_state *dm_state = NULL; | |
62f55537 | 9555 | struct drm_crtc *new_plane_crtc, *old_plane_crtc; |
0bc9706d | 9556 | struct drm_crtc_state *old_crtc_state, *new_crtc_state; |
54d76575 | 9557 | struct dm_crtc_state *dm_new_crtc_state, *dm_old_crtc_state; |
54d76575 | 9558 | struct dm_plane_state *dm_new_plane_state, *dm_old_plane_state; |
626bf90f | 9559 | struct amdgpu_crtc *new_acrtc; |
f6ff2a08 | 9560 | bool needs_reset; |
62f55537 | 9561 | int ret = 0; |
e7b07cee | 9562 | |
9b690ef3 | 9563 | |
9e869063 LL |
9564 | new_plane_crtc = new_plane_state->crtc; |
9565 | old_plane_crtc = old_plane_state->crtc; | |
9566 | dm_new_plane_state = to_dm_plane_state(new_plane_state); | |
9567 | dm_old_plane_state = to_dm_plane_state(old_plane_state); | |
62f55537 | 9568 | |
626bf90f SS |
9569 | if (plane->type == DRM_PLANE_TYPE_CURSOR) { |
9570 | if (!enable || !new_plane_crtc || | |
9571 | drm_atomic_plane_disabling(plane->state, new_plane_state)) | |
9572 | return 0; | |
9573 | ||
9574 | new_acrtc = to_amdgpu_crtc(new_plane_crtc); | |
9575 | ||
5f581248 SS |
9576 | if (new_plane_state->src_x != 0 || new_plane_state->src_y != 0) { |
9577 | DRM_DEBUG_ATOMIC("Cropping not supported for cursor plane\n"); | |
9578 | return -EINVAL; | |
9579 | } | |
9580 | ||
24f99d2b | 9581 | if (new_plane_state->fb) { |
b0455fda SS |
9582 | ret = dm_check_cursor_fb(new_acrtc, new_plane_state, |
9583 | new_plane_state->fb); | |
9584 | if (ret) | |
9585 | return ret; | |
24f99d2b SS |
9586 | } |
9587 | ||
9e869063 | 9588 | return 0; |
626bf90f | 9589 | } |
9b690ef3 | 9590 | |
f6ff2a08 NK |
9591 | needs_reset = should_reset_plane(state, plane, old_plane_state, |
9592 | new_plane_state); | |
9593 | ||
9e869063 LL |
9594 | /* Remove any changed/removed planes */ |
9595 | if (!enable) { | |
f6ff2a08 | 9596 | if (!needs_reset) |
9e869063 | 9597 | return 0; |
a7b06724 | 9598 | |
9e869063 LL |
9599 | if (!old_plane_crtc) |
9600 | return 0; | |
62f55537 | 9601 | |
9e869063 LL |
9602 | old_crtc_state = drm_atomic_get_old_crtc_state( |
9603 | state, old_plane_crtc); | |
9604 | dm_old_crtc_state = to_dm_crtc_state(old_crtc_state); | |
9b690ef3 | 9605 | |
9e869063 LL |
9606 | if (!dm_old_crtc_state->stream) |
9607 | return 0; | |
62f55537 | 9608 | |
9e869063 LL |
9609 | DRM_DEBUG_ATOMIC("Disabling DRM plane: %d on DRM crtc %d\n", |
9610 | plane->base.id, old_plane_crtc->base.id); | |
9b690ef3 | 9611 | |
9e869063 LL |
9612 | ret = dm_atomic_get_state(state, &dm_state); |
9613 | if (ret) | |
9614 | return ret; | |
eb3dc897 | 9615 | |
9e869063 LL |
9616 | if (!dc_remove_plane_from_context( |
9617 | dc, | |
9618 | dm_old_crtc_state->stream, | |
9619 | dm_old_plane_state->dc_state, | |
9620 | dm_state->context)) { | |
62f55537 | 9621 | |
c3537613 | 9622 | return -EINVAL; |
9e869063 | 9623 | } |
e7b07cee | 9624 | |
da5e1490 AP |
9625 | if (dm_old_plane_state->dc_state) |
9626 | dc_plane_state_release(dm_old_plane_state->dc_state); | |
9b690ef3 | 9627 | |
9e869063 | 9628 | dm_new_plane_state->dc_state = NULL; |
1dc90497 | 9629 | |
9e869063 | 9630 | *lock_and_validation_needed = true; |
1dc90497 | 9631 | |
9e869063 LL |
9632 | } else { /* Add new planes */ |
9633 | struct dc_plane_state *dc_new_plane_state; | |
1dc90497 | 9634 | |
9e869063 LL |
9635 | if (drm_atomic_plane_disabling(plane->state, new_plane_state)) |
9636 | return 0; | |
e7b07cee | 9637 | |
9e869063 LL |
9638 | if (!new_plane_crtc) |
9639 | return 0; | |
e7b07cee | 9640 | |
9e869063 LL |
9641 | new_crtc_state = drm_atomic_get_new_crtc_state(state, new_plane_crtc); |
9642 | dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); | |
1dc90497 | 9643 | |
9e869063 LL |
9644 | if (!dm_new_crtc_state->stream) |
9645 | return 0; | |
62f55537 | 9646 | |
f6ff2a08 | 9647 | if (!needs_reset) |
9e869063 | 9648 | return 0; |
62f55537 | 9649 | |
8bf0d9cd | 9650 | ret = amdgpu_dm_plane_helper_check_state(new_plane_state, new_crtc_state); |
8c44515b AP |
9651 | if (ret) |
9652 | return ret; | |
9653 | ||
9e869063 | 9654 | WARN_ON(dm_new_plane_state->dc_state); |
9b690ef3 | 9655 | |
9e869063 LL |
9656 | dc_new_plane_state = dc_create_plane_state(dc); |
9657 | if (!dc_new_plane_state) | |
9658 | return -ENOMEM; | |
62f55537 | 9659 | |
35f33086 BL |
9660 | /* Block top most plane from being a video plane */ |
9661 | if (plane->type == DRM_PLANE_TYPE_OVERLAY) { | |
9662 | if (is_video_format(new_plane_state->fb->format->format) && *is_top_most_overlay) | |
9663 | return -EINVAL; | |
9664 | else | |
9665 | *is_top_most_overlay = false; | |
9666 | } | |
9667 | ||
4711c033 LT |
9668 | DRM_DEBUG_ATOMIC("Enabling DRM plane: %d on DRM crtc %d\n", |
9669 | plane->base.id, new_plane_crtc->base.id); | |
8c45c5db | 9670 | |
695af5f9 | 9671 | ret = fill_dc_plane_attributes( |
1348969a | 9672 | drm_to_adev(new_plane_crtc->dev), |
9e869063 LL |
9673 | dc_new_plane_state, |
9674 | new_plane_state, | |
9675 | new_crtc_state); | |
9676 | if (ret) { | |
9677 | dc_plane_state_release(dc_new_plane_state); | |
9678 | return ret; | |
9679 | } | |
62f55537 | 9680 | |
9e869063 LL |
9681 | ret = dm_atomic_get_state(state, &dm_state); |
9682 | if (ret) { | |
9683 | dc_plane_state_release(dc_new_plane_state); | |
9684 | return ret; | |
9685 | } | |
eb3dc897 | 9686 | |
9e869063 LL |
9687 | /* |
9688 | * Any atomic check errors that occur after this will | |
9689 | * not need a release. The plane state will be attached | |
9690 | * to the stream, and therefore part of the atomic | |
9691 | * state. It'll be released when the atomic state is | |
9692 | * cleaned. | |
9693 | */ | |
9694 | if (!dc_add_plane_to_context( | |
9695 | dc, | |
9696 | dm_new_crtc_state->stream, | |
9697 | dc_new_plane_state, | |
9698 | dm_state->context)) { | |
62f55537 | 9699 | |
9e869063 LL |
9700 | dc_plane_state_release(dc_new_plane_state); |
9701 | return -EINVAL; | |
9702 | } | |
8c45c5db | 9703 | |
9e869063 | 9704 | dm_new_plane_state->dc_state = dc_new_plane_state; |
000b59ea | 9705 | |
214993e1 ML |
9706 | dm_new_crtc_state->mpo_requested |= (plane->type == DRM_PLANE_TYPE_OVERLAY); |
9707 | ||
9e869063 LL |
9708 | /* Tell DC to do a full surface update every time there |
9709 | * is a plane change. Inefficient, but works for now. | |
9710 | */ | |
9711 | dm_new_plane_state->dc_state->update_flags.bits.full_update = 1; | |
9712 | ||
9713 | *lock_and_validation_needed = true; | |
62f55537 | 9714 | } |
e7b07cee HW |
9715 | |
9716 | ||
62f55537 AG |
9717 | return ret; |
9718 | } | |
a87fa993 | 9719 | |
69cb5629 VZ |
9720 | static void dm_get_oriented_plane_size(struct drm_plane_state *plane_state, |
9721 | int *src_w, int *src_h) | |
9722 | { | |
9723 | switch (plane_state->rotation & DRM_MODE_ROTATE_MASK) { | |
9724 | case DRM_MODE_ROTATE_90: | |
9725 | case DRM_MODE_ROTATE_270: | |
9726 | *src_w = plane_state->src_h >> 16; | |
9727 | *src_h = plane_state->src_w >> 16; | |
9728 | break; | |
9729 | case DRM_MODE_ROTATE_0: | |
9730 | case DRM_MODE_ROTATE_180: | |
9731 | default: | |
9732 | *src_w = plane_state->src_w >> 16; | |
9733 | *src_h = plane_state->src_h >> 16; | |
9734 | break; | |
9735 | } | |
9736 | } | |
9737 | ||
12f4849a SS |
9738 | static int dm_check_crtc_cursor(struct drm_atomic_state *state, |
9739 | struct drm_crtc *crtc, | |
9740 | struct drm_crtc_state *new_crtc_state) | |
9741 | { | |
d1bfbe8a SS |
9742 | struct drm_plane *cursor = crtc->cursor, *underlying; |
9743 | struct drm_plane_state *new_cursor_state, *new_underlying_state; | |
9744 | int i; | |
9745 | int cursor_scale_w, cursor_scale_h, underlying_scale_w, underlying_scale_h; | |
69cb5629 VZ |
9746 | int cursor_src_w, cursor_src_h; |
9747 | int underlying_src_w, underlying_src_h; | |
12f4849a SS |
9748 | |
9749 | /* On DCE and DCN there is no dedicated hardware cursor plane. We get a | |
9750 | * cursor per pipe but it's going to inherit the scaling and | |
9751 | * positioning from the underlying pipe. Check the cursor plane's | |
d1bfbe8a | 9752 | * blending properties match the underlying planes'. */ |
12f4849a | 9753 | |
d1bfbe8a SS |
9754 | new_cursor_state = drm_atomic_get_new_plane_state(state, cursor); |
9755 | if (!new_cursor_state || !new_cursor_state->fb) { | |
12f4849a SS |
9756 | return 0; |
9757 | } | |
9758 | ||
69cb5629 VZ |
9759 | dm_get_oriented_plane_size(new_cursor_state, &cursor_src_w, &cursor_src_h); |
9760 | cursor_scale_w = new_cursor_state->crtc_w * 1000 / cursor_src_w; | |
9761 | cursor_scale_h = new_cursor_state->crtc_h * 1000 / cursor_src_h; | |
12f4849a | 9762 | |
d1bfbe8a SS |
9763 | for_each_new_plane_in_state_reverse(state, underlying, new_underlying_state, i) { |
9764 | /* Narrow down to non-cursor planes on the same CRTC as the cursor */ | |
9765 | if (new_underlying_state->crtc != crtc || underlying == crtc->cursor) | |
9766 | continue; | |
12f4849a | 9767 | |
d1bfbe8a SS |
9768 | /* Ignore disabled planes */ |
9769 | if (!new_underlying_state->fb) | |
9770 | continue; | |
9771 | ||
69cb5629 VZ |
9772 | dm_get_oriented_plane_size(new_underlying_state, |
9773 | &underlying_src_w, &underlying_src_h); | |
9774 | underlying_scale_w = new_underlying_state->crtc_w * 1000 / underlying_src_w; | |
9775 | underlying_scale_h = new_underlying_state->crtc_h * 1000 / underlying_src_h; | |
d1bfbe8a SS |
9776 | |
9777 | if (cursor_scale_w != underlying_scale_w || | |
9778 | cursor_scale_h != underlying_scale_h) { | |
9779 | drm_dbg_atomic(crtc->dev, | |
9780 | "Cursor [PLANE:%d:%s] scaling doesn't match underlying [PLANE:%d:%s]\n", | |
9781 | cursor->base.id, cursor->name, underlying->base.id, underlying->name); | |
9782 | return -EINVAL; | |
9783 | } | |
9784 | ||
9785 | /* If this plane covers the whole CRTC, no need to check planes underneath */ | |
9786 | if (new_underlying_state->crtc_x <= 0 && | |
9787 | new_underlying_state->crtc_y <= 0 && | |
9788 | new_underlying_state->crtc_x + new_underlying_state->crtc_w >= new_crtc_state->mode.hdisplay && | |
9789 | new_underlying_state->crtc_y + new_underlying_state->crtc_h >= new_crtc_state->mode.vdisplay) | |
9790 | break; | |
12f4849a SS |
9791 | } |
9792 | ||
9793 | return 0; | |
9794 | } | |
9795 | ||
44be939f ML |
9796 | static int add_affected_mst_dsc_crtcs(struct drm_atomic_state *state, struct drm_crtc *crtc) |
9797 | { | |
9798 | struct drm_connector *connector; | |
128f8ed5 | 9799 | struct drm_connector_state *conn_state, *old_conn_state; |
44be939f ML |
9800 | struct amdgpu_dm_connector *aconnector = NULL; |
9801 | int i; | |
128f8ed5 RL |
9802 | for_each_oldnew_connector_in_state(state, connector, old_conn_state, conn_state, i) { |
9803 | if (!conn_state->crtc) | |
9804 | conn_state = old_conn_state; | |
9805 | ||
44be939f ML |
9806 | if (conn_state->crtc != crtc) |
9807 | continue; | |
9808 | ||
9809 | aconnector = to_amdgpu_dm_connector(connector); | |
f0127cb1 | 9810 | if (!aconnector->mst_output_port || !aconnector->mst_root) |
44be939f ML |
9811 | aconnector = NULL; |
9812 | else | |
9813 | break; | |
9814 | } | |
9815 | ||
9816 | if (!aconnector) | |
9817 | return 0; | |
9818 | ||
f0127cb1 | 9819 | return drm_dp_mst_add_affected_dsc_crtcs(state, &aconnector->mst_root->mst_mgr); |
44be939f ML |
9820 | } |
9821 | ||
b8592b48 LL |
9822 | /** |
9823 | * amdgpu_dm_atomic_check() - Atomic check implementation for AMDgpu DM. | |
c620e79b | 9824 | * |
b8592b48 LL |
9825 | * @dev: The DRM device |
9826 | * @state: The atomic state to commit | |
9827 | * | |
9828 | * Validate that the given atomic state is programmable by DC into hardware. | |
9829 | * This involves constructing a &struct dc_state reflecting the new hardware | |
9830 | * state we wish to commit, then querying DC to see if it is programmable. It's | |
9831 | * important not to modify the existing DC state. Otherwise, atomic_check | |
9832 | * may unexpectedly commit hardware changes. | |
9833 | * | |
9834 | * When validating the DC state, it's important that the right locks are | |
9835 | * acquired. For full updates case which removes/adds/updates streams on one | |
9836 | * CRTC while flipping on another CRTC, acquiring global lock will guarantee | |
9837 | * that any such full update commit will wait for completion of any outstanding | |
f6d7c7fa | 9838 | * flip using DRMs synchronization events. |
b8592b48 LL |
9839 | * |
9840 | * Note that DM adds the affected connectors for all CRTCs in state, when that | |
9841 | * might not seem necessary. This is because DC stream creation requires the | |
9842 | * DC sink, which is tied to the DRM connector state. Cleaning this up should | |
9843 | * be possible but non-trivial - a possible TODO item. | |
9844 | * | |
9845 | * Return: -Error code if validation failed. | |
9846 | */ | |
7578ecda AD |
9847 | static int amdgpu_dm_atomic_check(struct drm_device *dev, |
9848 | struct drm_atomic_state *state) | |
62f55537 | 9849 | { |
1348969a | 9850 | struct amdgpu_device *adev = drm_to_adev(dev); |
eb3dc897 | 9851 | struct dm_atomic_state *dm_state = NULL; |
62f55537 | 9852 | struct dc *dc = adev->dm.dc; |
62f55537 | 9853 | struct drm_connector *connector; |
c2cea706 | 9854 | struct drm_connector_state *old_con_state, *new_con_state; |
62f55537 | 9855 | struct drm_crtc *crtc; |
fc9e9920 | 9856 | struct drm_crtc_state *old_crtc_state, *new_crtc_state; |
9e869063 LL |
9857 | struct drm_plane *plane; |
9858 | struct drm_plane_state *old_plane_state, *new_plane_state; | |
74a16675 | 9859 | enum dc_status status; |
1e88ad0a | 9860 | int ret, i; |
62f55537 | 9861 | bool lock_and_validation_needed = false; |
35f33086 | 9862 | bool is_top_most_overlay = true; |
214993e1 | 9863 | struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state; |
cdf657fc DA |
9864 | struct drm_dp_mst_topology_mgr *mgr; |
9865 | struct drm_dp_mst_topology_state *mst_state; | |
6513104b | 9866 | struct dsc_mst_fairness_vars vars[MAX_PIPES]; |
62f55537 | 9867 | |
e8a98235 | 9868 | trace_amdgpu_dm_atomic_check_begin(state); |
c44a22b3 | 9869 | |
62f55537 | 9870 | ret = drm_atomic_helper_check_modeset(dev, state); |
68ca1c3e S |
9871 | if (ret) { |
9872 | DRM_DEBUG_DRIVER("drm_atomic_helper_check_modeset() failed\n"); | |
01e28f9c | 9873 | goto fail; |
68ca1c3e | 9874 | } |
62f55537 | 9875 | |
c5892a10 SW |
9876 | /* Check connector changes */ |
9877 | for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) { | |
9878 | struct dm_connector_state *dm_old_con_state = to_dm_connector_state(old_con_state); | |
9879 | struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state); | |
9880 | ||
9881 | /* Skip connectors that are disabled or part of modeset already. */ | |
c5892a10 SW |
9882 | if (!new_con_state->crtc) |
9883 | continue; | |
9884 | ||
9885 | new_crtc_state = drm_atomic_get_crtc_state(state, new_con_state->crtc); | |
9886 | if (IS_ERR(new_crtc_state)) { | |
68ca1c3e | 9887 | DRM_DEBUG_DRIVER("drm_atomic_get_crtc_state() failed\n"); |
c5892a10 SW |
9888 | ret = PTR_ERR(new_crtc_state); |
9889 | goto fail; | |
9890 | } | |
9891 | ||
3c6d1aeb | 9892 | if (dm_old_con_state->abm_level != dm_new_con_state->abm_level || |
9893 | dm_old_con_state->scaling != dm_new_con_state->scaling) | |
c5892a10 SW |
9894 | new_crtc_state->connectors_changed = true; |
9895 | } | |
9896 | ||
349a19b2 | 9897 | if (dc_resource_is_dsc_encoding_supported(dc)) { |
44be939f ML |
9898 | for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { |
9899 | if (drm_atomic_crtc_needs_modeset(new_crtc_state)) { | |
9900 | ret = add_affected_mst_dsc_crtcs(state, crtc); | |
68ca1c3e S |
9901 | if (ret) { |
9902 | DRM_DEBUG_DRIVER("add_affected_mst_dsc_crtcs() failed\n"); | |
44be939f | 9903 | goto fail; |
68ca1c3e | 9904 | } |
44be939f ML |
9905 | } |
9906 | } | |
9907 | } | |
1e88ad0a | 9908 | for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { |
886876ec EB |
9909 | dm_old_crtc_state = to_dm_crtc_state(old_crtc_state); |
9910 | ||
1e88ad0a | 9911 | if (!drm_atomic_crtc_needs_modeset(new_crtc_state) && |
98e6436d | 9912 | !new_crtc_state->color_mgmt_changed && |
886876ec EB |
9913 | old_crtc_state->vrr_enabled == new_crtc_state->vrr_enabled && |
9914 | dm_old_crtc_state->dsc_force_changed == false) | |
1e88ad0a | 9915 | continue; |
7bef1af3 | 9916 | |
03fc4cf4 | 9917 | ret = amdgpu_dm_verify_lut_sizes(new_crtc_state); |
68ca1c3e S |
9918 | if (ret) { |
9919 | DRM_DEBUG_DRIVER("amdgpu_dm_verify_lut_sizes() failed\n"); | |
03fc4cf4 | 9920 | goto fail; |
68ca1c3e | 9921 | } |
03fc4cf4 | 9922 | |
1e88ad0a S |
9923 | if (!new_crtc_state->enable) |
9924 | continue; | |
fc9e9920 | 9925 | |
1e88ad0a | 9926 | ret = drm_atomic_add_affected_connectors(state, crtc); |
68ca1c3e S |
9927 | if (ret) { |
9928 | DRM_DEBUG_DRIVER("drm_atomic_add_affected_connectors() failed\n"); | |
706bc8c5 | 9929 | goto fail; |
68ca1c3e | 9930 | } |
fc9e9920 | 9931 | |
1e88ad0a | 9932 | ret = drm_atomic_add_affected_planes(state, crtc); |
68ca1c3e S |
9933 | if (ret) { |
9934 | DRM_DEBUG_DRIVER("drm_atomic_add_affected_planes() failed\n"); | |
1e88ad0a | 9935 | goto fail; |
68ca1c3e | 9936 | } |
115a385c | 9937 | |
cbac53f7 | 9938 | if (dm_old_crtc_state->dsc_force_changed) |
115a385c | 9939 | new_crtc_state->mode_changed = true; |
e7b07cee HW |
9940 | } |
9941 | ||
2d9e6431 NK |
9942 | /* |
9943 | * Add all primary and overlay planes on the CRTC to the state | |
9944 | * whenever a plane is enabled to maintain correct z-ordering | |
9945 | * and to enable fast surface updates. | |
9946 | */ | |
9947 | drm_for_each_crtc(crtc, dev) { | |
9948 | bool modified = false; | |
9949 | ||
9950 | for_each_oldnew_plane_in_state(state, plane, old_plane_state, new_plane_state, i) { | |
9951 | if (plane->type == DRM_PLANE_TYPE_CURSOR) | |
9952 | continue; | |
9953 | ||
9954 | if (new_plane_state->crtc == crtc || | |
9955 | old_plane_state->crtc == crtc) { | |
9956 | modified = true; | |
9957 | break; | |
9958 | } | |
9959 | } | |
9960 | ||
9961 | if (!modified) | |
9962 | continue; | |
9963 | ||
9964 | drm_for_each_plane_mask(plane, state->dev, crtc->state->plane_mask) { | |
9965 | if (plane->type == DRM_PLANE_TYPE_CURSOR) | |
9966 | continue; | |
9967 | ||
9968 | new_plane_state = | |
9969 | drm_atomic_get_plane_state(state, plane); | |
9970 | ||
9971 | if (IS_ERR(new_plane_state)) { | |
9972 | ret = PTR_ERR(new_plane_state); | |
68ca1c3e | 9973 | DRM_DEBUG_DRIVER("new_plane_state is BAD\n"); |
2d9e6431 NK |
9974 | goto fail; |
9975 | } | |
9976 | } | |
9977 | } | |
9978 | ||
22c42b0e LL |
9979 | /* |
9980 | * DC consults the zpos (layer_index in DC terminology) to determine the | |
9981 | * hw plane on which to enable the hw cursor (see | |
9982 | * `dcn10_can_pipe_disable_cursor`). By now, all modified planes are in | |
9983 | * atomic state, so call drm helper to normalize zpos. | |
9984 | */ | |
ac0bb08d LL |
9985 | ret = drm_atomic_normalize_zpos(dev, state); |
9986 | if (ret) { | |
9987 | drm_dbg(dev, "drm_atomic_normalize_zpos() failed\n"); | |
9988 | goto fail; | |
9989 | } | |
22c42b0e | 9990 | |
62f55537 | 9991 | /* Remove exiting planes if they are modified */ |
9e869063 LL |
9992 | for_each_oldnew_plane_in_state_reverse(state, plane, old_plane_state, new_plane_state, i) { |
9993 | ret = dm_update_plane_state(dc, state, plane, | |
9994 | old_plane_state, | |
9995 | new_plane_state, | |
9996 | false, | |
35f33086 BL |
9997 | &lock_and_validation_needed, |
9998 | &is_top_most_overlay); | |
68ca1c3e S |
9999 | if (ret) { |
10000 | DRM_DEBUG_DRIVER("dm_update_plane_state() failed\n"); | |
9e869063 | 10001 | goto fail; |
68ca1c3e | 10002 | } |
62f55537 AG |
10003 | } |
10004 | ||
10005 | /* Disable all crtcs which require disable */ | |
4b9674e5 LL |
10006 | for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { |
10007 | ret = dm_update_crtc_state(&adev->dm, state, crtc, | |
10008 | old_crtc_state, | |
10009 | new_crtc_state, | |
10010 | false, | |
10011 | &lock_and_validation_needed); | |
68ca1c3e S |
10012 | if (ret) { |
10013 | DRM_DEBUG_DRIVER("DISABLE: dm_update_crtc_state() failed\n"); | |
4b9674e5 | 10014 | goto fail; |
68ca1c3e | 10015 | } |
62f55537 AG |
10016 | } |
10017 | ||
10018 | /* Enable all crtcs which require enable */ | |
4b9674e5 LL |
10019 | for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { |
10020 | ret = dm_update_crtc_state(&adev->dm, state, crtc, | |
10021 | old_crtc_state, | |
10022 | new_crtc_state, | |
10023 | true, | |
10024 | &lock_and_validation_needed); | |
68ca1c3e S |
10025 | if (ret) { |
10026 | DRM_DEBUG_DRIVER("ENABLE: dm_update_crtc_state() failed\n"); | |
4b9674e5 | 10027 | goto fail; |
68ca1c3e | 10028 | } |
62f55537 AG |
10029 | } |
10030 | ||
10031 | /* Add new/modified planes */ | |
9e869063 LL |
10032 | for_each_oldnew_plane_in_state_reverse(state, plane, old_plane_state, new_plane_state, i) { |
10033 | ret = dm_update_plane_state(dc, state, plane, | |
10034 | old_plane_state, | |
10035 | new_plane_state, | |
10036 | true, | |
35f33086 BL |
10037 | &lock_and_validation_needed, |
10038 | &is_top_most_overlay); | |
68ca1c3e S |
10039 | if (ret) { |
10040 | DRM_DEBUG_DRIVER("dm_update_plane_state() failed\n"); | |
9e869063 | 10041 | goto fail; |
68ca1c3e | 10042 | } |
62f55537 AG |
10043 | } |
10044 | ||
876fcc42 | 10045 | if (dc_resource_is_dsc_encoding_supported(dc)) { |
7cce4cd6 LP |
10046 | ret = pre_validate_dsc(state, &dm_state, vars); |
10047 | if (ret != 0) | |
876fcc42 | 10048 | goto fail; |
876fcc42 | 10049 | } |
876fcc42 | 10050 | |
b349f76e ES |
10051 | /* Run this here since we want to validate the streams we created */ |
10052 | ret = drm_atomic_helper_check_planes(dev, state); | |
68ca1c3e S |
10053 | if (ret) { |
10054 | DRM_DEBUG_DRIVER("drm_atomic_helper_check_planes() failed\n"); | |
b349f76e | 10055 | goto fail; |
68ca1c3e | 10056 | } |
62f55537 | 10057 | |
214993e1 ML |
10058 | for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) { |
10059 | dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); | |
10060 | if (dm_new_crtc_state->mpo_requested) | |
10061 | DRM_DEBUG_DRIVER("MPO enablement requested on crtc:[%p]\n", crtc); | |
10062 | } | |
10063 | ||
12f4849a SS |
10064 | /* Check cursor planes scaling */ |
10065 | for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) { | |
10066 | ret = dm_check_crtc_cursor(state, crtc, new_crtc_state); | |
68ca1c3e S |
10067 | if (ret) { |
10068 | DRM_DEBUG_DRIVER("dm_check_crtc_cursor() failed\n"); | |
12f4849a | 10069 | goto fail; |
68ca1c3e | 10070 | } |
12f4849a SS |
10071 | } |
10072 | ||
43d10d30 NK |
10073 | if (state->legacy_cursor_update) { |
10074 | /* | |
10075 | * This is a fast cursor update coming from the plane update | |
10076 | * helper, check if it can be done asynchronously for better | |
10077 | * performance. | |
10078 | */ | |
10079 | state->async_update = | |
10080 | !drm_atomic_helper_async_check(dev, state); | |
10081 | ||
10082 | /* | |
10083 | * Skip the remaining global validation if this is an async | |
10084 | * update. Cursor updates can be done without affecting | |
10085 | * state or bandwidth calcs and this avoids the performance | |
10086 | * penalty of locking the private state object and | |
10087 | * allocating a new dc_state. | |
10088 | */ | |
10089 | if (state->async_update) | |
10090 | return 0; | |
10091 | } | |
10092 | ||
ebdd27e1 | 10093 | /* Check scaling and underscan changes*/ |
1f6010a9 | 10094 | /* TODO Removed scaling changes validation due to inability to commit |
e7b07cee HW |
10095 | * new stream into context w\o causing full reset. Need to |
10096 | * decide how to handle. | |
10097 | */ | |
c2cea706 | 10098 | for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) { |
54d76575 LSL |
10099 | struct dm_connector_state *dm_old_con_state = to_dm_connector_state(old_con_state); |
10100 | struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state); | |
10101 | struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc); | |
e7b07cee HW |
10102 | |
10103 | /* Skip any modesets/resets */ | |
0bc9706d LSL |
10104 | if (!acrtc || drm_atomic_crtc_needs_modeset( |
10105 | drm_atomic_get_new_crtc_state(state, &acrtc->base))) | |
e7b07cee HW |
10106 | continue; |
10107 | ||
b830ebc9 | 10108 | /* Skip any thing not scale or underscan changes */ |
54d76575 | 10109 | if (!is_scaling_state_different(dm_new_con_state, dm_old_con_state)) |
e7b07cee HW |
10110 | continue; |
10111 | ||
10112 | lock_and_validation_needed = true; | |
10113 | } | |
10114 | ||
c689e1e3 LP |
10115 | /* set the slot info for each mst_state based on the link encoding format */ |
10116 | for_each_new_mst_mgr_in_state(state, mgr, mst_state, i) { | |
10117 | struct amdgpu_dm_connector *aconnector; | |
10118 | struct drm_connector *connector; | |
10119 | struct drm_connector_list_iter iter; | |
10120 | u8 link_coding_cap; | |
10121 | ||
10122 | drm_connector_list_iter_begin(dev, &iter); | |
10123 | drm_for_each_connector_iter(connector, &iter) { | |
10124 | if (connector->index == mst_state->mgr->conn_base_id) { | |
10125 | aconnector = to_amdgpu_dm_connector(connector); | |
10126 | link_coding_cap = dc_link_dp_mst_decide_link_encoding_format(aconnector->dc_link); | |
10127 | drm_dp_mst_update_slots(mst_state, link_coding_cap); | |
10128 | ||
10129 | break; | |
10130 | } | |
10131 | } | |
10132 | drm_connector_list_iter_end(&iter); | |
10133 | } | |
c689e1e3 | 10134 | |
f6d7c7fa NK |
10135 | /** |
10136 | * Streams and planes are reset when there are changes that affect | |
10137 | * bandwidth. Anything that affects bandwidth needs to go through | |
10138 | * DC global validation to ensure that the configuration can be applied | |
10139 | * to hardware. | |
10140 | * | |
10141 | * We have to currently stall out here in atomic_check for outstanding | |
10142 | * commits to finish in this case because our IRQ handlers reference | |
10143 | * DRM state directly - we can end up disabling interrupts too early | |
10144 | * if we don't. | |
10145 | * | |
10146 | * TODO: Remove this stall and drop DM state private objects. | |
a87fa993 | 10147 | */ |
f6d7c7fa | 10148 | if (lock_and_validation_needed) { |
eb3dc897 | 10149 | ret = dm_atomic_get_state(state, &dm_state); |
68ca1c3e S |
10150 | if (ret) { |
10151 | DRM_DEBUG_DRIVER("dm_atomic_get_state() failed\n"); | |
eb3dc897 | 10152 | goto fail; |
68ca1c3e | 10153 | } |
e7b07cee HW |
10154 | |
10155 | ret = do_aquire_global_lock(dev, state); | |
68ca1c3e S |
10156 | if (ret) { |
10157 | DRM_DEBUG_DRIVER("do_aquire_global_lock() failed\n"); | |
e7b07cee | 10158 | goto fail; |
68ca1c3e | 10159 | } |
1dc90497 | 10160 | |
7cce4cd6 LP |
10161 | ret = compute_mst_dsc_configs_for_state(state, dm_state->context, vars); |
10162 | if (ret) { | |
68ca1c3e | 10163 | DRM_DEBUG_DRIVER("compute_mst_dsc_configs_for_state() failed\n"); |
8c20a1ed | 10164 | goto fail; |
68ca1c3e | 10165 | } |
8c20a1ed | 10166 | |
6513104b | 10167 | ret = dm_update_mst_vcpi_slots_for_dsc(state, dm_state->context, vars); |
68ca1c3e S |
10168 | if (ret) { |
10169 | DRM_DEBUG_DRIVER("dm_update_mst_vcpi_slots_for_dsc() failed\n"); | |
29b9ba74 | 10170 | goto fail; |
68ca1c3e | 10171 | } |
29b9ba74 | 10172 | |
ded58c7b ZL |
10173 | /* |
10174 | * Perform validation of MST topology in the state: | |
10175 | * We need to perform MST atomic check before calling | |
10176 | * dc_validate_global_state(), or there is a chance | |
10177 | * to get stuck in an infinite loop and hang eventually. | |
10178 | */ | |
10179 | ret = drm_dp_mst_atomic_check(state); | |
68ca1c3e S |
10180 | if (ret) { |
10181 | DRM_DEBUG_DRIVER("drm_dp_mst_atomic_check() failed\n"); | |
ded58c7b | 10182 | goto fail; |
68ca1c3e | 10183 | } |
85fb8bb9 | 10184 | status = dc_validate_global_state(dc, dm_state->context, true); |
74a16675 | 10185 | if (status != DC_OK) { |
68ca1c3e | 10186 | DRM_DEBUG_DRIVER("DC global validation failure: %s (%d)", |
74a16675 | 10187 | dc_status_to_str(status), status); |
e7b07cee HW |
10188 | ret = -EINVAL; |
10189 | goto fail; | |
10190 | } | |
bd200d19 | 10191 | } else { |
674e78ac | 10192 | /* |
bd200d19 NK |
10193 | * The commit is a fast update. Fast updates shouldn't change |
10194 | * the DC context, affect global validation, and can have their | |
10195 | * commit work done in parallel with other commits not touching | |
10196 | * the same resource. If we have a new DC context as part of | |
10197 | * the DM atomic state from validation we need to free it and | |
10198 | * retain the existing one instead. | |
fde9f39a MR |
10199 | * |
10200 | * Furthermore, since the DM atomic state only contains the DC | |
10201 | * context and can safely be annulled, we can free the state | |
10202 | * and clear the associated private object now to free | |
10203 | * some memory and avoid a possible use-after-free later. | |
674e78ac | 10204 | */ |
bd200d19 | 10205 | |
fde9f39a MR |
10206 | for (i = 0; i < state->num_private_objs; i++) { |
10207 | struct drm_private_obj *obj = state->private_objs[i].ptr; | |
bd200d19 | 10208 | |
fde9f39a MR |
10209 | if (obj->funcs == adev->dm.atomic_obj.funcs) { |
10210 | int j = state->num_private_objs-1; | |
bd200d19 | 10211 | |
fde9f39a MR |
10212 | dm_atomic_destroy_state(obj, |
10213 | state->private_objs[i].state); | |
10214 | ||
10215 | /* If i is not at the end of the array then the | |
10216 | * last element needs to be moved to where i was | |
10217 | * before the array can safely be truncated. | |
10218 | */ | |
10219 | if (i != j) | |
10220 | state->private_objs[i] = | |
10221 | state->private_objs[j]; | |
bd200d19 | 10222 | |
fde9f39a MR |
10223 | state->private_objs[j].ptr = NULL; |
10224 | state->private_objs[j].state = NULL; | |
10225 | state->private_objs[j].old_state = NULL; | |
10226 | state->private_objs[j].new_state = NULL; | |
10227 | ||
10228 | state->num_private_objs = j; | |
10229 | break; | |
10230 | } | |
bd200d19 | 10231 | } |
e7b07cee HW |
10232 | } |
10233 | ||
caff0e66 NK |
10234 | /* Store the overall update type for use later in atomic check. */ |
10235 | for_each_new_crtc_in_state (state, crtc, new_crtc_state, i) { | |
10236 | struct dm_crtc_state *dm_new_crtc_state = | |
10237 | to_dm_crtc_state(new_crtc_state); | |
10238 | ||
f6d7c7fa NK |
10239 | dm_new_crtc_state->update_type = lock_and_validation_needed ? |
10240 | UPDATE_TYPE_FULL : | |
10241 | UPDATE_TYPE_FAST; | |
e7b07cee HW |
10242 | } |
10243 | ||
10244 | /* Must be success */ | |
10245 | WARN_ON(ret); | |
e8a98235 RS |
10246 | |
10247 | trace_amdgpu_dm_atomic_check_finish(state, ret); | |
10248 | ||
e7b07cee HW |
10249 | return ret; |
10250 | ||
10251 | fail: | |
10252 | if (ret == -EDEADLK) | |
01e28f9c | 10253 | DRM_DEBUG_DRIVER("Atomic check stopped to avoid deadlock.\n"); |
e7b07cee | 10254 | else if (ret == -EINTR || ret == -EAGAIN || ret == -ERESTARTSYS) |
01e28f9c | 10255 | DRM_DEBUG_DRIVER("Atomic check stopped due to signal.\n"); |
e7b07cee | 10256 | else |
01e28f9c | 10257 | DRM_DEBUG_DRIVER("Atomic check failed with err: %d \n", ret); |
e7b07cee | 10258 | |
e8a98235 RS |
10259 | trace_amdgpu_dm_atomic_check_finish(state, ret); |
10260 | ||
e7b07cee HW |
10261 | return ret; |
10262 | } | |
10263 | ||
3ee6b26b AD |
10264 | static bool is_dp_capable_without_timing_msa(struct dc *dc, |
10265 | struct amdgpu_dm_connector *amdgpu_dm_connector) | |
e7b07cee | 10266 | { |
ae67558b | 10267 | u8 dpcd_data; |
e7b07cee HW |
10268 | bool capable = false; |
10269 | ||
c84dec2f | 10270 | if (amdgpu_dm_connector->dc_link && |
e7b07cee HW |
10271 | dm_helpers_dp_read_dpcd( |
10272 | NULL, | |
c84dec2f | 10273 | amdgpu_dm_connector->dc_link, |
e7b07cee HW |
10274 | DP_DOWN_STREAM_PORT_COUNT, |
10275 | &dpcd_data, | |
10276 | sizeof(dpcd_data))) { | |
10277 | capable = (dpcd_data & DP_MSA_TIMING_PAR_IGNORED) ? true:false; | |
10278 | } | |
10279 | ||
10280 | return capable; | |
10281 | } | |
f9b4f20c | 10282 | |
46db138d SW |
10283 | static bool dm_edid_parser_send_cea(struct amdgpu_display_manager *dm, |
10284 | unsigned int offset, | |
10285 | unsigned int total_length, | |
ae67558b | 10286 | u8 *data, |
46db138d SW |
10287 | unsigned int length, |
10288 | struct amdgpu_hdmi_vsdb_info *vsdb) | |
10289 | { | |
10290 | bool res; | |
10291 | union dmub_rb_cmd cmd; | |
10292 | struct dmub_cmd_send_edid_cea *input; | |
10293 | struct dmub_cmd_edid_cea_output *output; | |
10294 | ||
10295 | if (length > DMUB_EDID_CEA_DATA_CHUNK_BYTES) | |
10296 | return false; | |
10297 | ||
10298 | memset(&cmd, 0, sizeof(cmd)); | |
10299 | ||
10300 | input = &cmd.edid_cea.data.input; | |
10301 | ||
10302 | cmd.edid_cea.header.type = DMUB_CMD__EDID_CEA; | |
10303 | cmd.edid_cea.header.sub_type = 0; | |
10304 | cmd.edid_cea.header.payload_bytes = | |
10305 | sizeof(cmd.edid_cea) - sizeof(cmd.edid_cea.header); | |
10306 | input->offset = offset; | |
10307 | input->length = length; | |
eb9e59eb | 10308 | input->cea_total_length = total_length; |
46db138d SW |
10309 | memcpy(input->payload, data, length); |
10310 | ||
10311 | res = dc_dmub_srv_cmd_with_reply_data(dm->dc->ctx->dmub_srv, &cmd); | |
10312 | if (!res) { | |
10313 | DRM_ERROR("EDID CEA parser failed\n"); | |
10314 | return false; | |
10315 | } | |
10316 | ||
10317 | output = &cmd.edid_cea.data.output; | |
10318 | ||
10319 | if (output->type == DMUB_CMD__EDID_CEA_ACK) { | |
10320 | if (!output->ack.success) { | |
10321 | DRM_ERROR("EDID CEA ack failed at offset %d\n", | |
10322 | output->ack.offset); | |
10323 | } | |
10324 | } else if (output->type == DMUB_CMD__EDID_CEA_AMD_VSDB) { | |
10325 | if (!output->amd_vsdb.vsdb_found) | |
10326 | return false; | |
10327 | ||
10328 | vsdb->freesync_supported = output->amd_vsdb.freesync_supported; | |
10329 | vsdb->amd_vsdb_version = output->amd_vsdb.amd_vsdb_version; | |
10330 | vsdb->min_refresh_rate_hz = output->amd_vsdb.min_frame_rate; | |
10331 | vsdb->max_refresh_rate_hz = output->amd_vsdb.max_frame_rate; | |
10332 | } else { | |
b76a8062 | 10333 | DRM_WARN("Unknown EDID CEA parser results\n"); |
46db138d SW |
10334 | return false; |
10335 | } | |
10336 | ||
10337 | return true; | |
10338 | } | |
10339 | ||
10340 | static bool parse_edid_cea_dmcu(struct amdgpu_display_manager *dm, | |
ae67558b | 10341 | u8 *edid_ext, int len, |
f9b4f20c SW |
10342 | struct amdgpu_hdmi_vsdb_info *vsdb_info) |
10343 | { | |
10344 | int i; | |
f9b4f20c SW |
10345 | |
10346 | /* send extension block to DMCU for parsing */ | |
10347 | for (i = 0; i < len; i += 8) { | |
10348 | bool res; | |
10349 | int offset; | |
10350 | ||
10351 | /* send 8 bytes a time */ | |
46db138d | 10352 | if (!dc_edid_parser_send_cea(dm->dc, i, len, &edid_ext[i], 8)) |
f9b4f20c SW |
10353 | return false; |
10354 | ||
10355 | if (i+8 == len) { | |
10356 | /* EDID block sent completed, expect result */ | |
10357 | int version, min_rate, max_rate; | |
10358 | ||
46db138d | 10359 | res = dc_edid_parser_recv_amd_vsdb(dm->dc, &version, &min_rate, &max_rate); |
f9b4f20c SW |
10360 | if (res) { |
10361 | /* amd vsdb found */ | |
10362 | vsdb_info->freesync_supported = 1; | |
10363 | vsdb_info->amd_vsdb_version = version; | |
10364 | vsdb_info->min_refresh_rate_hz = min_rate; | |
10365 | vsdb_info->max_refresh_rate_hz = max_rate; | |
10366 | return true; | |
10367 | } | |
10368 | /* not amd vsdb */ | |
10369 | return false; | |
10370 | } | |
10371 | ||
10372 | /* check for ack*/ | |
46db138d | 10373 | res = dc_edid_parser_recv_cea_ack(dm->dc, &offset); |
f9b4f20c SW |
10374 | if (!res) |
10375 | return false; | |
10376 | } | |
10377 | ||
10378 | return false; | |
10379 | } | |
10380 | ||
46db138d | 10381 | static bool parse_edid_cea_dmub(struct amdgpu_display_manager *dm, |
ae67558b | 10382 | u8 *edid_ext, int len, |
46db138d SW |
10383 | struct amdgpu_hdmi_vsdb_info *vsdb_info) |
10384 | { | |
10385 | int i; | |
10386 | ||
10387 | /* send extension block to DMCU for parsing */ | |
10388 | for (i = 0; i < len; i += 8) { | |
10389 | /* send 8 bytes a time */ | |
10390 | if (!dm_edid_parser_send_cea(dm, i, len, &edid_ext[i], 8, vsdb_info)) | |
10391 | return false; | |
10392 | } | |
10393 | ||
10394 | return vsdb_info->freesync_supported; | |
10395 | } | |
10396 | ||
10397 | static bool parse_edid_cea(struct amdgpu_dm_connector *aconnector, | |
ae67558b | 10398 | u8 *edid_ext, int len, |
46db138d SW |
10399 | struct amdgpu_hdmi_vsdb_info *vsdb_info) |
10400 | { | |
10401 | struct amdgpu_device *adev = drm_to_adev(aconnector->base.dev); | |
53f4da73 | 10402 | bool ret; |
46db138d | 10403 | |
53f4da73 | 10404 | mutex_lock(&adev->dm.dc_lock); |
46db138d | 10405 | if (adev->dm.dmub_srv) |
53f4da73 | 10406 | ret = parse_edid_cea_dmub(&adev->dm, edid_ext, len, vsdb_info); |
46db138d | 10407 | else |
53f4da73 SW |
10408 | ret = parse_edid_cea_dmcu(&adev->dm, edid_ext, len, vsdb_info); |
10409 | mutex_unlock(&adev->dm.dc_lock); | |
10410 | return ret; | |
46db138d SW |
10411 | } |
10412 | ||
7c7dd774 | 10413 | static int parse_hdmi_amd_vsdb(struct amdgpu_dm_connector *aconnector, |
f9b4f20c SW |
10414 | struct edid *edid, struct amdgpu_hdmi_vsdb_info *vsdb_info) |
10415 | { | |
ae67558b | 10416 | u8 *edid_ext = NULL; |
f9b4f20c SW |
10417 | int i; |
10418 | bool valid_vsdb_found = false; | |
10419 | ||
10420 | /*----- drm_find_cea_extension() -----*/ | |
10421 | /* No EDID or EDID extensions */ | |
10422 | if (edid == NULL || edid->extensions == 0) | |
7c7dd774 | 10423 | return -ENODEV; |
f9b4f20c SW |
10424 | |
10425 | /* Find CEA extension */ | |
10426 | for (i = 0; i < edid->extensions; i++) { | |
10427 | edid_ext = (uint8_t *)edid + EDID_LENGTH * (i + 1); | |
10428 | if (edid_ext[0] == CEA_EXT) | |
10429 | break; | |
10430 | } | |
10431 | ||
10432 | if (i == edid->extensions) | |
7c7dd774 | 10433 | return -ENODEV; |
f9b4f20c SW |
10434 | |
10435 | /*----- cea_db_offsets() -----*/ | |
10436 | if (edid_ext[0] != CEA_EXT) | |
7c7dd774 | 10437 | return -ENODEV; |
f9b4f20c SW |
10438 | |
10439 | valid_vsdb_found = parse_edid_cea(aconnector, edid_ext, EDID_LENGTH, vsdb_info); | |
7c7dd774 AB |
10440 | |
10441 | return valid_vsdb_found ? i : -ENODEV; | |
f9b4f20c SW |
10442 | } |
10443 | ||
c620e79b RS |
10444 | /** |
10445 | * amdgpu_dm_update_freesync_caps - Update Freesync capabilities | |
10446 | * | |
41ee1f18 AD |
10447 | * @connector: Connector to query. |
10448 | * @edid: EDID from monitor | |
c620e79b RS |
10449 | * |
10450 | * Amdgpu supports Freesync in DP and HDMI displays, and it is required to keep | |
10451 | * track of some of the display information in the internal data struct used by | |
10452 | * amdgpu_dm. This function checks which type of connector we need to set the | |
10453 | * FreeSync parameters. | |
10454 | */ | |
98e6436d | 10455 | void amdgpu_dm_update_freesync_caps(struct drm_connector *connector, |
c620e79b | 10456 | struct edid *edid) |
e7b07cee | 10457 | { |
eb0709ba | 10458 | int i = 0; |
e7b07cee HW |
10459 | struct detailed_timing *timing; |
10460 | struct detailed_non_pixel *data; | |
10461 | struct detailed_data_monitor_range *range; | |
c84dec2f HW |
10462 | struct amdgpu_dm_connector *amdgpu_dm_connector = |
10463 | to_amdgpu_dm_connector(connector); | |
bb47de73 | 10464 | struct dm_connector_state *dm_con_state = NULL; |
9ad54467 | 10465 | struct dc_sink *sink; |
e7b07cee HW |
10466 | |
10467 | struct drm_device *dev = connector->dev; | |
1348969a | 10468 | struct amdgpu_device *adev = drm_to_adev(dev); |
f9b4f20c | 10469 | struct amdgpu_hdmi_vsdb_info vsdb_info = {0}; |
c620e79b | 10470 | bool freesync_capable = false; |
5b49da02 | 10471 | enum adaptive_sync_type as_type = ADAPTIVE_SYNC_TYPE_NONE; |
b830ebc9 | 10472 | |
8218d7f1 HW |
10473 | if (!connector->state) { |
10474 | DRM_ERROR("%s - Connector has no state", __func__); | |
bb47de73 | 10475 | goto update; |
8218d7f1 HW |
10476 | } |
10477 | ||
9b2fdc33 AP |
10478 | sink = amdgpu_dm_connector->dc_sink ? |
10479 | amdgpu_dm_connector->dc_sink : | |
10480 | amdgpu_dm_connector->dc_em_sink; | |
10481 | ||
10482 | if (!edid || !sink) { | |
98e6436d AK |
10483 | dm_con_state = to_dm_connector_state(connector->state); |
10484 | ||
10485 | amdgpu_dm_connector->min_vfreq = 0; | |
10486 | amdgpu_dm_connector->max_vfreq = 0; | |
10487 | amdgpu_dm_connector->pixel_clock_mhz = 0; | |
9b2fdc33 AP |
10488 | connector->display_info.monitor_range.min_vfreq = 0; |
10489 | connector->display_info.monitor_range.max_vfreq = 0; | |
10490 | freesync_capable = false; | |
98e6436d | 10491 | |
bb47de73 | 10492 | goto update; |
98e6436d AK |
10493 | } |
10494 | ||
8218d7f1 HW |
10495 | dm_con_state = to_dm_connector_state(connector->state); |
10496 | ||
e7b07cee | 10497 | if (!adev->dm.freesync_module) |
bb47de73 | 10498 | goto update; |
f9b4f20c | 10499 | |
9b2fdc33 AP |
10500 | if (sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT |
10501 | || sink->sink_signal == SIGNAL_TYPE_EDP) { | |
f9b4f20c SW |
10502 | bool edid_check_required = false; |
10503 | ||
10504 | if (edid) { | |
e7b07cee HW |
10505 | edid_check_required = is_dp_capable_without_timing_msa( |
10506 | adev->dm.dc, | |
c84dec2f | 10507 | amdgpu_dm_connector); |
e7b07cee | 10508 | } |
e7b07cee | 10509 | |
f9b4f20c SW |
10510 | if (edid_check_required == true && (edid->version > 1 || |
10511 | (edid->version == 1 && edid->revision > 1))) { | |
10512 | for (i = 0; i < 4; i++) { | |
e7b07cee | 10513 | |
f9b4f20c SW |
10514 | timing = &edid->detailed_timings[i]; |
10515 | data = &timing->data.other_data; | |
10516 | range = &data->data.range; | |
10517 | /* | |
10518 | * Check if monitor has continuous frequency mode | |
10519 | */ | |
10520 | if (data->type != EDID_DETAIL_MONITOR_RANGE) | |
10521 | continue; | |
10522 | /* | |
10523 | * Check for flag range limits only. If flag == 1 then | |
10524 | * no additional timing information provided. | |
10525 | * Default GTF, GTF Secondary curve and CVT are not | |
10526 | * supported | |
10527 | */ | |
10528 | if (range->flags != 1) | |
10529 | continue; | |
a0ffc3fd | 10530 | |
f9b4f20c SW |
10531 | amdgpu_dm_connector->min_vfreq = range->min_vfreq; |
10532 | amdgpu_dm_connector->max_vfreq = range->max_vfreq; | |
10533 | amdgpu_dm_connector->pixel_clock_mhz = | |
10534 | range->pixel_clock_mhz * 10; | |
a0ffc3fd | 10535 | |
f9b4f20c SW |
10536 | connector->display_info.monitor_range.min_vfreq = range->min_vfreq; |
10537 | connector->display_info.monitor_range.max_vfreq = range->max_vfreq; | |
e7b07cee | 10538 | |
f9b4f20c SW |
10539 | break; |
10540 | } | |
98e6436d | 10541 | |
f9b4f20c SW |
10542 | if (amdgpu_dm_connector->max_vfreq - |
10543 | amdgpu_dm_connector->min_vfreq > 10) { | |
98e6436d | 10544 | |
f9b4f20c SW |
10545 | freesync_capable = true; |
10546 | } | |
10547 | } | |
9b2fdc33 | 10548 | } else if (edid && sink->sink_signal == SIGNAL_TYPE_HDMI_TYPE_A) { |
7c7dd774 AB |
10549 | i = parse_hdmi_amd_vsdb(amdgpu_dm_connector, edid, &vsdb_info); |
10550 | if (i >= 0 && vsdb_info.freesync_supported) { | |
f9b4f20c SW |
10551 | timing = &edid->detailed_timings[i]; |
10552 | data = &timing->data.other_data; | |
10553 | ||
10554 | amdgpu_dm_connector->min_vfreq = vsdb_info.min_refresh_rate_hz; | |
5b49da02 SJK |
10555 | amdgpu_dm_connector->max_vfreq = vsdb_info.max_refresh_rate_hz; |
10556 | if (amdgpu_dm_connector->max_vfreq - amdgpu_dm_connector->min_vfreq > 10) | |
10557 | freesync_capable = true; | |
10558 | ||
10559 | connector->display_info.monitor_range.min_vfreq = vsdb_info.min_refresh_rate_hz; | |
10560 | connector->display_info.monitor_range.max_vfreq = vsdb_info.max_refresh_rate_hz; | |
10561 | } | |
10562 | } | |
10563 | ||
10564 | as_type = dm_get_adaptive_sync_support_type(amdgpu_dm_connector->dc_link); | |
10565 | ||
10566 | if (as_type == FREESYNC_TYPE_PCON_IN_WHITELIST) { | |
10567 | i = parse_hdmi_amd_vsdb(amdgpu_dm_connector, edid, &vsdb_info); | |
10568 | if (i >= 0 && vsdb_info.freesync_supported && vsdb_info.amd_vsdb_version > 0) { | |
10569 | ||
10570 | amdgpu_dm_connector->pack_sdp_v1_3 = true; | |
10571 | amdgpu_dm_connector->as_type = as_type; | |
10572 | amdgpu_dm_connector->vsdb_info = vsdb_info; | |
10573 | ||
10574 | amdgpu_dm_connector->min_vfreq = vsdb_info.min_refresh_rate_hz; | |
f9b4f20c SW |
10575 | amdgpu_dm_connector->max_vfreq = vsdb_info.max_refresh_rate_hz; |
10576 | if (amdgpu_dm_connector->max_vfreq - amdgpu_dm_connector->min_vfreq > 10) | |
10577 | freesync_capable = true; | |
10578 | ||
10579 | connector->display_info.monitor_range.min_vfreq = vsdb_info.min_refresh_rate_hz; | |
10580 | connector->display_info.monitor_range.max_vfreq = vsdb_info.max_refresh_rate_hz; | |
e7b07cee HW |
10581 | } |
10582 | } | |
bb47de73 NK |
10583 | |
10584 | update: | |
10585 | if (dm_con_state) | |
10586 | dm_con_state->freesync_capable = freesync_capable; | |
10587 | ||
10588 | if (connector->vrr_capable_property) | |
10589 | drm_connector_set_vrr_capable_property(connector, | |
10590 | freesync_capable); | |
e7b07cee HW |
10591 | } |
10592 | ||
3d4e52d0 VL |
10593 | void amdgpu_dm_trigger_timing_sync(struct drm_device *dev) |
10594 | { | |
1348969a | 10595 | struct amdgpu_device *adev = drm_to_adev(dev); |
3d4e52d0 VL |
10596 | struct dc *dc = adev->dm.dc; |
10597 | int i; | |
10598 | ||
10599 | mutex_lock(&adev->dm.dc_lock); | |
10600 | if (dc->current_state) { | |
10601 | for (i = 0; i < dc->current_state->stream_count; ++i) | |
10602 | dc->current_state->streams[i] | |
10603 | ->triggered_crtc_reset.enabled = | |
10604 | adev->dm.force_timing_sync; | |
10605 | ||
10606 | dm_enable_per_frame_crtc_master_sync(dc->current_state); | |
10607 | dc_trigger_sync(dc, dc->current_state); | |
10608 | } | |
10609 | mutex_unlock(&adev->dm.dc_lock); | |
10610 | } | |
9d83722d RS |
10611 | |
10612 | void dm_write_reg_func(const struct dc_context *ctx, uint32_t address, | |
ae67558b | 10613 | u32 value, const char *func_name) |
9d83722d RS |
10614 | { |
10615 | #ifdef DM_CHECK_ADDR_0 | |
10616 | if (address == 0) { | |
10617 | DC_ERR("invalid register write. address = 0"); | |
10618 | return; | |
10619 | } | |
10620 | #endif | |
10621 | cgs_write_register(ctx->cgs_device, address, value); | |
10622 | trace_amdgpu_dc_wreg(&ctx->perf_trace->write_count, address, value); | |
10623 | } | |
10624 | ||
10625 | uint32_t dm_read_reg_func(const struct dc_context *ctx, uint32_t address, | |
10626 | const char *func_name) | |
10627 | { | |
ae67558b | 10628 | u32 value; |
9d83722d RS |
10629 | #ifdef DM_CHECK_ADDR_0 |
10630 | if (address == 0) { | |
10631 | DC_ERR("invalid register read; address = 0\n"); | |
10632 | return 0; | |
10633 | } | |
10634 | #endif | |
10635 | ||
10636 | if (ctx->dmub_srv && | |
10637 | ctx->dmub_srv->reg_helper_offload.gather_in_progress && | |
10638 | !ctx->dmub_srv->reg_helper_offload.should_burst_write) { | |
10639 | ASSERT(false); | |
10640 | return 0; | |
10641 | } | |
10642 | ||
10643 | value = cgs_read_register(ctx->cgs_device, address); | |
10644 | ||
10645 | trace_amdgpu_dc_rreg(&ctx->perf_trace->read_count, address, value); | |
10646 | ||
10647 | return value; | |
10648 | } | |
81927e28 | 10649 | |
ead08b95 SW |
10650 | int amdgpu_dm_process_dmub_aux_transfer_sync( |
10651 | struct dc_context *ctx, | |
10652 | unsigned int link_index, | |
10653 | struct aux_payload *payload, | |
10654 | enum aux_return_code_type *operation_result) | |
88f52b1f JS |
10655 | { |
10656 | struct amdgpu_device *adev = ctx->driver_context; | |
88f52b1f | 10657 | struct dmub_notification *p_notify = adev->dm.dmub_notify; |
ead08b95 | 10658 | int ret = -1; |
88f52b1f | 10659 | |
ead08b95 SW |
10660 | mutex_lock(&adev->dm.dpia_aux_lock); |
10661 | if (!dc_process_dmub_aux_transfer_async(ctx->dc, link_index, payload)) { | |
10662 | *operation_result = AUX_RET_ERROR_ENGINE_ACQUIRE; | |
10663 | goto out; | |
3335a135 | 10664 | } |
ead08b95 SW |
10665 | |
10666 | if (!wait_for_completion_timeout(&adev->dm.dmub_aux_transfer_done, 10 * HZ)) { | |
10667 | DRM_ERROR("wait_for_completion_timeout timeout!"); | |
10668 | *operation_result = AUX_RET_ERROR_TIMEOUT; | |
10669 | goto out; | |
10670 | } | |
10671 | ||
10672 | if (p_notify->result != AUX_RET_SUCCESS) { | |
10673 | /* | |
10674 | * Transient states before tunneling is enabled could | |
10675 | * lead to this error. We can ignore this for now. | |
10676 | */ | |
10677 | if (p_notify->result != AUX_RET_ERROR_PROTOCOL_ERROR) { | |
10678 | DRM_WARN("DPIA AUX failed on 0x%x(%d), error %d\n", | |
10679 | payload->address, payload->length, | |
10680 | p_notify->result); | |
88f52b1f | 10681 | } |
ead08b95 SW |
10682 | *operation_result = AUX_RET_ERROR_INVALID_REPLY; |
10683 | goto out; | |
10684 | } | |
10685 | ||
10686 | ||
10687 | payload->reply[0] = adev->dm.dmub_notify->aux_reply.command; | |
10688 | if (!payload->write && p_notify->aux_reply.length && | |
10689 | (payload->reply[0] == AUX_TRANSACTION_REPLY_AUX_ACK)) { | |
10690 | ||
10691 | if (payload->length != p_notify->aux_reply.length) { | |
10692 | DRM_WARN("invalid read length %d from DPIA AUX 0x%x(%d)!\n", | |
10693 | p_notify->aux_reply.length, | |
10694 | payload->address, payload->length); | |
10695 | *operation_result = AUX_RET_ERROR_INVALID_REPLY; | |
10696 | goto out; | |
88f52b1f | 10697 | } |
ead08b95 SW |
10698 | |
10699 | memcpy(payload->data, p_notify->aux_reply.data, | |
10700 | p_notify->aux_reply.length); | |
88f52b1f JS |
10701 | } |
10702 | ||
ead08b95 SW |
10703 | /* success */ |
10704 | ret = p_notify->aux_reply.length; | |
10705 | *operation_result = p_notify->result; | |
10706 | out: | |
0cf8307a | 10707 | reinit_completion(&adev->dm.dmub_aux_transfer_done); |
ead08b95 SW |
10708 | mutex_unlock(&adev->dm.dpia_aux_lock); |
10709 | return ret; | |
88f52b1f JS |
10710 | } |
10711 | ||
ead08b95 SW |
10712 | int amdgpu_dm_process_dmub_set_config_sync( |
10713 | struct dc_context *ctx, | |
10714 | unsigned int link_index, | |
10715 | struct set_config_cmd_payload *payload, | |
10716 | enum set_config_status *operation_result) | |
81927e28 JS |
10717 | { |
10718 | struct amdgpu_device *adev = ctx->driver_context; | |
ead08b95 SW |
10719 | bool is_cmd_complete; |
10720 | int ret; | |
81927e28 | 10721 | |
ead08b95 SW |
10722 | mutex_lock(&adev->dm.dpia_aux_lock); |
10723 | is_cmd_complete = dc_process_dmub_set_config_async(ctx->dc, | |
10724 | link_index, payload, adev->dm.dmub_notify); | |
88f52b1f | 10725 | |
ead08b95 SW |
10726 | if (is_cmd_complete || wait_for_completion_timeout(&adev->dm.dmub_aux_transfer_done, 10 * HZ)) { |
10727 | ret = 0; | |
10728 | *operation_result = adev->dm.dmub_notify->sc_status; | |
10729 | } else { | |
9e3a50d2 | 10730 | DRM_ERROR("wait_for_completion_timeout timeout!"); |
ead08b95 SW |
10731 | ret = -1; |
10732 | *operation_result = SET_CONFIG_UNKNOWN_ERROR; | |
81927e28 JS |
10733 | } |
10734 | ||
0cf8307a SW |
10735 | if (!is_cmd_complete) |
10736 | reinit_completion(&adev->dm.dmub_aux_transfer_done); | |
ead08b95 SW |
10737 | mutex_unlock(&adev->dm.dpia_aux_lock); |
10738 | return ret; | |
81927e28 | 10739 | } |
1edf5ae1 ZL |
10740 | |
10741 | /* | |
10742 | * Check whether seamless boot is supported. | |
10743 | * | |
10744 | * So far we only support seamless boot on CHIP_VANGOGH. | |
10745 | * If everything goes well, we may consider expanding | |
10746 | * seamless boot to other ASICs. | |
10747 | */ | |
10748 | bool check_seamless_boot_capability(struct amdgpu_device *adev) | |
10749 | { | |
20875141 PY |
10750 | switch (adev->ip_versions[DCE_HWIP][0]) { |
10751 | case IP_VERSION(3, 0, 1): | |
1edf5ae1 ZL |
10752 | if (!adev->mman.keep_stolen_vga_memory) |
10753 | return true; | |
10754 | break; | |
10755 | default: | |
10756 | break; | |
10757 | } | |
10758 | ||
10759 | return false; | |
10760 | } |