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drm/i915: convert INTEL_DISPLAY_ENABLED() into a function
[thirdparty/linux.git] / drivers / gpu / drm / i915 / display / intel_sdvo.c
CommitLineData
79e53945
JB		 1/*
2 * Copyright 2006 Dave Airlie <airlied@linux.ie>
3 * Copyright © 2006-2007 Intel Corporation
4 * Jesse Barnes <jesse.barnes@intel.com>
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
15 * Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
22 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
23 * DEALINGS IN THE SOFTWARE.
24 *
25 * Authors:
26 * Eric Anholt <eric@anholt.net>
27 */
ec7f29ff 28
79e53945 29#include <linux/delay.h>
2d1a8a48 30#include <linux/export.h>
ec7f29ff
JN		 31#include <linux/i2c.h>
32#include <linux/slab.h>
33
4fc8cb47 34#include <drm/display/drm_hdmi_helper.h>
c6f95f27 35#include <drm/drm_atomic_helper.h>
760285e7
DH		 36#include <drm/drm_crtc.h>
37#include <drm/drm_edid.h>
ec7f29ff 38
79e53945 39#include "i915_drv.h"
801543b2 40#include "i915_reg.h"
12392a74 41#include "intel_atomic.h"
8e10cd13 42#include "intel_audio.h"
ec7f29ff 43#include "intel_connector.h"
7c53e628 44#include "intel_crtc.h"
7785ae0b 45#include "intel_de.h"
1d455f8d 46#include "intel_display_types.h"
998d2cd3 47#include "intel_fdi.h"
8834e365 48#include "intel_fifo_underrun.h"
3ce2ea65 49#include "intel_gmbus.h"
0550691d 50#include "intel_hdmi.h"
dbeb38d9 51#include "intel_hotplug.h"
44c1220a 52#include "intel_panel.h"
596fee14 53#include "intel_sdvo.h"
79e53945
JB		 54#include "intel_sdvo_regs.h"
55
14571b4c
ZW		 56#define SDVO_TMDS_MASK (SDVO_OUTPUT_TMDS0 | SDVO_OUTPUT_TMDS1)
57#define SDVO_RGB_MASK (SDVO_OUTPUT_RGB0 | SDVO_OUTPUT_RGB1)
58#define SDVO_LVDS_MASK (SDVO_OUTPUT_LVDS0 | SDVO_OUTPUT_LVDS1)
a0b1c7a5 59#define SDVO_TV_MASK (SDVO_OUTPUT_CVBS0 | SDVO_OUTPUT_SVID0 | SDVO_OUTPUT_YPRPB0)
14571b4c 60
a5d1d0a1 61#define SDVO_OUTPUT_MASK (SDVO_TMDS_MASK | SDVO_RGB_MASK | SDVO_LVDS_MASK | SDVO_TV_MASK)
14571b4c 62
a5d1d0a1
VS		 63#define IS_TV(c) ((c)->output_flag & SDVO_TV_MASK)
64#define IS_TMDS(c) ((c)->output_flag & SDVO_TMDS_MASK)
65#define IS_LVDS(c) ((c)->output_flag & SDVO_LVDS_MASK)
66#define IS_TV_OR_LVDS(c) ((c)->output_flag & (SDVO_TV_MASK | SDVO_LVDS_MASK))
67#define IS_DIGITAL(c) ((c)->output_flag & (SDVO_TMDS_MASK | SDVO_LVDS_MASK))
14571b4c 68
c0ff6c6e
VS		 69#define HAS_DDC(c) ((c)->output_flag & (SDVO_RGB_MASK | SDVO_TMDS_MASK | \
70 SDVO_LVDS_MASK))
79e53945 71
4d9194de 72static const char * const tv_format_names[] = {
ce6feabd
ZY		 73 "NTSC_M" , "NTSC_J" , "NTSC_443",
74 "PAL_B" , "PAL_D" , "PAL_G" ,
75 "PAL_H" , "PAL_I" , "PAL_M" ,
76 "PAL_N" , "PAL_NC" , "PAL_60" ,
77 "SECAM_B" , "SECAM_D" , "SECAM_G" ,
78 "SECAM_K" , "SECAM_K1", "SECAM_L" ,
79 "SECAM_60"
80};
81
53abb679 82#define TV_FORMAT_NUM ARRAY_SIZE(tv_format_names)
ce6feabd 83
c0ff6c6e
VS		 84struct intel_sdvo;
85
86struct intel_sdvo_ddc {
87 struct i2c_adapter ddc;
88 struct intel_sdvo *sdvo;
89 u8 ddc_bus;
90};
91
ea5b213a
CW		 92struct intel_sdvo {
93 struct intel_encoder base;
94
f899fc64 95 struct i2c_adapter *i2c;
f9c10a9b 96 u8 slave_addr;
e2f0ba97 97
c0ff6c6e 98 struct intel_sdvo_ddc ddc[3];
e957d772 99
e2f0ba97 100 /* Register for the SDVO device: SDVOB or SDVOC */
f0f59a00 101 i915_reg_t sdvo_reg;
79e53945 102
e2f0ba97
JB		 103 /*
104 * Capabilities of the SDVO device returned by
19d415a2 105 * intel_sdvo_get_capabilities()
e2f0ba97 106 */
79e53945 107 struct intel_sdvo_caps caps;
e2f0ba97 108
90f8ed85
VS		 109 u8 colorimetry_cap;
110
e2f0ba97 111 /* Pixel clock limitations reported by the SDVO device, in kHz */
79e53945
JB		 112 int pixel_clock_min, pixel_clock_max;
113
cc68c81a
SF		 114 /*
115 * Hotplug activation bits for this device
116 */
a9dc3395 117 u16 hotplug_active;
cc68c81a 118
e751823d
EE		 119 /*
120 * the sdvo flag gets lost in round trip: dtd->adjusted_mode->dtd
121 */
a9dc3395 122 u8 dtd_sdvo_flags;
14571b4c
ZW		 123};
124
125struct intel_sdvo_connector {
615fb93f
CW		 126 struct intel_connector base;
127
14571b4c 128 /* Mark the type of connector */
a9dc3395 129 u16 output_flag;
14571b4c
ZW		 130
131 /* This contains all current supported TV format */
40039750 132 u8 tv_format_supported[TV_FORMAT_NUM];
14571b4c 133 int format_supported_num;
c5521706 134 struct drm_property *tv_format;
14571b4c 135
b9219c5e 136 /* add the property for the SDVO-TV */
c5521706
CW		 137 struct drm_property *left;
138 struct drm_property *right;
139 struct drm_property *top;
140 struct drm_property *bottom;
141 struct drm_property *hpos;
142 struct drm_property *vpos;
143 struct drm_property *contrast;
144 struct drm_property *saturation;
145 struct drm_property *hue;
146 struct drm_property *sharpness;
147 struct drm_property *flicker_filter;
148 struct drm_property *flicker_filter_adaptive;
149 struct drm_property *flicker_filter_2d;
150 struct drm_property *tv_chroma_filter;
151 struct drm_property *tv_luma_filter;
e044218a 152 struct drm_property *dot_crawl;
b9219c5e
ZY		 153
154 /* add the property for the SDVO-TV/LVDS */
c5521706 155 struct drm_property *brightness;
b9219c5e 156
b9219c5e 157 /* this is to get the range of margin.*/
630d30a4 158 u32 max_hscan, max_vscan;
aa2b8807
VS		 159
160 /**
161 * This is set if we treat the device as HDMI, instead of DVI.
162 */
163 bool is_hdmi;
630d30a4
ML		 164};
165
166struct intel_sdvo_connector_state {
167 /* base.base: tv.saturation/contrast/hue/brightness */
168 struct intel_digital_connector_state base;
169
170 struct {
171 unsigned overscan_h, overscan_v, hpos, vpos, sharpness;
172 unsigned flicker_filter, flicker_filter_2d, flicker_filter_adaptive;
173 unsigned chroma_filter, luma_filter, dot_crawl;
174 } tv;
79e53945
JB		 175};
176
8aca63aa 177static struct intel_sdvo *to_sdvo(struct intel_encoder *encoder)
ea5b213a 178{
8aca63aa 179 return container_of(encoder, struct intel_sdvo, base);
ea5b213a
CW		 180}
181
43a6d19c 182static struct intel_sdvo *intel_attached_sdvo(struct intel_connector *connector)
df0e9248 183{
8aca63aa 184 return to_sdvo(intel_attached_encoder(connector));
df0e9248
CW		 185}
186
630d30a4
ML		 187static struct intel_sdvo_connector *
188to_intel_sdvo_connector(struct drm_connector *connector)
189{
190 return container_of(connector, struct intel_sdvo_connector, base.base);
191}
192
5f88a9c6
VS		 193#define to_intel_sdvo_connector_state(conn_state) \
194 container_of((conn_state), struct intel_sdvo_connector_state, base.base)
615fb93f 195
fb7a46f3 196static bool
aa7d827b 197intel_sdvo_output_setup(struct intel_sdvo *intel_sdvo);
32aad86f
CW		 198static bool
199intel_sdvo_tv_create_property(struct intel_sdvo *intel_sdvo,
200 struct intel_sdvo_connector *intel_sdvo_connector,
201 int type);
202static bool
203intel_sdvo_create_enhance_property(struct intel_sdvo *intel_sdvo,
204 struct intel_sdvo_connector *intel_sdvo_connector);
fb7a46f3 205
c16336b9 206/*
79e53945
JB		 207 * Writes the SDVOB or SDVOC with the given value, but always writes both
208 * SDVOB and SDVOC to work around apparent hardware issues (according to
209 * comments in the BIOS).
210 */
ea5b213a 211static void intel_sdvo_write_sdvox(struct intel_sdvo *intel_sdvo, u32 val)
79e53945 212{
4ef69c7a 213 struct drm_device *dev = intel_sdvo->base.base.dev;
fac5e23e 214 struct drm_i915_private *dev_priv = to_i915(dev);
79e53945
JB		 215 u32 bval = val, cval = val;
216 int i;
217
2a5c0832 218 if (HAS_PCH_SPLIT(dev_priv)) {
d2afcc44
JN		 219 intel_de_write(dev_priv, intel_sdvo->sdvo_reg, val);
220 intel_de_posting_read(dev_priv, intel_sdvo->sdvo_reg);
e8504ee2
VS		 221 /*
222 * HW workaround, need to write this twice for issue
223 * that may result in first write getting masked.
224 */
6e266956 225 if (HAS_PCH_IBX(dev_priv)) {
d2afcc44
JN		 226 intel_de_write(dev_priv, intel_sdvo->sdvo_reg, val);
227 intel_de_posting_read(dev_priv, intel_sdvo->sdvo_reg);
e8504ee2 228 }
461ed3ca
ZY		 229 return;
230 }
231
c6eddd31 232 if (intel_sdvo->base.port == PORT_B)
d2afcc44 233 cval = intel_de_read(dev_priv, GEN3_SDVOC);
e2debe91 234 else
d2afcc44 235 bval = intel_de_read(dev_priv, GEN3_SDVOB);
e2debe91 236
79e53945
JB		 237 /*
238 * Write the registers twice for luck. Sometimes,
239 * writing them only once doesn't appear to 'stick'.
240 * The BIOS does this too. Yay, magic
241 */
c16336b9 242 for (i = 0; i < 2; i++) {
d2afcc44
JN		 243 intel_de_write(dev_priv, GEN3_SDVOB, bval);
244 intel_de_posting_read(dev_priv, GEN3_SDVOB);
c16336b9 245
d2afcc44
JN		 246 intel_de_write(dev_priv, GEN3_SDVOC, cval);
247 intel_de_posting_read(dev_priv, GEN3_SDVOC);
79e53945
JB		 248 }
249}
250
32aad86f 251static bool intel_sdvo_read_byte(struct intel_sdvo *intel_sdvo, u8 addr, u8 *ch)
79e53945 252{
79e53945
JB		 253 struct i2c_msg msgs[] = {
254 {
e957d772 255 .addr = intel_sdvo->slave_addr,
79e53945
JB		 256 .flags = 0,
257 .len = 1,
e957d772 258 .buf = &addr,
79e53945
JB		 259 },
260 {
e957d772 261 .addr = intel_sdvo->slave_addr,
79e53945
JB		 262 .flags = I2C_M_RD,
263 .len = 1,
e957d772 264 .buf = ch,
79e53945
JB		 265 }
266 };
32aad86f 267 int ret;
79e53945 268
f899fc64 269 if ((ret = i2c_transfer(intel_sdvo->i2c, msgs, 2)) == 2)
79e53945 270 return true;
79e53945 271
8a4c47f3 272 DRM_DEBUG_KMS("i2c transfer returned %d\n", ret);
79e53945
JB		 273 return false;
274}
275
7b8062ea
VS		 276#define SDVO_CMD_NAME_ENTRY(cmd_) { .cmd = SDVO_CMD_ ## cmd_, .name = #cmd_ }
277
79e53945 278/** Mapping of command numbers to names, for debug output */
7b8062ea 279static const struct {
e2f0ba97 280 u8 cmd;
2e88e40b 281 const char *name;
008bd15c 282} __packed sdvo_cmd_names[] = {
7b8062ea
VS		 283 SDVO_CMD_NAME_ENTRY(RESET),
284 SDVO_CMD_NAME_ENTRY(GET_DEVICE_CAPS),
285 SDVO_CMD_NAME_ENTRY(GET_FIRMWARE_REV),
286 SDVO_CMD_NAME_ENTRY(GET_TRAINED_INPUTS),
287 SDVO_CMD_NAME_ENTRY(GET_ACTIVE_OUTPUTS),
288 SDVO_CMD_NAME_ENTRY(SET_ACTIVE_OUTPUTS),
289 SDVO_CMD_NAME_ENTRY(GET_IN_OUT_MAP),
290 SDVO_CMD_NAME_ENTRY(SET_IN_OUT_MAP),
291 SDVO_CMD_NAME_ENTRY(GET_ATTACHED_DISPLAYS),
292 SDVO_CMD_NAME_ENTRY(GET_HOT_PLUG_SUPPORT),
293 SDVO_CMD_NAME_ENTRY(SET_ACTIVE_HOT_PLUG),
294 SDVO_CMD_NAME_ENTRY(GET_ACTIVE_HOT_PLUG),
295 SDVO_CMD_NAME_ENTRY(GET_INTERRUPT_EVENT_SOURCE),
296 SDVO_CMD_NAME_ENTRY(SET_TARGET_INPUT),
297 SDVO_CMD_NAME_ENTRY(SET_TARGET_OUTPUT),
298 SDVO_CMD_NAME_ENTRY(GET_INPUT_TIMINGS_PART1),
299 SDVO_CMD_NAME_ENTRY(GET_INPUT_TIMINGS_PART2),
300 SDVO_CMD_NAME_ENTRY(SET_INPUT_TIMINGS_PART1),
301 SDVO_CMD_NAME_ENTRY(SET_INPUT_TIMINGS_PART2),
302 SDVO_CMD_NAME_ENTRY(SET_OUTPUT_TIMINGS_PART1),
303 SDVO_CMD_NAME_ENTRY(SET_OUTPUT_TIMINGS_PART2),
304 SDVO_CMD_NAME_ENTRY(GET_OUTPUT_TIMINGS_PART1),
305 SDVO_CMD_NAME_ENTRY(GET_OUTPUT_TIMINGS_PART2),
306 SDVO_CMD_NAME_ENTRY(CREATE_PREFERRED_INPUT_TIMING),
307 SDVO_CMD_NAME_ENTRY(GET_PREFERRED_INPUT_TIMING_PART1),
308 SDVO_CMD_NAME_ENTRY(GET_PREFERRED_INPUT_TIMING_PART2),
309 SDVO_CMD_NAME_ENTRY(GET_INPUT_PIXEL_CLOCK_RANGE),
310 SDVO_CMD_NAME_ENTRY(GET_OUTPUT_PIXEL_CLOCK_RANGE),
311 SDVO_CMD_NAME_ENTRY(GET_SUPPORTED_CLOCK_RATE_MULTS),
312 SDVO_CMD_NAME_ENTRY(GET_CLOCK_RATE_MULT),
313 SDVO_CMD_NAME_ENTRY(SET_CLOCK_RATE_MULT),
314 SDVO_CMD_NAME_ENTRY(GET_SUPPORTED_TV_FORMATS),
315 SDVO_CMD_NAME_ENTRY(GET_TV_FORMAT),
316 SDVO_CMD_NAME_ENTRY(SET_TV_FORMAT),
317 SDVO_CMD_NAME_ENTRY(GET_SUPPORTED_POWER_STATES),
318 SDVO_CMD_NAME_ENTRY(GET_POWER_STATE),
319 SDVO_CMD_NAME_ENTRY(SET_ENCODER_POWER_STATE),
320 SDVO_CMD_NAME_ENTRY(SET_DISPLAY_POWER_STATE),
321 SDVO_CMD_NAME_ENTRY(SET_CONTROL_BUS_SWITCH),
322 SDVO_CMD_NAME_ENTRY(GET_SDTV_RESOLUTION_SUPPORT),
323 SDVO_CMD_NAME_ENTRY(GET_SCALED_HDTV_RESOLUTION_SUPPORT),
324 SDVO_CMD_NAME_ENTRY(GET_SUPPORTED_ENHANCEMENTS),
0206e353
AJ		 325
326 /* Add the op code for SDVO enhancements */
7b8062ea
VS		 327 SDVO_CMD_NAME_ENTRY(GET_MAX_HPOS),
328 SDVO_CMD_NAME_ENTRY(GET_HPOS),
329 SDVO_CMD_NAME_ENTRY(SET_HPOS),
330 SDVO_CMD_NAME_ENTRY(GET_MAX_VPOS),
331 SDVO_CMD_NAME_ENTRY(GET_VPOS),
332 SDVO_CMD_NAME_ENTRY(SET_VPOS),
333 SDVO_CMD_NAME_ENTRY(GET_MAX_SATURATION),
334 SDVO_CMD_NAME_ENTRY(GET_SATURATION),
335 SDVO_CMD_NAME_ENTRY(SET_SATURATION),
336 SDVO_CMD_NAME_ENTRY(GET_MAX_HUE),
337 SDVO_CMD_NAME_ENTRY(GET_HUE),
338 SDVO_CMD_NAME_ENTRY(SET_HUE),
339 SDVO_CMD_NAME_ENTRY(GET_MAX_CONTRAST),
340 SDVO_CMD_NAME_ENTRY(GET_CONTRAST),
341 SDVO_CMD_NAME_ENTRY(SET_CONTRAST),
342 SDVO_CMD_NAME_ENTRY(GET_MAX_BRIGHTNESS),
343 SDVO_CMD_NAME_ENTRY(GET_BRIGHTNESS),
344 SDVO_CMD_NAME_ENTRY(SET_BRIGHTNESS),
345 SDVO_CMD_NAME_ENTRY(GET_MAX_OVERSCAN_H),
346 SDVO_CMD_NAME_ENTRY(GET_OVERSCAN_H),
347 SDVO_CMD_NAME_ENTRY(SET_OVERSCAN_H),
348 SDVO_CMD_NAME_ENTRY(GET_MAX_OVERSCAN_V),
349 SDVO_CMD_NAME_ENTRY(GET_OVERSCAN_V),
350 SDVO_CMD_NAME_ENTRY(SET_OVERSCAN_V),
351 SDVO_CMD_NAME_ENTRY(GET_MAX_FLICKER_FILTER),
352 SDVO_CMD_NAME_ENTRY(GET_FLICKER_FILTER),
353 SDVO_CMD_NAME_ENTRY(SET_FLICKER_FILTER),
354 SDVO_CMD_NAME_ENTRY(GET_MAX_FLICKER_FILTER_ADAPTIVE),
355 SDVO_CMD_NAME_ENTRY(GET_FLICKER_FILTER_ADAPTIVE),
356 SDVO_CMD_NAME_ENTRY(SET_FLICKER_FILTER_ADAPTIVE),
357 SDVO_CMD_NAME_ENTRY(GET_MAX_FLICKER_FILTER_2D),
358 SDVO_CMD_NAME_ENTRY(GET_FLICKER_FILTER_2D),
359 SDVO_CMD_NAME_ENTRY(SET_FLICKER_FILTER_2D),
360 SDVO_CMD_NAME_ENTRY(GET_MAX_SHARPNESS),
361 SDVO_CMD_NAME_ENTRY(GET_SHARPNESS),
362 SDVO_CMD_NAME_ENTRY(SET_SHARPNESS),
363 SDVO_CMD_NAME_ENTRY(GET_DOT_CRAWL),
364 SDVO_CMD_NAME_ENTRY(SET_DOT_CRAWL),
365 SDVO_CMD_NAME_ENTRY(GET_MAX_TV_CHROMA_FILTER),
366 SDVO_CMD_NAME_ENTRY(GET_TV_CHROMA_FILTER),
367 SDVO_CMD_NAME_ENTRY(SET_TV_CHROMA_FILTER),
368 SDVO_CMD_NAME_ENTRY(GET_MAX_TV_LUMA_FILTER),
369 SDVO_CMD_NAME_ENTRY(GET_TV_LUMA_FILTER),
370 SDVO_CMD_NAME_ENTRY(SET_TV_LUMA_FILTER),
0206e353
AJ		 371
372 /* HDMI op code */
7b8062ea
VS		 373 SDVO_CMD_NAME_ENTRY(GET_SUPP_ENCODE),
374 SDVO_CMD_NAME_ENTRY(GET_ENCODE),
375 SDVO_CMD_NAME_ENTRY(SET_ENCODE),
376 SDVO_CMD_NAME_ENTRY(SET_PIXEL_REPLI),
377 SDVO_CMD_NAME_ENTRY(GET_PIXEL_REPLI),
378 SDVO_CMD_NAME_ENTRY(GET_COLORIMETRY_CAP),
379 SDVO_CMD_NAME_ENTRY(SET_COLORIMETRY),
380 SDVO_CMD_NAME_ENTRY(GET_COLORIMETRY),
381 SDVO_CMD_NAME_ENTRY(GET_AUDIO_ENCRYPT_PREFER),
382 SDVO_CMD_NAME_ENTRY(SET_AUDIO_STAT),
383 SDVO_CMD_NAME_ENTRY(GET_AUDIO_STAT),
384 SDVO_CMD_NAME_ENTRY(GET_HBUF_INDEX),
385 SDVO_CMD_NAME_ENTRY(SET_HBUF_INDEX),
386 SDVO_CMD_NAME_ENTRY(GET_HBUF_INFO),
387 SDVO_CMD_NAME_ENTRY(GET_HBUF_AV_SPLIT),
388 SDVO_CMD_NAME_ENTRY(SET_HBUF_AV_SPLIT),
389 SDVO_CMD_NAME_ENTRY(GET_HBUF_TXRATE),
390 SDVO_CMD_NAME_ENTRY(SET_HBUF_TXRATE),
391 SDVO_CMD_NAME_ENTRY(SET_HBUF_DATA),
392 SDVO_CMD_NAME_ENTRY(GET_HBUF_DATA),
79e53945
JB		 393};
394
7b8062ea
VS		 395#undef SDVO_CMD_NAME_ENTRY
396
a46f4e9e
VS		 397static const char *sdvo_cmd_name(u8 cmd)
398{
399 int i;
400
401 for (i = 0; i < ARRAY_SIZE(sdvo_cmd_names); i++) {
402 if (cmd == sdvo_cmd_names[i].cmd)
403 return sdvo_cmd_names[i].name;
404 }
405
406 return NULL;
407}
408
c6eddd31 409#define SDVO_NAME(svdo) ((svdo)->base.port == PORT_B ? "SDVOB" : "SDVOC")
79e53945 410
ea5b213a 411static void intel_sdvo_debug_write(struct intel_sdvo *intel_sdvo, u8 cmd,
32aad86f 412 const void *args, int args_len)
79e53945 413{
cb7cbb4b 414 struct drm_i915_private *dev_priv = to_i915(intel_sdvo->base.base.dev);
a46f4e9e 415 const char *cmd_name;
84fcb469 416 int i, pos = 0;
cb70b713 417 char buffer[64];
84fcb469
DV		 418
419#define BUF_PRINT(args...) \
cb70b713 420 pos += snprintf(buffer + pos, max_t(int, sizeof(buffer) - pos, 0), args)
79e53945 421
84fcb469
DV		 422 for (i = 0; i < args_len; i++) {
423 BUF_PRINT("%02X ", ((u8 *)args)[i]);
424 }
425 for (; i < 8; i++) {
426 BUF_PRINT(" ");
427 }
a46f4e9e
VS		 428
429 cmd_name = sdvo_cmd_name(cmd);
430 if (cmd_name)
431 BUF_PRINT("(%s)", cmd_name);
432 else
84fcb469 433 BUF_PRINT("(%02X)", cmd);
cb70b713 434
cb7cbb4b 435 drm_WARN_ON(&dev_priv->drm, pos >= sizeof(buffer) - 1);
84fcb469 436#undef BUF_PRINT
84fcb469
DV		 437
438 DRM_DEBUG_KMS("%s: W: %02X %s\n", SDVO_NAME(intel_sdvo), cmd, buffer);
79e53945 439}
79e53945 440
4d9194de 441static const char * const cmd_status_names[] = {
c598a664
VS		 442 [SDVO_CMD_STATUS_POWER_ON] = "Power on",
443 [SDVO_CMD_STATUS_SUCCESS] = "Success",
444 [SDVO_CMD_STATUS_NOTSUPP] = "Not supported",
445 [SDVO_CMD_STATUS_INVALID_ARG] = "Invalid arg",
446 [SDVO_CMD_STATUS_PENDING] = "Pending",
447 [SDVO_CMD_STATUS_TARGET_NOT_SPECIFIED] = "Target not specified",
448 [SDVO_CMD_STATUS_SCALING_NOT_SUPP] = "Scaling not supported",
e957d772
CW		 449};
450
a46f4e9e
VS		 451static const char *sdvo_cmd_status(u8 status)
452{
453 if (status < ARRAY_SIZE(cmd_status_names))
454 return cmd_status_names[status];
455 else
456 return NULL;
457}
458
a8506684
DV		 459static bool __intel_sdvo_write_cmd(struct intel_sdvo *intel_sdvo, u8 cmd,
460 const void *args, int args_len,
461 bool unlocked)
79e53945 462{
3bf3f452
BW		 463 u8 *buf, status;
464 struct i2c_msg *msgs;
465 int i, ret = true;
466
a8506684 467 /* Would be simpler to allocate both in one go ? */
5c67eeb6 468 buf = kzalloc(args_len * 2 + 2, GFP_KERNEL);
3bf3f452
BW		 469 if (!buf)
470 return false;
471
472 msgs = kcalloc(args_len + 3, sizeof(*msgs), GFP_KERNEL);
0274df3e 473 if (!msgs) {
a8506684 474 kfree(buf);
3bf3f452 475 return false;
a8506684 476 }
79e53945 477
ea5b213a 478 intel_sdvo_debug_write(intel_sdvo, cmd, args, args_len);
79e53945
JB		 479
480 for (i = 0; i < args_len; i++) {
e957d772
CW		 481 msgs[i].addr = intel_sdvo->slave_addr;
482 msgs[i].flags = 0;
483 msgs[i].len = 2;
484 msgs[i].buf = buf + 2 *i;
485 buf[2*i + 0] = SDVO_I2C_ARG_0 - i;
486 buf[2*i + 1] = ((u8*)args)[i];
487 }
488 msgs[i].addr = intel_sdvo->slave_addr;
489 msgs[i].flags = 0;
490 msgs[i].len = 2;
491 msgs[i].buf = buf + 2*i;
492 buf[2*i + 0] = SDVO_I2C_OPCODE;
493 buf[2*i + 1] = cmd;
494
495 /* the following two are to read the response */
496 status = SDVO_I2C_CMD_STATUS;
497 msgs[i+1].addr = intel_sdvo->slave_addr;
498 msgs[i+1].flags = 0;
499 msgs[i+1].len = 1;
500 msgs[i+1].buf = &status;
501
502 msgs[i+2].addr = intel_sdvo->slave_addr;
503 msgs[i+2].flags = I2C_M_RD;
504 msgs[i+2].len = 1;
505 msgs[i+2].buf = &status;
506
a8506684
DV		 507 if (unlocked)
508 ret = i2c_transfer(intel_sdvo->i2c, msgs, i+3);
509 else
510 ret = __i2c_transfer(intel_sdvo->i2c, msgs, i+3);
e957d772
CW		 511 if (ret < 0) {
512 DRM_DEBUG_KMS("I2c transfer returned %d\n", ret);
3bf3f452
BW		 513 ret = false;
514 goto out;
e957d772
CW		 515 }
516 if (ret != i+3) {
517 /* failure in I2C transfer */
518 DRM_DEBUG_KMS("I2c transfer returned %d/%d\n", ret, i+3);
3bf3f452 519 ret = false;
e957d772
CW		 520 }
521
3bf3f452
BW		 522out:
523 kfree(msgs);
524 kfree(buf);
525 return ret;
79e53945
JB		 526}
527
a8506684
DV		 528static bool intel_sdvo_write_cmd(struct intel_sdvo *intel_sdvo, u8 cmd,
529 const void *args, int args_len)
530{
531 return __intel_sdvo_write_cmd(intel_sdvo, cmd, args, args_len, true);
532}
533
b5c616a7
CW		 534static bool intel_sdvo_read_response(struct intel_sdvo *intel_sdvo,
535 void *response, int response_len)
79e53945 536{
cb7cbb4b 537 struct drm_i915_private *dev_priv = to_i915(intel_sdvo->base.base.dev);
a46f4e9e 538 const char *cmd_status;
fc37381c 539 u8 retry = 15; /* 5 quick checks, followed by 10 long checks */
b5c616a7 540 u8 status;
84fcb469 541 int i, pos = 0;
cb70b713 542 char buffer[64];
79e53945 543
bca29283 544 buffer[0] = '\0';
d121a5d2 545
b5c616a7
CW		 546 /*
547 * The documentation states that all commands will be
548 * processed within 15µs, and that we need only poll
549 * the status byte a maximum of 3 times in order for the
550 * command to be complete.
551 *
552 * Check 5 times in case the hardware failed to read the docs.
fc37381c
CW		 553 *
554 * Also beware that the first response by many devices is to
555 * reply PENDING and stall for time. TVs are notorious for
556 * requiring longer than specified to complete their replies.
557 * Originally (in the DDX long ago), the delay was only ever 15ms
558 * with an additional delay of 30ms applied for TVs added later after
559 * many experiments. To accommodate both sets of delays, we do a
560 * sequence of slow checks if the device is falling behind and fails
561 * to reply within 5*15µs.
b5c616a7 562 */
d121a5d2
CW		 563 if (!intel_sdvo_read_byte(intel_sdvo,
564 SDVO_I2C_CMD_STATUS,
565 &status))
566 goto log_fail;
567
1ad87e72 568 while ((status == SDVO_CMD_STATUS_PENDING ||
46a3f4a3 569 status == SDVO_CMD_STATUS_TARGET_NOT_SPECIFIED) && --retry) {
fc37381c
CW		 570 if (retry < 10)
571 msleep(15);
572 else
573 udelay(15);
574
b5c616a7
CW		 575 if (!intel_sdvo_read_byte(intel_sdvo,
576 SDVO_I2C_CMD_STATUS,
577 &status))
d121a5d2
CW		 578 goto log_fail;
579 }
b5c616a7 580
84fcb469 581#define BUF_PRINT(args...) \
cb70b713 582 pos += snprintf(buffer + pos, max_t(int, sizeof(buffer) - pos, 0), args)
84fcb469 583
a46f4e9e
VS		 584 cmd_status = sdvo_cmd_status(status);
585 if (cmd_status)
586 BUF_PRINT("(%s)", cmd_status);
79e53945 587 else
84fcb469 588 BUF_PRINT("(??? %d)", status);
79e53945 589
b5c616a7
CW		 590 if (status != SDVO_CMD_STATUS_SUCCESS)
591 goto log_fail;
79e53945 592
b5c616a7
CW		 593 /* Read the command response */
594 for (i = 0; i < response_len; i++) {
595 if (!intel_sdvo_read_byte(intel_sdvo,
596 SDVO_I2C_RETURN_0 + i,
597 &((u8 *)response)[i]))
598 goto log_fail;
84fcb469 599 BUF_PRINT(" %02X", ((u8 *)response)[i]);
b5c616a7 600 }
cb70b713 601
cb7cbb4b 602 drm_WARN_ON(&dev_priv->drm, pos >= sizeof(buffer) - 1);
84fcb469 603#undef BUF_PRINT
84fcb469
DV		 604
605 DRM_DEBUG_KMS("%s: R: %s\n", SDVO_NAME(intel_sdvo), buffer);
b5c616a7 606 return true;
79e53945 607
b5c616a7 608log_fail:
bca29283
VS		 609 DRM_DEBUG_KMS("%s: R: ... failed %s\n",
610 SDVO_NAME(intel_sdvo), buffer);
b5c616a7 611 return false;
79e53945
JB		 612}
613
5e7234c9 614static int intel_sdvo_get_pixel_multiplier(const struct drm_display_mode *adjusted_mode)
79e53945 615{
aad941d5 616 if (adjusted_mode->crtc_clock >= 100000)
79e53945 617 return 1;
aad941d5 618 else if (adjusted_mode->crtc_clock >= 50000)
79e53945
JB		 619 return 2;
620 else
621 return 4;
622}
623
a8506684
DV		 624static bool __intel_sdvo_set_control_bus_switch(struct intel_sdvo *intel_sdvo,
625 u8 ddc_bus)
79e53945 626{
d121a5d2 627 /* This must be the immediately preceding write before the i2c xfer */
a8506684
DV		 628 return __intel_sdvo_write_cmd(intel_sdvo,
629 SDVO_CMD_SET_CONTROL_BUS_SWITCH,
630 &ddc_bus, 1, false);
79e53945
JB		 631}
632
32aad86f 633static bool intel_sdvo_set_value(struct intel_sdvo *intel_sdvo, u8 cmd, const void *data, int len)
79e53945 634{
d121a5d2
CW		 635 if (!intel_sdvo_write_cmd(intel_sdvo, cmd, data, len))
636 return false;
637
638 return intel_sdvo_read_response(intel_sdvo, NULL, 0);
32aad86f 639}
79e53945 640
32aad86f
CW		 641static bool
642intel_sdvo_get_value(struct intel_sdvo *intel_sdvo, u8 cmd, void *value, int len)
643{
644 if (!intel_sdvo_write_cmd(intel_sdvo, cmd, NULL, 0))
645 return false;
79e53945 646
32aad86f
CW		 647 return intel_sdvo_read_response(intel_sdvo, value, len);
648}
79e53945 649
32aad86f
CW		 650static bool intel_sdvo_set_target_input(struct intel_sdvo *intel_sdvo)
651{
652 struct intel_sdvo_set_target_input_args targets = {0};
653 return intel_sdvo_set_value(intel_sdvo,
654 SDVO_CMD_SET_TARGET_INPUT,
655 &targets, sizeof(targets));
79e53945
JB		 656}
657
c16336b9 658/*
79e53945
JB		 659 * Return whether each input is trained.
660 *
661 * This function is making an assumption about the layout of the response,
662 * which should be checked against the docs.
663 */
ea5b213a 664static bool intel_sdvo_get_trained_inputs(struct intel_sdvo *intel_sdvo, bool *input_1, bool *input_2)
79e53945
JB		 665{
666 struct intel_sdvo_get_trained_inputs_response response;
79e53945 667
1a3665c8 668 BUILD_BUG_ON(sizeof(response) != 1);
32aad86f
CW		 669 if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_TRAINED_INPUTS,
670 &response, sizeof(response)))
79e53945
JB		 671 return false;
672
673 *input_1 = response.input0_trained;
674 *input_2 = response.input1_trained;
675 return true;
676}
677
ea5b213a 678static bool intel_sdvo_set_active_outputs(struct intel_sdvo *intel_sdvo,
79e53945
JB		 679 u16 outputs)
680{
32aad86f
CW		 681 return intel_sdvo_set_value(intel_sdvo,
682 SDVO_CMD_SET_ACTIVE_OUTPUTS,
683 &outputs, sizeof(outputs));
79e53945
JB		 684}
685
4ac41f47
DV		 686static bool intel_sdvo_get_active_outputs(struct intel_sdvo *intel_sdvo,
687 u16 *outputs)
688{
689 return intel_sdvo_get_value(intel_sdvo,
690 SDVO_CMD_GET_ACTIVE_OUTPUTS,
691 outputs, sizeof(*outputs));
692}
693
ea5b213a 694static bool intel_sdvo_set_encoder_power_state(struct intel_sdvo *intel_sdvo,
79e53945
JB		 695 int mode)
696{
32aad86f 697 u8 state = SDVO_ENCODER_STATE_ON;
79e53945
JB		 698
699 switch (mode) {
700 case DRM_MODE_DPMS_ON:
701 state = SDVO_ENCODER_STATE_ON;
702 break;
703 case DRM_MODE_DPMS_STANDBY:
704 state = SDVO_ENCODER_STATE_STANDBY;
705 break;
706 case DRM_MODE_DPMS_SUSPEND:
707 state = SDVO_ENCODER_STATE_SUSPEND;
708 break;
709 case DRM_MODE_DPMS_OFF:
710 state = SDVO_ENCODER_STATE_OFF;
711 break;
712 }
713
32aad86f
CW		 714 return intel_sdvo_set_value(intel_sdvo,
715 SDVO_CMD_SET_ENCODER_POWER_STATE, &state, sizeof(state));
79e53945
JB		 716}
717
ea5b213a 718static bool intel_sdvo_get_input_pixel_clock_range(struct intel_sdvo *intel_sdvo,
79e53945
JB		 719 int *clock_min,
720 int *clock_max)
721{
722 struct intel_sdvo_pixel_clock_range clocks;
79e53945 723
1a3665c8 724 BUILD_BUG_ON(sizeof(clocks) != 4);
32aad86f
CW		 725 if (!intel_sdvo_get_value(intel_sdvo,
726 SDVO_CMD_GET_INPUT_PIXEL_CLOCK_RANGE,
727 &clocks, sizeof(clocks)))
79e53945
JB		 728 return false;
729
730 /* Convert the values from units of 10 kHz to kHz. */
731 *clock_min = clocks.min * 10;
732 *clock_max = clocks.max * 10;
79e53945
JB		 733 return true;
734}
735
ea5b213a 736static bool intel_sdvo_set_target_output(struct intel_sdvo *intel_sdvo,
79e53945
JB		 737 u16 outputs)
738{
32aad86f
CW		 739 return intel_sdvo_set_value(intel_sdvo,
740 SDVO_CMD_SET_TARGET_OUTPUT,
741 &outputs, sizeof(outputs));
79e53945
JB		 742}
743
ea5b213a 744static bool intel_sdvo_set_timing(struct intel_sdvo *intel_sdvo, u8 cmd,
79e53945
JB		 745 struct intel_sdvo_dtd *dtd)
746{
32aad86f
CW		 747 return intel_sdvo_set_value(intel_sdvo, cmd, &dtd->part1, sizeof(dtd->part1)) &&
748 intel_sdvo_set_value(intel_sdvo, cmd + 1, &dtd->part2, sizeof(dtd->part2));
79e53945
JB		 749}
750
045ac3b5
JB		 751static bool intel_sdvo_get_timing(struct intel_sdvo *intel_sdvo, u8 cmd,
752 struct intel_sdvo_dtd *dtd)
753{
754 return intel_sdvo_get_value(intel_sdvo, cmd, &dtd->part1, sizeof(dtd->part1)) &&
755 intel_sdvo_get_value(intel_sdvo, cmd + 1, &dtd->part2, sizeof(dtd->part2));
756}
757
ea5b213a 758static bool intel_sdvo_set_input_timing(struct intel_sdvo *intel_sdvo,
79e53945
JB		 759 struct intel_sdvo_dtd *dtd)
760{
ea5b213a 761 return intel_sdvo_set_timing(intel_sdvo,
79e53945
JB		 762 SDVO_CMD_SET_INPUT_TIMINGS_PART1, dtd);
763}
764
ea5b213a 765static bool intel_sdvo_set_output_timing(struct intel_sdvo *intel_sdvo,
79e53945
JB		 766 struct intel_sdvo_dtd *dtd)
767{
ea5b213a 768 return intel_sdvo_set_timing(intel_sdvo,
79e53945
JB		 769 SDVO_CMD_SET_OUTPUT_TIMINGS_PART1, dtd);
770}
771
045ac3b5
JB		 772static bool intel_sdvo_get_input_timing(struct intel_sdvo *intel_sdvo,
773 struct intel_sdvo_dtd *dtd)
774{
775 return intel_sdvo_get_timing(intel_sdvo,
776 SDVO_CMD_GET_INPUT_TIMINGS_PART1, dtd);
777}
778
e2f0ba97 779static bool
ea5b213a 780intel_sdvo_create_preferred_input_timing(struct intel_sdvo *intel_sdvo,
aa2b8807 781 struct intel_sdvo_connector *intel_sdvo_connector,
54b6af69 782 const struct drm_display_mode *mode)
e2f0ba97
JB		 783{
784 struct intel_sdvo_preferred_input_timing_args args;
e2f0ba97 785
e642c6f1 786 memset(&args, 0, sizeof(args));
54b6af69
VS		 787 args.clock = mode->clock / 10;
788 args.width = mode->hdisplay;
789 args.height = mode->vdisplay;
e642c6f1 790 args.interlace = 0;
12682a97 791
7b554301
VS		 792 if (IS_LVDS(intel_sdvo_connector)) {
793 const struct drm_display_mode *fixed_mode =
09270678 794 intel_panel_fixed_mode(&intel_sdvo_connector->base, mode);
7b554301 795
54b6af69
VS		 796 if (fixed_mode->hdisplay != args.width ||
797 fixed_mode->vdisplay != args.height)
7b554301
VS		 798 args.scaled = 1;
799 }
12682a97 800
32aad86f
CW		 801 return intel_sdvo_set_value(intel_sdvo,
802 SDVO_CMD_CREATE_PREFERRED_INPUT_TIMING,
803 &args, sizeof(args));
e2f0ba97
JB		 804}
805
ea5b213a 806static bool intel_sdvo_get_preferred_input_timing(struct intel_sdvo *intel_sdvo,
e2f0ba97
JB		 807 struct intel_sdvo_dtd *dtd)
808{
1a3665c8
CW		 809 BUILD_BUG_ON(sizeof(dtd->part1) != 8);
810 BUILD_BUG_ON(sizeof(dtd->part2) != 8);
32aad86f
CW		 811 return intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART1,
812 &dtd->part1, sizeof(dtd->part1)) &&
813 intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART2,
814 &dtd->part2, sizeof(dtd->part2));
e2f0ba97 815}
79e53945 816
ea5b213a 817static bool intel_sdvo_set_clock_rate_mult(struct intel_sdvo *intel_sdvo, u8 val)
79e53945 818{
32aad86f 819 return intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_CLOCK_RATE_MULT, &val, 1);
79e53945
JB		 820}
821
e2f0ba97 822static void intel_sdvo_get_dtd_from_mode(struct intel_sdvo_dtd *dtd,
32aad86f 823 const struct drm_display_mode *mode)
79e53945 824{
a9dc3395
JN		 825 u16 width, height;
826 u16 h_blank_len, h_sync_len, v_blank_len, v_sync_len;
827 u16 h_sync_offset, v_sync_offset;
6651819b 828 int mode_clock;
79e53945 829
1c4a814e
DV		 830 memset(dtd, 0, sizeof(*dtd));
831
c6ebd4c0
DV		 832 width = mode->hdisplay;
833 height = mode->vdisplay;
79e53945
JB		 834
835 /* do some mode translations */
c6ebd4c0
DV		 836 h_blank_len = mode->htotal - mode->hdisplay;
837 h_sync_len = mode->hsync_end - mode->hsync_start;
79e53945 838
c6ebd4c0
DV		 839 v_blank_len = mode->vtotal - mode->vdisplay;
840 v_sync_len = mode->vsync_end - mode->vsync_start;
79e53945 841
c6ebd4c0
DV		 842 h_sync_offset = mode->hsync_start - mode->hdisplay;
843 v_sync_offset = mode->vsync_start - mode->vdisplay;
79e53945 844
6651819b 845 mode_clock = mode->clock;
6651819b
DV		 846 mode_clock /= 10;
847 dtd->part1.clock = mode_clock;
848
e2f0ba97
JB		 849 dtd->part1.h_active = width & 0xff;
850 dtd->part1.h_blank = h_blank_len & 0xff;
851 dtd->part1.h_high = (((width >> 8) & 0xf) << 4) |
79e53945 852 ((h_blank_len >> 8) & 0xf);
e2f0ba97
JB		 853 dtd->part1.v_active = height & 0xff;
854 dtd->part1.v_blank = v_blank_len & 0xff;
855 dtd->part1.v_high = (((height >> 8) & 0xf) << 4) |
79e53945
JB		 856 ((v_blank_len >> 8) & 0xf);
857
171a9e96 858 dtd->part2.h_sync_off = h_sync_offset & 0xff;
e2f0ba97
JB		 859 dtd->part2.h_sync_width = h_sync_len & 0xff;
860 dtd->part2.v_sync_off_width = (v_sync_offset & 0xf) << 4 |
79e53945 861 (v_sync_len & 0xf);
e2f0ba97 862 dtd->part2.sync_off_width_high = ((h_sync_offset & 0x300) >> 2) |
79e53945
JB		 863 ((h_sync_len & 0x300) >> 4) | ((v_sync_offset & 0x30) >> 2) |
864 ((v_sync_len & 0x30) >> 4);
865
e2f0ba97 866 dtd->part2.dtd_flags = 0x18;
59d92bfa
DV		 867 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
868 dtd->part2.dtd_flags |= DTD_FLAG_INTERLACE;
79e53945 869 if (mode->flags & DRM_MODE_FLAG_PHSYNC)
59d92bfa 870 dtd->part2.dtd_flags |= DTD_FLAG_HSYNC_POSITIVE;
79e53945 871 if (mode->flags & DRM_MODE_FLAG_PVSYNC)
59d92bfa 872 dtd->part2.dtd_flags |= DTD_FLAG_VSYNC_POSITIVE;
e2f0ba97 873
e2f0ba97 874 dtd->part2.v_sync_off_high = v_sync_offset & 0xc0;
e2f0ba97
JB		 875}
876
1c4a814e 877static void intel_sdvo_get_mode_from_dtd(struct drm_display_mode *pmode,
32aad86f 878 const struct intel_sdvo_dtd *dtd)
e2f0ba97 879{
1c4a814e
DV		 880 struct drm_display_mode mode = {};
881
882 mode.hdisplay = dtd->part1.h_active;
883 mode.hdisplay += ((dtd->part1.h_high >> 4) & 0x0f) << 8;
884 mode.hsync_start = mode.hdisplay + dtd->part2.h_sync_off;
885 mode.hsync_start += (dtd->part2.sync_off_width_high & 0xc0) << 2;
886 mode.hsync_end = mode.hsync_start + dtd->part2.h_sync_width;
887 mode.hsync_end += (dtd->part2.sync_off_width_high & 0x30) << 4;
888 mode.htotal = mode.hdisplay + dtd->part1.h_blank;
889 mode.htotal += (dtd->part1.h_high & 0xf) << 8;
890
891 mode.vdisplay = dtd->part1.v_active;
892 mode.vdisplay += ((dtd->part1.v_high >> 4) & 0x0f) << 8;
893 mode.vsync_start = mode.vdisplay;
894 mode.vsync_start += (dtd->part2.v_sync_off_width >> 4) & 0xf;
895 mode.vsync_start += (dtd->part2.sync_off_width_high & 0x0c) << 2;
896 mode.vsync_start += dtd->part2.v_sync_off_high & 0xc0;
897 mode.vsync_end = mode.vsync_start +
e2f0ba97 898 (dtd->part2.v_sync_off_width & 0xf);
1c4a814e
DV		 899 mode.vsync_end += (dtd->part2.sync_off_width_high & 0x3) << 4;
900 mode.vtotal = mode.vdisplay + dtd->part1.v_blank;
901 mode.vtotal += (dtd->part1.v_high & 0xf) << 8;
e2f0ba97 902
1c4a814e 903 mode.clock = dtd->part1.clock * 10;
e2f0ba97 904
59d92bfa 905 if (dtd->part2.dtd_flags & DTD_FLAG_INTERLACE)
1c4a814e 906 mode.flags |= DRM_MODE_FLAG_INTERLACE;
59d92bfa 907 if (dtd->part2.dtd_flags & DTD_FLAG_HSYNC_POSITIVE)
1c4a814e 908 mode.flags |= DRM_MODE_FLAG_PHSYNC;
3cea210f 909 else
1c4a814e 910 mode.flags |= DRM_MODE_FLAG_NHSYNC;
59d92bfa 911 if (dtd->part2.dtd_flags & DTD_FLAG_VSYNC_POSITIVE)
1c4a814e 912 mode.flags |= DRM_MODE_FLAG_PVSYNC;
3cea210f 913 else
1c4a814e
DV		 914 mode.flags |= DRM_MODE_FLAG_NVSYNC;
915
916 drm_mode_set_crtcinfo(&mode, 0);
917
918 drm_mode_copy(pmode, &mode);
e2f0ba97
JB		 919}
920
e27d8538 921static bool intel_sdvo_check_supp_encode(struct intel_sdvo *intel_sdvo)
e2f0ba97 922{
e27d8538 923 struct intel_sdvo_encode encode;
e2f0ba97 924
1a3665c8 925 BUILD_BUG_ON(sizeof(encode) != 2);
e27d8538
CW		 926 return intel_sdvo_get_value(intel_sdvo,
927 SDVO_CMD_GET_SUPP_ENCODE,
928 &encode, sizeof(encode));
e2f0ba97
JB		 929}
930
ea5b213a 931static bool intel_sdvo_set_encode(struct intel_sdvo *intel_sdvo,
a9dc3395 932 u8 mode)
e2f0ba97 933{
32aad86f 934 return intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_ENCODE, &mode, 1);
e2f0ba97
JB		 935}
936
ea5b213a 937static bool intel_sdvo_set_colorimetry(struct intel_sdvo *intel_sdvo,
a9dc3395 938 u8 mode)
e2f0ba97 939{
32aad86f 940 return intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_COLORIMETRY, &mode, 1);
e2f0ba97
JB		 941}
942
d9757193
VS		 943static bool intel_sdvo_set_pixel_replication(struct intel_sdvo *intel_sdvo,
944 u8 pixel_repeat)
945{
946 return intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_PIXEL_REPLI,
947 &pixel_repeat, 1);
948}
949
dc49a56b
VS		 950static bool intel_sdvo_set_audio_state(struct intel_sdvo *intel_sdvo,
951 u8 audio_state)
952{
953 return intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_AUDIO_STAT,
954 &audio_state, 1);
955}
956
5a5efbf4
VS		 957static bool intel_sdvo_get_hbuf_size(struct intel_sdvo *intel_sdvo,
958 u8 *hbuf_size)
959{
960 if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_HBUF_INFO,
961 hbuf_size, 1))
962 return false;
963
964 /* Buffer size is 0 based, hooray! However zero means zero. */
965 if (*hbuf_size)
966 (*hbuf_size)++;
967
968 return true;
969}
970
e2f0ba97 971#if 0
ea5b213a 972static void intel_sdvo_dump_hdmi_buf(struct intel_sdvo *intel_sdvo)
e2f0ba97
JB		 973{
974 int i, j;
a9dc3395
JN		 975 u8 set_buf_index[2];
976 u8 av_split;
977 u8 buf_size;
978 u8 buf[48];
979 u8 *pos;
e2f0ba97 980
32aad86f 981 intel_sdvo_get_value(encoder, SDVO_CMD_GET_HBUF_AV_SPLIT, &av_split, 1);
e2f0ba97
JB		 982
983 for (i = 0; i <= av_split; i++) {
984 set_buf_index[0] = i; set_buf_index[1] = 0;
c751ce4f 985 intel_sdvo_write_cmd(encoder, SDVO_CMD_SET_HBUF_INDEX,
e2f0ba97 986 set_buf_index, 2);
c751ce4f
EA		 987 intel_sdvo_write_cmd(encoder, SDVO_CMD_GET_HBUF_INFO, NULL, 0);
988 intel_sdvo_read_response(encoder, &buf_size, 1);
e2f0ba97
JB		 989
990 pos = buf;
991 for (j = 0; j <= buf_size; j += 8) {
c751ce4f 992 intel_sdvo_write_cmd(encoder, SDVO_CMD_GET_HBUF_DATA,
e2f0ba97 993 NULL, 0);
c751ce4f 994 intel_sdvo_read_response(encoder, pos, 8);
e2f0ba97
JB		 995 pos += 8;
996 }
997 }
998}
999#endif
1000
b6e0e543 1001static bool intel_sdvo_write_infoframe(struct intel_sdvo *intel_sdvo,
a9dc3395
JN		 1002 unsigned int if_index, u8 tx_rate,
1003 const u8 *data, unsigned int length)
b6e0e543 1004{
a9dc3395
JN		 1005 u8 set_buf_index[2] = { if_index, 0 };
1006 u8 hbuf_size, tmp[8];
b6e0e543
DV		 1007 int i;
1008
1009 if (!intel_sdvo_set_value(intel_sdvo,
1010 SDVO_CMD_SET_HBUF_INDEX,
1011 set_buf_index, 2))
1012 return false;
1013
5a5efbf4 1014 if (!intel_sdvo_get_hbuf_size(intel_sdvo, &hbuf_size))
b6e0e543
DV		 1015 return false;
1016
5a5efbf4 1017 DRM_DEBUG_KMS("writing sdvo hbuf: %i, length %u, hbuf_size: %i\n",
b6e0e543
DV		 1018 if_index, length, hbuf_size);
1019
b5716a4e
VS		 1020 if (hbuf_size < length)
1021 return false;
1022
b6e0e543
DV		 1023 for (i = 0; i < hbuf_size; i += 8) {
1024 memset(tmp, 0, 8);
1025 if (i < length)
1026 memcpy(tmp, data + i, min_t(unsigned, 8, length - i));
1027
1028 if (!intel_sdvo_set_value(intel_sdvo,
1029 SDVO_CMD_SET_HBUF_DATA,
1030 tmp, 8))
1031 return false;
1032 }
1033
1034 return intel_sdvo_set_value(intel_sdvo,
1035 SDVO_CMD_SET_HBUF_TXRATE,
1036 &tx_rate, 1);
1037}
1038
0d567f1e
VS		 1039static ssize_t intel_sdvo_read_infoframe(struct intel_sdvo *intel_sdvo,
1040 unsigned int if_index,
1041 u8 *data, unsigned int length)
1042{
1043 u8 set_buf_index[2] = { if_index, 0 };
1044 u8 hbuf_size, tx_rate, av_split;
1045 int i;
1046
1047 if (!intel_sdvo_get_value(intel_sdvo,
1048 SDVO_CMD_GET_HBUF_AV_SPLIT,
1049 &av_split, 1))
1050 return -ENXIO;
1051
1052 if (av_split < if_index)
1053 return 0;
1054
cc54d5e8
VS		 1055 if (!intel_sdvo_set_value(intel_sdvo,
1056 SDVO_CMD_SET_HBUF_INDEX,
1057 set_buf_index, 2))
1058 return -ENXIO;
1059
0d567f1e
VS		 1060 if (!intel_sdvo_get_value(intel_sdvo,
1061 SDVO_CMD_GET_HBUF_TXRATE,
1062 &tx_rate, 1))
1063 return -ENXIO;
1064
72715b54
VS		 1065 /* TX_DISABLED doesn't mean disabled for ELD */
1066 if (if_index != SDVO_HBUF_INDEX_ELD && tx_rate == SDVO_HBUF_TX_DISABLED)
0d567f1e
VS		 1067 return 0;
1068
5a5efbf4
VS		 1069 if (!intel_sdvo_get_hbuf_size(intel_sdvo, &hbuf_size))
1070 return false;
0d567f1e 1071
5a5efbf4 1072 DRM_DEBUG_KMS("reading sdvo hbuf: %i, length %u, hbuf_size: %i\n",
0d567f1e
VS		 1073 if_index, length, hbuf_size);
1074
1075 hbuf_size = min_t(unsigned int, length, hbuf_size);
1076
1077 for (i = 0; i < hbuf_size; i += 8) {
1078 if (!intel_sdvo_write_cmd(intel_sdvo, SDVO_CMD_GET_HBUF_DATA, NULL, 0))
1079 return -ENXIO;
1080 if (!intel_sdvo_read_response(intel_sdvo, &data[i],
1081 min_t(unsigned int, 8, hbuf_size - i)))
1082 return -ENXIO;
1083 }
1084
1085 return hbuf_size;
1086}
1087
769be632
VS		 1088static bool intel_sdvo_compute_avi_infoframe(struct intel_sdvo *intel_sdvo,
1089 struct intel_crtc_state *crtc_state,
1090 struct drm_connector_state *conn_state)
e2f0ba97 1091{
cb7cbb4b 1092 struct drm_i915_private *dev_priv = to_i915(intel_sdvo->base.base.dev);
769be632 1093 struct hdmi_avi_infoframe *frame = &crtc_state->infoframes.avi.avi;
c3735f5c 1094 const struct drm_display_mode *adjusted_mode =
1326a92c 1095 &crtc_state->hw.adjusted_mode;
15dcd350 1096 int ret;
15dcd350 1097
769be632
VS		 1098 if (!crtc_state->has_hdmi_sink)
1099 return true;
1100
1101 crtc_state->infoframes.enable |=
1102 intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_AVI);
1103
1104 ret = drm_hdmi_avi_infoframe_from_display_mode(frame,
13d0add3 1105 conn_state->connector,
c3735f5c 1106 adjusted_mode);
769be632 1107 if (ret)
15dcd350 1108 return false;
3c17fe4b 1109
769be632 1110 drm_hdmi_avi_infoframe_quant_range(frame,
c3735f5c
VS		 1111 conn_state->connector,
1112 adjusted_mode,
769be632 1113 crtc_state->limited_color_range ?
c3735f5c 1114 HDMI_QUANTIZATION_RANGE_LIMITED :
1581b2df 1115 HDMI_QUANTIZATION_RANGE_FULL);
abedc077 1116
769be632 1117 ret = hdmi_avi_infoframe_check(frame);
cb7cbb4b 1118 if (drm_WARN_ON(&dev_priv->drm, ret))
769be632
VS		 1119 return false;
1120
1121 return true;
1122}
1123
1124static bool intel_sdvo_set_avi_infoframe(struct intel_sdvo *intel_sdvo,
1125 const struct intel_crtc_state *crtc_state)
1126{
cb7cbb4b 1127 struct drm_i915_private *dev_priv = to_i915(intel_sdvo->base.base.dev);
769be632
VS		 1128 u8 sdvo_data[HDMI_INFOFRAME_SIZE(AVI)];
1129 const union hdmi_infoframe *frame = &crtc_state->infoframes.avi;
1130 ssize_t len;
1131
1132 if ((crtc_state->infoframes.enable &
1133 intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_AVI)) == 0)
1134 return true;
1135
cb7cbb4b
PB		 1136 if (drm_WARN_ON(&dev_priv->drm,
1137 frame->any.type != HDMI_INFOFRAME_TYPE_AVI))
769be632
VS		 1138 return false;
1139
1140 len = hdmi_infoframe_pack_only(frame, sdvo_data, sizeof(sdvo_data));
cb7cbb4b 1141 if (drm_WARN_ON(&dev_priv->drm, len < 0))
15dcd350 1142 return false;
81014b9d 1143
b6e0e543
DV		 1144 return intel_sdvo_write_infoframe(intel_sdvo, SDVO_HBUF_INDEX_AVI_IF,
1145 SDVO_HBUF_TX_VSYNC,
7f668346 1146 sdvo_data, len);
e2f0ba97
JB		 1147}
1148
0d567f1e
VS		 1149static void intel_sdvo_get_avi_infoframe(struct intel_sdvo *intel_sdvo,
1150 struct intel_crtc_state *crtc_state)
1151{
1152 u8 sdvo_data[HDMI_INFOFRAME_SIZE(AVI)];
1153 union hdmi_infoframe *frame = &crtc_state->infoframes.avi;
1154 ssize_t len;
1155 int ret;
1156
1157 if (!crtc_state->has_hdmi_sink)
1158 return;
1159
1160 len = intel_sdvo_read_infoframe(intel_sdvo, SDVO_HBUF_INDEX_AVI_IF,
1161 sdvo_data, sizeof(sdvo_data));
1162 if (len < 0) {
1163 DRM_DEBUG_KMS("failed to read AVI infoframe\n");
1164 return;
1165 } else if (len == 0) {
1166 return;
1167 }
1168
1169 crtc_state->infoframes.enable |=
1170 intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_AVI);
1171
700bbf83 1172 ret = hdmi_infoframe_unpack(frame, sdvo_data, len);
0d567f1e
VS		 1173 if (ret) {
1174 DRM_DEBUG_KMS("Failed to unpack AVI infoframe\n");
1175 return;
1176 }
1177
1178 if (frame->any.type != HDMI_INFOFRAME_TYPE_AVI)
1179 DRM_DEBUG_KMS("Found the wrong infoframe type 0x%x (expected 0x%02x)\n",
1180 frame->any.type, HDMI_INFOFRAME_TYPE_AVI);
1181}
1182
72715b54
VS		 1183static void intel_sdvo_get_eld(struct intel_sdvo *intel_sdvo,
1184 struct intel_crtc_state *crtc_state)
1185{
1186 struct drm_i915_private *i915 = to_i915(intel_sdvo->base.base.dev);
1187 ssize_t len;
1188 u8 val;
1189
1190 if (!crtc_state->has_audio)
1191 return;
1192
1193 if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_AUDIO_STAT, &val, 1))
1194 return;
1195
1196 if ((val & SDVO_AUDIO_ELD_VALID) == 0)
1197 return;
1198
1199 len = intel_sdvo_read_infoframe(intel_sdvo, SDVO_HBUF_INDEX_ELD,
1200 crtc_state->eld, sizeof(crtc_state->eld));
1201 if (len < 0)
1202 drm_dbg_kms(&i915->drm, "failed to read ELD\n");
1203}
1204
630d30a4 1205static bool intel_sdvo_set_tv_format(struct intel_sdvo *intel_sdvo,
5f88a9c6 1206 const struct drm_connector_state *conn_state)
7026d4ac 1207{
ce6feabd 1208 struct intel_sdvo_tv_format format;
a9dc3395 1209 u32 format_map;
ce6feabd 1210
630d30a4 1211 format_map = 1 << conn_state->tv.mode;
ce6feabd 1212 memset(&format, 0, sizeof(format));
32aad86f 1213 memcpy(&format, &format_map, min(sizeof(format), sizeof(format_map)));
ce6feabd 1214
32aad86f
CW		 1215 BUILD_BUG_ON(sizeof(format) != 6);
1216 return intel_sdvo_set_value(intel_sdvo,
1217 SDVO_CMD_SET_TV_FORMAT,
1218 &format, sizeof(format));
7026d4ac
ZW		 1219}
1220
32aad86f
CW		 1221static bool
1222intel_sdvo_set_output_timings_from_mode(struct intel_sdvo *intel_sdvo,
31ea7857 1223 struct intel_sdvo_connector *intel_sdvo_connector,
e811f5ae 1224 const struct drm_display_mode *mode)
e2f0ba97 1225{
32aad86f 1226 struct intel_sdvo_dtd output_dtd;
79e53945 1227
32aad86f 1228 if (!intel_sdvo_set_target_output(intel_sdvo,
31ea7857 1229 intel_sdvo_connector->output_flag))
32aad86f 1230 return false;
e2f0ba97 1231
32aad86f
CW		 1232 intel_sdvo_get_dtd_from_mode(&output_dtd, mode);
1233 if (!intel_sdvo_set_output_timing(intel_sdvo, &output_dtd))
1234 return false;
e2f0ba97 1235
32aad86f
CW		 1236 return true;
1237}
1238
c16336b9
CW		 1239/*
1240 * Asks the sdvo controller for the preferred input mode given the output mode.
1241 * Unfortunately we have to set up the full output mode to do that.
1242 */
32aad86f 1243static bool
c9a29698 1244intel_sdvo_get_preferred_input_mode(struct intel_sdvo *intel_sdvo,
aa2b8807 1245 struct intel_sdvo_connector *intel_sdvo_connector,
e811f5ae 1246 const struct drm_display_mode *mode,
c9a29698 1247 struct drm_display_mode *adjusted_mode)
32aad86f 1248{
c9a29698
DV		 1249 struct intel_sdvo_dtd input_dtd;
1250
32aad86f
CW		 1251 /* Reset the input timing to the screen. Assume always input 0. */
1252 if (!intel_sdvo_set_target_input(intel_sdvo))
1253 return false;
e2f0ba97 1254
32aad86f 1255 if (!intel_sdvo_create_preferred_input_timing(intel_sdvo,
aa2b8807 1256 intel_sdvo_connector,
54b6af69 1257 mode))
32aad86f 1258 return false;
e2f0ba97 1259
32aad86f 1260 if (!intel_sdvo_get_preferred_input_timing(intel_sdvo,
c9a29698 1261 &input_dtd))
32aad86f 1262 return false;
e2f0ba97 1263
c9a29698 1264 intel_sdvo_get_mode_from_dtd(adjusted_mode, &input_dtd);
e751823d 1265 intel_sdvo->dtd_sdvo_flags = input_dtd.part2.sdvo_flags;
79e53945 1266
32aad86f
CW		 1267 return true;
1268}
12682a97 1269
e83d12e0 1270static int i9xx_adjust_sdvo_tv_clock(struct intel_crtc_state *pipe_config)
70484559 1271{
cb7cbb4b 1272 struct drm_i915_private *dev_priv = to_i915(pipe_config->uapi.crtc->dev);
d320aaaa 1273 unsigned int dotclock = pipe_config->hw.adjusted_mode.crtc_clock;
70484559
DV		 1274 struct dpll *clock = &pipe_config->dpll;
1275
c16336b9
CW		 1276 /*
1277 * SDVO TV has fixed PLL values depend on its clock range,
1278 * this mirrors vbios setting.
1279 */
70484559
DV		 1280 if (dotclock >= 100000 && dotclock < 140500) {
1281 clock->p1 = 2;
1282 clock->p2 = 10;
1283 clock->n = 3;
1284 clock->m1 = 16;
1285 clock->m2 = 8;
1286 } else if (dotclock >= 140500 && dotclock <= 200000) {
1287 clock->p1 = 1;
1288 clock->p2 = 10;
1289 clock->n = 6;
1290 clock->m1 = 12;
1291 clock->m2 = 8;
1292 } else {
e83d12e0
VS		 1293 drm_dbg_kms(&dev_priv->drm,
1294 "SDVO TV clock out of range: %i\n", dotclock);
1295 return -EINVAL;
70484559
DV		 1296 }
1297
1298 pipe_config->clock_set = true;
e83d12e0
VS		 1299
1300 return 0;
70484559
DV		 1301}
1302
f2f9c8cb 1303static bool intel_has_hdmi_sink(struct intel_sdvo_connector *intel_sdvo_connector,
814df0ce
VS		 1304 const struct drm_connector_state *conn_state)
1305{
f2f9c8cb
JN		 1306 struct drm_connector *connector = conn_state->connector;
1307
1308 return intel_sdvo_connector->is_hdmi &&
1309 connector->display_info.is_hdmi &&
814df0ce
VS		 1310 READ_ONCE(to_intel_digital_connector_state(conn_state)->force_audio) != HDMI_AUDIO_OFF_DVI;
1311}
1312
90f8ed85
VS		 1313static bool intel_sdvo_limited_color_range(struct intel_encoder *encoder,
1314 const struct intel_crtc_state *crtc_state,
1315 const struct drm_connector_state *conn_state)
1316{
1317 struct intel_sdvo *intel_sdvo = to_sdvo(encoder);
1318
1319 if ((intel_sdvo->colorimetry_cap & SDVO_COLORIMETRY_RGB220) == 0)
1320 return false;
1321
1322 return intel_hdmi_limited_color_range(crtc_state, conn_state);
1323}
1324
8388eb06
VS		 1325static bool intel_sdvo_has_audio(struct intel_encoder *encoder,
1326 const struct intel_crtc_state *crtc_state,
1327 const struct drm_connector_state *conn_state)
1328{
dd9f377a
JN		 1329 struct drm_connector *connector = conn_state->connector;
1330 struct intel_sdvo_connector *intel_sdvo_connector =
1331 to_intel_sdvo_connector(connector);
8388eb06
VS		 1332 const struct intel_digital_connector_state *intel_conn_state =
1333 to_intel_digital_connector_state(conn_state);
1334
1335 if (!crtc_state->has_hdmi_sink)
1336 return false;
1337
1338 if (intel_conn_state->force_audio == HDMI_AUDIO_AUTO)
dd9f377a
JN		 1339 return intel_sdvo_connector->is_hdmi &&
1340 connector->display_info.has_audio;
8388eb06
VS		 1341 else
1342 return intel_conn_state->force_audio == HDMI_AUDIO_ON;
1343}
1344
204474a6
LP		 1345static int intel_sdvo_compute_config(struct intel_encoder *encoder,
1346 struct intel_crtc_state *pipe_config,
1347 struct drm_connector_state *conn_state)
32aad86f 1348{
8aca63aa 1349 struct intel_sdvo *intel_sdvo = to_sdvo(encoder);
aa2b8807
VS		 1350 struct intel_sdvo_connector *intel_sdvo_connector =
1351 to_intel_sdvo_connector(conn_state->connector);
1326a92c
ML		 1352 struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
1353 struct drm_display_mode *mode = &pipe_config->hw.mode;
12682a97 1354
998d2cd3
ID		 1355 if (HAS_PCH_SPLIT(to_i915(encoder->base.dev))) {
1356 pipe_config->has_pch_encoder = true;
1357 if (!intel_fdi_compute_pipe_bpp(pipe_config))
1358 return -EINVAL;
1359 }
1360
5d2d38dd 1361 DRM_DEBUG_KMS("forcing bpc to 8 for SDVO\n");
998d2cd3 1362 /* FIXME: Don't increase pipe_bpp */
5d2d38dd 1363 pipe_config->pipe_bpp = 8*3;
a04d27cd 1364 pipe_config->sink_format = INTEL_OUTPUT_FORMAT_RGB;
d9facae6 1365 pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
5d2d38dd 1366
c16336b9
CW		 1367 /*
1368 * We need to construct preferred input timings based on our
32aad86f
CW		 1369 * output timings. To do that, we have to set the output
1370 * timings, even though this isn't really the right place in
1371 * the sequence to do it. Oh well.
1372 */
aa2b8807 1373 if (IS_TV(intel_sdvo_connector)) {
31ea7857
VS		 1374 if (!intel_sdvo_set_output_timings_from_mode(intel_sdvo,
1375 intel_sdvo_connector,
1376 mode))
204474a6 1377 return -EINVAL;
12682a97 1378
c9a29698 1379 (void) intel_sdvo_get_preferred_input_mode(intel_sdvo,
aa2b8807 1380 intel_sdvo_connector,
c9a29698
DV		 1381 mode,
1382 adjusted_mode);
09ede541 1383 pipe_config->sdvo_tv_clock = true;
aa2b8807 1384 } else if (IS_LVDS(intel_sdvo_connector)) {
09270678
VS		 1385 const struct drm_display_mode *fixed_mode =
1386 intel_panel_fixed_mode(&intel_sdvo_connector->base, mode);
cff4c2c6
VS		 1387 int ret;
1388
1389 ret = intel_panel_compute_config(&intel_sdvo_connector->base,
1390 adjusted_mode);
1391 if (ret)
1392 return ret;
1393
31ea7857
VS		 1394 if (!intel_sdvo_set_output_timings_from_mode(intel_sdvo,
1395 intel_sdvo_connector,
1396 fixed_mode))
204474a6 1397 return -EINVAL;
12682a97 1398
c9a29698 1399 (void) intel_sdvo_get_preferred_input_mode(intel_sdvo,
aa2b8807 1400 intel_sdvo_connector,
c9a29698
DV		 1401 mode,
1402 adjusted_mode);
e2f0ba97 1403 }
32aad86f 1404
e4dd27aa 1405 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)
204474a6 1406 return -EINVAL;
e4dd27aa 1407
c16336b9
CW		 1408 /*
1409 * Make the CRTC code factor in the SDVO pixel multiplier. The
6c9547ff 1410 * SDVO device will factor out the multiplier during mode_set.
32aad86f 1411 */
6cc5f341
DV		 1412 pipe_config->pixel_multiplier =
1413 intel_sdvo_get_pixel_multiplier(adjusted_mode);
32aad86f 1414
f2f9c8cb 1415 pipe_config->has_hdmi_sink = intel_has_hdmi_sink(intel_sdvo_connector, conn_state);
b32962f8 1416
8e10cd13
VS		 1417 pipe_config->has_audio =
1418 intel_sdvo_has_audio(encoder, pipe_config, conn_state) &&
1419 intel_audio_compute_config(encoder, pipe_config, conn_state);
9f04003e 1420
90f8ed85
VS		 1421 pipe_config->limited_color_range =
1422 intel_sdvo_limited_color_range(encoder, pipe_config,
1423 conn_state);
55bc60db 1424
70484559 1425 /* Clock computation needs to happen after pixel multiplier. */
e83d12e0
VS		 1426 if (IS_TV(intel_sdvo_connector)) {
1427 int ret;
1428
1429 ret = i9xx_adjust_sdvo_tv_clock(pipe_config);
1430 if (ret)
1431 return ret;
1432 }
70484559 1433
c504f4df
VS		 1434 if (conn_state->picture_aspect_ratio)
1435 adjusted_mode->picture_aspect_ratio =
1436 conn_state->picture_aspect_ratio;
7949dd47 1437
769be632
VS		 1438 if (!intel_sdvo_compute_avi_infoframe(intel_sdvo,
1439 pipe_config, conn_state)) {
1440 DRM_DEBUG_KMS("bad AVI infoframe\n");
1441 return -EINVAL;
1442 }
1443
204474a6 1444 return 0;
e2f0ba97
JB		 1445}
1446
630d30a4
ML		 1447#define UPDATE_PROPERTY(input, NAME) \
1448 do { \
1449 val = input; \
1450 intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_##NAME, &val, sizeof(val)); \
1451 } while (0)
1452
1453static void intel_sdvo_update_props(struct intel_sdvo *intel_sdvo,
5f88a9c6 1454 const struct intel_sdvo_connector_state *sdvo_state)
630d30a4 1455{
5f88a9c6 1456 const struct drm_connector_state *conn_state = &sdvo_state->base.base;
630d30a4
ML		 1457 struct intel_sdvo_connector *intel_sdvo_conn =
1458 to_intel_sdvo_connector(conn_state->connector);
a9dc3395 1459 u16 val;
630d30a4
ML		 1460
1461 if (intel_sdvo_conn->left)
1462 UPDATE_PROPERTY(sdvo_state->tv.overscan_h, OVERSCAN_H);
1463
1464 if (intel_sdvo_conn->top)
1465 UPDATE_PROPERTY(sdvo_state->tv.overscan_v, OVERSCAN_V);
1466
1467 if (intel_sdvo_conn->hpos)
1468 UPDATE_PROPERTY(sdvo_state->tv.hpos, HPOS);
1469
1470 if (intel_sdvo_conn->vpos)
1471 UPDATE_PROPERTY(sdvo_state->tv.vpos, VPOS);
1472
1473 if (intel_sdvo_conn->saturation)
1474 UPDATE_PROPERTY(conn_state->tv.saturation, SATURATION);
1475
1476 if (intel_sdvo_conn->contrast)
1477 UPDATE_PROPERTY(conn_state->tv.contrast, CONTRAST);
1478
1479 if (intel_sdvo_conn->hue)
1480 UPDATE_PROPERTY(conn_state->tv.hue, HUE);
1481
1482 if (intel_sdvo_conn->brightness)
1483 UPDATE_PROPERTY(conn_state->tv.brightness, BRIGHTNESS);
1484
1485 if (intel_sdvo_conn->sharpness)
1486 UPDATE_PROPERTY(sdvo_state->tv.sharpness, SHARPNESS);
1487
1488 if (intel_sdvo_conn->flicker_filter)
1489 UPDATE_PROPERTY(sdvo_state->tv.flicker_filter, FLICKER_FILTER);
1490
1491 if (intel_sdvo_conn->flicker_filter_2d)
1492 UPDATE_PROPERTY(sdvo_state->tv.flicker_filter_2d, FLICKER_FILTER_2D);
1493
1494 if (intel_sdvo_conn->flicker_filter_adaptive)
1495 UPDATE_PROPERTY(sdvo_state->tv.flicker_filter_adaptive, FLICKER_FILTER_ADAPTIVE);
1496
1497 if (intel_sdvo_conn->tv_chroma_filter)
1498 UPDATE_PROPERTY(sdvo_state->tv.chroma_filter, TV_CHROMA_FILTER);
1499
1500 if (intel_sdvo_conn->tv_luma_filter)
1501 UPDATE_PROPERTY(sdvo_state->tv.luma_filter, TV_LUMA_FILTER);
1502
1503 if (intel_sdvo_conn->dot_crawl)
1504 UPDATE_PROPERTY(sdvo_state->tv.dot_crawl, DOT_CRAWL);
1505
1506#undef UPDATE_PROPERTY
1507}
1508
ede9771d
VS		 1509static void intel_sdvo_pre_enable(struct intel_atomic_state *state,
1510 struct intel_encoder *intel_encoder,
5f88a9c6
VS		 1511 const struct intel_crtc_state *crtc_state,
1512 const struct drm_connector_state *conn_state)
e2f0ba97 1513{
66478475 1514 struct drm_i915_private *dev_priv = to_i915(intel_encoder->base.dev);
2225f3c6 1515 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1326a92c 1516 const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
5f88a9c6
VS		 1517 const struct intel_sdvo_connector_state *sdvo_state =
1518 to_intel_sdvo_connector_state(conn_state);
09270678 1519 struct intel_sdvo_connector *intel_sdvo_connector =
aa2b8807 1520 to_intel_sdvo_connector(conn_state->connector);
1326a92c 1521 const struct drm_display_mode *mode = &crtc_state->hw.mode;
8aca63aa 1522 struct intel_sdvo *intel_sdvo = to_sdvo(intel_encoder);
6c9547ff 1523 u32 sdvox;
e2f0ba97 1524 struct intel_sdvo_in_out_map in_out;
6651819b 1525 struct intel_sdvo_dtd input_dtd, output_dtd;
6c9547ff 1526 int rate;
e2f0ba97 1527
630d30a4
ML		 1528 intel_sdvo_update_props(intel_sdvo, sdvo_state);
1529
c16336b9
CW		 1530 /*
1531 * First, set the input mapping for the first input to our controlled
e2f0ba97
JB		 1532 * output. This is only correct if we're a single-input device, in
1533 * which case the first input is the output from the appropriate SDVO
1534 * channel on the motherboard. In a two-input device, the first input
1535 * will be SDVOB and the second SDVOC.
1536 */
31ea7857 1537 in_out.in0 = intel_sdvo_connector->output_flag;
e2f0ba97
JB		 1538 in_out.in1 = 0;
1539
c74696b9
PR		 1540 intel_sdvo_set_value(intel_sdvo,
1541 SDVO_CMD_SET_IN_OUT_MAP,
1542 &in_out, sizeof(in_out));
e2f0ba97 1543
6c9547ff
CW		 1544 /* Set the output timings to the screen */
1545 if (!intel_sdvo_set_target_output(intel_sdvo,
31ea7857 1546 intel_sdvo_connector->output_flag))
6c9547ff 1547 return;
e2f0ba97 1548
6651819b 1549 /* lvds has a special fixed output timing. */
09270678
VS		 1550 if (IS_LVDS(intel_sdvo_connector)) {
1551 const struct drm_display_mode *fixed_mode =
1552 intel_panel_fixed_mode(&intel_sdvo_connector->base, mode);
1553
1554 intel_sdvo_get_dtd_from_mode(&output_dtd, fixed_mode);
1555 } else {
6651819b 1556 intel_sdvo_get_dtd_from_mode(&output_dtd, mode);
09270678 1557 }
c8d4bb54 1558 if (!intel_sdvo_set_output_timing(intel_sdvo, &output_dtd))
c808c4ae
WK		 1559 drm_info(&dev_priv->drm,
1560 "Setting output timings on %s failed\n",
c8d4bb54 1561 SDVO_NAME(intel_sdvo));
79e53945
JB		 1562
1563 /* Set the input timing to the screen. Assume always input 0. */
32aad86f
CW		 1564 if (!intel_sdvo_set_target_input(intel_sdvo))
1565 return;
79e53945 1566
f9fe0530 1567 if (crtc_state->has_hdmi_sink) {
97aaf910
CW		 1568 intel_sdvo_set_encode(intel_sdvo, SDVO_ENCODE_HDMI);
1569 intel_sdvo_set_colorimetry(intel_sdvo,
90f8ed85
VS		 1570 crtc_state->limited_color_range ?
1571 SDVO_COLORIMETRY_RGB220 :
97aaf910 1572 SDVO_COLORIMETRY_RGB256);
769be632 1573 intel_sdvo_set_avi_infoframe(intel_sdvo, crtc_state);
d9757193
VS		 1574 intel_sdvo_set_pixel_replication(intel_sdvo,
1575 !!(adjusted_mode->flags &
1576 DRM_MODE_FLAG_DBLCLK));
97aaf910
CW		 1577 } else
1578 intel_sdvo_set_encode(intel_sdvo, SDVO_ENCODE_DVI);
7026d4ac 1579
aa2b8807 1580 if (IS_TV(intel_sdvo_connector) &&
630d30a4 1581 !intel_sdvo_set_tv_format(intel_sdvo, conn_state))
6c9547ff 1582 return;
e2f0ba97 1583
6651819b 1584 intel_sdvo_get_dtd_from_mode(&input_dtd, adjusted_mode);
eeb47937 1585
aa2b8807 1586 if (IS_TV(intel_sdvo_connector) || IS_LVDS(intel_sdvo_connector))
e751823d 1587 input_dtd.part2.sdvo_flags = intel_sdvo->dtd_sdvo_flags;
c8d4bb54 1588 if (!intel_sdvo_set_input_timing(intel_sdvo, &input_dtd))
c808c4ae
WK		 1589 drm_info(&dev_priv->drm,
1590 "Setting input timings on %s failed\n",
c8d4bb54 1591 SDVO_NAME(intel_sdvo));
79e53945 1592
f9fe0530 1593 switch (crtc_state->pixel_multiplier) {
6c9547ff 1594 default:
b4329a01
PB		 1595 drm_WARN(&dev_priv->drm, 1,
1596 "unknown pixel multiplier specified\n");
df561f66 1597 fallthrough;
32aad86f
CW		 1598 case 1: rate = SDVO_CLOCK_RATE_MULT_1X; break;
1599 case 2: rate = SDVO_CLOCK_RATE_MULT_2X; break;
1600 case 4: rate = SDVO_CLOCK_RATE_MULT_4X; break;
79e53945 1601 }
32aad86f
CW		 1602 if (!intel_sdvo_set_clock_rate_mult(intel_sdvo, rate))
1603 return;
79e53945
JB		 1604
1605 /* Set the SDVO control regs. */
005e9537 1606 if (DISPLAY_VER(dev_priv) >= 4) {
ba68e086
PZ		 1607 /* The real mode polarity is set by the SDVO commands, using
1608 * struct intel_sdvo_dtd. */
1609 sdvox = SDVO_VSYNC_ACTIVE_HIGH | SDVO_HSYNC_ACTIVE_HIGH;
005e9537 1610 if (DISPLAY_VER(dev_priv) < 5)
6714afb1 1611 sdvox |= SDVO_BORDER_ENABLE;
e2f0ba97 1612 } else {
d2afcc44 1613 sdvox = intel_de_read(dev_priv, intel_sdvo->sdvo_reg);
c6eddd31 1614 if (intel_sdvo->base.port == PORT_B)
e2f0ba97 1615 sdvox &= SDVOB_PRESERVE_MASK;
2a5c0832 1616 else
e2f0ba97 1617 sdvox &= SDVOC_PRESERVE_MASK;
e2f0ba97
JB		 1618 sdvox |= (9 << 19) | SDVO_BORDER_ENABLE;
1619 }
3573c410 1620
b9eb89b2 1621 if (HAS_PCH_CPT(dev_priv))
eeb47937 1622 sdvox |= SDVO_PIPE_SEL_CPT(crtc->pipe);
3573c410 1623 else
eeb47937 1624 sdvox |= SDVO_PIPE_SEL(crtc->pipe);
3573c410 1625
005e9537 1626 if (DISPLAY_VER(dev_priv) >= 4) {
e2f0ba97 1627 /* done in crtc_mode_set as the dpll_md reg must be written early */
50a0bc90 1628 } else if (IS_I945G(dev_priv) || IS_I945GM(dev_priv) ||
73f67aa8 1629 IS_G33(dev_priv) || IS_PINEVIEW(dev_priv)) {
e2f0ba97 1630 /* done in crtc_mode_set as it lives inside the dpll register */
79e53945 1631 } else {
f9fe0530 1632 sdvox |= (crtc_state->pixel_multiplier - 1)
6cc5f341 1633 << SDVO_PORT_MULTIPLY_SHIFT;
79e53945
JB		 1634 }
1635
6714afb1 1636 if (input_dtd.part2.sdvo_flags & SDVO_NEED_TO_STALL &&
005e9537 1637 DISPLAY_VER(dev_priv) < 5)
12682a97 1638 sdvox |= SDVO_STALL_SELECT;
ea5b213a 1639 intel_sdvo_write_sdvox(intel_sdvo, sdvox);
79e53945
JB		 1640}
1641
4ac41f47 1642static bool intel_sdvo_connector_get_hw_state(struct intel_connector *connector)
79e53945 1643{
4ac41f47
DV		 1644 struct intel_sdvo_connector *intel_sdvo_connector =
1645 to_intel_sdvo_connector(&connector->base);
43a6d19c 1646 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
2f28c50b 1647 u16 active_outputs = 0;
4ac41f47
DV		 1648
1649 intel_sdvo_get_active_outputs(intel_sdvo, &active_outputs);
1650
9757973f 1651 return active_outputs & intel_sdvo_connector->output_flag;
4ac41f47
DV		 1652}
1653
76203467
VS		 1654bool intel_sdvo_port_enabled(struct drm_i915_private *dev_priv,
1655 i915_reg_t sdvo_reg, enum pipe *pipe)
1656{
1657 u32 val;
1658
d2afcc44 1659 val = intel_de_read(dev_priv, sdvo_reg);
76203467
VS		 1660
1661 /* asserts want to know the pipe even if the port is disabled */
1662 if (HAS_PCH_CPT(dev_priv))
1663 *pipe = (val & SDVO_PIPE_SEL_MASK_CPT) >> SDVO_PIPE_SEL_SHIFT_CPT;
1664 else if (IS_CHERRYVIEW(dev_priv))
1665 *pipe = (val & SDVO_PIPE_SEL_MASK_CHV) >> SDVO_PIPE_SEL_SHIFT_CHV;
1666 else
1667 *pipe = (val & SDVO_PIPE_SEL_MASK) >> SDVO_PIPE_SEL_SHIFT;
1668
1669 return val & SDVO_ENABLE;
1670}
1671
4ac41f47
DV		 1672static bool intel_sdvo_get_hw_state(struct intel_encoder *encoder,
1673 enum pipe *pipe)
1674{
76203467 1675 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
8aca63aa 1676 struct intel_sdvo *intel_sdvo = to_sdvo(encoder);
2f28c50b 1677 u16 active_outputs = 0;
76203467 1678 bool ret;
4ac41f47 1679
7a7d1fb7 1680 intel_sdvo_get_active_outputs(intel_sdvo, &active_outputs);
4ac41f47 1681
76203467 1682 ret = intel_sdvo_port_enabled(dev_priv, intel_sdvo->sdvo_reg, pipe);
4ac41f47 1683
76203467 1684 return ret || active_outputs;
4ac41f47
DV		 1685}
1686
045ac3b5 1687static void intel_sdvo_get_config(struct intel_encoder *encoder,
5cec258b 1688 struct intel_crtc_state *pipe_config)
045ac3b5 1689{
6c49f241 1690 struct drm_device *dev = encoder->base.dev;
fac5e23e 1691 struct drm_i915_private *dev_priv = to_i915(dev);
8aca63aa 1692 struct intel_sdvo *intel_sdvo = to_sdvo(encoder);
045ac3b5 1693 struct intel_sdvo_dtd dtd;
6c49f241 1694 int encoder_pixel_multiplier = 0;
18442d08 1695 int dotclock;
6c49f241
DV		 1696 u32 flags = 0, sdvox;
1697 u8 val;
045ac3b5
JB		 1698 bool ret;
1699
e1214b95
VS		 1700 pipe_config->output_types |= BIT(INTEL_OUTPUT_SDVO);
1701
d2afcc44 1702 sdvox = intel_de_read(dev_priv, intel_sdvo->sdvo_reg);
b5a9fa09 1703
045ac3b5
JB		 1704 ret = intel_sdvo_get_input_timing(intel_sdvo, &dtd);
1705 if (!ret) {
c16336b9
CW		 1706 /*
1707 * Some sdvo encoders are not spec compliant and don't
1708 * implement the mandatory get_timings function.
1709 */
c808c4ae 1710 drm_dbg(&dev_priv->drm, "failed to retrieve SDVO DTD\n");
bb760063
DV		 1711 pipe_config->quirks |= PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS;
1712 } else {
1713 if (dtd.part2.dtd_flags & DTD_FLAG_HSYNC_POSITIVE)
1714 flags |= DRM_MODE_FLAG_PHSYNC;
1715 else
1716 flags |= DRM_MODE_FLAG_NHSYNC;
045ac3b5 1717
bb760063
DV		 1718 if (dtd.part2.dtd_flags & DTD_FLAG_VSYNC_POSITIVE)
1719 flags |= DRM_MODE_FLAG_PVSYNC;
1720 else
1721 flags |= DRM_MODE_FLAG_NVSYNC;
045ac3b5
JB		 1722 }
1723
1326a92c 1724 pipe_config->hw.adjusted_mode.flags |= flags;
045ac3b5 1725
fdafa9e2
DV		 1726 /*
1727 * pixel multiplier readout is tricky: Only on i915g/gm it is stored in
1728 * the sdvo port register, on all other platforms it is part of the dpll
1729 * state. Since the general pipe state readout happens before the
1730 * encoder->get_config we so already have a valid pixel multplier on all
1731 * other platfroms.
1732 */
50a0bc90 1733 if (IS_I915G(dev_priv) || IS_I915GM(dev_priv)) {
6c49f241
DV		 1734 pipe_config->pixel_multiplier =
1735 ((sdvox & SDVO_PORT_MULTIPLY_MASK)
1736 >> SDVO_PORT_MULTIPLY_SHIFT) + 1;
1737 }
045ac3b5 1738
2b85886a 1739 dotclock = pipe_config->port_clock;
e3b247da 1740
2b85886a
VS		 1741 if (pipe_config->pixel_multiplier)
1742 dotclock /= pipe_config->pixel_multiplier;
18442d08 1743
1326a92c 1744 pipe_config->hw.adjusted_mode.crtc_clock = dotclock;
18442d08 1745
6c49f241 1746 /* Cross check the port pixel multiplier with the sdvo encoder state. */
53b91408
DL		 1747 if (intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_CLOCK_RATE_MULT,
1748 &val, 1)) {
1749 switch (val) {
1750 case SDVO_CLOCK_RATE_MULT_1X:
1751 encoder_pixel_multiplier = 1;
1752 break;
1753 case SDVO_CLOCK_RATE_MULT_2X:
1754 encoder_pixel_multiplier = 2;
1755 break;
1756 case SDVO_CLOCK_RATE_MULT_4X:
1757 encoder_pixel_multiplier = 4;
1758 break;
1759 }
6c49f241 1760 }
fdafa9e2 1761
b4329a01
PB		 1762 drm_WARN(dev,
1763 encoder_pixel_multiplier != pipe_config->pixel_multiplier,
1764 "SDVO pixel multiplier mismatch, port: %i, encoder: %i\n",
1765 pipe_config->pixel_multiplier, encoder_pixel_multiplier);
0d567f1e 1766
90f8ed85
VS		 1767 if (intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_COLORIMETRY,
1768 &val, 1)) {
1769 if (val == SDVO_COLORIMETRY_RGB220)
1770 pipe_config->limited_color_range = true;
1771 }
b5a9fa09 1772
dc49a56b
VS		 1773 if (intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_AUDIO_STAT,
1774 &val, 1)) {
b9c92d78 1775 if (val & SDVO_AUDIO_PRESENCE_DETECT)
dc49a56b
VS		 1776 pipe_config->has_audio = true;
1777 }
de44e256 1778
9f04003e
DV		 1779 if (intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_ENCODE,
1780 &val, 1)) {
1781 if (val == SDVO_ENCODE_HDMI)
1782 pipe_config->has_hdmi_sink = true;
1783 }
1784
0d567f1e 1785 intel_sdvo_get_avi_infoframe(intel_sdvo, pipe_config);
72715b54
VS		 1786
1787 intel_sdvo_get_eld(intel_sdvo, pipe_config);
045ac3b5
JB		 1788}
1789
dc49a56b
VS		 1790static void intel_sdvo_disable_audio(struct intel_sdvo *intel_sdvo)
1791{
1792 intel_sdvo_set_audio_state(intel_sdvo, 0);
1793}
1794
1795static void intel_sdvo_enable_audio(struct intel_sdvo *intel_sdvo,
1796 const struct intel_crtc_state *crtc_state,
1797 const struct drm_connector_state *conn_state)
1798{
8e10cd13 1799 const u8 *eld = crtc_state->eld;
dc49a56b
VS		 1800
1801 intel_sdvo_set_audio_state(intel_sdvo, 0);
1802
1803 intel_sdvo_write_infoframe(intel_sdvo, SDVO_HBUF_INDEX_ELD,
1804 SDVO_HBUF_TX_DISABLED,
1805 eld, drm_eld_size(eld));
1806
1807 intel_sdvo_set_audio_state(intel_sdvo, SDVO_AUDIO_ELD_VALID |
1808 SDVO_AUDIO_PRESENCE_DETECT);
1809}
1810
ede9771d
VS		 1811static void intel_disable_sdvo(struct intel_atomic_state *state,
1812 struct intel_encoder *encoder,
5f88a9c6
VS		 1813 const struct intel_crtc_state *old_crtc_state,
1814 const struct drm_connector_state *conn_state)
ce22c320 1815{
fac5e23e 1816 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
8aca63aa 1817 struct intel_sdvo *intel_sdvo = to_sdvo(encoder);
2225f3c6 1818 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
ce22c320
DV		 1819 u32 temp;
1820
dc49a56b
VS		 1821 if (old_crtc_state->has_audio)
1822 intel_sdvo_disable_audio(intel_sdvo);
1823
ce22c320
DV		 1824 intel_sdvo_set_active_outputs(intel_sdvo, 0);
1825 if (0)
1826 intel_sdvo_set_encoder_power_state(intel_sdvo,
1827 DRM_MODE_DPMS_OFF);
1828
d2afcc44 1829 temp = intel_de_read(dev_priv, intel_sdvo->sdvo_reg);
776ca7cf 1830
1612c8bd
VS		 1831 temp &= ~SDVO_ENABLE;
1832 intel_sdvo_write_sdvox(intel_sdvo, temp);
1833
1834 /*
1835 * HW workaround for IBX, we need to move the port
1836 * to transcoder A after disabling it to allow the
1837 * matching DP port to be enabled on transcoder A.
1838 */
1839 if (HAS_PCH_IBX(dev_priv) && crtc->pipe == PIPE_B) {
0c241d5b
VS		 1840 /*
1841 * We get CPU/PCH FIFO underruns on the other pipe when
1842 * doing the workaround. Sweep them under the rug.
1843 */
1844 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, false);
1845 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false);
1846
76203467
VS		 1847 temp &= ~SDVO_PIPE_SEL_MASK;
1848 temp |= SDVO_ENABLE | SDVO_PIPE_SEL(PIPE_A);
1612c8bd
VS		 1849 intel_sdvo_write_sdvox(intel_sdvo, temp);
1850
1851 temp &= ~SDVO_ENABLE;
1852 intel_sdvo_write_sdvox(intel_sdvo, temp);
0c241d5b 1853
0f0f74bc 1854 intel_wait_for_vblank_if_active(dev_priv, PIPE_A);
0c241d5b
VS		 1855 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, true);
1856 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true);
ce22c320
DV		 1857 }
1858}
1859
ede9771d
VS		 1860static void pch_disable_sdvo(struct intel_atomic_state *state,
1861 struct intel_encoder *encoder,
5f88a9c6
VS		 1862 const struct intel_crtc_state *old_crtc_state,
1863 const struct drm_connector_state *old_conn_state)
3c65d1d1
VS		 1864{
1865}
1866
ede9771d
VS		 1867static void pch_post_disable_sdvo(struct intel_atomic_state *state,
1868 struct intel_encoder *encoder,
5f88a9c6
VS		 1869 const struct intel_crtc_state *old_crtc_state,
1870 const struct drm_connector_state *old_conn_state)
3c65d1d1 1871{
ede9771d 1872 intel_disable_sdvo(state, encoder, old_crtc_state, old_conn_state);
3c65d1d1
VS		 1873}
1874
ede9771d
VS		 1875static void intel_enable_sdvo(struct intel_atomic_state *state,
1876 struct intel_encoder *encoder,
5f88a9c6
VS		 1877 const struct intel_crtc_state *pipe_config,
1878 const struct drm_connector_state *conn_state)
ce22c320
DV		 1879{
1880 struct drm_device *dev = encoder->base.dev;
fac5e23e 1881 struct drm_i915_private *dev_priv = to_i915(dev);
8aca63aa 1882 struct intel_sdvo *intel_sdvo = to_sdvo(encoder);
31ea7857
VS		 1883 struct intel_sdvo_connector *intel_sdvo_connector =
1884 to_intel_sdvo_connector(conn_state->connector);
f15f01a7 1885 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
79e53945 1886 u32 temp;
ce22c320
DV		 1887 bool input1, input2;
1888 int i;
d0a7b6de 1889 bool success;
ce22c320 1890
d2afcc44 1891 temp = intel_de_read(dev_priv, intel_sdvo->sdvo_reg);
3c65d1d1
VS		 1892 temp |= SDVO_ENABLE;
1893 intel_sdvo_write_sdvox(intel_sdvo, temp);
776ca7cf 1894
ce22c320 1895 for (i = 0; i < 2; i++)
7b06894b 1896 intel_crtc_wait_for_next_vblank(crtc);
ce22c320 1897
d0a7b6de 1898 success = intel_sdvo_get_trained_inputs(intel_sdvo, &input1, &input2);
c16336b9
CW		 1899 /*
1900 * Warn if the device reported failure to sync.
1901 *
ce22c320
DV		 1902 * A lot of SDVO devices fail to notify of sync, but it's
1903 * a given it the status is a success, we succeeded.
1904 */
d0a7b6de 1905 if (success && !input1) {
c808c4ae
WK		 1906 drm_dbg_kms(&dev_priv->drm,
1907 "First %s output reported failure to "
1908 "sync\n", SDVO_NAME(intel_sdvo));
ce22c320
DV		 1909 }
1910
1911 if (0)
1912 intel_sdvo_set_encoder_power_state(intel_sdvo,
1913 DRM_MODE_DPMS_ON);
31ea7857 1914 intel_sdvo_set_active_outputs(intel_sdvo, intel_sdvo_connector->output_flag);
dc49a56b
VS		 1915
1916 if (pipe_config->has_audio)
1917 intel_sdvo_enable_audio(intel_sdvo, pipe_config, conn_state);
ce22c320
DV		 1918}
1919
c19de8eb
DL		 1920static enum drm_mode_status
1921intel_sdvo_mode_valid(struct drm_connector *connector,
1922 struct drm_display_mode *mode)
79e53945 1923{
43a6d19c 1924 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(to_intel_connector(connector));
aa2b8807
VS		 1925 struct intel_sdvo_connector *intel_sdvo_connector =
1926 to_intel_sdvo_connector(connector);
24b23882 1927 int max_dotclk = to_i915(connector->dev)->max_dotclk_freq;
f2f9c8cb 1928 bool has_hdmi_sink = intel_has_hdmi_sink(intel_sdvo_connector, connector->state);
d9757193 1929 int clock = mode->clock;
79e53945 1930
e4dd27aa
VS		 1931 if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
1932 return MODE_NO_DBLESCAN;
1933
d9757193 1934 if (clock > max_dotclk)
79e53945
JB		 1935 return MODE_CLOCK_HIGH;
1936
d9757193
VS		 1937 if (mode->flags & DRM_MODE_FLAG_DBLCLK) {
1938 if (!has_hdmi_sink)
1939 return MODE_CLOCK_LOW;
1940 clock *= 2;
1941 }
1942
1943 if (intel_sdvo->pixel_clock_min > clock)
1944 return MODE_CLOCK_LOW;
1945
1946 if (intel_sdvo->pixel_clock_max < clock)
24b23882
MK		 1947 return MODE_CLOCK_HIGH;
1948
aa2b8807 1949 if (IS_LVDS(intel_sdvo_connector)) {
8a567b11 1950 enum drm_mode_status status;
12682a97 1951
8a567b11
VS		 1952 status = intel_panel_mode_valid(&intel_sdvo_connector->base, mode);
1953 if (status != MODE_OK)
1954 return status;
12682a97 1955 }
1956
79e53945
JB		 1957 return MODE_OK;
1958}
1959
ea5b213a 1960static bool intel_sdvo_get_capabilities(struct intel_sdvo *intel_sdvo, struct intel_sdvo_caps *caps)
79e53945 1961{
1a3665c8 1962 BUILD_BUG_ON(sizeof(*caps) != 8);
e957d772
CW		 1963 if (!intel_sdvo_get_value(intel_sdvo,
1964 SDVO_CMD_GET_DEVICE_CAPS,
1965 caps, sizeof(*caps)))
1966 return false;
1967
1968 DRM_DEBUG_KMS("SDVO capabilities:\n"
1969 " vendor_id: %d\n"
1970 " device_id: %d\n"
1971 " device_rev_id: %d\n"
1972 " sdvo_version_major: %d\n"
1973 " sdvo_version_minor: %d\n"
469c0962 1974 " sdvo_num_inputs: %d\n"
e957d772
CW		 1975 " smooth_scaling: %d\n"
1976 " sharp_scaling: %d\n"
1977 " up_scaling: %d\n"
1978 " down_scaling: %d\n"
1979 " stall_support: %d\n"
1980 " output_flags: %d\n",
1981 caps->vendor_id,
1982 caps->device_id,
1983 caps->device_rev_id,
1984 caps->sdvo_version_major,
1985 caps->sdvo_version_minor,
469c0962 1986 caps->sdvo_num_inputs,
e957d772
CW		 1987 caps->smooth_scaling,
1988 caps->sharp_scaling,
1989 caps->up_scaling,
1990 caps->down_scaling,
1991 caps->stall_support,
1992 caps->output_flags);
1993
1994 return true;
79e53945
JB		 1995}
1996
90f8ed85
VS		 1997static u8 intel_sdvo_get_colorimetry_cap(struct intel_sdvo *intel_sdvo)
1998{
1999 u8 cap;
2000
2001 if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_COLORIMETRY_CAP,
2002 &cap, sizeof(cap)))
2003 return SDVO_COLORIMETRY_RGB256;
2004
2005 return cap;
2006}
2007
a9dc3395 2008static u16 intel_sdvo_get_hotplug_support(struct intel_sdvo *intel_sdvo)
79e53945 2009{
50a0bc90 2010 struct drm_i915_private *dev_priv = to_i915(intel_sdvo->base.base.dev);
a9dc3395 2011 u16 hotplug;
79e53945 2012
50a0bc90 2013 if (!I915_HAS_HOTPLUG(dev_priv))
1d83d957
VS		 2014 return 0;
2015
c16336b9
CW		 2016 /*
2017 * HW Erratum: SDVO Hotplug is broken on all i945G chips, there's noise
2018 * on the line.
2019 */
50a0bc90 2020 if (IS_I945G(dev_priv) || IS_I945GM(dev_priv))
5fa7ac9c 2021 return 0;
768b107e 2022
5fa7ac9c
JN		 2023 if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_HOT_PLUG_SUPPORT,
2024 &hotplug, sizeof(hotplug)))
2025 return 0;
768b107e 2026
5fa7ac9c 2027 return hotplug;
79e53945
JB		 2028}
2029
cc68c81a 2030static void intel_sdvo_enable_hotplug(struct intel_encoder *encoder)
79e53945 2031{
8aca63aa 2032 struct intel_sdvo *intel_sdvo = to_sdvo(encoder);
79e53945 2033
5fa7ac9c 2034 intel_sdvo_write_cmd(intel_sdvo, SDVO_CMD_SET_ACTIVE_HOT_PLUG,
1b2cb026
VS		 2035 &intel_sdvo->hotplug_active, 2);
2036}
2037
3944709d
ID		 2038static enum intel_hotplug_state
2039intel_sdvo_hotplug(struct intel_encoder *encoder,
8c8919c7 2040 struct intel_connector *connector)
1b2cb026
VS		 2041{
2042 intel_sdvo_enable_hotplug(encoder);
2043
8c8919c7 2044 return intel_encoder_hotplug(encoder, connector);
79e53945
JB		 2045}
2046
27cbdc6b 2047static const struct drm_edid *
e957d772 2048intel_sdvo_get_edid(struct drm_connector *connector)
f899fc64 2049{
c0ff6c6e
VS		 2050 struct i2c_adapter *ddc = connector->ddc;
2051
2052 if (!ddc)
2053 return NULL;
2054
2055 return drm_edid_read_ddc(connector, ddc);
f899fc64
CW		 2056}
2057
ff482d83 2058/* Mac mini hack -- use the same DDC as the analog connector */
27cbdc6b 2059static const struct drm_edid *
ff482d83
CW		 2060intel_sdvo_get_analog_edid(struct drm_connector *connector)
2061{
27cbdc6b 2062 struct drm_i915_private *i915 = to_i915(connector->dev);
c0ff6c6e 2063 struct i2c_adapter *ddc;
27cbdc6b 2064
c0ff6c6e
VS		 2065 ddc = intel_gmbus_get_adapter(i915, i915->display.vbt.crt_ddc_pin);
2066 if (!ddc)
2067 return NULL;
ff482d83 2068
c0ff6c6e 2069 return drm_edid_read_ddc(connector, ddc);
ff482d83
CW		 2070}
2071
c43b5634 2072static enum drm_connector_status
8bf38485 2073intel_sdvo_tmds_sink_detect(struct drm_connector *connector)
9dff6af8 2074{
9d1a903d 2075 enum drm_connector_status status;
27cbdc6b 2076 const struct drm_edid *drm_edid;
9dff6af8 2077
27cbdc6b 2078 drm_edid = intel_sdvo_get_edid(connector);
57cdaf90 2079
9d1a903d
CW		 2080 /*
2081 * When there is no edid and no monitor is connected with VGA
2082 * port, try to use the CRT ddc to read the EDID for DVI-connector.
57cdaf90 2083 */
27cbdc6b
JN		 2084 if (!drm_edid)
2085 drm_edid = intel_sdvo_get_analog_edid(connector);
149c36a3 2086
2f551c84 2087 status = connector_status_unknown;
27cbdc6b 2088 if (drm_edid) {
149c36a3 2089 /* DDC bus is shared, match EDID to connector type */
e1039cde 2090 if (drm_edid_is_digital(drm_edid))
9d1a903d 2091 status = connector_status_connected;
dd9f377a 2092 else
13946743 2093 status = connector_status_disconnected;
27cbdc6b 2094 drm_edid_free(drm_edid);
9d1a903d 2095 }
7f36e7ed 2096
2b8d33f7 2097 return status;
9dff6af8
ML		 2098}
2099
52220085
CW		 2100static bool
2101intel_sdvo_connector_matches_edid(struct intel_sdvo_connector *sdvo,
27cbdc6b 2102 const struct drm_edid *drm_edid)
52220085 2103{
e1039cde 2104 bool monitor_is_digital = drm_edid_is_digital(drm_edid);
52220085
CW		 2105 bool connector_is_digital = !!IS_DIGITAL(sdvo);
2106
2107 DRM_DEBUG_KMS("connector_is_digital? %d, monitor_is_digital? %d\n",
2108 connector_is_digital, monitor_is_digital);
2109 return connector_is_digital == monitor_is_digital;
2110}
2111
7b334fcb 2112static enum drm_connector_status
930a9e28 2113intel_sdvo_detect(struct drm_connector *connector, bool force)
79e53945 2114{
b81dddb9 2115 struct drm_i915_private *i915 = to_i915(connector->dev);
43a6d19c 2116 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(to_intel_connector(connector));
615fb93f 2117 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
14571b4c 2118 enum drm_connector_status ret;
b81dddb9 2119 u16 response;
79e53945 2120
164c8598 2121 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
c23cc417 2122 connector->base.id, connector->name);
164c8598 2123
fe63ea7c 2124 if (!intel_display_device_enabled(i915))
b81dddb9
VS		 2125 return connector_status_disconnected;
2126
1d6f7b19
VS		 2127 if (!intel_sdvo_set_target_output(intel_sdvo,
2128 intel_sdvo_connector->output_flag))
2129 return connector_status_unknown;
2130
fc37381c
CW		 2131 if (!intel_sdvo_get_value(intel_sdvo,
2132 SDVO_CMD_GET_ATTACHED_DISPLAYS,
2133 &response, 2))
32aad86f 2134 return connector_status_unknown;
79e53945 2135
e957d772
CW		 2136 DRM_DEBUG_KMS("SDVO response %d %d [%x]\n",
2137 response & 0xff, response >> 8,
2138 intel_sdvo_connector->output_flag);
e2f0ba97 2139
fb7a46f3 2140 if (response == 0)
79e53945 2141 return connector_status_disconnected;
fb7a46f3 2142
615fb93f 2143 if ((intel_sdvo_connector->output_flag & response) == 0)
14571b4c 2144 ret = connector_status_disconnected;
13946743 2145 else if (IS_TMDS(intel_sdvo_connector))
8bf38485 2146 ret = intel_sdvo_tmds_sink_detect(connector);
13946743 2147 else {
27cbdc6b 2148 const struct drm_edid *drm_edid;
13946743
CW		 2149
2150 /* if we have an edid check it matches the connection */
27cbdc6b
JN		 2151 drm_edid = intel_sdvo_get_edid(connector);
2152 if (!drm_edid)
2153 drm_edid = intel_sdvo_get_analog_edid(connector);
2154 if (drm_edid) {
52220085 2155 if (intel_sdvo_connector_matches_edid(intel_sdvo_connector,
27cbdc6b 2156 drm_edid))
13946743 2157 ret = connector_status_connected;
52220085
CW		 2158 else
2159 ret = connector_status_disconnected;
2160
27cbdc6b
JN		 2161 drm_edid_free(drm_edid);
2162 } else {
13946743 2163 ret = connector_status_connected;
27cbdc6b 2164 }
13946743 2165 }
14571b4c 2166
14571b4c 2167 return ret;
79e53945
JB		 2168}
2169
7407ec6e 2170static int intel_sdvo_get_ddc_modes(struct drm_connector *connector)
79e53945 2171{
7407ec6e 2172 int num_modes = 0;
27cbdc6b 2173 const struct drm_edid *drm_edid;
79e53945 2174
46a3f4a3 2175 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
c23cc417 2176 connector->base.id, connector->name);
46a3f4a3 2177
79e53945 2178 /* set the bus switch and get the modes */
27cbdc6b 2179 drm_edid = intel_sdvo_get_edid(connector);
79e53945 2180
57cdaf90
KP		 2181 /*
2182 * Mac mini hack. On this device, the DVI-I connector shares one DDC
2183 * link between analog and digital outputs. So, if the regular SDVO
2184 * DDC fails, check to see if the analog output is disconnected, in
2185 * which case we'll look there for the digital DDC data.
e2f0ba97 2186 */
27cbdc6b
JN		 2187 if (!drm_edid)
2188 drm_edid = intel_sdvo_get_analog_edid(connector);
f899fc64 2189
27cbdc6b 2190 if (!drm_edid)
7407ec6e 2191 return 0;
13946743 2192
7407ec6e 2193 if (intel_sdvo_connector_matches_edid(to_intel_sdvo_connector(connector),
27cbdc6b
JN		 2194 drm_edid))
2195 num_modes += intel_connector_update_modes(connector, drm_edid);
7407ec6e 2196
27cbdc6b 2197 drm_edid_free(drm_edid);
7407ec6e
VS		 2198
2199 return num_modes;
e2f0ba97
JB		 2200}
2201
2202/*
2203 * Set of SDVO TV modes.
2204 * Note! This is in reply order (see loop in get_tv_modes).
2205 * XXX: all 60Hz refresh?
2206 */
b1f559ec 2207static const struct drm_display_mode sdvo_tv_modes[] = {
7026d4ac
ZW		 2208 { DRM_MODE("320x200", DRM_MODE_TYPE_DRIVER, 5815, 320, 321, 384,
2209 416, 0, 200, 201, 232, 233, 0,
e2f0ba97 2210 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 2211 { DRM_MODE("320x240", DRM_MODE_TYPE_DRIVER, 6814, 320, 321, 384,
2212 416, 0, 240, 241, 272, 273, 0,
e2f0ba97 2213 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 2214 { DRM_MODE("400x300", DRM_MODE_TYPE_DRIVER, 9910, 400, 401, 464,
2215 496, 0, 300, 301, 332, 333, 0,
e2f0ba97 2216 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 2217 { DRM_MODE("640x350", DRM_MODE_TYPE_DRIVER, 16913, 640, 641, 704,
2218 736, 0, 350, 351, 382, 383, 0,
e2f0ba97 2219 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 2220 { DRM_MODE("640x400", DRM_MODE_TYPE_DRIVER, 19121, 640, 641, 704,
2221 736, 0, 400, 401, 432, 433, 0,
e2f0ba97 2222 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 2223 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 22654, 640, 641, 704,
2224 736, 0, 480, 481, 512, 513, 0,
e2f0ba97 2225 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 2226 { DRM_MODE("704x480", DRM_MODE_TYPE_DRIVER, 24624, 704, 705, 768,
2227 800, 0, 480, 481, 512, 513, 0,
e2f0ba97 2228 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 2229 { DRM_MODE("704x576", DRM_MODE_TYPE_DRIVER, 29232, 704, 705, 768,
2230 800, 0, 576, 577, 608, 609, 0,
e2f0ba97 2231 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 2232 { DRM_MODE("720x350", DRM_MODE_TYPE_DRIVER, 18751, 720, 721, 784,
2233 816, 0, 350, 351, 382, 383, 0,
e2f0ba97 2234 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 2235 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 21199, 720, 721, 784,
2236 816, 0, 400, 401, 432, 433, 0,
e2f0ba97 2237 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 2238 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 25116, 720, 721, 784,
2239 816, 0, 480, 481, 512, 513, 0,
e2f0ba97 2240 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 2241 { DRM_MODE("720x540", DRM_MODE_TYPE_DRIVER, 28054, 720, 721, 784,
2242 816, 0, 540, 541, 572, 573, 0,
e2f0ba97 2243 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 2244 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 29816, 720, 721, 784,
2245 816, 0, 576, 577, 608, 609, 0,
e2f0ba97 2246 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 2247 { DRM_MODE("768x576", DRM_MODE_TYPE_DRIVER, 31570, 768, 769, 832,
2248 864, 0, 576, 577, 608, 609, 0,
e2f0ba97 2249 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 2250 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 34030, 800, 801, 864,
2251 896, 0, 600, 601, 632, 633, 0,
e2f0ba97 2252 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 2253 { DRM_MODE("832x624", DRM_MODE_TYPE_DRIVER, 36581, 832, 833, 896,
2254 928, 0, 624, 625, 656, 657, 0,
e2f0ba97 2255 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 2256 { DRM_MODE("920x766", DRM_MODE_TYPE_DRIVER, 48707, 920, 921, 984,
2257 1016, 0, 766, 767, 798, 799, 0,
e2f0ba97 2258 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 2259 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 53827, 1024, 1025, 1088,
2260 1120, 0, 768, 769, 800, 801, 0,
e2f0ba97 2261 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 2262 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 87265, 1280, 1281, 1344,
2263 1376, 0, 1024, 1025, 1056, 1057, 0,
e2f0ba97
JB		 2264 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
2265};
2266
7407ec6e 2267static int intel_sdvo_get_tv_modes(struct drm_connector *connector)
e2f0ba97 2268{
43a6d19c 2269 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(to_intel_connector(connector));
31ea7857
VS		 2270 struct intel_sdvo_connector *intel_sdvo_connector =
2271 to_intel_sdvo_connector(connector);
630d30a4 2272 const struct drm_connector_state *conn_state = connector->state;
7026d4ac 2273 struct intel_sdvo_sdtv_resolution_request tv_res;
a9dc3395 2274 u32 reply = 0, format_map = 0;
7407ec6e 2275 int num_modes = 0;
ce6feabd 2276 int i;
e2f0ba97 2277
46a3f4a3 2278 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
c23cc417 2279 connector->base.id, connector->name);
46a3f4a3 2280
c16336b9
CW		 2281 /*
2282 * Read the list of supported input resolutions for the selected TV
e2f0ba97
JB		 2283 * format.
2284 */
630d30a4 2285 format_map = 1 << conn_state->tv.mode;
ce6feabd 2286 memcpy(&tv_res, &format_map,
32aad86f 2287 min(sizeof(format_map), sizeof(struct intel_sdvo_sdtv_resolution_request)));
ce6feabd 2288
31ea7857 2289 if (!intel_sdvo_set_target_output(intel_sdvo, intel_sdvo_connector->output_flag))
7407ec6e 2290 return 0;
ce6feabd 2291
32aad86f 2292 BUILD_BUG_ON(sizeof(tv_res) != 3);
e957d772
CW		 2293 if (!intel_sdvo_write_cmd(intel_sdvo,
2294 SDVO_CMD_GET_SDTV_RESOLUTION_SUPPORT,
32aad86f 2295 &tv_res, sizeof(tv_res)))
7407ec6e 2296 return 0;
32aad86f 2297 if (!intel_sdvo_read_response(intel_sdvo, &reply, 3))
7407ec6e 2298 return 0;
e2f0ba97 2299
7407ec6e 2300 for (i = 0; i < ARRAY_SIZE(sdvo_tv_modes); i++) {
7026d4ac
ZW		 2301 if (reply & (1 << i)) {
2302 struct drm_display_mode *nmode;
2303 nmode = drm_mode_duplicate(connector->dev,
32aad86f 2304 &sdvo_tv_modes[i]);
7407ec6e 2305 if (nmode) {
7026d4ac 2306 drm_mode_probed_add(connector, nmode);
7407ec6e
VS		 2307 num_modes++;
2308 }
7026d4ac 2309 }
7407ec6e
VS		 2310 }
2311
2312 return num_modes;
e2f0ba97
JB		 2313}
2314
7407ec6e 2315static int intel_sdvo_get_lvds_modes(struct drm_connector *connector)
7086c87f 2316{
fac5e23e 2317 struct drm_i915_private *dev_priv = to_i915(connector->dev);
7086c87f 2318
c808c4ae
WK		 2319 drm_dbg_kms(&dev_priv->drm, "[CONNECTOR:%d:%s]\n",
2320 connector->base.id, connector->name);
46a3f4a3 2321
5e52622e 2322 return intel_panel_get_modes(to_intel_connector(connector));
7086c87f
ML		 2323}
2324
e2f0ba97
JB		 2325static int intel_sdvo_get_modes(struct drm_connector *connector)
2326{
615fb93f 2327 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
e2f0ba97 2328
615fb93f 2329 if (IS_TV(intel_sdvo_connector))
7407ec6e 2330 return intel_sdvo_get_tv_modes(connector);
615fb93f 2331 else if (IS_LVDS(intel_sdvo_connector))
7407ec6e 2332 return intel_sdvo_get_lvds_modes(connector);
e2f0ba97 2333 else
7407ec6e 2334 return intel_sdvo_get_ddc_modes(connector);
79e53945
JB		 2335}
2336
ce6feabd 2337static int
630d30a4
ML		 2338intel_sdvo_connector_atomic_get_property(struct drm_connector *connector,
2339 const struct drm_connector_state *state,
2340 struct drm_property *property,
a9dc3395 2341 u64 *val)
ce6feabd 2342{
615fb93f 2343 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
630d30a4 2344 const struct intel_sdvo_connector_state *sdvo_state = to_intel_sdvo_connector_state((void *)state);
c5521706
CW		 2345
2346 if (property == intel_sdvo_connector->tv_format) {
630d30a4 2347 int i;
b9219c5e 2348
630d30a4
ML		 2349 for (i = 0; i < intel_sdvo_connector->format_supported_num; i++)
2350 if (state->tv.mode == intel_sdvo_connector->tv_format_supported[i]) {
2351 *val = i;
b9219c5e 2352
32aad86f 2353 return 0;
630d30a4 2354 }
b9219c5e 2355
cb7cbb4b 2356 drm_WARN_ON(connector->dev, 1);
630d30a4
ML		 2357 *val = 0;
2358 } else if (property == intel_sdvo_connector->top ||
2359 property == intel_sdvo_connector->bottom)
2360 *val = intel_sdvo_connector->max_vscan - sdvo_state->tv.overscan_v;
2361 else if (property == intel_sdvo_connector->left ||
2362 property == intel_sdvo_connector->right)
2363 *val = intel_sdvo_connector->max_hscan - sdvo_state->tv.overscan_h;
2364 else if (property == intel_sdvo_connector->hpos)
2365 *val = sdvo_state->tv.hpos;
2366 else if (property == intel_sdvo_connector->vpos)
2367 *val = sdvo_state->tv.vpos;
2368 else if (property == intel_sdvo_connector->saturation)
2369 *val = state->tv.saturation;
2370 else if (property == intel_sdvo_connector->contrast)
2371 *val = state->tv.contrast;
2372 else if (property == intel_sdvo_connector->hue)
2373 *val = state->tv.hue;
2374 else if (property == intel_sdvo_connector->brightness)
2375 *val = state->tv.brightness;
2376 else if (property == intel_sdvo_connector->sharpness)
2377 *val = sdvo_state->tv.sharpness;
2378 else if (property == intel_sdvo_connector->flicker_filter)
2379 *val = sdvo_state->tv.flicker_filter;
2380 else if (property == intel_sdvo_connector->flicker_filter_2d)
2381 *val = sdvo_state->tv.flicker_filter_2d;
2382 else if (property == intel_sdvo_connector->flicker_filter_adaptive)
2383 *val = sdvo_state->tv.flicker_filter_adaptive;
2384 else if (property == intel_sdvo_connector->tv_chroma_filter)
2385 *val = sdvo_state->tv.chroma_filter;
2386 else if (property == intel_sdvo_connector->tv_luma_filter)
2387 *val = sdvo_state->tv.luma_filter;
2388 else if (property == intel_sdvo_connector->dot_crawl)
2389 *val = sdvo_state->tv.dot_crawl;
2390 else
2391 return intel_digital_connector_atomic_get_property(connector, state, property, val);
32aad86f 2392
630d30a4
ML		 2393 return 0;
2394}
b9219c5e 2395
630d30a4
ML		 2396static int
2397intel_sdvo_connector_atomic_set_property(struct drm_connector *connector,
2398 struct drm_connector_state *state,
2399 struct drm_property *property,
a9dc3395 2400 u64 val)
630d30a4
ML		 2401{
2402 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
2403 struct intel_sdvo_connector_state *sdvo_state = to_intel_sdvo_connector_state(state);
b9219c5e 2404
630d30a4
ML		 2405 if (property == intel_sdvo_connector->tv_format) {
2406 state->tv.mode = intel_sdvo_connector->tv_format_supported[val];
b9219c5e 2407
630d30a4
ML		 2408 if (state->crtc) {
2409 struct drm_crtc_state *crtc_state =
2410 drm_atomic_get_new_crtc_state(state->state, state->crtc);
b9219c5e 2411
630d30a4
ML		 2412 crtc_state->connectors_changed = true;
2413 }
2414 } else if (property == intel_sdvo_connector->top ||
2415 property == intel_sdvo_connector->bottom)
2416 /* Cannot set these independent from each other */
2417 sdvo_state->tv.overscan_v = intel_sdvo_connector->max_vscan - val;
2418 else if (property == intel_sdvo_connector->left ||
2419 property == intel_sdvo_connector->right)
2420 /* Cannot set these independent from each other */
2421 sdvo_state->tv.overscan_h = intel_sdvo_connector->max_hscan - val;
2422 else if (property == intel_sdvo_connector->hpos)
2423 sdvo_state->tv.hpos = val;
2424 else if (property == intel_sdvo_connector->vpos)
2425 sdvo_state->tv.vpos = val;
2426 else if (property == intel_sdvo_connector->saturation)
2427 state->tv.saturation = val;
2428 else if (property == intel_sdvo_connector->contrast)
2429 state->tv.contrast = val;
2430 else if (property == intel_sdvo_connector->hue)
2431 state->tv.hue = val;
2432 else if (property == intel_sdvo_connector->brightness)
2433 state->tv.brightness = val;
2434 else if (property == intel_sdvo_connector->sharpness)
2435 sdvo_state->tv.sharpness = val;
2436 else if (property == intel_sdvo_connector->flicker_filter)
2437 sdvo_state->tv.flicker_filter = val;
2438 else if (property == intel_sdvo_connector->flicker_filter_2d)
2439 sdvo_state->tv.flicker_filter_2d = val;
2440 else if (property == intel_sdvo_connector->flicker_filter_adaptive)
2441 sdvo_state->tv.flicker_filter_adaptive = val;
2442 else if (property == intel_sdvo_connector->tv_chroma_filter)
2443 sdvo_state->tv.chroma_filter = val;
2444 else if (property == intel_sdvo_connector->tv_luma_filter)
2445 sdvo_state->tv.luma_filter = val;
2446 else if (property == intel_sdvo_connector->dot_crawl)
2447 sdvo_state->tv.dot_crawl = val;
2448 else
2449 return intel_digital_connector_atomic_set_property(connector, state, property, val);
c5521706 2450
32aad86f 2451 return 0;
ce6feabd
ZY		 2452}
2453
630d30a4
ML		 2454static struct drm_connector_state *
2455intel_sdvo_connector_duplicate_state(struct drm_connector *connector)
2456{
2457 struct intel_sdvo_connector_state *state;
2458
2459 state = kmemdup(connector->state, sizeof(*state), GFP_KERNEL);
2460 if (!state)
2461 return NULL;
2462
2463 __drm_atomic_helper_connector_duplicate_state(connector, &state->base.base);
2464 return &state->base.base;
2465}
2466
79e53945 2467static const struct drm_connector_funcs intel_sdvo_connector_funcs = {
79e53945
JB		 2468 .detect = intel_sdvo_detect,
2469 .fill_modes = drm_helper_probe_single_connector_modes,
630d30a4
ML		 2470 .atomic_get_property = intel_sdvo_connector_atomic_get_property,
2471 .atomic_set_property = intel_sdvo_connector_atomic_set_property,
5bb306b1
VS		 2472 .late_register = intel_connector_register,
2473 .early_unregister = intel_connector_unregister,
d4b26e4f 2474 .destroy = intel_connector_destroy,
c6f95f27 2475 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
630d30a4 2476 .atomic_duplicate_state = intel_sdvo_connector_duplicate_state,
79e53945
JB		 2477};
2478
630d30a4 2479static int intel_sdvo_atomic_check(struct drm_connector *conn,
6f3b6278 2480 struct drm_atomic_state *state)
630d30a4 2481{
6f3b6278
SP		 2482 struct drm_connector_state *new_conn_state =
2483 drm_atomic_get_new_connector_state(state, conn);
630d30a4
ML		 2484 struct drm_connector_state *old_conn_state =
2485 drm_atomic_get_old_connector_state(state, conn);
2486 struct intel_sdvo_connector_state *old_state =
2487 to_intel_sdvo_connector_state(old_conn_state);
2488 struct intel_sdvo_connector_state *new_state =
2489 to_intel_sdvo_connector_state(new_conn_state);
2490
2491 if (new_conn_state->crtc &&
2492 (memcmp(&old_state->tv, &new_state->tv, sizeof(old_state->tv)) ||
2493 memcmp(&old_conn_state->tv, &new_conn_state->tv, sizeof(old_conn_state->tv)))) {
2494 struct drm_crtc_state *crtc_state =
6f3b6278 2495 drm_atomic_get_new_crtc_state(state,
630d30a4
ML		 2496 new_conn_state->crtc);
2497
2498 crtc_state->connectors_changed = true;
2499 }
2500
6f3b6278 2501 return intel_digital_connector_atomic_check(conn, state);
630d30a4
ML		 2502}
2503
79e53945
JB		 2504static const struct drm_connector_helper_funcs intel_sdvo_connector_helper_funcs = {
2505 .get_modes = intel_sdvo_get_modes,
2506 .mode_valid = intel_sdvo_mode_valid,
630d30a4 2507 .atomic_check = intel_sdvo_atomic_check,
79e53945
JB		 2508};
2509
c0ff6c6e 2510static void intel_sdvo_encoder_destroy(struct drm_encoder *_encoder)
79e53945 2511{
c0ff6c6e
VS		 2512 struct intel_encoder *encoder = to_intel_encoder(_encoder);
2513 struct intel_sdvo *sdvo = to_sdvo(encoder);
2514 int i;
d2a82a6f 2515
c0ff6c6e
VS		 2516 for (i = 0; i < ARRAY_SIZE(sdvo->ddc); i++) {
2517 if (sdvo->ddc[i].ddc_bus)
2518 i2c_del_adapter(&sdvo->ddc[i].ddc);
2519 }
2520
2521 drm_encoder_cleanup(&encoder->base);
2522 kfree(sdvo);
2523};
79e53945
JB		 2524
2525static const struct drm_encoder_funcs intel_sdvo_enc_funcs = {
c0ff6c6e 2526 .destroy = intel_sdvo_encoder_destroy,
79e53945
JB		 2527};
2528
c0ff6c6e
VS		 2529static int
2530intel_sdvo_guess_ddc_bus(struct intel_sdvo *sdvo,
2531 struct intel_sdvo_connector *connector)
b66d8424 2532{
a9dc3395 2533 u16 mask = 0;
c0ff6c6e 2534 int num_bits;
b66d8424 2535
c16336b9
CW		 2536 /*
2537 * Make a mask of outputs less than or equal to our own priority in the
b66d8424
CW		 2538 * list.
2539 */
c0ff6c6e 2540 switch (connector->output_flag) {
b66d8424
CW		 2541 case SDVO_OUTPUT_LVDS1:
2542 mask |= SDVO_OUTPUT_LVDS1;
df561f66 2543 fallthrough;
b66d8424
CW		 2544 case SDVO_OUTPUT_LVDS0:
2545 mask |= SDVO_OUTPUT_LVDS0;
df561f66 2546 fallthrough;
b66d8424
CW		 2547 case SDVO_OUTPUT_TMDS1:
2548 mask |= SDVO_OUTPUT_TMDS1;
df561f66 2549 fallthrough;
b66d8424
CW		 2550 case SDVO_OUTPUT_TMDS0:
2551 mask |= SDVO_OUTPUT_TMDS0;
df561f66 2552 fallthrough;
b66d8424
CW		 2553 case SDVO_OUTPUT_RGB1:
2554 mask |= SDVO_OUTPUT_RGB1;
df561f66 2555 fallthrough;
b66d8424
CW		 2556 case SDVO_OUTPUT_RGB0:
2557 mask |= SDVO_OUTPUT_RGB0;
2558 break;
2559 }
2560
2561 /* Count bits to find what number we are in the priority list. */
2562 mask &= sdvo->caps.output_flags;
2563 num_bits = hweight16(mask);
2564 /* If more than 3 outputs, default to DDC bus 3 for now. */
2565 if (num_bits > 3)
2566 num_bits = 3;
2567
2568 /* Corresponds to SDVO_CONTROL_BUS_DDCx */
c0ff6c6e 2569 return num_bits;
b66d8424 2570}
79e53945 2571
c16336b9 2572/*
e2f0ba97
JB		 2573 * Choose the appropriate DDC bus for control bus switch command for this
2574 * SDVO output based on the controlled output.
2575 *
2576 * DDC bus number assignment is in a priority order of RGB outputs, then TMDS
2577 * outputs, then LVDS outputs.
2578 */
c0ff6c6e
VS		 2579static struct intel_sdvo_ddc *
2580intel_sdvo_select_ddc_bus(struct intel_sdvo *sdvo,
2581 struct intel_sdvo_connector *connector)
e2f0ba97 2582{
0eb8252a 2583 struct drm_i915_private *dev_priv = to_i915(sdvo->base.base.dev);
32c32155 2584 const struct sdvo_device_mapping *mapping;
c0ff6c6e 2585 int ddc_bus;
e2f0ba97 2586
c6eddd31 2587 if (sdvo->base.port == PORT_B)
a434689c 2588 mapping = &dev_priv->display.vbt.sdvo_mappings[0];
b1083333 2589 else
a434689c 2590 mapping = &dev_priv->display.vbt.sdvo_mappings[1];
e2f0ba97 2591
b66d8424 2592 if (mapping->initialized)
c0ff6c6e 2593 ddc_bus = (mapping->ddc_pin & 0xf0) >> 4;
b66d8424 2594 else
c0ff6c6e
VS		 2595 ddc_bus = intel_sdvo_guess_ddc_bus(sdvo, connector);
2596
2597 if (ddc_bus < 1 || ddc_bus > 3)
2598 return NULL;
2599
2600 return &sdvo->ddc[ddc_bus - 1];
e2f0ba97
JB		 2601}
2602
e957d772 2603static void
0eb8252a 2604intel_sdvo_select_i2c_bus(struct intel_sdvo *sdvo)
e957d772 2605{
0eb8252a 2606 struct drm_i915_private *dev_priv = to_i915(sdvo->base.base.dev);
32c32155 2607 const struct sdvo_device_mapping *mapping;
46eb3036 2608 u8 pin;
e957d772 2609
c6eddd31 2610 if (sdvo->base.port == PORT_B)
a434689c 2611 mapping = &dev_priv->display.vbt.sdvo_mappings[0];
e957d772 2612 else
a434689c 2613 mapping = &dev_priv->display.vbt.sdvo_mappings[1];
e957d772 2614
88ac7939
JN		 2615 if (mapping->initialized &&
2616 intel_gmbus_is_valid_pin(dev_priv, mapping->i2c_pin))
e957d772 2617 pin = mapping->i2c_pin;
6cb1612a 2618 else
988c7015 2619 pin = GMBUS_PIN_DPB;
e957d772 2620
9c7e9db1
VS		 2621 drm_dbg_kms(&dev_priv->drm, "[ENCODER:%d:%s] I2C pin %d, slave addr 0x%x\n",
2622 sdvo->base.base.base.id, sdvo->base.base.name,
2623 pin, sdvo->slave_addr);
2624
6cb1612a
JN		 2625 sdvo->i2c = intel_gmbus_get_adapter(dev_priv, pin);
2626
c16336b9
CW		 2627 /*
2628 * With gmbus we should be able to drive sdvo i2c at 2MHz, but somehow
6cb1612a 2629 * our code totally fails once we start using gmbus. Hence fall back to
c16336b9
CW		 2630 * bit banging for now.
2631 */
6cb1612a 2632 intel_gmbus_force_bit(sdvo->i2c, true);
e957d772
CW		 2633}
2634
fbfcc4f3
JN		 2635/* undo any changes intel_sdvo_select_i2c_bus() did to sdvo->i2c */
2636static void
2637intel_sdvo_unselect_i2c_bus(struct intel_sdvo *sdvo)
2638{
2639 intel_gmbus_force_bit(sdvo->i2c, false);
e957d772
CW		 2640}
2641
e2f0ba97 2642static bool
739f8dbc 2643intel_sdvo_is_hdmi_connector(struct intel_sdvo *intel_sdvo)
e2f0ba97 2644{
97aaf910 2645 return intel_sdvo_check_supp_encode(intel_sdvo);
e2f0ba97
JB		 2646}
2647
714605e4 2648static u8
0eb8252a 2649intel_sdvo_get_slave_addr(struct intel_sdvo *sdvo)
714605e4 2650{
0eb8252a 2651 struct drm_i915_private *dev_priv = to_i915(sdvo->base.base.dev);
32c32155 2652 const struct sdvo_device_mapping *my_mapping, *other_mapping;
714605e4 2653
c6eddd31 2654 if (sdvo->base.port == PORT_B) {
a434689c
JN		 2655 my_mapping = &dev_priv->display.vbt.sdvo_mappings[0];
2656 other_mapping = &dev_priv->display.vbt.sdvo_mappings[1];
714605e4 2657 } else {
a434689c
JN		 2658 my_mapping = &dev_priv->display.vbt.sdvo_mappings[1];
2659 other_mapping = &dev_priv->display.vbt.sdvo_mappings[0];
714605e4 2660 }
2661
2662 /* If the BIOS described our SDVO device, take advantage of it. */
2663 if (my_mapping->slave_addr)
2664 return my_mapping->slave_addr;
2665
c16336b9
CW		 2666 /*
2667 * If the BIOS only described a different SDVO device, use the
714605e4 2668 * address that it isn't using.
2669 */
2670 if (other_mapping->slave_addr) {
2671 if (other_mapping->slave_addr == 0x70)
2672 return 0x72;
2673 else
2674 return 0x70;
2675 }
2676
c16336b9
CW		 2677 /*
2678 * No SDVO device info is found for another DVO port,
714605e4 2679 * so use mapping assumption we had before BIOS parsing.
2680 */
c6eddd31 2681 if (sdvo->base.port == PORT_B)
714605e4 2682 return 0x70;
2683 else
2684 return 0x72;
2685}
2686
c0ff6c6e
VS		 2687static int
2688intel_sdvo_init_ddc_proxy(struct intel_sdvo_ddc *ddc,
2689 struct intel_sdvo *sdvo, int bit);
2690
c393454d 2691static int
df0e9248
CW		 2692intel_sdvo_connector_init(struct intel_sdvo_connector *connector,
2693 struct intel_sdvo *encoder)
14571b4c 2694{
c0ff6c6e
VS		 2695 struct drm_i915_private *i915 = to_i915(encoder->base.base.dev);
2696 struct intel_sdvo_ddc *ddc = NULL;
c393454d
ID		 2697 int ret;
2698
c0ff6c6e
VS		 2699 if (HAS_DDC(connector))
2700 ddc = intel_sdvo_select_ddc_bus(encoder, connector);
2701
2702 ret = drm_connector_init_with_ddc(encoder->base.base.dev,
2703 &connector->base.base,
2704 &intel_sdvo_connector_funcs,
2705 connector->base.base.connector_type,
2706 ddc ? &ddc->ddc : NULL);
c393454d
ID		 2707 if (ret < 0)
2708 return ret;
6070a4a9 2709
c0ff6c6e 2710 drm_connector_helper_add(&connector->base.base,
df0e9248 2711 &intel_sdvo_connector_helper_funcs);
14571b4c 2712
df0e9248 2713 connector->base.base.display_info.subpixel_order = SubPixelHorizontalRGB;
8648c604 2714 connector->base.base.interlace_allowed = true;
4ac41f47 2715 connector->base.get_hw_state = intel_sdvo_connector_get_hw_state;
14571b4c 2716
df0e9248 2717 intel_connector_attach_encoder(&connector->base, &encoder->base);
c393454d 2718
c0ff6c6e
VS		 2719 if (ddc)
2720 drm_dbg_kms(&i915->drm, "[CONNECTOR:%d:%s] using %s\n",
2721 connector->base.base.base.id, connector->base.base.name,
2722 ddc->ddc.name);
2723
c393454d 2724 return 0;
14571b4c 2725}
6070a4a9 2726
7f36e7ed 2727static void
55bc60db
VS		 2728intel_sdvo_add_hdmi_properties(struct intel_sdvo *intel_sdvo,
2729 struct intel_sdvo_connector *connector)
7f36e7ed 2730{
3f43c48d 2731 intel_attach_force_audio_property(&connector->base.base);
90f8ed85 2732 if (intel_sdvo->colorimetry_cap & SDVO_COLORIMETRY_RGB220)
e953fd7b 2733 intel_attach_broadcast_rgb_property(&connector->base.base);
7949dd47 2734 intel_attach_aspect_ratio_property(&connector->base.base);
7f36e7ed
CW		 2735}
2736
08d9bc92
ACO		 2737static struct intel_sdvo_connector *intel_sdvo_connector_alloc(void)
2738{
2739 struct intel_sdvo_connector *sdvo_connector;
630d30a4 2740 struct intel_sdvo_connector_state *conn_state;
08d9bc92
ACO		 2741
2742 sdvo_connector = kzalloc(sizeof(*sdvo_connector), GFP_KERNEL);
2743 if (!sdvo_connector)
2744 return NULL;
2745
630d30a4
ML		 2746 conn_state = kzalloc(sizeof(*conn_state), GFP_KERNEL);
2747 if (!conn_state) {
08d9bc92
ACO		 2748 kfree(sdvo_connector);
2749 return NULL;
2750 }
2751
630d30a4
ML		 2752 __drm_atomic_helper_connector_reset(&sdvo_connector->base.base,
2753 &conn_state->base.base);
2754
26e60294 2755 intel_panel_init_alloc(&sdvo_connector->base);
345b7c4b 2756
08d9bc92
ACO		 2757 return sdvo_connector;
2758}
2759
fb7a46f3 2760static bool
739f8dbc 2761intel_sdvo_dvi_init(struct intel_sdvo *intel_sdvo, u16 type)
fb7a46f3 2762{
4ef69c7a 2763 struct drm_encoder *encoder = &intel_sdvo->base.base;
14571b4c 2764 struct drm_connector *connector;
cc68c81a 2765 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
14571b4c 2766 struct intel_connector *intel_connector;
615fb93f 2767 struct intel_sdvo_connector *intel_sdvo_connector;
14571b4c 2768
739f8dbc 2769 DRM_DEBUG_KMS("initialising DVI type 0x%x\n", type);
46a3f4a3 2770
08d9bc92 2771 intel_sdvo_connector = intel_sdvo_connector_alloc();
615fb93f 2772 if (!intel_sdvo_connector)
14571b4c
ZW		 2773 return false;
2774
739f8dbc 2775 intel_sdvo_connector->output_flag = type;
14571b4c 2776
615fb93f 2777 intel_connector = &intel_sdvo_connector->base;
14571b4c 2778 connector = &intel_connector->base;
5fa7ac9c
JN		 2779 if (intel_sdvo_get_hotplug_support(intel_sdvo) &
2780 intel_sdvo_connector->output_flag) {
5fa7ac9c 2781 intel_sdvo->hotplug_active |= intel_sdvo_connector->output_flag;
c16336b9
CW		 2782 /*
2783 * Some SDVO devices have one-shot hotplug interrupts.
cc68c81a
SF		 2784 * Ensure that they get re-enabled when an interrupt happens.
2785 */
5fb908eb 2786 intel_connector->polled = DRM_CONNECTOR_POLL_HPD;
1b2cb026 2787 intel_encoder->hotplug = intel_sdvo_hotplug;
3a2fb2c3 2788 intel_sdvo_enable_hotplug(intel_encoder);
5fa7ac9c 2789 } else {
821450c6 2790 intel_connector->polled = DRM_CONNECTOR_POLL_CONNECT | DRM_CONNECTOR_POLL_DISCONNECT;
5fa7ac9c 2791 }
14571b4c
ZW		 2792 encoder->encoder_type = DRM_MODE_ENCODER_TMDS;
2793 connector->connector_type = DRM_MODE_CONNECTOR_DVID;
2794
739f8dbc 2795 if (intel_sdvo_is_hdmi_connector(intel_sdvo)) {
14571b4c 2796 connector->connector_type = DRM_MODE_CONNECTOR_HDMIA;
aa2b8807 2797 intel_sdvo_connector->is_hdmi = true;
14571b4c 2798 }
14571b4c 2799
c393454d
ID		 2800 if (intel_sdvo_connector_init(intel_sdvo_connector, intel_sdvo) < 0) {
2801 kfree(intel_sdvo_connector);
2802 return false;
2803 }
2804
aa2b8807 2805 if (intel_sdvo_connector->is_hdmi)
55bc60db 2806 intel_sdvo_add_hdmi_properties(intel_sdvo, intel_sdvo_connector);
14571b4c
ZW		 2807
2808 return true;
2809}
2810
2811static bool
739f8dbc 2812intel_sdvo_tv_init(struct intel_sdvo *intel_sdvo, u16 type)
14571b4c 2813{
4ef69c7a
CW		 2814 struct drm_encoder *encoder = &intel_sdvo->base.base;
2815 struct drm_connector *connector;
2816 struct intel_connector *intel_connector;
2817 struct intel_sdvo_connector *intel_sdvo_connector;
14571b4c 2818
739f8dbc 2819 DRM_DEBUG_KMS("initialising TV type 0x%x\n", type);
46a3f4a3 2820
08d9bc92 2821 intel_sdvo_connector = intel_sdvo_connector_alloc();
615fb93f
CW		 2822 if (!intel_sdvo_connector)
2823 return false;
14571b4c 2824
615fb93f 2825 intel_connector = &intel_sdvo_connector->base;
4ef69c7a
CW		 2826 connector = &intel_connector->base;
2827 encoder->encoder_type = DRM_MODE_ENCODER_TVDAC;
2828 connector->connector_type = DRM_MODE_CONNECTOR_SVIDEO;
14571b4c 2829
4ef69c7a 2830 intel_sdvo_connector->output_flag = type;
14571b4c 2831
c393454d
ID		 2832 if (intel_sdvo_connector_init(intel_sdvo_connector, intel_sdvo) < 0) {
2833 kfree(intel_sdvo_connector);
2834 return false;
2835 }
14571b4c 2836
4ef69c7a 2837 if (!intel_sdvo_tv_create_property(intel_sdvo, intel_sdvo_connector, type))
32aad86f 2838 goto err;
14571b4c 2839
4ef69c7a 2840 if (!intel_sdvo_create_enhance_property(intel_sdvo, intel_sdvo_connector))
32aad86f 2841 goto err;
14571b4c 2842
4ef69c7a 2843 return true;
32aad86f
CW		 2844
2845err:
d4b26e4f 2846 intel_connector_destroy(connector);
32aad86f 2847 return false;
14571b4c
ZW		 2848}
2849
2850static bool
739f8dbc 2851intel_sdvo_analog_init(struct intel_sdvo *intel_sdvo, u16 type)
14571b4c 2852{
4ef69c7a
CW		 2853 struct drm_encoder *encoder = &intel_sdvo->base.base;
2854 struct drm_connector *connector;
2855 struct intel_connector *intel_connector;
2856 struct intel_sdvo_connector *intel_sdvo_connector;
14571b4c 2857
739f8dbc 2858 DRM_DEBUG_KMS("initialising analog type 0x%x\n", type);
46a3f4a3 2859
8ce7da47 2860 intel_sdvo_connector = intel_sdvo_connector_alloc();
615fb93f
CW		 2861 if (!intel_sdvo_connector)
2862 return false;
14571b4c 2863
615fb93f 2864 intel_connector = &intel_sdvo_connector->base;
4ef69c7a 2865 connector = &intel_connector->base;
821450c6 2866 intel_connector->polled = DRM_CONNECTOR_POLL_CONNECT;
4ef69c7a
CW		 2867 encoder->encoder_type = DRM_MODE_ENCODER_DAC;
2868 connector->connector_type = DRM_MODE_CONNECTOR_VGA;
2869
739f8dbc 2870 intel_sdvo_connector->output_flag = type;
4ef69c7a 2871
c393454d
ID		 2872 if (intel_sdvo_connector_init(intel_sdvo_connector, intel_sdvo) < 0) {
2873 kfree(intel_sdvo_connector);
2874 return false;
2875 }
2876
4ef69c7a 2877 return true;
14571b4c
ZW		 2878}
2879
2880static bool
739f8dbc 2881intel_sdvo_lvds_init(struct intel_sdvo *intel_sdvo, u16 type)
14571b4c 2882{
4ef69c7a 2883 struct drm_encoder *encoder = &intel_sdvo->base.base;
3cf05076 2884 struct drm_i915_private *i915 = to_i915(encoder->dev);
4ef69c7a
CW		 2885 struct drm_connector *connector;
2886 struct intel_connector *intel_connector;
2887 struct intel_sdvo_connector *intel_sdvo_connector;
14571b4c 2888
739f8dbc 2889 DRM_DEBUG_KMS("initialising LVDS type 0x%x\n", type);
46a3f4a3 2890
08d9bc92 2891 intel_sdvo_connector = intel_sdvo_connector_alloc();
615fb93f
CW		 2892 if (!intel_sdvo_connector)
2893 return false;
14571b4c 2894
615fb93f
CW		 2895 intel_connector = &intel_sdvo_connector->base;
2896 connector = &intel_connector->base;
4ef69c7a
CW		 2897 encoder->encoder_type = DRM_MODE_ENCODER_LVDS;
2898 connector->connector_type = DRM_MODE_CONNECTOR_LVDS;
2899
739f8dbc 2900 intel_sdvo_connector->output_flag = type;
4ef69c7a 2901
c393454d
ID		 2902 if (intel_sdvo_connector_init(intel_sdvo_connector, intel_sdvo) < 0) {
2903 kfree(intel_sdvo_connector);
2904 return false;
2905 }
2906
4ef69c7a 2907 if (!intel_sdvo_create_enhance_property(intel_sdvo, intel_sdvo_connector))
32aad86f
CW		 2908 goto err;
2909
3f9ffce5 2910 intel_bios_init_panel_late(i915, &intel_connector->panel, NULL, NULL);
3cf05076 2911
50203b94
VS		 2912 /*
2913 * Fetch modes from VBT. For SDVO prefer the VBT mode since some
2914 * SDVO->LVDS transcoders can't cope with the EDID mode.
2915 */
db10c14a
VS		 2916 intel_panel_add_vbt_sdvo_fixed_mode(intel_connector);
2917
2918 if (!intel_panel_preferred_fixed_mode(intel_connector)) {
a3cd4f44
VS		 2919 mutex_lock(&i915->drm.mode_config.mutex);
2920
c0ff6c6e 2921 intel_ddc_get_modes(connector, connector->ddc);
eb89e83c 2922 intel_panel_add_edid_fixed_modes(intel_connector, false);
a3cd4f44
VS		 2923
2924 mutex_unlock(&i915->drm.mode_config.mutex);
50203b94 2925 }
7b554301 2926
15d045fd 2927 intel_panel_init(intel_connector, NULL);
aa2b8807 2928
43af6743 2929 if (!intel_panel_preferred_fixed_mode(intel_connector))
aa2b8807
VS		 2930 goto err;
2931
32aad86f
CW		 2932 return true;
2933
2934err:
d4b26e4f 2935 intel_connector_destroy(connector);
32aad86f 2936 return false;
14571b4c
ZW		 2937}
2938
cc1e6639
VS		 2939static u16 intel_sdvo_filter_output_flags(u16 flags)
2940{
2941 flags &= SDVO_OUTPUT_MASK;
2942
2943 /* SDVO requires XXX1 function may not exist unless it has XXX0 function.*/
2944 if (!(flags & SDVO_OUTPUT_TMDS0))
2945 flags &= ~SDVO_OUTPUT_TMDS1;
2946
2947 if (!(flags & SDVO_OUTPUT_RGB0))
2948 flags &= ~SDVO_OUTPUT_RGB1;
2949
2950 if (!(flags & SDVO_OUTPUT_LVDS0))
2951 flags &= ~SDVO_OUTPUT_LVDS1;
2952
2953 return flags;
2954}
2955
79708d14
VS		 2956static bool intel_sdvo_output_init(struct intel_sdvo *sdvo, u16 type)
2957{
2958 if (type & SDVO_TMDS_MASK)
2959 return intel_sdvo_dvi_init(sdvo, type);
2960 else if (type & SDVO_TV_MASK)
2961 return intel_sdvo_tv_init(sdvo, type);
2962 else if (type & SDVO_RGB_MASK)
2963 return intel_sdvo_analog_init(sdvo, type);
2964 else if (type & SDVO_LVDS_MASK)
2965 return intel_sdvo_lvds_init(sdvo, type);
2966 else
2967 return false;
2968}
2969
14571b4c 2970static bool
aa7d827b 2971intel_sdvo_output_setup(struct intel_sdvo *intel_sdvo)
14571b4c 2972{
79708d14
VS		 2973 static const u16 probe_order[] = {
2974 SDVO_OUTPUT_TMDS0,
2975 SDVO_OUTPUT_TMDS1,
2976 /* TV has no XXX1 function block */
2977 SDVO_OUTPUT_SVID0,
2978 SDVO_OUTPUT_CVBS0,
2979 SDVO_OUTPUT_YPRPB0,
2980 SDVO_OUTPUT_RGB0,
2981 SDVO_OUTPUT_RGB1,
2982 SDVO_OUTPUT_LVDS0,
2983 SDVO_OUTPUT_LVDS1,
2984 };
aa7d827b 2985 u16 flags;
79708d14 2986 int i;
64b7b557 2987
aa7d827b
VS		 2988 flags = intel_sdvo_filter_output_flags(intel_sdvo->caps.output_flags);
2989
2990 if (flags == 0) {
2991 DRM_DEBUG_KMS("%s: Unknown SDVO output type (0x%04x)\n",
2992 SDVO_NAME(intel_sdvo), intel_sdvo->caps.output_flags);
2993 return false;
2994 }
fb7a46f3 2995
79708d14
VS		 2996 for (i = 0; i < ARRAY_SIZE(probe_order); i++) {
2997 u16 type = flags & probe_order[i];
14571b4c 2998
79708d14
VS		 2999 if (!type)
3000 continue;
14571b4c 3001
79708d14 3002 if (!intel_sdvo_output_init(intel_sdvo, type))
14571b4c 3003 return false;
79708d14 3004 }
fb7a46f3 3005
34053ee1 3006 intel_sdvo->base.pipe_mask = ~0;
fb7a46f3 3007
14571b4c 3008 return true;
fb7a46f3 3009}
3010
d0ddfbd3
JN		 3011static void intel_sdvo_output_cleanup(struct intel_sdvo *intel_sdvo)
3012{
3013 struct drm_device *dev = intel_sdvo->base.base.dev;
3014 struct drm_connector *connector, *tmp;
3015
3016 list_for_each_entry_safe(connector, tmp,
3017 &dev->mode_config.connector_list, head) {
43a6d19c 3018 if (intel_attached_encoder(to_intel_connector(connector)) == &intel_sdvo->base) {
34ea3d38 3019 drm_connector_unregister(connector);
d4b26e4f 3020 intel_connector_destroy(connector);
d9255d57 3021 }
d0ddfbd3
JN		 3022 }
3023}
3024
32aad86f
CW		 3025static bool intel_sdvo_tv_create_property(struct intel_sdvo *intel_sdvo,
3026 struct intel_sdvo_connector *intel_sdvo_connector,
3027 int type)
ce6feabd 3028{
4ef69c7a 3029 struct drm_device *dev = intel_sdvo->base.base.dev;
ce6feabd 3030 struct intel_sdvo_tv_format format;
a9dc3395 3031 u32 format_map, i;
ce6feabd 3032
32aad86f
CW		 3033 if (!intel_sdvo_set_target_output(intel_sdvo, type))
3034 return false;
ce6feabd 3035
1a3665c8 3036 BUILD_BUG_ON(sizeof(format) != 6);
32aad86f
CW		 3037 if (!intel_sdvo_get_value(intel_sdvo,
3038 SDVO_CMD_GET_SUPPORTED_TV_FORMATS,
3039 &format, sizeof(format)))
3040 return false;
ce6feabd 3041
32aad86f 3042 memcpy(&format_map, &format, min(sizeof(format_map), sizeof(format)));
ce6feabd
ZY		 3043
3044 if (format_map == 0)
32aad86f 3045 return false;
ce6feabd 3046
615fb93f 3047 intel_sdvo_connector->format_supported_num = 0;
ce6feabd 3048 for (i = 0 ; i < TV_FORMAT_NUM; i++)
40039750
CW		 3049 if (format_map & (1 << i))
3050 intel_sdvo_connector->tv_format_supported[intel_sdvo_connector->format_supported_num++] = i;
ce6feabd
ZY		 3051
3052
c5521706 3053 intel_sdvo_connector->tv_format =
32aad86f
CW		 3054 drm_property_create(dev, DRM_MODE_PROP_ENUM,
3055 "mode", intel_sdvo_connector->format_supported_num);
c5521706 3056 if (!intel_sdvo_connector->tv_format)
fcc8d672 3057 return false;
ce6feabd 3058
615fb93f 3059 for (i = 0; i < intel_sdvo_connector->format_supported_num; i++)
30e9db6d
VS		 3060 drm_property_add_enum(intel_sdvo_connector->tv_format, i,
3061 tv_format_names[intel_sdvo_connector->tv_format_supported[i]]);
ce6feabd 3062
630d30a4 3063 intel_sdvo_connector->base.base.state->tv.mode = intel_sdvo_connector->tv_format_supported[0];
10223df2
VS		 3064 drm_object_attach_property(&intel_sdvo_connector->base.base.base,
3065 intel_sdvo_connector->tv_format, 0);
32aad86f 3066 return true;
ce6feabd
ZY		 3067
3068}
3069
630d30a4 3070#define _ENHANCEMENT(state_assignment, name, NAME) do { \
c5521706
CW		 3071 if (enhancements.name) { \
3072 if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_MAX_##NAME, &data_value, 4) || \
3073 !intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_##NAME, &response, 2)) \
3074 return false; \
c5521706 3075 intel_sdvo_connector->name = \
d9bc3c02 3076 drm_property_create_range(dev, 0, #name, 0, data_value[0]); \
c5521706 3077 if (!intel_sdvo_connector->name) return false; \
630d30a4 3078 state_assignment = response; \
662595df 3079 drm_object_attach_property(&connector->base, \
630d30a4 3080 intel_sdvo_connector->name, 0); \
c5521706
CW		 3081 DRM_DEBUG_KMS(#name ": max %d, default %d, current %d\n", \
3082 data_value[0], data_value[1], response); \
3083 } \
0206e353 3084} while (0)
c5521706 3085
630d30a4
ML		 3086#define ENHANCEMENT(state, name, NAME) _ENHANCEMENT((state)->name, name, NAME)
3087
c5521706
CW		 3088static bool
3089intel_sdvo_create_enhance_property_tv(struct intel_sdvo *intel_sdvo,
3090 struct intel_sdvo_connector *intel_sdvo_connector,
3091 struct intel_sdvo_enhancements_reply enhancements)
b9219c5e 3092{
4ef69c7a 3093 struct drm_device *dev = intel_sdvo->base.base.dev;
32aad86f 3094 struct drm_connector *connector = &intel_sdvo_connector->base.base;
630d30a4
ML		 3095 struct drm_connector_state *conn_state = connector->state;
3096 struct intel_sdvo_connector_state *sdvo_state =
3097 to_intel_sdvo_connector_state(conn_state);
a9dc3395 3098 u16 response, data_value[2];
b9219c5e 3099
c16336b9 3100 /* when horizontal overscan is supported, Add the left/right property */
c5521706
CW		 3101 if (enhancements.overscan_h) {
3102 if (!intel_sdvo_get_value(intel_sdvo,
3103 SDVO_CMD_GET_MAX_OVERSCAN_H,
3104 &data_value, 4))
3105 return false;
32aad86f 3106
c5521706
CW		 3107 if (!intel_sdvo_get_value(intel_sdvo,
3108 SDVO_CMD_GET_OVERSCAN_H,
3109 &response, 2))
3110 return false;
fcc8d672 3111
630d30a4
ML		 3112 sdvo_state->tv.overscan_h = response;
3113
c5521706 3114 intel_sdvo_connector->max_hscan = data_value[0];
c5521706 3115 intel_sdvo_connector->left =
d9bc3c02 3116 drm_property_create_range(dev, 0, "left_margin", 0, data_value[0]);
c5521706
CW		 3117 if (!intel_sdvo_connector->left)
3118 return false;
fcc8d672 3119
662595df 3120 drm_object_attach_property(&connector->base,
630d30a4 3121 intel_sdvo_connector->left, 0);
fcc8d672 3122
c5521706 3123 intel_sdvo_connector->right =
d9bc3c02 3124 drm_property_create_range(dev, 0, "right_margin", 0, data_value[0]);
c5521706
CW		 3125 if (!intel_sdvo_connector->right)
3126 return false;
32aad86f 3127
662595df 3128 drm_object_attach_property(&connector->base,
630d30a4 3129 intel_sdvo_connector->right, 0);
c5521706
CW		 3130 DRM_DEBUG_KMS("h_overscan: max %d, "
3131 "default %d, current %d\n",
3132 data_value[0], data_value[1], response);
3133 }
32aad86f 3134
c5521706
CW		 3135 if (enhancements.overscan_v) {
3136 if (!intel_sdvo_get_value(intel_sdvo,
3137 SDVO_CMD_GET_MAX_OVERSCAN_V,
3138 &data_value, 4))
3139 return false;
fcc8d672 3140
c5521706
CW		 3141 if (!intel_sdvo_get_value(intel_sdvo,
3142 SDVO_CMD_GET_OVERSCAN_V,
3143 &response, 2))
3144 return false;
32aad86f 3145
630d30a4
ML		 3146 sdvo_state->tv.overscan_v = response;
3147
c5521706 3148 intel_sdvo_connector->max_vscan = data_value[0];
c5521706 3149 intel_sdvo_connector->top =
d9bc3c02
SH		 3150 drm_property_create_range(dev, 0,
3151 "top_margin", 0, data_value[0]);
c5521706
CW		 3152 if (!intel_sdvo_connector->top)
3153 return false;
32aad86f 3154
662595df 3155 drm_object_attach_property(&connector->base,
630d30a4 3156 intel_sdvo_connector->top, 0);
fcc8d672 3157
c5521706 3158 intel_sdvo_connector->bottom =
d9bc3c02
SH		 3159 drm_property_create_range(dev, 0,
3160 "bottom_margin", 0, data_value[0]);
c5521706
CW		 3161 if (!intel_sdvo_connector->bottom)
3162 return false;
32aad86f 3163
662595df 3164 drm_object_attach_property(&connector->base,
630d30a4 3165 intel_sdvo_connector->bottom, 0);
c5521706
CW		 3166 DRM_DEBUG_KMS("v_overscan: max %d, "
3167 "default %d, current %d\n",
3168 data_value[0], data_value[1], response);
3169 }
32aad86f 3170
630d30a4
ML		 3171 ENHANCEMENT(&sdvo_state->tv, hpos, HPOS);
3172 ENHANCEMENT(&sdvo_state->tv, vpos, VPOS);
3173 ENHANCEMENT(&conn_state->tv, saturation, SATURATION);
3174 ENHANCEMENT(&conn_state->tv, contrast, CONTRAST);
3175 ENHANCEMENT(&conn_state->tv, hue, HUE);
3176 ENHANCEMENT(&conn_state->tv, brightness, BRIGHTNESS);
3177 ENHANCEMENT(&sdvo_state->tv, sharpness, SHARPNESS);
3178 ENHANCEMENT(&sdvo_state->tv, flicker_filter, FLICKER_FILTER);
3179 ENHANCEMENT(&sdvo_state->tv, flicker_filter_adaptive, FLICKER_FILTER_ADAPTIVE);
3180 ENHANCEMENT(&sdvo_state->tv, flicker_filter_2d, FLICKER_FILTER_2D);
3181 _ENHANCEMENT(sdvo_state->tv.chroma_filter, tv_chroma_filter, TV_CHROMA_FILTER);
3182 _ENHANCEMENT(sdvo_state->tv.luma_filter, tv_luma_filter, TV_LUMA_FILTER);
fcc8d672 3183
e044218a
CW		 3184 if (enhancements.dot_crawl) {
3185 if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_DOT_CRAWL, &response, 2))
3186 return false;
3187
630d30a4 3188 sdvo_state->tv.dot_crawl = response & 0x1;
e044218a 3189 intel_sdvo_connector->dot_crawl =
d9bc3c02 3190 drm_property_create_range(dev, 0, "dot_crawl", 0, 1);
e044218a
CW		 3191 if (!intel_sdvo_connector->dot_crawl)
3192 return false;
3193
662595df 3194 drm_object_attach_property(&connector->base,
630d30a4 3195 intel_sdvo_connector->dot_crawl, 0);
e044218a
CW		 3196 DRM_DEBUG_KMS("dot crawl: current %d\n", response);
3197 }
3198
c5521706
CW		 3199 return true;
3200}
32aad86f 3201
c5521706
CW		 3202static bool
3203intel_sdvo_create_enhance_property_lvds(struct intel_sdvo *intel_sdvo,
3204 struct intel_sdvo_connector *intel_sdvo_connector,
3205 struct intel_sdvo_enhancements_reply enhancements)
3206{
4ef69c7a 3207 struct drm_device *dev = intel_sdvo->base.base.dev;
c5521706 3208 struct drm_connector *connector = &intel_sdvo_connector->base.base;
a9dc3395 3209 u16 response, data_value[2];
32aad86f 3210
630d30a4 3211 ENHANCEMENT(&connector->state->tv, brightness, BRIGHTNESS);
fcc8d672 3212
c5521706
CW		 3213 return true;
3214}
3215#undef ENHANCEMENT
630d30a4 3216#undef _ENHANCEMENT
32aad86f 3217
c5521706
CW		 3218static bool intel_sdvo_create_enhance_property(struct intel_sdvo *intel_sdvo,
3219 struct intel_sdvo_connector *intel_sdvo_connector)
3220{
3221 union {
3222 struct intel_sdvo_enhancements_reply reply;
a9dc3395 3223 u16 response;
c5521706 3224 } enhancements;
32aad86f 3225
1a3665c8
CW		 3226 BUILD_BUG_ON(sizeof(enhancements) != 2);
3227
99016646
ID		 3228 if (!intel_sdvo_get_value(intel_sdvo,
3229 SDVO_CMD_GET_SUPPORTED_ENHANCEMENTS,
3230 &enhancements, sizeof(enhancements)) ||
3231 enhancements.response == 0) {
c5521706
CW		 3232 DRM_DEBUG_KMS("No enhancement is supported\n");
3233 return true;
b9219c5e 3234 }
32aad86f 3235
c5521706
CW		 3236 if (IS_TV(intel_sdvo_connector))
3237 return intel_sdvo_create_enhance_property_tv(intel_sdvo, intel_sdvo_connector, enhancements.reply);
0206e353 3238 else if (IS_LVDS(intel_sdvo_connector))
c5521706
CW		 3239 return intel_sdvo_create_enhance_property_lvds(intel_sdvo, intel_sdvo_connector, enhancements.reply);
3240 else
3241 return true;
e957d772
CW		 3242}
3243
3244static int intel_sdvo_ddc_proxy_xfer(struct i2c_adapter *adapter,
3245 struct i2c_msg *msgs,
3246 int num)
3247{
c0ff6c6e
VS		 3248 struct intel_sdvo_ddc *ddc = adapter->algo_data;
3249 struct intel_sdvo *sdvo = ddc->sdvo;
fcc8d672 3250
c0ff6c6e 3251 if (!__intel_sdvo_set_control_bus_switch(sdvo, 1 << ddc->ddc_bus))
e957d772
CW		 3252 return -EIO;
3253
3254 return sdvo->i2c->algo->master_xfer(sdvo->i2c, msgs, num);
3255}
3256
3257static u32 intel_sdvo_ddc_proxy_func(struct i2c_adapter *adapter)
3258{
c0ff6c6e
VS		 3259 struct intel_sdvo_ddc *ddc = adapter->algo_data;
3260 struct intel_sdvo *sdvo = ddc->sdvo;
3261
e957d772
CW		 3262 return sdvo->i2c->algo->functionality(sdvo->i2c);
3263}
3264
3265static const struct i2c_algorithm intel_sdvo_ddc_proxy = {
3266 .master_xfer = intel_sdvo_ddc_proxy_xfer,
3267 .functionality = intel_sdvo_ddc_proxy_func
3268};
3269
a8506684
DV		 3270static void proxy_lock_bus(struct i2c_adapter *adapter,
3271 unsigned int flags)
3272{
c0ff6c6e
VS		 3273 struct intel_sdvo_ddc *ddc = adapter->algo_data;
3274 struct intel_sdvo *sdvo = ddc->sdvo;
3275
a8506684
DV		 3276 sdvo->i2c->lock_ops->lock_bus(sdvo->i2c, flags);
3277}
3278
3279static int proxy_trylock_bus(struct i2c_adapter *adapter,
3280 unsigned int flags)
3281{
c0ff6c6e
VS		 3282 struct intel_sdvo_ddc *ddc = adapter->algo_data;
3283 struct intel_sdvo *sdvo = ddc->sdvo;
3284
a8506684
DV		 3285 return sdvo->i2c->lock_ops->trylock_bus(sdvo->i2c, flags);
3286}
3287
3288static void proxy_unlock_bus(struct i2c_adapter *adapter,
3289 unsigned int flags)
3290{
c0ff6c6e
VS		 3291 struct intel_sdvo_ddc *ddc = adapter->algo_data;
3292 struct intel_sdvo *sdvo = ddc->sdvo;
3293
a8506684
DV		 3294 sdvo->i2c->lock_ops->unlock_bus(sdvo->i2c, flags);
3295}
3296
0db1aa42 3297static const struct i2c_lock_operations proxy_lock_ops = {
a8506684
DV		 3298 .lock_bus = proxy_lock_bus,
3299 .trylock_bus = proxy_trylock_bus,
3300 .unlock_bus = proxy_unlock_bus,
3301};
3302
c0ff6c6e
VS		 3303static int
3304intel_sdvo_init_ddc_proxy(struct intel_sdvo_ddc *ddc,
3305 struct intel_sdvo *sdvo, int ddc_bus)
e957d772 3306{
0eb8252a 3307 struct drm_i915_private *dev_priv = to_i915(sdvo->base.base.dev);
8ff5446a 3308 struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev);
52a05c30 3309
c0ff6c6e
VS		 3310 ddc->sdvo = sdvo;
3311 ddc->ddc_bus = ddc_bus;
e957d772 3312
c0ff6c6e
VS		 3313 ddc->ddc.owner = THIS_MODULE;
3314 ddc->ddc.class = I2C_CLASS_DDC;
3315 snprintf(ddc->ddc.name, I2C_NAME_SIZE, "SDVO %c DDC%d",
3316 port_name(sdvo->base.port), ddc_bus);
3317 ddc->ddc.dev.parent = &pdev->dev;
3318 ddc->ddc.algo_data = ddc;
3319 ddc->ddc.algo = &intel_sdvo_ddc_proxy;
3320 ddc->ddc.lock_ops = &proxy_lock_ops;
3321
3322 return i2c_add_adapter(&ddc->ddc);
b9219c5e
ZY		 3323}
3324
39432640 3325static bool is_sdvo_port_valid(struct drm_i915_private *dev_priv, enum port port)
2a5c0832
VS		 3326{
3327 if (HAS_PCH_SPLIT(dev_priv))
39432640 3328 return port == PORT_B;
2a5c0832 3329 else
39432640
VS		 3330 return port == PORT_B || port == PORT_C;
3331}
3332
3333static bool assert_sdvo_port_valid(struct drm_i915_private *dev_priv,
3334 enum port port)
3335{
3336 return !drm_WARN(&dev_priv->drm, !is_sdvo_port_valid(dev_priv, port),
3337 "Platform does not support SDVO %c\n", port_name(port));
2a5c0832
VS		 3338}
3339
c39055b0 3340bool intel_sdvo_init(struct drm_i915_private *dev_priv,
f0f59a00 3341 i915_reg_t sdvo_reg, enum port port)
79e53945 3342{
21d40d37 3343 struct intel_encoder *intel_encoder;
ea5b213a 3344 struct intel_sdvo *intel_sdvo;
79e53945 3345 int i;
2a5c0832 3346
679df6f1
VS		 3347 if (!assert_port_valid(dev_priv, port))
3348 return false;
3349
39432640
VS		 3350 if (!assert_sdvo_port_valid(dev_priv, port))
3351 return false;
2a5c0832 3352
b14c5679 3353 intel_sdvo = kzalloc(sizeof(*intel_sdvo), GFP_KERNEL);
ea5b213a 3354 if (!intel_sdvo)
7d57382e 3355 return false;
79e53945 3356
56184e3d 3357 /* encoder type will be decided later */
ea5b213a 3358 intel_encoder = &intel_sdvo->base;
21d40d37 3359 intel_encoder->type = INTEL_OUTPUT_SDVO;
79f255a0 3360 intel_encoder->power_domain = POWER_DOMAIN_PORT_OTHER;
03cdc1d4 3361 intel_encoder->port = port;
0eb8252a 3362
c39055b0
ACO		 3363 drm_encoder_init(&dev_priv->drm, &intel_encoder->base,
3364 &intel_sdvo_enc_funcs, 0,
580d8ed5 3365 "SDVO %c", port_name(port));
79e53945 3366
0eb8252a 3367 intel_sdvo->sdvo_reg = sdvo_reg;
0eb8252a 3368 intel_sdvo->slave_addr = intel_sdvo_get_slave_addr(intel_sdvo) >> 1;
c0ff6c6e 3369
0eb8252a 3370 intel_sdvo_select_i2c_bus(intel_sdvo);
0eb8252a 3371
79e53945
JB		 3372 /* Read the regs to test if we can talk to the device */
3373 for (i = 0; i < 0x40; i++) {
f899fc64
CW		 3374 u8 byte;
3375
3376 if (!intel_sdvo_read_byte(intel_sdvo, i, &byte)) {
c808c4ae
WK		 3377 drm_dbg_kms(&dev_priv->drm,
3378 "No SDVO device found on %s\n",
3379 SDVO_NAME(intel_sdvo));
f899fc64 3380 goto err;
79e53945
JB		 3381 }
3382 }
3383
6cc5f341 3384 intel_encoder->compute_config = intel_sdvo_compute_config;
6e266956 3385 if (HAS_PCH_SPLIT(dev_priv)) {
3c65d1d1
VS		 3386 intel_encoder->disable = pch_disable_sdvo;
3387 intel_encoder->post_disable = pch_post_disable_sdvo;
3388 } else {
3389 intel_encoder->disable = intel_disable_sdvo;
3390 }
192d47a6 3391 intel_encoder->pre_enable = intel_sdvo_pre_enable;
ce22c320 3392 intel_encoder->enable = intel_enable_sdvo;
4ac41f47 3393 intel_encoder->get_hw_state = intel_sdvo_get_hw_state;
045ac3b5 3394 intel_encoder->get_config = intel_sdvo_get_config;
ce22c320 3395
af901ca1 3396 /* In default case sdvo lvds is false */
32aad86f 3397 if (!intel_sdvo_get_capabilities(intel_sdvo, &intel_sdvo->caps))
f899fc64 3398 goto err;
79e53945 3399
90f8ed85
VS		 3400 intel_sdvo->colorimetry_cap =
3401 intel_sdvo_get_colorimetry_cap(intel_sdvo);
3402
c0ff6c6e
VS		 3403 for (i = 0; i < ARRAY_SIZE(intel_sdvo->ddc); i++) {
3404 int ret;
3405
3406 ret = intel_sdvo_init_ddc_proxy(&intel_sdvo->ddc[i],
3407 intel_sdvo, i + 1);
3408 if (ret)
3409 goto err;
3410 }
3411
aa7d827b 3412 if (!intel_sdvo_output_setup(intel_sdvo)) {
c808c4ae
WK		 3413 drm_dbg_kms(&dev_priv->drm,
3414 "SDVO output failed to setup on %s\n",
3415 SDVO_NAME(intel_sdvo));
d0ddfbd3
JN		 3416 /* Output_setup can leave behind connectors! */
3417 goto err_output;
79e53945
JB		 3418 }
3419
c16336b9
CW		 3420 /*
3421 * Only enable the hotplug irq if we need it, to work around noisy
7ba220ce
CW		 3422 * hotplug lines.
3423 */
3424 if (intel_sdvo->hotplug_active) {
c6eddd31 3425 if (intel_sdvo->base.port == PORT_B)
2a5c0832
VS		 3426 intel_encoder->hpd_pin = HPD_SDVO_B;
3427 else
3428 intel_encoder->hpd_pin = HPD_SDVO_C;
7ba220ce
CW		 3429 }
3430
e506d6fd
DV		 3431 /*
3432 * Cloning SDVO with anything is often impossible, since the SDVO
3433 * encoder can request a special input timing mode. And even if that's
3434 * not the case we have evidence that cloning a plain unscaled mode with
3435 * VGA doesn't really work. Furthermore the cloning flags are way too
3436 * simplistic anyway to express such constraints, so just give up on
3437 * cloning for SDVO encoders.
3438 */
bc079e8b 3439 intel_sdvo->base.cloneable = 0;
e506d6fd 3440
79e53945 3441 /* Set the input timing to the screen. Assume always input 0. */
32aad86f 3442 if (!intel_sdvo_set_target_input(intel_sdvo))
d0ddfbd3 3443 goto err_output;
79e53945 3444
32aad86f
CW		 3445 if (!intel_sdvo_get_input_pixel_clock_range(intel_sdvo,
3446 &intel_sdvo->pixel_clock_min,
3447 &intel_sdvo->pixel_clock_max))
d0ddfbd3 3448 goto err_output;
79e53945 3449
c808c4ae 3450 drm_dbg_kms(&dev_priv->drm, "%s device VID/DID: %02X:%02X.%02X, "
342dc382 3451 "clock range %dMHz - %dMHz, "
469c0962 3452 "num inputs: %d, "
342dc382 3453 "output 1: %c, output 2: %c\n",
ea5b213a
CW		 3454 SDVO_NAME(intel_sdvo),
3455 intel_sdvo->caps.vendor_id, intel_sdvo->caps.device_id,
3456 intel_sdvo->caps.device_rev_id,
3457 intel_sdvo->pixel_clock_min / 1000,
3458 intel_sdvo->pixel_clock_max / 1000,
469c0962 3459 intel_sdvo->caps.sdvo_num_inputs,
342dc382 3460 /* check currently supported outputs */
ea5b213a 3461 intel_sdvo->caps.output_flags &
a6ebd538
VS		 3462 (SDVO_OUTPUT_TMDS0 | SDVO_OUTPUT_RGB0 |
3463 SDVO_OUTPUT_LVDS0 | SDVO_OUTPUT_SVID0 |
3464 SDVO_OUTPUT_CVBS0 | SDVO_OUTPUT_YPRPB0) ? 'Y' : 'N',
ea5b213a 3465 intel_sdvo->caps.output_flags &
a6ebd538
VS		 3466 (SDVO_OUTPUT_TMDS1 | SDVO_OUTPUT_RGB1 |
3467 SDVO_OUTPUT_LVDS1) ? 'Y' : 'N');
7d57382e 3468 return true;
79e53945 3469
d0ddfbd3
JN		 3470err_output:
3471 intel_sdvo_output_cleanup(intel_sdvo);
f899fc64 3472err:
fbfcc4f3 3473 intel_sdvo_unselect_i2c_bus(intel_sdvo);
c0ff6c6e 3474 intel_sdvo_encoder_destroy(&intel_encoder->base);
79e53945 3475
7d57382e 3476 return false;
79e53945 3477}
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