[thirdparty/linux.git] / drivers / gpu / drm / v3d / v3d_debugfs.c

// SPDX-License-Identifier: GPL-2.0+
/* Copyright (C) 2014-2018 Broadcom */

#include <linux/circ_buf.h>
#include <linux/ctype.h>
#include <linux/debugfs.h>
#include <linux/pm_runtime.h>
#include <linux/seq_file.h>
#include <drm/drmP.h>

#include "v3d_drv.h"
#include "v3d_regs.h"

#define REGDEF(reg) { reg, #reg }
struct v3d_reg_def {
	u32 reg;
	const char *name;
};

static const struct v3d_reg_def v3d_hub_reg_defs[] = {
	REGDEF(V3D_HUB_AXICFG),
	REGDEF(V3D_HUB_UIFCFG),
	REGDEF(V3D_HUB_IDENT0),
	REGDEF(V3D_HUB_IDENT1),
	REGDEF(V3D_HUB_IDENT2),
	REGDEF(V3D_HUB_IDENT3),
	REGDEF(V3D_HUB_INT_STS),
	REGDEF(V3D_HUB_INT_MSK_STS),
};

static const struct v3d_reg_def v3d_gca_reg_defs[] = {
	REGDEF(V3D_GCA_SAFE_SHUTDOWN),
	REGDEF(V3D_GCA_SAFE_SHUTDOWN_ACK),
};

static const struct v3d_reg_def v3d_core_reg_defs[] = {
	REGDEF(V3D_CTL_IDENT0),
	REGDEF(V3D_CTL_IDENT1),
	REGDEF(V3D_CTL_IDENT2),
	REGDEF(V3D_CTL_MISCCFG),
	REGDEF(V3D_CTL_INT_STS),
	REGDEF(V3D_CTL_INT_MSK_STS),
	REGDEF(V3D_CLE_CT0CS),
	REGDEF(V3D_CLE_CT0CA),
	REGDEF(V3D_CLE_CT0EA),
	REGDEF(V3D_CLE_CT1CS),
	REGDEF(V3D_CLE_CT1CA),
	REGDEF(V3D_CLE_CT1EA),

	REGDEF(V3D_PTB_BPCA),
	REGDEF(V3D_PTB_BPCS),

	REGDEF(V3D_MMU_CTL),
	REGDEF(V3D_MMU_VIO_ADDR),

	REGDEF(V3D_GMP_STATUS),
	REGDEF(V3D_GMP_CFG),
	REGDEF(V3D_GMP_VIO_ADDR),
};

static int v3d_v3d_debugfs_regs(struct seq_file *m, void *unused)
{
	struct drm_info_node *node = (struct drm_info_node *)m->private;
	struct drm_device *dev = node->minor->dev;
	struct v3d_dev *v3d = to_v3d_dev(dev);
	int i, core;

	for (i = 0; i < ARRAY_SIZE(v3d_hub_reg_defs); i++) {
		seq_printf(m, "%s (0x%04x): 0x%08x\n",
			   v3d_hub_reg_defs[i].name, v3d_hub_reg_defs[i].reg,
			   V3D_READ(v3d_hub_reg_defs[i].reg));
	}

	if (v3d->ver < 41) {
		for (i = 0; i < ARRAY_SIZE(v3d_gca_reg_defs); i++) {
			seq_printf(m, "%s (0x%04x): 0x%08x\n",
				   v3d_gca_reg_defs[i].name,
				   v3d_gca_reg_defs[i].reg,
				   V3D_GCA_READ(v3d_gca_reg_defs[i].reg));
		}
	}

	for (core = 0; core < v3d->cores; core++) {
		for (i = 0; i < ARRAY_SIZE(v3d_core_reg_defs); i++) {
			seq_printf(m, "core %d %s (0x%04x): 0x%08x\n",
				   core,
				   v3d_core_reg_defs[i].name,
				   v3d_core_reg_defs[i].reg,
				   V3D_CORE_READ(core,
						 v3d_core_reg_defs[i].reg));
		}
	}

	return 0;
}

static int v3d_v3d_debugfs_ident(struct seq_file *m, void *unused)
{
	struct drm_info_node *node = (struct drm_info_node *)m->private;
	struct drm_device *dev = node->minor->dev;
	struct v3d_dev *v3d = to_v3d_dev(dev);
	u32 ident0, ident1, ident2, ident3, cores;
	int ret, core;

	ret = pm_runtime_get_sync(v3d->dev);
	if (ret < 0)
		return ret;

	ident0 = V3D_READ(V3D_HUB_IDENT0);
	ident1 = V3D_READ(V3D_HUB_IDENT1);
	ident2 = V3D_READ(V3D_HUB_IDENT2);
	ident3 = V3D_READ(V3D_HUB_IDENT3);
	cores = V3D_GET_FIELD(ident1, V3D_HUB_IDENT1_NCORES);

	seq_printf(m, "Revision:   %d.%d.%d.%d\n",
		   V3D_GET_FIELD(ident1, V3D_HUB_IDENT1_TVER),
		   V3D_GET_FIELD(ident1, V3D_HUB_IDENT1_REV),
		   V3D_GET_FIELD(ident3, V3D_HUB_IDENT3_IPREV),
		   V3D_GET_FIELD(ident3, V3D_HUB_IDENT3_IPIDX));
	seq_printf(m, "MMU:        %s\n",
		   (ident2 & V3D_HUB_IDENT2_WITH_MMU) ? "yes" : "no");
	seq_printf(m, "TFU:        %s\n",
		   (ident1 & V3D_HUB_IDENT1_WITH_TFU) ? "yes" : "no");
	seq_printf(m, "TSY:        %s\n",
		   (ident1 & V3D_HUB_IDENT1_WITH_TSY) ? "yes" : "no");
	seq_printf(m, "MSO:        %s\n",
		   (ident1 & V3D_HUB_IDENT1_WITH_MSO) ? "yes" : "no");
	seq_printf(m, "L3C:        %s (%dkb)\n",
		   (ident1 & V3D_HUB_IDENT1_WITH_L3C) ? "yes" : "no",
		   V3D_GET_FIELD(ident2, V3D_HUB_IDENT2_L3C_NKB));

	for (core = 0; core < cores; core++) {
		u32 misccfg;
		u32 nslc, ntmu, qups;

		ident0 = V3D_CORE_READ(core, V3D_CTL_IDENT0);
		ident1 = V3D_CORE_READ(core, V3D_CTL_IDENT1);
		ident2 = V3D_CORE_READ(core, V3D_CTL_IDENT2);
		misccfg = V3D_CORE_READ(core, V3D_CTL_MISCCFG);

		nslc = V3D_GET_FIELD(ident1, V3D_IDENT1_NSLC);
		ntmu = V3D_GET_FIELD(ident1, V3D_IDENT1_NTMU);
		qups = V3D_GET_FIELD(ident1, V3D_IDENT1_QUPS);

		seq_printf(m, "Core %d:\n", core);
		seq_printf(m, "  Revision:     %d.%d\n",
			   V3D_GET_FIELD(ident0, V3D_IDENT0_VER),
			   V3D_GET_FIELD(ident1, V3D_IDENT1_REV));
		seq_printf(m, "  Slices:       %d\n", nslc);
		seq_printf(m, "  TMUs:         %d\n", nslc * ntmu);
		seq_printf(m, "  QPUs:         %d\n", nslc * qups);
		seq_printf(m, "  Semaphores:   %d\n",
			   V3D_GET_FIELD(ident1, V3D_IDENT1_NSEM));
		seq_printf(m, "  BCG int:      %d\n",
			   (ident2 & V3D_IDENT2_BCG_INT) != 0);
		seq_printf(m, "  Override TMU: %d\n",
			   (misccfg & V3D_MISCCFG_OVRTMUOUT) != 0);
	}

	pm_runtime_mark_last_busy(v3d->dev);
	pm_runtime_put_autosuspend(v3d->dev);

	return 0;
}

static int v3d_debugfs_bo_stats(struct seq_file *m, void *unused)
{
	struct drm_info_node *node = (struct drm_info_node *)m->private;
	struct drm_device *dev = node->minor->dev;
	struct v3d_dev *v3d = to_v3d_dev(dev);

	mutex_lock(&v3d->bo_lock);
	seq_printf(m, "allocated bos:          %d\n",
		   v3d->bo_stats.num_allocated);
	seq_printf(m, "allocated bo size (kb): %ld\n",
		   (long)v3d->bo_stats.pages_allocated << (PAGE_SHIFT - 10));
	mutex_unlock(&v3d->bo_lock);

	return 0;
}

static int v3d_measure_clock(struct seq_file *m, void *unused)
{
	struct drm_info_node *node = (struct drm_info_node *)m->private;
	struct drm_device *dev = node->minor->dev;
	struct v3d_dev *v3d = to_v3d_dev(dev);
	uint32_t cycles;
	int core = 0;
	int measure_ms = 1000;

	if (v3d->ver >= 40) {
		V3D_CORE_WRITE(core, V3D_V4_PCTR_0_SRC_0_3,
			       V3D_SET_FIELD(V3D_PCTR_CYCLE_COUNT,
					     V3D_PCTR_S0));
		V3D_CORE_WRITE(core, V3D_V4_PCTR_0_CLR, 1);
		V3D_CORE_WRITE(core, V3D_V4_PCTR_0_EN, 1);
	} else {
		V3D_CORE_WRITE(core, V3D_V3_PCTR_0_PCTRS0,
			       V3D_PCTR_CYCLE_COUNT);
		V3D_CORE_WRITE(core, V3D_V3_PCTR_0_CLR, 1);
		V3D_CORE_WRITE(core, V3D_V3_PCTR_0_EN,
			       V3D_V3_PCTR_0_EN_ENABLE |
			       1);
	}
	msleep(measure_ms);
	cycles = V3D_CORE_READ(core, V3D_PCTR_0_PCTR0);

	seq_printf(m, "cycles: %d (%d.%d Mhz)\n",
		   cycles,
		   cycles / (measure_ms * 1000),
		   (cycles / (measure_ms * 100)) % 10);

	return 0;
}

static const struct drm_info_list v3d_debugfs_list[] = {
	{"v3d_ident", v3d_v3d_debugfs_ident, 0},
	{"v3d_regs", v3d_v3d_debugfs_regs, 0},
	{"measure_clock", v3d_measure_clock, 0},
	{"bo_stats", v3d_debugfs_bo_stats, 0},
};

int
v3d_debugfs_init(struct drm_minor *minor)
{
	return drm_debugfs_create_files(v3d_debugfs_list,
					ARRAY_SIZE(v3d_debugfs_list),
					minor->debugfs_root, minor);
}
Commit	Line	Data
57692c94 EA	1	// SPDX-License-Identifier: GPL-2.0+
	2	/* Copyright (C) 2014-2018 Broadcom */
	3
	4	#include <linux/circ_buf.h>
	5	#include <linux/ctype.h>
	6	#include <linux/debugfs.h>
	7	#include <linux/pm_runtime.h>
	8	#include <linux/seq_file.h>
	9	#include <drm/drmP.h>
	10
	11	#include "v3d_drv.h"
	12	#include "v3d_regs.h"
	13
	14	#define REGDEF(reg) { reg, #reg }
	15	struct v3d_reg_def {
	16	u32 reg;
	17	const char *name;
	18	};
	19
	20	static const struct v3d_reg_def v3d_hub_reg_defs[] = {
	21	REGDEF(V3D_HUB_AXICFG),
	22	REGDEF(V3D_HUB_UIFCFG),
	23	REGDEF(V3D_HUB_IDENT0),
	24	REGDEF(V3D_HUB_IDENT1),
	25	REGDEF(V3D_HUB_IDENT2),
	26	REGDEF(V3D_HUB_IDENT3),
	27	REGDEF(V3D_HUB_INT_STS),
	28	REGDEF(V3D_HUB_INT_MSK_STS),
	29	};
	30
	31	static const struct v3d_reg_def v3d_gca_reg_defs[] = {
	32	REGDEF(V3D_GCA_SAFE_SHUTDOWN),
	33	REGDEF(V3D_GCA_SAFE_SHUTDOWN_ACK),
	34	};
	35
	36	static const struct v3d_reg_def v3d_core_reg_defs[] = {
	37	REGDEF(V3D_CTL_IDENT0),
	38	REGDEF(V3D_CTL_IDENT1),
	39	REGDEF(V3D_CTL_IDENT2),
	40	REGDEF(V3D_CTL_MISCCFG),
	41	REGDEF(V3D_CTL_INT_STS),
	42	REGDEF(V3D_CTL_INT_MSK_STS),
	43	REGDEF(V3D_CLE_CT0CS),
	44	REGDEF(V3D_CLE_CT0CA),
	45	REGDEF(V3D_CLE_CT0EA),
	46	REGDEF(V3D_CLE_CT1CS),
	47	REGDEF(V3D_CLE_CT1CA),
	48	REGDEF(V3D_CLE_CT1EA),
	49
	50	REGDEF(V3D_PTB_BPCA),
	51	REGDEF(V3D_PTB_BPCS),
	52
	53	REGDEF(V3D_MMU_CTL),
	54	REGDEF(V3D_MMU_VIO_ADDR),
	55
	56	REGDEF(V3D_GMP_STATUS),
	57	REGDEF(V3D_GMP_CFG),
	58	REGDEF(V3D_GMP_VIO_ADDR),
	59	};
	60
	61	static int v3d_v3d_debugfs_regs(struct seq_file m, void unused)
	62	{
	63	struct drm_info_node node = (struct drm_info_node )m->private;
	64	struct drm_device *dev = node->minor->dev;
65	struct v3d_dev *v3d = to_v3d_dev(dev);
66	int i, core;
67
68	for (i = 0; i < ARRAY_SIZE(v3d_hub_reg_defs); i++) {
69	seq_printf(m, "%s (0x%04x): 0x%08x\n",
70	v3d_hub_reg_defs[i].name, v3d_hub_reg_defs[i].reg,
71	V3D_READ(v3d_hub_reg_defs[i].reg));
72	}
73
2f20fa8d EA	74	if (v3d->ver < 41) {
	75	for (i = 0; i < ARRAY_SIZE(v3d_gca_reg_defs); i++) {
	76	seq_printf(m, "%s (0x%04x): 0x%08x\n",
	77	v3d_gca_reg_defs[i].name,
	78	v3d_gca_reg_defs[i].reg,
	79	V3D_GCA_READ(v3d_gca_reg_defs[i].reg));
	80	}
57692c94 EA	81	}
	82
	83	for (core = 0; core < v3d->cores; core++) {
	84	for (i = 0; i < ARRAY_SIZE(v3d_core_reg_defs); i++) {
	85	seq_printf(m, "core %d %s (0x%04x): 0x%08x\n",
	86	core,
	87	v3d_core_reg_defs[i].name,
	88	v3d_core_reg_defs[i].reg,
	89	V3D_CORE_READ(core,
	90	v3d_core_reg_defs[i].reg));
	91	}
	92	}
	93
	94	return 0;
	95	}
	96
	97	static int v3d_v3d_debugfs_ident(struct seq_file m, void unused)
	98	{
	99	struct drm_info_node node = (struct drm_info_node )m->private;
	100	struct drm_device *dev = node->minor->dev;
	101	struct v3d_dev *v3d = to_v3d_dev(dev);
	102	u32 ident0, ident1, ident2, ident3, cores;
	103	int ret, core;
	104
	105	ret = pm_runtime_get_sync(v3d->dev);
	106	if (ret < 0)
	107	return ret;
	108
	109	ident0 = V3D_READ(V3D_HUB_IDENT0);
	110	ident1 = V3D_READ(V3D_HUB_IDENT1);
	111	ident2 = V3D_READ(V3D_HUB_IDENT2);
	112	ident3 = V3D_READ(V3D_HUB_IDENT3);
	113	cores = V3D_GET_FIELD(ident1, V3D_HUB_IDENT1_NCORES);
	114
	115	seq_printf(m, "Revision: %d.%d.%d.%d\n",
	116	V3D_GET_FIELD(ident1, V3D_HUB_IDENT1_TVER),
	117	V3D_GET_FIELD(ident1, V3D_HUB_IDENT1_REV),
	118	V3D_GET_FIELD(ident3, V3D_HUB_IDENT3_IPREV),
	119	V3D_GET_FIELD(ident3, V3D_HUB_IDENT3_IPIDX));
	120	seq_printf(m, "MMU: %s\n",
	121	(ident2 & V3D_HUB_IDENT2_WITH_MMU) ? "yes" : "no");
	122	seq_printf(m, "TFU: %s\n",
	123	(ident1 & V3D_HUB_IDENT1_WITH_TFU) ? "yes" : "no");
	124	seq_printf(m, "TSY: %s\n",
	125	(ident1 & V3D_HUB_IDENT1_WITH_TSY) ? "yes" : "no");
	126	seq_printf(m, "MSO: %s\n",
	127	(ident1 & V3D_HUB_IDENT1_WITH_MSO) ? "yes" : "no");
	128	seq_printf(m, "L3C: %s (%dkb)\n",
	129	(ident1 & V3D_HUB_IDENT1_WITH_L3C) ? "yes" : "no",
	130	V3D_GET_FIELD(ident2, V3D_HUB_IDENT2_L3C_NKB));
	131
	132	for (core = 0; core < cores; core++) {
	133	u32 misccfg;
	134	u32 nslc, ntmu, qups;
	135
	136	ident0 = V3D_CORE_READ(core, V3D_CTL_IDENT0);
	137	ident1 = V3D_CORE_READ(core, V3D_CTL_IDENT1);
	138	ident2 = V3D_CORE_READ(core, V3D_CTL_IDENT2);
	139	misccfg = V3D_CORE_READ(core, V3D_CTL_MISCCFG);
	140
	141	nslc = V3D_GET_FIELD(ident1, V3D_IDENT1_NSLC);
	142	ntmu = V3D_GET_FIELD(ident1, V3D_IDENT1_NTMU);
	143	qups = V3D_GET_FIELD(ident1, V3D_IDENT1_QUPS);
	144
145	seq_printf(m, "Core %d:\n", core);
146	seq_printf(m, " Revision: %d.%d\n",
147	V3D_GET_FIELD(ident0, V3D_IDENT0_VER),
148	V3D_GET_FIELD(ident1, V3D_IDENT1_REV));
149	seq_printf(m, " Slices: %d\n", nslc);
150	seq_printf(m, " TMUs: %d\n", nslc * ntmu);
151	seq_printf(m, " QPUs: %d\n", nslc * qups);
152	seq_printf(m, " Semaphores: %d\n",
153	V3D_GET_FIELD(ident1, V3D_IDENT1_NSEM));
154	seq_printf(m, " BCG int: %d\n",
155	(ident2 & V3D_IDENT2_BCG_INT) != 0);
156	seq_printf(m, " Override TMU: %d\n",
157	(misccfg & V3D_MISCCFG_OVRTMUOUT) != 0);
158	}
159
160	pm_runtime_mark_last_busy(v3d->dev);
161	pm_runtime_put_autosuspend(v3d->dev);
162
163	return 0;
164	}
165
166	static int v3d_debugfs_bo_stats(struct seq_file m, void unused)
167	{
168	struct drm_info_node node = (struct drm_info_node )m->private;
169	struct drm_device *dev = node->minor->dev;
170	struct v3d_dev *v3d = to_v3d_dev(dev);
171
172	mutex_lock(&v3d->bo_lock);
173	seq_printf(m, "allocated bos: %d\n",
174	v3d->bo_stats.num_allocated);
175	seq_printf(m, "allocated bo size (kb): %ld\n",
176	(long)v3d->bo_stats.pages_allocated << (PAGE_SHIFT - 10));
177	mutex_unlock(&v3d->bo_lock);
178
179	return 0;
180	}
181
6915c9a5 EA	182	static int v3d_measure_clock(struct seq_file m, void unused)
	183	{
	184	struct drm_info_node node = (struct drm_info_node )m->private;
	185	struct drm_device *dev = node->minor->dev;
	186	struct v3d_dev *v3d = to_v3d_dev(dev);
	187	uint32_t cycles;
	188	int core = 0;
	189	int measure_ms = 1000;
	190
	191	if (v3d->ver >= 40) {
	192	V3D_CORE_WRITE(core, V3D_V4_PCTR_0_SRC_0_3,
	193	V3D_SET_FIELD(V3D_PCTR_CYCLE_COUNT,
	194	V3D_PCTR_S0));
	195	V3D_CORE_WRITE(core, V3D_V4_PCTR_0_CLR, 1);
	196	V3D_CORE_WRITE(core, V3D_V4_PCTR_0_EN, 1);
	197	} else {
	198	V3D_CORE_WRITE(core, V3D_V3_PCTR_0_PCTRS0,
	199	V3D_PCTR_CYCLE_COUNT);
	200	V3D_CORE_WRITE(core, V3D_V3_PCTR_0_CLR, 1);
	201	V3D_CORE_WRITE(core, V3D_V3_PCTR_0_EN,
	202	V3D_V3_PCTR_0_EN_ENABLE \|
	203	1);
	204	}
	205	msleep(measure_ms);
	206	cycles = V3D_CORE_READ(core, V3D_PCTR_0_PCTR0);
	207
	208	seq_printf(m, "cycles: %d (%d.%d Mhz)\n",
	209	cycles,
	210	cycles / (measure_ms * 1000),
	211	(cycles / (measure_ms * 100)) % 10);
	212
	213	return 0;
	214	}
	215
57692c94 EA	216	static const struct drm_info_list v3d_debugfs_list[] = {
	217	{"v3d_ident", v3d_v3d_debugfs_ident, 0},
	218	{"v3d_regs", v3d_v3d_debugfs_regs, 0},
6915c9a5	219	{"measure_clock", v3d_measure_clock, 0},
57692c94 EA	220	{"bo_stats", v3d_debugfs_bo_stats, 0},
	221	};
	222
	223	int
	224	v3d_debugfs_init(struct drm_minor *minor)
	225	{
	226	return drm_debugfs_create_files(v3d_debugfs_list,
	227	ARRAY_SIZE(v3d_debugfs_list),
	228	minor->debugfs_root, minor);
	229	}