[thirdparty/linux.git] / drivers / gpu / drm / v3d / v3d_debugfs.c

// SPDX-License-Identifier: GPL-2.0+
/* Copyright (C) 2014-2018 Broadcom */

#include <linux/circ_buf.h>
#include <linux/ctype.h>
#include <linux/debugfs.h>
#include <linux/pm_runtime.h>
#include <linux/seq_file.h>
#include <linux/string_helpers.h>

#include <drm/drm_debugfs.h>

#include "v3d_drv.h"
#include "v3d_regs.h"

#define REGDEF(reg) { reg, #reg }
struct v3d_reg_def {
	u32 reg;
	const char *name;
};

static const struct v3d_reg_def v3d_hub_reg_defs[] = {
	REGDEF(V3D_HUB_AXICFG),
	REGDEF(V3D_HUB_UIFCFG),
	REGDEF(V3D_HUB_IDENT0),
	REGDEF(V3D_HUB_IDENT1),
	REGDEF(V3D_HUB_IDENT2),
	REGDEF(V3D_HUB_IDENT3),
	REGDEF(V3D_HUB_INT_STS),
	REGDEF(V3D_HUB_INT_MSK_STS),

	REGDEF(V3D_MMU_CTL),
	REGDEF(V3D_MMU_VIO_ADDR),
	REGDEF(V3D_MMU_VIO_ID),
	REGDEF(V3D_MMU_DEBUG_INFO),
};

static const struct v3d_reg_def v3d_gca_reg_defs[] = {
	REGDEF(V3D_GCA_SAFE_SHUTDOWN),
	REGDEF(V3D_GCA_SAFE_SHUTDOWN_ACK),
};

static const struct v3d_reg_def v3d_core_reg_defs[] = {
	REGDEF(V3D_CTL_IDENT0),
	REGDEF(V3D_CTL_IDENT1),
	REGDEF(V3D_CTL_IDENT2),
	REGDEF(V3D_CTL_MISCCFG),
	REGDEF(V3D_CTL_INT_STS),
	REGDEF(V3D_CTL_INT_MSK_STS),
	REGDEF(V3D_CLE_CT0CS),
	REGDEF(V3D_CLE_CT0CA),
	REGDEF(V3D_CLE_CT0EA),
	REGDEF(V3D_CLE_CT1CS),
	REGDEF(V3D_CLE_CT1CA),
	REGDEF(V3D_CLE_CT1EA),

	REGDEF(V3D_PTB_BPCA),
	REGDEF(V3D_PTB_BPCS),

	REGDEF(V3D_GMP_STATUS),
	REGDEF(V3D_GMP_CFG),
	REGDEF(V3D_GMP_VIO_ADDR),

	REGDEF(V3D_ERR_FDBGO),
	REGDEF(V3D_ERR_FDBGB),
	REGDEF(V3D_ERR_FDBGS),
	REGDEF(V3D_ERR_STAT),
};

static const struct v3d_reg_def v3d_csd_reg_defs[] = {
	REGDEF(V3D_CSD_STATUS),
	REGDEF(V3D_CSD_CURRENT_CFG0),
	REGDEF(V3D_CSD_CURRENT_CFG1),
	REGDEF(V3D_CSD_CURRENT_CFG2),
	REGDEF(V3D_CSD_CURRENT_CFG3),
	REGDEF(V3D_CSD_CURRENT_CFG4),
	REGDEF(V3D_CSD_CURRENT_CFG5),
	REGDEF(V3D_CSD_CURRENT_CFG6),
};

static int v3d_v3d_debugfs_regs(struct seq_file *m, void *unused)
{
	struct drm_info_node *node = (struct drm_info_node *)m->private;
	struct drm_device *dev = node->minor->dev;
	struct v3d_dev *v3d = to_v3d_dev(dev);
	int i, core;

	for (i = 0; i < ARRAY_SIZE(v3d_hub_reg_defs); i++) {
		seq_printf(m, "%s (0x%04x): 0x%08x\n",
			   v3d_hub_reg_defs[i].name, v3d_hub_reg_defs[i].reg,
			   V3D_READ(v3d_hub_reg_defs[i].reg));
	}

	if (v3d->ver < 41) {
		for (i = 0; i < ARRAY_SIZE(v3d_gca_reg_defs); i++) {
			seq_printf(m, "%s (0x%04x): 0x%08x\n",
				   v3d_gca_reg_defs[i].name,
				   v3d_gca_reg_defs[i].reg,
				   V3D_GCA_READ(v3d_gca_reg_defs[i].reg));
		}
	}

	for (core = 0; core < v3d->cores; core++) {
		for (i = 0; i < ARRAY_SIZE(v3d_core_reg_defs); i++) {
			seq_printf(m, "core %d %s (0x%04x): 0x%08x\n",
				   core,
				   v3d_core_reg_defs[i].name,
				   v3d_core_reg_defs[i].reg,
				   V3D_CORE_READ(core,
						 v3d_core_reg_defs[i].reg));
		}

		if (v3d_has_csd(v3d)) {
			for (i = 0; i < ARRAY_SIZE(v3d_csd_reg_defs); i++) {
				seq_printf(m, "core %d %s (0x%04x): 0x%08x\n",
					   core,
					   v3d_csd_reg_defs[i].name,
					   v3d_csd_reg_defs[i].reg,
					   V3D_CORE_READ(core,
							 v3d_csd_reg_defs[i].reg));
			}
		}
	}

	return 0;
}

static int v3d_v3d_debugfs_ident(struct seq_file *m, void *unused)
{
	struct drm_info_node *node = (struct drm_info_node *)m->private;
	struct drm_device *dev = node->minor->dev;
	struct v3d_dev *v3d = to_v3d_dev(dev);
	u32 ident0, ident1, ident2, ident3, cores;
	int ret, core;

	ret = pm_runtime_get_sync(v3d->drm.dev);
	if (ret < 0)
		return ret;

	ident0 = V3D_READ(V3D_HUB_IDENT0);
	ident1 = V3D_READ(V3D_HUB_IDENT1);
	ident2 = V3D_READ(V3D_HUB_IDENT2);
	ident3 = V3D_READ(V3D_HUB_IDENT3);
	cores = V3D_GET_FIELD(ident1, V3D_HUB_IDENT1_NCORES);

	seq_printf(m, "Revision:   %d.%d.%d.%d\n",
		   V3D_GET_FIELD(ident1, V3D_HUB_IDENT1_TVER),
		   V3D_GET_FIELD(ident1, V3D_HUB_IDENT1_REV),
		   V3D_GET_FIELD(ident3, V3D_HUB_IDENT3_IPREV),
		   V3D_GET_FIELD(ident3, V3D_HUB_IDENT3_IPIDX));
	seq_printf(m, "MMU:        %s\n",
		   str_yes_no(ident2 & V3D_HUB_IDENT2_WITH_MMU));
	seq_printf(m, "TFU:        %s\n",
		   str_yes_no(ident1 & V3D_HUB_IDENT1_WITH_TFU));
	seq_printf(m, "TSY:        %s\n",
		   str_yes_no(ident1 & V3D_HUB_IDENT1_WITH_TSY));
	seq_printf(m, "MSO:        %s\n",
		   str_yes_no(ident1 & V3D_HUB_IDENT1_WITH_MSO));
	seq_printf(m, "L3C:        %s (%dkb)\n",
		   str_yes_no(ident1 & V3D_HUB_IDENT1_WITH_L3C),
		   V3D_GET_FIELD(ident2, V3D_HUB_IDENT2_L3C_NKB));

	for (core = 0; core < cores; core++) {
		u32 misccfg;
		u32 nslc, ntmu, qups;

		ident0 = V3D_CORE_READ(core, V3D_CTL_IDENT0);
		ident1 = V3D_CORE_READ(core, V3D_CTL_IDENT1);
		ident2 = V3D_CORE_READ(core, V3D_CTL_IDENT2);
		misccfg = V3D_CORE_READ(core, V3D_CTL_MISCCFG);

		nslc = V3D_GET_FIELD(ident1, V3D_IDENT1_NSLC);
		ntmu = V3D_GET_FIELD(ident1, V3D_IDENT1_NTMU);
		qups = V3D_GET_FIELD(ident1, V3D_IDENT1_QUPS);

		seq_printf(m, "Core %d:\n", core);
		seq_printf(m, "  Revision:     %d.%d\n",
			   V3D_GET_FIELD(ident0, V3D_IDENT0_VER),
			   V3D_GET_FIELD(ident1, V3D_IDENT1_REV));
		seq_printf(m, "  Slices:       %d\n", nslc);
		seq_printf(m, "  TMUs:         %d\n", nslc * ntmu);
		seq_printf(m, "  QPUs:         %d\n", nslc * qups);
		seq_printf(m, "  Semaphores:   %d\n",
			   V3D_GET_FIELD(ident1, V3D_IDENT1_NSEM));
		seq_printf(m, "  BCG int:      %d\n",
			   (ident2 & V3D_IDENT2_BCG_INT) != 0);
		seq_printf(m, "  Override TMU: %d\n",
			   (misccfg & V3D_MISCCFG_OVRTMUOUT) != 0);
	}

	pm_runtime_mark_last_busy(v3d->drm.dev);
	pm_runtime_put_autosuspend(v3d->drm.dev);

	return 0;
}

static int v3d_debugfs_bo_stats(struct seq_file *m, void *unused)
{
	struct drm_info_node *node = (struct drm_info_node *)m->private;
	struct drm_device *dev = node->minor->dev;
	struct v3d_dev *v3d = to_v3d_dev(dev);

	mutex_lock(&v3d->bo_lock);
	seq_printf(m, "allocated bos:          %d\n",
		   v3d->bo_stats.num_allocated);
	seq_printf(m, "allocated bo size (kb): %ld\n",
		   (long)v3d->bo_stats.pages_allocated << (PAGE_SHIFT - 10));
	mutex_unlock(&v3d->bo_lock);

	return 0;
}

static int v3d_measure_clock(struct seq_file *m, void *unused)
{
	struct drm_info_node *node = (struct drm_info_node *)m->private;
	struct drm_device *dev = node->minor->dev;
	struct v3d_dev *v3d = to_v3d_dev(dev);
	uint32_t cycles;
	int core = 0;
	int measure_ms = 1000;
	int ret;

	ret = pm_runtime_get_sync(v3d->drm.dev);
	if (ret < 0)
		return ret;

	if (v3d->ver >= 40) {
		V3D_CORE_WRITE(core, V3D_V4_PCTR_0_SRC_0_3,
			       V3D_SET_FIELD(V3D_PCTR_CYCLE_COUNT,
					     V3D_PCTR_S0));
		V3D_CORE_WRITE(core, V3D_V4_PCTR_0_CLR, 1);
		V3D_CORE_WRITE(core, V3D_V4_PCTR_0_EN, 1);
	} else {
		V3D_CORE_WRITE(core, V3D_V3_PCTR_0_PCTRS0,
			       V3D_PCTR_CYCLE_COUNT);
		V3D_CORE_WRITE(core, V3D_V3_PCTR_0_CLR, 1);
		V3D_CORE_WRITE(core, V3D_V3_PCTR_0_EN,
			       V3D_V3_PCTR_0_EN_ENABLE |
			       1);
	}
	msleep(measure_ms);
	cycles = V3D_CORE_READ(core, V3D_PCTR_0_PCTR0);

	seq_printf(m, "cycles: %d (%d.%d Mhz)\n",
		   cycles,
		   cycles / (measure_ms * 1000),
		   (cycles / (measure_ms * 100)) % 10);

	pm_runtime_mark_last_busy(v3d->drm.dev);
	pm_runtime_put_autosuspend(v3d->drm.dev);

	return 0;
}

static const struct drm_info_list v3d_debugfs_list[] = {
	{"v3d_ident", v3d_v3d_debugfs_ident, 0},
	{"v3d_regs", v3d_v3d_debugfs_regs, 0},
	{"measure_clock", v3d_measure_clock, 0},
	{"bo_stats", v3d_debugfs_bo_stats, 0},
};

void
v3d_debugfs_init(struct drm_minor *minor)
{
	drm_debugfs_create_files(v3d_debugfs_list,
				 ARRAY_SIZE(v3d_debugfs_list),
				 minor->debugfs_root, minor);
}
Commit	Line	Data
57692c94 EA	1	// SPDX-License-Identifier: GPL-2.0+
	2	/* Copyright (C) 2014-2018 Broadcom */
	3
	4	#include <linux/circ_buf.h>
	5	#include <linux/ctype.h>
	6	#include <linux/debugfs.h>
	7	#include <linux/pm_runtime.h>
	8	#include <linux/seq_file.h>
b8c75bd9	9	#include <linux/string_helpers.h>
220989e7 SR	10
220989e7 SR	11	#include <drm/drm_debugfs.h>
57692c94 EA	12
	13	#include "v3d_drv.h"
	14	#include "v3d_regs.h"
	15
	16	#define REGDEF(reg) { reg, #reg }
	17	struct v3d_reg_def {
	18	u32 reg;
	19	const char *name;
	20	};
	21
	22	static const struct v3d_reg_def v3d_hub_reg_defs[] = {
	23	REGDEF(V3D_HUB_AXICFG),
	24	REGDEF(V3D_HUB_UIFCFG),
	25	REGDEF(V3D_HUB_IDENT0),
	26	REGDEF(V3D_HUB_IDENT1),
	27	REGDEF(V3D_HUB_IDENT2),
	28	REGDEF(V3D_HUB_IDENT3),
	29	REGDEF(V3D_HUB_INT_STS),
	30	REGDEF(V3D_HUB_INT_MSK_STS),
145986ec EA	31
	32	REGDEF(V3D_MMU_CTL),
	33	REGDEF(V3D_MMU_VIO_ADDR),
	34	REGDEF(V3D_MMU_VIO_ID),
091d6283	35	REGDEF(V3D_MMU_DEBUG_INFO),
57692c94 EA	36	};
	37
	38	static const struct v3d_reg_def v3d_gca_reg_defs[] = {
	39	REGDEF(V3D_GCA_SAFE_SHUTDOWN),
	40	REGDEF(V3D_GCA_SAFE_SHUTDOWN_ACK),
	41	};
	42
	43	static const struct v3d_reg_def v3d_core_reg_defs[] = {
	44	REGDEF(V3D_CTL_IDENT0),
	45	REGDEF(V3D_CTL_IDENT1),
	46	REGDEF(V3D_CTL_IDENT2),
	47	REGDEF(V3D_CTL_MISCCFG),
	48	REGDEF(V3D_CTL_INT_STS),
	49	REGDEF(V3D_CTL_INT_MSK_STS),
	50	REGDEF(V3D_CLE_CT0CS),
	51	REGDEF(V3D_CLE_CT0CA),
	52	REGDEF(V3D_CLE_CT0EA),
	53	REGDEF(V3D_CLE_CT1CS),
	54	REGDEF(V3D_CLE_CT1CA),
	55	REGDEF(V3D_CLE_CT1EA),
	56
	57	REGDEF(V3D_PTB_BPCA),
	58	REGDEF(V3D_PTB_BPCS),
	59
57692c94 EA	60	REGDEF(V3D_GMP_STATUS),
	61	REGDEF(V3D_GMP_CFG),
	62	REGDEF(V3D_GMP_VIO_ADDR),
1ba9d7cb EA	63
	64	REGDEF(V3D_ERR_FDBGO),
	65	REGDEF(V3D_ERR_FDBGB),
	66	REGDEF(V3D_ERR_FDBGS),
	67	REGDEF(V3D_ERR_STAT),
57692c94 EA	68	};
57692c94 EA	69
d223f98f EA	70	static const struct v3d_reg_def v3d_csd_reg_defs[] = {
	71	REGDEF(V3D_CSD_STATUS),
	72	REGDEF(V3D_CSD_CURRENT_CFG0),
	73	REGDEF(V3D_CSD_CURRENT_CFG1),
	74	REGDEF(V3D_CSD_CURRENT_CFG2),
	75	REGDEF(V3D_CSD_CURRENT_CFG3),
	76	REGDEF(V3D_CSD_CURRENT_CFG4),
	77	REGDEF(V3D_CSD_CURRENT_CFG5),
	78	REGDEF(V3D_CSD_CURRENT_CFG6),
	79	};
	80
57692c94 EA	81	static int v3d_v3d_debugfs_regs(struct seq_file m, void unused)
	82	{
	83	struct drm_info_node node = (struct drm_info_node )m->private;
	84	struct drm_device *dev = node->minor->dev;
	85	struct v3d_dev *v3d = to_v3d_dev(dev);
	86	int i, core;
	87
	88	for (i = 0; i < ARRAY_SIZE(v3d_hub_reg_defs); i++) {
	89	seq_printf(m, "%s (0x%04x): 0x%08x\n",
	90	v3d_hub_reg_defs[i].name, v3d_hub_reg_defs[i].reg,
	91	V3D_READ(v3d_hub_reg_defs[i].reg));
	92	}
	93
2f20fa8d EA	94	if (v3d->ver < 41) {
	95	for (i = 0; i < ARRAY_SIZE(v3d_gca_reg_defs); i++) {
	96	seq_printf(m, "%s (0x%04x): 0x%08x\n",
	97	v3d_gca_reg_defs[i].name,
	98	v3d_gca_reg_defs[i].reg,
	99	V3D_GCA_READ(v3d_gca_reg_defs[i].reg));
	100	}
57692c94 EA	101	}
	102
	103	for (core = 0; core < v3d->cores; core++) {
	104	for (i = 0; i < ARRAY_SIZE(v3d_core_reg_defs); i++) {
	105	seq_printf(m, "core %d %s (0x%04x): 0x%08x\n",
	106	core,
	107	v3d_core_reg_defs[i].name,
	108	v3d_core_reg_defs[i].reg,
	109	V3D_CORE_READ(core,
	110	v3d_core_reg_defs[i].reg));
	111	}
d223f98f EA	112
	113	if (v3d_has_csd(v3d)) {
	114	for (i = 0; i < ARRAY_SIZE(v3d_csd_reg_defs); i++) {
	115	seq_printf(m, "core %d %s (0x%04x): 0x%08x\n",
	116	core,
	117	v3d_csd_reg_defs[i].name,
	118	v3d_csd_reg_defs[i].reg,
	119	V3D_CORE_READ(core,
	120	v3d_csd_reg_defs[i].reg));
	121	}
	122	}
57692c94 EA	123	}
	124
	125	return 0;
	126	}
	127
	128	static int v3d_v3d_debugfs_ident(struct seq_file m, void unused)
	129	{
	130	struct drm_info_node node = (struct drm_info_node )m->private;
	131	struct drm_device *dev = node->minor->dev;
	132	struct v3d_dev *v3d = to_v3d_dev(dev);
	133	u32 ident0, ident1, ident2, ident3, cores;
	134	int ret, core;
	135
bc662528	136	ret = pm_runtime_get_sync(v3d->drm.dev);
57692c94 EA	137	if (ret < 0)
	138	return ret;
	139
	140	ident0 = V3D_READ(V3D_HUB_IDENT0);
	141	ident1 = V3D_READ(V3D_HUB_IDENT1);
	142	ident2 = V3D_READ(V3D_HUB_IDENT2);
	143	ident3 = V3D_READ(V3D_HUB_IDENT3);
	144	cores = V3D_GET_FIELD(ident1, V3D_HUB_IDENT1_NCORES);
	145
	146	seq_printf(m, "Revision: %d.%d.%d.%d\n",
	147	V3D_GET_FIELD(ident1, V3D_HUB_IDENT1_TVER),
	148	V3D_GET_FIELD(ident1, V3D_HUB_IDENT1_REV),
	149	V3D_GET_FIELD(ident3, V3D_HUB_IDENT3_IPREV),
	150	V3D_GET_FIELD(ident3, V3D_HUB_IDENT3_IPIDX));
	151	seq_printf(m, "MMU: %s\n",
b8c75bd9	152	str_yes_no(ident2 & V3D_HUB_IDENT2_WITH_MMU));
57692c94	153	seq_printf(m, "TFU: %s\n",
b8c75bd9	154	str_yes_no(ident1 & V3D_HUB_IDENT1_WITH_TFU));
57692c94	155	seq_printf(m, "TSY: %s\n",
b8c75bd9	156	str_yes_no(ident1 & V3D_HUB_IDENT1_WITH_TSY));
57692c94	157	seq_printf(m, "MSO: %s\n",
b8c75bd9	158	str_yes_no(ident1 & V3D_HUB_IDENT1_WITH_MSO));
57692c94	159	seq_printf(m, "L3C: %s (%dkb)\n",
b8c75bd9	160	str_yes_no(ident1 & V3D_HUB_IDENT1_WITH_L3C),
57692c94 EA	161	V3D_GET_FIELD(ident2, V3D_HUB_IDENT2_L3C_NKB));
	162
	163	for (core = 0; core < cores; core++) {
	164	u32 misccfg;
	165	u32 nslc, ntmu, qups;
	166
	167	ident0 = V3D_CORE_READ(core, V3D_CTL_IDENT0);
	168	ident1 = V3D_CORE_READ(core, V3D_CTL_IDENT1);
	169	ident2 = V3D_CORE_READ(core, V3D_CTL_IDENT2);
	170	misccfg = V3D_CORE_READ(core, V3D_CTL_MISCCFG);
	171
	172	nslc = V3D_GET_FIELD(ident1, V3D_IDENT1_NSLC);
	173	ntmu = V3D_GET_FIELD(ident1, V3D_IDENT1_NTMU);
	174	qups = V3D_GET_FIELD(ident1, V3D_IDENT1_QUPS);
	175
	176	seq_printf(m, "Core %d:\n", core);
	177	seq_printf(m, " Revision: %d.%d\n",
	178	V3D_GET_FIELD(ident0, V3D_IDENT0_VER),
	179	V3D_GET_FIELD(ident1, V3D_IDENT1_REV));
	180	seq_printf(m, " Slices: %d\n", nslc);
	181	seq_printf(m, " TMUs: %d\n", nslc * ntmu);
	182	seq_printf(m, " QPUs: %d\n", nslc * qups);
	183	seq_printf(m, " Semaphores: %d\n",
	184	V3D_GET_FIELD(ident1, V3D_IDENT1_NSEM));
	185	seq_printf(m, " BCG int: %d\n",
	186	(ident2 & V3D_IDENT2_BCG_INT) != 0);
	187	seq_printf(m, " Override TMU: %d\n",
	188	(misccfg & V3D_MISCCFG_OVRTMUOUT) != 0);
	189	}
	190
bc662528 DV	191	pm_runtime_mark_last_busy(v3d->drm.dev);
bc662528 DV	192	pm_runtime_put_autosuspend(v3d->drm.dev);
57692c94 EA	193
	194	return 0;
	195	}
	196
	197	static int v3d_debugfs_bo_stats(struct seq_file m, void unused)
	198	{
	199	struct drm_info_node node = (struct drm_info_node )m->private;
	200	struct drm_device *dev = node->minor->dev;
	201	struct v3d_dev *v3d = to_v3d_dev(dev);
	202
	203	mutex_lock(&v3d->bo_lock);
	204	seq_printf(m, "allocated bos: %d\n",
	205	v3d->bo_stats.num_allocated);
	206	seq_printf(m, "allocated bo size (kb): %ld\n",
	207	(long)v3d->bo_stats.pages_allocated << (PAGE_SHIFT - 10));
	208	mutex_unlock(&v3d->bo_lock);
	209
	210	return 0;
	211	}
	212
6915c9a5 EA	213	static int v3d_measure_clock(struct seq_file m, void unused)
	214	{
	215	struct drm_info_node node = (struct drm_info_node )m->private;
	216	struct drm_device *dev = node->minor->dev;
	217	struct v3d_dev *v3d = to_v3d_dev(dev);
	218	uint32_t cycles;
	219	int core = 0;
	220	int measure_ms = 1000;
935f3d88 EA	221	int ret;
935f3d88 EA	222
bc662528	223	ret = pm_runtime_get_sync(v3d->drm.dev);
935f3d88 EA	224	if (ret < 0)
935f3d88 EA	225	return ret;
6915c9a5 EA	226
	227	if (v3d->ver >= 40) {
	228	V3D_CORE_WRITE(core, V3D_V4_PCTR_0_SRC_0_3,
	229	V3D_SET_FIELD(V3D_PCTR_CYCLE_COUNT,
	230	V3D_PCTR_S0));
	231	V3D_CORE_WRITE(core, V3D_V4_PCTR_0_CLR, 1);
	232	V3D_CORE_WRITE(core, V3D_V4_PCTR_0_EN, 1);
	233	} else {
	234	V3D_CORE_WRITE(core, V3D_V3_PCTR_0_PCTRS0,
	235	V3D_PCTR_CYCLE_COUNT);
	236	V3D_CORE_WRITE(core, V3D_V3_PCTR_0_CLR, 1);
	237	V3D_CORE_WRITE(core, V3D_V3_PCTR_0_EN,
	238	V3D_V3_PCTR_0_EN_ENABLE \|
	239	1);
	240	}
	241	msleep(measure_ms);
	242	cycles = V3D_CORE_READ(core, V3D_PCTR_0_PCTR0);
	243
	244	seq_printf(m, "cycles: %d (%d.%d Mhz)\n",
	245	cycles,
	246	cycles / (measure_ms * 1000),
	247	(cycles / (measure_ms * 100)) % 10);
	248
bc662528 DV	249	pm_runtime_mark_last_busy(v3d->drm.dev);
bc662528 DV	250	pm_runtime_put_autosuspend(v3d->drm.dev);
935f3d88	251
6915c9a5 EA	252	return 0;
	253	}
	254
57692c94 EA	255	static const struct drm_info_list v3d_debugfs_list[] = {
	256	{"v3d_ident", v3d_v3d_debugfs_ident, 0},
	257	{"v3d_regs", v3d_v3d_debugfs_regs, 0},
6915c9a5	258	{"measure_clock", v3d_measure_clock, 0},
57692c94 EA	259	{"bo_stats", v3d_debugfs_bo_stats, 0},
	260	};
	261
7ce84471	262	void
57692c94 EA	263	v3d_debugfs_init(struct drm_minor *minor)
57692c94 EA	264	{
19660e89 WK	265	drm_debugfs_create_files(v3d_debugfs_list,
	266	ARRAY_SIZE(v3d_debugfs_list),
	267	minor->debugfs_root, minor);
57692c94	268	}