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9119f547 BG |
1 | // SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause |
2 | /* | |
3 | * Copyright (C) 2018, STMicroelectronics - All Rights Reserved | |
4 | */ | |
5 | ||
fb5b2463 PD |
6 | #define LOG_CATEGORY UCLASS_HWSPINLOCK |
7 | ||
d678a59d | 8 | #include <common.h> |
9119f547 BG |
9 | #include <clk.h> |
10 | #include <dm.h> | |
11 | #include <hwspinlock.h> | |
336d4615 | 12 | #include <malloc.h> |
9119f547 | 13 | #include <asm/io.h> |
cd93d625 | 14 | #include <linux/bitops.h> |
9119f547 BG |
15 | |
16 | #define STM32_MUTEX_COREID BIT(8) | |
17 | #define STM32_MUTEX_LOCK_BIT BIT(31) | |
18 | #define STM32_MUTEX_NUM_LOCKS 32 | |
19 | ||
20 | struct stm32mp1_hws_priv { | |
21 | fdt_addr_t base; | |
22 | }; | |
23 | ||
24 | static int stm32mp1_lock(struct udevice *dev, int index) | |
25 | { | |
26 | struct stm32mp1_hws_priv *priv = dev_get_priv(dev); | |
27 | u32 status; | |
28 | ||
29 | if (index >= STM32_MUTEX_NUM_LOCKS) | |
30 | return -EINVAL; | |
31 | ||
32 | status = readl(priv->base + index * sizeof(u32)); | |
33 | if (status == (STM32_MUTEX_LOCK_BIT | STM32_MUTEX_COREID)) | |
34 | return -EBUSY; | |
35 | ||
36 | writel(STM32_MUTEX_LOCK_BIT | STM32_MUTEX_COREID, | |
37 | priv->base + index * sizeof(u32)); | |
38 | ||
39 | status = readl(priv->base + index * sizeof(u32)); | |
40 | if (status != (STM32_MUTEX_LOCK_BIT | STM32_MUTEX_COREID)) | |
41 | return -EINVAL; | |
42 | ||
43 | return 0; | |
44 | } | |
45 | ||
46 | static int stm32mp1_unlock(struct udevice *dev, int index) | |
47 | { | |
48 | struct stm32mp1_hws_priv *priv = dev_get_priv(dev); | |
49 | ||
50 | if (index >= STM32_MUTEX_NUM_LOCKS) | |
51 | return -EINVAL; | |
52 | ||
53 | writel(STM32_MUTEX_COREID, priv->base + index * sizeof(u32)); | |
54 | ||
55 | return 0; | |
56 | } | |
57 | ||
58 | static int stm32mp1_hwspinlock_probe(struct udevice *dev) | |
59 | { | |
60 | struct stm32mp1_hws_priv *priv = dev_get_priv(dev); | |
61 | struct clk clk; | |
62 | int ret; | |
63 | ||
64 | priv->base = dev_read_addr(dev); | |
65 | if (priv->base == FDT_ADDR_T_NONE) | |
66 | return -EINVAL; | |
67 | ||
68 | ret = clk_get_by_index(dev, 0, &clk); | |
69 | if (ret) | |
70 | return ret; | |
71 | ||
c9309f40 | 72 | return clk_enable(&clk); |
9119f547 BG |
73 | } |
74 | ||
75 | static const struct hwspinlock_ops stm32mp1_hwspinlock_ops = { | |
76 | .lock = stm32mp1_lock, | |
77 | .unlock = stm32mp1_unlock, | |
78 | }; | |
79 | ||
80 | static const struct udevice_id stm32mp1_hwspinlock_ids[] = { | |
81 | { .compatible = "st,stm32-hwspinlock" }, | |
82 | {} | |
83 | }; | |
84 | ||
85 | U_BOOT_DRIVER(hwspinlock_stm32mp1) = { | |
86 | .name = "hwspinlock_stm32mp1", | |
87 | .id = UCLASS_HWSPINLOCK, | |
88 | .of_match = stm32mp1_hwspinlock_ids, | |
89 | .ops = &stm32mp1_hwspinlock_ops, | |
90 | .probe = stm32mp1_hwspinlock_probe, | |
41575d8e | 91 | .priv_auto = sizeof(struct stm32mp1_hws_priv), |
9119f547 | 92 | }; |