[thirdparty/u-boot.git] / drivers / i2c / designware_i2c_pci.c

// SPDX-License-Identifier: GPL-2.0+
/*
 * (C) Copyright 2009
 * Vipin Kumar, STMicroelectronics, vipin.kumar@st.com.
 * Copyright 2019 Google Inc
 */

#include <common.h>
#include <dm.h>
#include <log.h>
#include <spl.h>
#include <acpi/acpigen.h>
#include <acpi/acpi_device.h>
#include <asm/lpss.h>
#include <dm/acpi.h>
#include <dm/device-internal.h>
#include <dm/uclass-internal.h>
#include "designware_i2c.h"

enum {
	VANILLA		= 0,	/* standard I2C with no tweaks */
	INTEL_APL,		/* Apollo Lake I2C */
};

/* BayTrail HCNT/LCNT/SDA hold time */
static struct dw_scl_sda_cfg byt_config = {
	.ss_hcnt = 0x200,
	.fs_hcnt = 0x55,
	.ss_lcnt = 0x200,
	.fs_lcnt = 0x99,
	.sda_hold = 0x6,
};

/* Have a weak function for now - possibly should be a new uclass */
__weak void lpss_reset_release(void *regs);

static int designware_i2c_pci_of_to_plat(struct udevice *dev)
{
	struct dw_i2c *priv = dev_get_priv(dev);

	if (spl_phase() < PHASE_SPL) {
		u32 base;
		int ret;

		ret = dev_read_u32(dev, "early-regs", &base);
		if (ret)
			return log_msg_ret("early-regs", ret);

		/* Set i2c base address */
		dm_pci_write_config32(dev, PCI_BASE_ADDRESS_0, base);

		/* Enable memory access and bus master */
		dm_pci_write_config32(dev, PCI_COMMAND, PCI_COMMAND_MEMORY |
				      PCI_COMMAND_MASTER);
	}

	if (spl_phase() < PHASE_BOARD_F) {
		/* Handle early, fixed mapping into a different address space */
		priv->regs = (struct i2c_regs *)dm_pci_read_bar32(dev, 0);
	} else {
		priv->regs = (struct i2c_regs *)
			dm_pci_map_bar(dev, PCI_BASE_ADDRESS_0, 0, 0,
				       PCI_REGION_TYPE, PCI_REGION_MEM);
	}
	if (!priv->regs)
		return -EINVAL;

	/* Save base address from PCI BAR */
	if (IS_ENABLED(CONFIG_INTEL_BAYTRAIL))
		/* Use BayTrail specific timing values */
		priv->scl_sda_cfg = &byt_config;
	if (dev_get_driver_data(dev) == INTEL_APL)
		priv->has_spk_cnt = true;

	return designware_i2c_of_to_plat(dev);
}

static int designware_i2c_pci_probe(struct udevice *dev)
{
	struct dw_i2c *priv = dev_get_priv(dev);

	if (dev_get_driver_data(dev) == INTEL_APL) {
		/* Ensure controller is in D0 state */
		lpss_set_power_state(dev, STATE_D0);

		lpss_reset_release(priv->regs);
	}

	return designware_i2c_probe(dev);
}

static int designware_i2c_pci_bind(struct udevice *dev)
{
	char name[20];

	if (dev_has_ofnode(dev))
		return 0;

	sprintf(name, "i2c_designware#%u", dev_seq(dev));
	device_set_name(dev, name);

	return 0;
}

/*
 * Write ACPI object to describe speed configuration.
 *
 * ACPI Object: Name ("xxxx", Package () { scl_lcnt, scl_hcnt, sda_hold }
 *
 * SSCN: I2C_SPEED_STANDARD
 * FMCN: I2C_SPEED_FAST
 * FPCN: I2C_SPEED_FAST_PLUS
 * HSCN: I2C_SPEED_HIGH
 */
static void dw_i2c_acpi_write_speed_config(struct acpi_ctx *ctx,
					   struct dw_i2c_speed_config *config)
{
	switch (config->speed_mode) {
	case IC_SPEED_MODE_HIGH:
		acpigen_write_name(ctx, "HSCN");
		break;
	case IC_SPEED_MODE_FAST_PLUS:
		acpigen_write_name(ctx, "FPCN");
		break;
	case IC_SPEED_MODE_FAST:
		acpigen_write_name(ctx, "FMCN");
		break;
	case IC_SPEED_MODE_STANDARD:
	default:
		acpigen_write_name(ctx, "SSCN");
	}

	/* Package () { scl_lcnt, scl_hcnt, sda_hold } */
	acpigen_write_package(ctx, 3);
	acpigen_write_word(ctx, config->scl_hcnt);
	acpigen_write_word(ctx, config->scl_lcnt);
	acpigen_write_dword(ctx, config->sda_hold);
	acpigen_pop_len(ctx);
}

/*
 * Generate I2C timing information into the SSDT for the OS driver to consume,
 * optionally applying override values provided by the caller.
 */
static int dw_i2c_acpi_fill_ssdt(const struct udevice *dev,
				 struct acpi_ctx *ctx)
{
	struct dw_i2c_speed_config config;
	char path[ACPI_PATH_MAX];
	uint speed;
	int ret;

	/* If no device-tree node, ignore this since we assume it isn't used */
	if (!dev_has_ofnode(dev))
		return 0;

	ret = acpi_device_path(dev, path, sizeof(path));
	if (ret)
		return log_msg_ret("path", ret);

	speed = dev_read_u32_default(dev, "clock-frequency", 100000);
	acpigen_write_scope(ctx, path);
	ret = dw_i2c_gen_speed_config(dev, speed, &config);
	if (ret)
		return log_msg_ret("config", ret);
	dw_i2c_acpi_write_speed_config(ctx, &config);
	acpigen_pop_len(ctx);

	return 0;
}

struct acpi_ops dw_i2c_acpi_ops = {
	.fill_ssdt	= dw_i2c_acpi_fill_ssdt,
};

static const struct udevice_id designware_i2c_pci_ids[] = {
	{ .compatible = "snps,designware-i2c-pci" },
	{ .compatible = "intel,apl-i2c", .data = INTEL_APL },
	{ }
};

DM_DRIVER_ALIAS(i2c_designware_pci, intel_apl_i2c)

U_BOOT_DRIVER(i2c_designware_pci) = {
	.name	= "i2c_designware_pci",
	.id	= UCLASS_I2C,
	.of_match = designware_i2c_pci_ids,
	.bind	= designware_i2c_pci_bind,
	.of_to_plat	= designware_i2c_pci_of_to_plat,
	.probe	= designware_i2c_pci_probe,
	.priv_auto	= sizeof(struct dw_i2c),
	.remove = designware_i2c_remove,
	.flags = DM_FLAG_OS_PREPARE,
	.ops	= &designware_i2c_ops,
	ACPI_OPS_PTR(&dw_i2c_acpi_ops)
};

static struct pci_device_id designware_pci_supported[] = {
	/* Intel BayTrail has 7 I2C controller located on the PCI bus */
	{ PCI_VDEVICE(INTEL, 0x0f41) },
	{ PCI_VDEVICE(INTEL, 0x0f42) },
	{ PCI_VDEVICE(INTEL, 0x0f43) },
	{ PCI_VDEVICE(INTEL, 0x0f44) },
	{ PCI_VDEVICE(INTEL, 0x0f45) },
	{ PCI_VDEVICE(INTEL, 0x0f46) },
	{ PCI_VDEVICE(INTEL, 0x0f47) },
	{ PCI_VDEVICE(INTEL, 0x5aac), .driver_data = INTEL_APL },
	{ PCI_VDEVICE(INTEL, 0x5aae), .driver_data = INTEL_APL },
	{ PCI_VDEVICE(INTEL, 0x5ab0), .driver_data = INTEL_APL },
	{ PCI_VDEVICE(INTEL, 0x5ab2), .driver_data = INTEL_APL },
	{ PCI_VDEVICE(INTEL, 0x5ab4), .driver_data = INTEL_APL },
	{ PCI_VDEVICE(INTEL, 0x5ab6), .driver_data = INTEL_APL },
	{},
};

U_BOOT_PCI_DEVICE(i2c_designware_pci, designware_pci_supported);
Commit	Line	Data
457df233 SG	1	// SPDX-License-Identifier: GPL-2.0+
	2	/*
	3	* (C) Copyright 2009
eae488b7	4	* Vipin Kumar, STMicroelectronics, vipin.kumar@st.com.
457df233 SG	5	* Copyright 2019 Google Inc
	6	*/
	7
d678a59d	8	#include <common.h>
457df233	9	#include <dm.h>
f7ae49fc	10	#include <log.h>
fa11fe1b	11	#include <spl.h>
4b0ec52b SG	12	#include <acpi/acpigen.h>
4b0ec52b SG	13	#include <acpi/acpi_device.h>
070a9460	14	#include <asm/lpss.h>
4b0ec52b SG	15	#include <dm/acpi.h>
	16	#include <dm/device-internal.h>
	17	#include <dm/uclass-internal.h>
457df233 SG	18	#include "designware_i2c.h"
457df233 SG	19
070a9460 SG	20	enum {
	21	VANILLA = 0, /* standard I2C with no tweaks */
	22	INTEL_APL, /* Apollo Lake I2C */
	23	};
	24
457df233 SG	25	/* BayTrail HCNT/LCNT/SDA hold time */
	26	static struct dw_scl_sda_cfg byt_config = {
	27	.ss_hcnt = 0x200,
	28	.fs_hcnt = 0x55,
	29	.ss_lcnt = 0x200,
	30	.fs_lcnt = 0x99,
	31	.sda_hold = 0x6,
	32	};
	33
070a9460 SG	34	/* Have a weak function for now - possibly should be a new uclass */
	35	__weak void lpss_reset_release(void *regs);
	36
d1998a9f	37	static int designware_i2c_pci_of_to_plat(struct udevice *dev)
457df233 SG	38	{
	39	struct dw_i2c *priv = dev_get_priv(dev);
	40
fa11fe1b SG	41	if (spl_phase() < PHASE_SPL) {
	42	u32 base;
	43	int ret;
	44
	45	ret = dev_read_u32(dev, "early-regs", &base);
	46	if (ret)
	47	return log_msg_ret("early-regs", ret);
	48
	49	/* Set i2c base address */
	50	dm_pci_write_config32(dev, PCI_BASE_ADDRESS_0, base);
	51
	52	/* Enable memory access and bus master */
	53	dm_pci_write_config32(dev, PCI_COMMAND, PCI_COMMAND_MEMORY \|
	54	PCI_COMMAND_MASTER);
	55	}
	56
	57	if (spl_phase() < PHASE_BOARD_F) {
	58	/* Handle early, fixed mapping into a different address space */
	59	priv->regs = (struct i2c_regs *)dm_pci_read_bar32(dev, 0);
	60	} else {
	61	priv->regs = (struct i2c_regs *)
2635e3b5 AS	62	dm_pci_map_bar(dev, PCI_BASE_ADDRESS_0, 0, 0,
2635e3b5 AS	63	PCI_REGION_TYPE, PCI_REGION_MEM);
fa11fe1b SG	64	}
	65	if (!priv->regs)
	66	return -EINVAL;
	67
457df233	68	/* Save base address from PCI BAR */
457df233 SG	69	if (IS_ENABLED(CONFIG_INTEL_BAYTRAIL))
	70	/* Use BayTrail specific timing values */
	71	priv->scl_sda_cfg = &byt_config;
96fe11c3 SG	72	if (dev_get_driver_data(dev) == INTEL_APL)
96fe11c3 SG	73	priv->has_spk_cnt = true;
457df233	74
d1998a9f	75	return designware_i2c_of_to_plat(dev);
fa11fe1b SG	76	}
	77
	78	static int designware_i2c_pci_probe(struct udevice *dev)
	79	{
070a9460 SG	80	struct dw_i2c *priv = dev_get_priv(dev);
	81
	82	if (dev_get_driver_data(dev) == INTEL_APL) {
	83	/* Ensure controller is in D0 state */
	84	lpss_set_power_state(dev, STATE_D0);
	85
	86	lpss_reset_release(priv->regs);
	87	}
	88
457df233 SG	89	return designware_i2c_probe(dev);
	90	}
	91
	92	static int designware_i2c_pci_bind(struct udevice *dev)
	93	{
457df233 SG	94	char name[20];
457df233 SG	95
7d14ee44	96	if (dev_has_ofnode(dev))
4b0ec52b SG	97	return 0;
4b0ec52b SG	98
16df9932	99	sprintf(name, "i2c_designware#%u", dev_seq(dev));
457df233 SG	100	device_set_name(dev, name);
	101
	102	return 0;
	103	}
	104
4b0ec52b SG	105	/*
	106	* Write ACPI object to describe speed configuration.
	107	*
	108	* ACPI Object: Name ("xxxx", Package () { scl_lcnt, scl_hcnt, sda_hold }
	109	*
	110	* SSCN: I2C_SPEED_STANDARD
	111	* FMCN: I2C_SPEED_FAST
	112	* FPCN: I2C_SPEED_FAST_PLUS
	113	* HSCN: I2C_SPEED_HIGH
	114	*/
	115	static void dw_i2c_acpi_write_speed_config(struct acpi_ctx *ctx,
	116	struct dw_i2c_speed_config *config)
	117	{
	118	switch (config->speed_mode) {
	119	case IC_SPEED_MODE_HIGH:
	120	acpigen_write_name(ctx, "HSCN");
	121	break;
	122	case IC_SPEED_MODE_FAST_PLUS:
	123	acpigen_write_name(ctx, "FPCN");
	124	break;
	125	case IC_SPEED_MODE_FAST:
	126	acpigen_write_name(ctx, "FMCN");
	127	break;
	128	case IC_SPEED_MODE_STANDARD:
	129	default:
	130	acpigen_write_name(ctx, "SSCN");
	131	}
	132
	133	/* Package () { scl_lcnt, scl_hcnt, sda_hold } */
	134	acpigen_write_package(ctx, 3);
	135	acpigen_write_word(ctx, config->scl_hcnt);
	136	acpigen_write_word(ctx, config->scl_lcnt);
	137	acpigen_write_dword(ctx, config->sda_hold);
	138	acpigen_pop_len(ctx);
	139	}
	140
	141	/*
	142	* Generate I2C timing information into the SSDT for the OS driver to consume,
	143	* optionally applying override values provided by the caller.
	144	*/
	145	static int dw_i2c_acpi_fill_ssdt(const struct udevice *dev,
	146	struct acpi_ctx *ctx)
	147	{
	148	struct dw_i2c_speed_config config;
	149	char path[ACPI_PATH_MAX];
4b0ec52b	150	uint speed;
4b0ec52b SG	151	int ret;
	152
	153	/* If no device-tree node, ignore this since we assume it isn't used */
7d14ee44	154	if (!dev_has_ofnode(dev))
4b0ec52b SG	155	return 0;
	156
	157	ret = acpi_device_path(dev, path, sizeof(path));
	158	if (ret)
	159	return log_msg_ret("path", ret);
	160
4b0ec52b SG	161	speed = dev_read_u32_default(dev, "clock-frequency", 100000);
	162	acpigen_write_scope(ctx, path);
	163	ret = dw_i2c_gen_speed_config(dev, speed, &config);
	164	if (ret)
	165	return log_msg_ret("config", ret);
	166	dw_i2c_acpi_write_speed_config(ctx, &config);
	167	acpigen_pop_len(ctx);
	168
	169	return 0;
	170	}
	171
	172	struct acpi_ops dw_i2c_acpi_ops = {
	173	.fill_ssdt = dw_i2c_acpi_fill_ssdt,
	174	};
	175
fa11fe1b SG	176	static const struct udevice_id designware_i2c_pci_ids[] = {
fa11fe1b SG	177	{ .compatible = "snps,designware-i2c-pci" },
070a9460	178	{ .compatible = "intel,apl-i2c", .data = INTEL_APL },
fa11fe1b SG	179	{ }
	180	};
	181
dfb5bfbc SG	182	DM_DRIVER_ALIAS(i2c_designware_pci, intel_apl_i2c)
dfb5bfbc SG	183
457df233 SG	184	U_BOOT_DRIVER(i2c_designware_pci) = {
	185	.name = "i2c_designware_pci",
	186	.id = UCLASS_I2C,
fa11fe1b	187	.of_match = designware_i2c_pci_ids,
457df233	188	.bind = designware_i2c_pci_bind,
d1998a9f	189	.of_to_plat = designware_i2c_pci_of_to_plat,
457df233	190	.probe = designware_i2c_pci_probe,
41575d8e	191	.priv_auto = sizeof(struct dw_i2c),
457df233 SG	192	.remove = designware_i2c_remove,
	193	.flags = DM_FLAG_OS_PREPARE,
	194	.ops = &designware_i2c_ops,
4b0ec52b	195	ACPI_OPS_PTR(&dw_i2c_acpi_ops)
457df233 SG	196	};
	197
	198	static struct pci_device_id designware_pci_supported[] = {
	199	/* Intel BayTrail has 7 I2C controller located on the PCI bus */
	200	{ PCI_VDEVICE(INTEL, 0x0f41) },
	201	{ PCI_VDEVICE(INTEL, 0x0f42) },
	202	{ PCI_VDEVICE(INTEL, 0x0f43) },
	203	{ PCI_VDEVICE(INTEL, 0x0f44) },
	204	{ PCI_VDEVICE(INTEL, 0x0f45) },
	205	{ PCI_VDEVICE(INTEL, 0x0f46) },
	206	{ PCI_VDEVICE(INTEL, 0x0f47) },
070a9460 SG	207	{ PCI_VDEVICE(INTEL, 0x5aac), .driver_data = INTEL_APL },
	208	{ PCI_VDEVICE(INTEL, 0x5aae), .driver_data = INTEL_APL },
	209	{ PCI_VDEVICE(INTEL, 0x5ab0), .driver_data = INTEL_APL },
	210	{ PCI_VDEVICE(INTEL, 0x5ab2), .driver_data = INTEL_APL },
	211	{ PCI_VDEVICE(INTEL, 0x5ab4), .driver_data = INTEL_APL },
	212	{ PCI_VDEVICE(INTEL, 0x5ab6), .driver_data = INTEL_APL },
457df233 SG	213	{},
	214	};
	215
	216	U_BOOT_PCI_DEVICE(i2c_designware_pci, designware_pci_supported);