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i2c: mvtwsi: Fix style violations
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4ce5a728 1/*
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2 * Driver for the TWSI (i2c) controller found on the Marvell
3 * orion5x and kirkwood SoC families.
4ce5a728 4 *
57b4bce9 5 * Author: Albert Aribaud <albert.u.boot@aribaud.net>
306563a7 6 * Copyright (c) 2010 Albert Aribaud.
4ce5a728 7 *
1a459660 8 * SPDX-License-Identifier: GPL-2.0+
4ce5a728 9 */
306563a7 10
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11#include <common.h>
12#include <i2c.h>
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13#include <asm/errno.h>
14#include <asm/io.h>
15
306563a7 16/*
dd82242b 17 * include a file that will provide CONFIG_I2C_MVTWSI_BASE*
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18 * and possibly other settings
19 */
4ce5a728 20
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21#if defined(CONFIG_ORION5X)
22#include <asm/arch/orion5x.h>
81e33f4b 23#elif (defined(CONFIG_KIRKWOOD) || defined(CONFIG_ARCH_MVEBU))
3dc23f78 24#include <asm/arch/soc.h>
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25#elif defined(CONFIG_SUNXI)
26#include <asm/arch/i2c.h>
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27#else
28#error Driver mvtwsi not supported by SoC or board
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29#endif
30
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31/*
32 * TWSI register structure
33 */
4ce5a728 34
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35#ifdef CONFIG_SUNXI
36
37struct mvtwsi_registers {
38 u32 slave_address;
39 u32 xtnd_slave_addr;
40 u32 data;
41 u32 control;
42 u32 status;
43 u32 baudrate;
44 u32 soft_reset;
45};
46
47#else
48
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49struct mvtwsi_registers {
50 u32 slave_address;
51 u32 data;
52 u32 control;
53 union {
54 u32 status; /* when reading */
55 u32 baudrate; /* when writing */
56 };
57 u32 xtnd_slave_addr;
58 u32 reserved[2];
59 u32 soft_reset;
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60};
61
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62#endif
63
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64/*
65 * Control register fields
66 */
4ce5a728 67
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68#define MVTWSI_CONTROL_ACK 0x00000004
69#define MVTWSI_CONTROL_IFLG 0x00000008
70#define MVTWSI_CONTROL_STOP 0x00000010
71#define MVTWSI_CONTROL_START 0x00000020
72#define MVTWSI_CONTROL_TWSIEN 0x00000040
73#define MVTWSI_CONTROL_INTEN 0x00000080
4ce5a728 74
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75/*
76 * On sun6i and newer IFLG is a write-clear bit which is cleared by writing 1,
77 * on other platforms it is a normal r/w bit which is cleared by writing 0.
78 */
79
80#ifdef CONFIG_SUNXI_GEN_SUN6I
81#define MVTWSI_CONTROL_CLEAR_IFLG 0x00000008
82#else
83#define MVTWSI_CONTROL_CLEAR_IFLG 0x00000000
84#endif
85
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86/*
87 * Status register values -- only those expected in normal master
88 * operation on non-10-bit-address devices; whatever status we don't
89 * expect in nominal conditions (bus errors, arbitration losses,
90 * missing ACKs...) we just pass back to the caller as an error
91 * code.
92 */
4ce5a728 93
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94#define MVTWSI_STATUS_START 0x08
95#define MVTWSI_STATUS_REPEATED_START 0x10
96#define MVTWSI_STATUS_ADDR_W_ACK 0x18
97#define MVTWSI_STATUS_DATA_W_ACK 0x28
98#define MVTWSI_STATUS_ADDR_R_ACK 0x40
99#define MVTWSI_STATUS_ADDR_R_NAK 0x48
100#define MVTWSI_STATUS_DATA_R_ACK 0x50
101#define MVTWSI_STATUS_DATA_R_NAK 0x58
102#define MVTWSI_STATUS_IDLE 0xF8
103
104/*
dd82242b 105 * MVTWSI controller base
306563a7 106 */
4ce5a728 107
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108static struct mvtwsi_registers *twsi_get_base(struct i2c_adapter *adap)
109{
110 switch (adap->hwadapnr) {
111#ifdef CONFIG_I2C_MVTWSI_BASE0
112 case 0:
9ec43b0c 113 return (struct mvtwsi_registers *)CONFIG_I2C_MVTWSI_BASE0;
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114#endif
115#ifdef CONFIG_I2C_MVTWSI_BASE1
116 case 1:
9ec43b0c 117 return (struct mvtwsi_registers *)CONFIG_I2C_MVTWSI_BASE1;
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118#endif
119#ifdef CONFIG_I2C_MVTWSI_BASE2
120 case 2:
9ec43b0c 121 return (struct mvtwsi_registers *)CONFIG_I2C_MVTWSI_BASE2;
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122#endif
123#ifdef CONFIG_I2C_MVTWSI_BASE3
124 case 3:
9ec43b0c 125 return (struct mvtwsi_registers *)CONFIG_I2C_MVTWSI_BASE3;
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126#endif
127#ifdef CONFIG_I2C_MVTWSI_BASE4
128 case 4:
9ec43b0c 129 return (struct mvtwsi_registers *)CONFIG_I2C_MVTWSI_BASE4;
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130#endif
131#ifdef CONFIG_I2C_MVTWSI_BASE5
132 case 5:
9ec43b0c 133 return (struct mvtwsi_registers *)CONFIG_I2C_MVTWSI_BASE5;
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134#endif
135 default:
136 printf("Missing mvtwsi controller %d base\n", adap->hwadapnr);
137 break;
138 }
139
140 return NULL;
141}
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142
143/*
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144 * Returned statuses are 0 for success and nonzero otherwise.
145 * Currently, cmd_i2c and cmd_eeprom do not interpret an error status.
146 * Thus to ease debugging, the return status contains some debug info:
147 * - bits 31..24 are error class: 1 is timeout, 2 is 'status mismatch'.
148 * - bits 23..16 are the last value of the control register.
149 * - bits 15..8 are the last value of the status register.
150 * - bits 7..0 are the expected value of the status register.
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151 */
152
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153#define MVTWSI_ERROR_WRONG_STATUS 0x01
154#define MVTWSI_ERROR_TIMEOUT 0x02
4ce5a728 155
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156#define MVTWSI_ERROR(ec, lc, ls, es) (((ec << 24) & 0xFF000000) | \
157 ((lc << 16) & 0x00FF0000) | ((ls<<8) & 0x0000FF00) | (es & 0xFF))
4ce5a728 158
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159/*
160 * Wait for IFLG to raise, or return 'timeout'; then if status is as expected,
161 * return 0 (ok) or return 'wrong status'.
162 */
dd82242b 163static int twsi_wait(struct i2c_adapter *adap, int expected_status)
306563a7 164{
dd82242b 165 struct mvtwsi_registers *twsi = twsi_get_base(adap);
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166 int control, status;
167 int timeout = 1000;
168
169 do {
170 control = readl(&twsi->control);
171 if (control & MVTWSI_CONTROL_IFLG) {
172 status = readl(&twsi->status);
173 if (status == expected_status)
174 return 0;
175 else
176 return MVTWSI_ERROR(
177 MVTWSI_ERROR_WRONG_STATUS,
178 control, status, expected_status);
4ce5a728 179 }
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180 udelay(10); /* one clock cycle at 100 kHz */
181 } while (timeout--);
182 status = readl(&twsi->status);
183 return MVTWSI_ERROR(
184 MVTWSI_ERROR_TIMEOUT, control, status, expected_status);
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185}
186
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187/*
188 * Assert the START condition, either in a single I2C transaction
189 * or inside back-to-back ones (repeated starts).
190 */
d6b7757e 191static int twsi_start(struct i2c_adapter *adap, int expected_status, u8 *flags)
4ce5a728 192{
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193 struct mvtwsi_registers *twsi = twsi_get_base(adap);
194
306563a7 195 /* globally set TWSIEN in case it was not */
d6b7757e 196 *flags |= MVTWSI_CONTROL_TWSIEN;
306563a7 197 /* assert START */
d6b7757e 198 writel(*flags | MVTWSI_CONTROL_START |
2ca02995 199 MVTWSI_CONTROL_CLEAR_IFLG, &twsi->control);
306563a7 200 /* wait for controller to process START */
dd82242b 201 return twsi_wait(adap, expected_status);
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202}
203
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204/*
205 * Send a byte (i2c address or data).
206 */
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207static int twsi_send(struct i2c_adapter *adap, u8 byte, int expected_status,
208 u8 *flags)
4ce5a728 209{
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210 struct mvtwsi_registers *twsi = twsi_get_base(adap);
211
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212 /* put byte in data register for sending */
213 writel(byte, &twsi->data);
214 /* clear any pending interrupt -- that'll cause sending */
d6b7757e 215 writel(*flags | MVTWSI_CONTROL_CLEAR_IFLG, &twsi->control);
306563a7 216 /* wait for controller to receive byte and check ACK */
dd82242b 217 return twsi_wait(adap, expected_status);
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218}
219
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220/*
221 * Receive a byte.
222 * Global mvtwsi_control_flags variable says if we should ack or nak.
223 */
d6b7757e 224static int twsi_recv(struct i2c_adapter *adap, u8 *byte, u8 *flags)
4ce5a728 225{
dd82242b 226 struct mvtwsi_registers *twsi = twsi_get_base(adap);
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227 int expected_status, status;
228
229 /* compute expected status based on ACK bit in global control flags */
d6b7757e 230 if (*flags & MVTWSI_CONTROL_ACK)
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231 expected_status = MVTWSI_STATUS_DATA_R_ACK;
232 else
233 expected_status = MVTWSI_STATUS_DATA_R_NAK;
234 /* acknowledge *previous state* and launch receive */
d6b7757e 235 writel(*flags | MVTWSI_CONTROL_CLEAR_IFLG, &twsi->control);
306563a7 236 /* wait for controller to receive byte and assert ACK or NAK */
dd82242b 237 status = twsi_wait(adap, expected_status);
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238 /* if we did receive expected byte then store it */
239 if (status == 0)
240 *byte = readl(&twsi->data);
241 /* return status */
242 return status;
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243}
244
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245/*
246 * Assert the STOP condition.
247 * This is also used to force the bus back in idle (SDA=SCL=1).
248 */
dd82242b 249static int twsi_stop(struct i2c_adapter *adap, int status)
4ce5a728 250{
dd82242b 251 struct mvtwsi_registers *twsi = twsi_get_base(adap);
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252 int control, stop_status;
253 int timeout = 1000;
254
255 /* assert STOP */
256 control = MVTWSI_CONTROL_TWSIEN | MVTWSI_CONTROL_STOP;
904dfbfd 257 writel(control | MVTWSI_CONTROL_CLEAR_IFLG, &twsi->control);
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258 /* wait for IDLE; IFLG won't rise so twsi_wait() is no use. */
259 do {
260 stop_status = readl(&twsi->status);
261 if (stop_status == MVTWSI_STATUS_IDLE)
262 break;
263 udelay(10); /* one clock cycle at 100 kHz */
264 } while (timeout--);
265 control = readl(&twsi->control);
266 if (stop_status != MVTWSI_STATUS_IDLE)
267 if (status == 0)
268 status = MVTWSI_ERROR(
269 MVTWSI_ERROR_TIMEOUT,
270 control, status, MVTWSI_STATUS_IDLE);
271 return status;
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272}
273
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274static unsigned int twsi_calc_freq(const int n, const int m)
275{
276#ifdef CONFIG_SUNXI
277 return CONFIG_SYS_TCLK / (10 * (m + 1) * (1 << n));
278#else
279 return CONFIG_SYS_TCLK / (10 * (m + 1) * (2 << n));
280#endif
281}
306563a7 282
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283/*
284 * Reset controller.
306563a7 285 * Controller reset also resets the baud rate and slave address, so
0db2bbdc 286 * they must be re-established afterwards.
306563a7 287 */
0db2bbdc 288static void twsi_reset(struct i2c_adapter *adap)
306563a7 289{
dd82242b 290 struct mvtwsi_registers *twsi = twsi_get_base(adap);
d6b7757e 291
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292 /* reset controller */
293 writel(0, &twsi->soft_reset);
294 /* wait 2 ms -- this is what the Marvell LSP does */
295 udelay(20000);
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296}
297
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298/*
299 * I2C init called by cmd_i2c when doing 'i2c reset'.
300 * Sets baud to the highest possible value not exceeding requested one.
301 */
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302static unsigned int twsi_i2c_set_bus_speed(struct i2c_adapter *adap,
303 unsigned int requested_speed)
4ce5a728 304{
dd82242b 305 struct mvtwsi_registers *twsi = twsi_get_base(adap);
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306 unsigned int tmp_speed, highest_speed, n, m;
307 unsigned int baud = 0x44; /* baudrate at controller reset */
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308
309 /* use actual speed to collect progressively higher values */
310 highest_speed = 0;
311 /* compute m, n setting for highest speed not above requested speed */
312 for (n = 0; n < 8; n++) {
313 for (m = 0; m < 16; m++) {
f582a158 314 tmp_speed = twsi_calc_freq(n, m);
9ec43b0c 315 if ((tmp_speed <= requested_speed) &&
316 (tmp_speed > highest_speed)) {
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317 highest_speed = tmp_speed;
318 baud = (m << 3) | n;
319 }
320 }
4ce5a728 321 }
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322 writel(baud, &twsi->baudrate);
323 return 0;
324}
325
326static void twsi_i2c_init(struct i2c_adapter *adap, int speed, int slaveadd)
327{
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328 struct mvtwsi_registers *twsi = twsi_get_base(adap);
329
306563a7 330 /* reset controller */
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331 twsi_reset(adap);
332 /* set speed */
333 twsi_i2c_set_bus_speed(adap, speed);
334 /* set slave address even though we don't use it */
335 writel(slaveadd, &twsi->slave_address);
336 writel(0, &twsi->xtnd_slave_addr);
337 /* assert STOP but don't care for the result */
dd82242b 338 (void) twsi_stop(adap, 0);
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339}
340
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341/*
342 * Begin I2C transaction with expected start status, at given address.
343 * Common to i2c_probe, i2c_read and i2c_write.
344 * Expected address status will derive from direction bit (bit 0) in addr.
345 */
dd82242b 346static int i2c_begin(struct i2c_adapter *adap, int expected_start_status,
d6b7757e 347 u8 addr, u8 *flags)
4ce5a728 348{
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349 int status, expected_addr_status;
350
351 /* compute expected address status from direction bit in addr */
352 if (addr & 1) /* reading */
353 expected_addr_status = MVTWSI_STATUS_ADDR_R_ACK;
354 else /* writing */
355 expected_addr_status = MVTWSI_STATUS_ADDR_W_ACK;
356 /* assert START */
d6b7757e 357 status = twsi_start(adap, expected_start_status, flags);
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358 /* send out the address if the start went well */
359 if (status == 0)
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360 status = twsi_send(adap, addr, expected_addr_status,
361 flags);
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362 /* return ok or status of first failure to caller */
363 return status;
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364}
365
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366/*
367 * I2C probe called by cmd_i2c when doing 'i2c probe'.
368 * Begin read, nak data byte, end.
369 */
0db2bbdc 370static int twsi_i2c_probe(struct i2c_adapter *adap, uchar chip)
4ce5a728 371{
306563a7 372 u8 dummy_byte;
d6b7757e 373 u8 flags = 0;
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374 int status;
375
376 /* begin i2c read */
d6b7757e 377 status = i2c_begin(adap, MVTWSI_STATUS_START, (chip << 1) | 1, &flags);
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378 /* dummy read was accepted: receive byte but NAK it. */
379 if (status == 0)
d6b7757e 380 status = twsi_recv(adap, &dummy_byte, &flags);
306563a7 381 /* Stop transaction */
dd82242b 382 twsi_stop(adap, 0);
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383 /* return 0 or status of first failure */
384 return status;
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385}
386
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387/*
388 * I2C read called by cmd_i2c when doing 'i2c read' and by cmd_eeprom.c
389 * Begin write, send address byte(s), begin read, receive data bytes, end.
390 *
391 * NOTE: some EEPROMS want a stop right before the second start, while
392 * some will choke if it is there. Deciding which we should do is eeprom
393 * stuff, not i2c, but at the moment the APIs won't let us put it in
394 * cmd_eeprom, so we have to choose here, and for the moment that'll be
395 * a repeated start without a preceding stop.
396 */
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397static int twsi_i2c_read(struct i2c_adapter *adap, uchar chip, uint addr,
398 int alen, uchar *data, int length)
4ce5a728 399{
306563a7 400 int status;
d6b7757e 401 u8 flags = 0;
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402
403 /* begin i2c write to send the address bytes */
d6b7757e 404 status = i2c_begin(adap, MVTWSI_STATUS_START, (chip << 1), &flags);
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405 /* send addr bytes */
406 while ((status == 0) && alen--)
dd82242b 407 status = twsi_send(adap, addr >> (8*alen),
d6b7757e 408 MVTWSI_STATUS_DATA_W_ACK, &flags);
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409 /* begin i2c read to receive eeprom data bytes */
410 if (status == 0)
dd82242b 411 status = i2c_begin(adap, MVTWSI_STATUS_REPEATED_START,
d6b7757e 412 (chip << 1) | 1, &flags);
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413 /* prepare ACK if at least one byte must be received */
414 if (length > 0)
d6b7757e 415 flags |= MVTWSI_CONTROL_ACK;
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416 /* now receive actual bytes */
417 while ((status == 0) && length--) {
418 /* reset NAK if we if no more to read now */
419 if (length == 0)
d6b7757e 420 flags &= ~MVTWSI_CONTROL_ACK;
306563a7 421 /* read current byte */
d6b7757e 422 status = twsi_recv(adap, data++, &flags);
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423 }
424 /* Stop transaction */
dd82242b 425 status = twsi_stop(adap, status);
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426 /* return 0 or status of first failure */
427 return status;
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428}
429
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430/*
431 * I2C write called by cmd_i2c when doing 'i2c write' and by cmd_eeprom.c
432 * Begin write, send address byte(s), send data bytes, end.
433 */
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434static int twsi_i2c_write(struct i2c_adapter *adap, uchar chip, uint addr,
435 int alen, uchar *data, int length)
4ce5a728 436{
306563a7 437 int status;
d6b7757e 438 u8 flags = 0;
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439
440 /* begin i2c write to send the eeprom adress bytes then data bytes */
d6b7757e 441 status = i2c_begin(adap, MVTWSI_STATUS_START, (chip << 1), &flags);
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442 /* send addr bytes */
443 while ((status == 0) && alen--)
dd82242b 444 status = twsi_send(adap, addr >> (8*alen),
d6b7757e 445 MVTWSI_STATUS_DATA_W_ACK, &flags);
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446 /* send data bytes */
447 while ((status == 0) && (length-- > 0))
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448 status = twsi_send(adap, *(data++), MVTWSI_STATUS_DATA_W_ACK,
449 &flags);
306563a7 450 /* Stop transaction */
dd82242b 451 status = twsi_stop(adap, status);
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452 /* return 0 or status of first failure */
453 return status;
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454}
455
dd82242b 456#ifdef CONFIG_I2C_MVTWSI_BASE0
0db2bbdc
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457U_BOOT_I2C_ADAP_COMPLETE(twsi0, twsi_i2c_init, twsi_i2c_probe,
458 twsi_i2c_read, twsi_i2c_write,
459 twsi_i2c_set_bus_speed,
460 CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE, 0)
dd82242b
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461#endif
462#ifdef CONFIG_I2C_MVTWSI_BASE1
463U_BOOT_I2C_ADAP_COMPLETE(twsi1, twsi_i2c_init, twsi_i2c_probe,
464 twsi_i2c_read, twsi_i2c_write,
465 twsi_i2c_set_bus_speed,
466 CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE, 1)
467
468#endif
469#ifdef CONFIG_I2C_MVTWSI_BASE2
470U_BOOT_I2C_ADAP_COMPLETE(twsi2, twsi_i2c_init, twsi_i2c_probe,
471 twsi_i2c_read, twsi_i2c_write,
472 twsi_i2c_set_bus_speed,
473 CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE, 2)
474
475#endif
476#ifdef CONFIG_I2C_MVTWSI_BASE3
477U_BOOT_I2C_ADAP_COMPLETE(twsi3, twsi_i2c_init, twsi_i2c_probe,
478 twsi_i2c_read, twsi_i2c_write,
479 twsi_i2c_set_bus_speed,
480 CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE, 3)
481
482#endif
483#ifdef CONFIG_I2C_MVTWSI_BASE4
484U_BOOT_I2C_ADAP_COMPLETE(twsi4, twsi_i2c_init, twsi_i2c_probe,
485 twsi_i2c_read, twsi_i2c_write,
486 twsi_i2c_set_bus_speed,
487 CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE, 4)
488
489#endif
9d082687
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490#ifdef CONFIG_I2C_MVTWSI_BASE5
491U_BOOT_I2C_ADAP_COMPLETE(twsi5, twsi_i2c_init, twsi_i2c_probe,
492 twsi_i2c_read, twsi_i2c_write,
493 twsi_i2c_set_bus_speed,
494 CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE, 5)
495
496#endif