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4ce5a728 | 1 | /* |
306563a7 AA |
2 | * Driver for the TWSI (i2c) controller found on the Marvell |
3 | * orion5x and kirkwood SoC families. | |
4ce5a728 | 4 | * |
57b4bce9 | 5 | * Author: Albert Aribaud <albert.u.boot@aribaud.net> |
306563a7 | 6 | * Copyright (c) 2010 Albert Aribaud. |
4ce5a728 | 7 | * |
1a459660 | 8 | * SPDX-License-Identifier: GPL-2.0+ |
4ce5a728 | 9 | */ |
306563a7 | 10 | |
4ce5a728 HS |
11 | #include <common.h> |
12 | #include <i2c.h> | |
1221ce45 | 13 | #include <linux/errno.h> |
4ce5a728 | 14 | #include <asm/io.h> |
c68c6243 | 15 | #include <linux/compat.h> |
14a6ff2c | 16 | #ifdef CONFIG_DM_I2C |
17 | #include <dm.h> | |
18 | #endif | |
19 | ||
20 | DECLARE_GLOBAL_DATA_PTR; | |
4ce5a728 | 21 | |
306563a7 | 22 | /* |
49c801bf | 23 | * Include a file that will provide CONFIG_I2C_MVTWSI_BASE*, and possibly other |
24 | * settings | |
306563a7 | 25 | */ |
4ce5a728 | 26 | |
14a6ff2c | 27 | #ifndef CONFIG_DM_I2C |
306563a7 AA |
28 | #if defined(CONFIG_ORION5X) |
29 | #include <asm/arch/orion5x.h> | |
81e33f4b | 30 | #elif (defined(CONFIG_KIRKWOOD) || defined(CONFIG_ARCH_MVEBU)) |
3dc23f78 | 31 | #include <asm/arch/soc.h> |
aec9a0f1 | 32 | #elif defined(CONFIG_ARCH_SUNXI) |
6620377e | 33 | #include <asm/arch/i2c.h> |
306563a7 AA |
34 | #else |
35 | #error Driver mvtwsi not supported by SoC or board | |
4ce5a728 | 36 | #endif |
14a6ff2c | 37 | #endif /* CONFIG_DM_I2C */ |
4ce5a728 | 38 | |
a8f01ccf JS |
39 | /* |
40 | * On SUNXI, we get CONFIG_SYS_TCLK from this include, so we want to | |
41 | * always have it. | |
42 | */ | |
43 | #if defined(CONFIG_DM_I2C) && defined(CONFIG_ARCH_SUNXI) | |
44 | #include <asm/arch/i2c.h> | |
45 | #endif | |
46 | ||
306563a7 AA |
47 | /* |
48 | * TWSI register structure | |
49 | */ | |
4ce5a728 | 50 | |
aec9a0f1 | 51 | #ifdef CONFIG_ARCH_SUNXI |
6620377e HG |
52 | |
53 | struct mvtwsi_registers { | |
54 | u32 slave_address; | |
55 | u32 xtnd_slave_addr; | |
56 | u32 data; | |
57 | u32 control; | |
58 | u32 status; | |
59 | u32 baudrate; | |
60 | u32 soft_reset; | |
61 | }; | |
62 | ||
63 | #else | |
64 | ||
306563a7 AA |
65 | struct mvtwsi_registers { |
66 | u32 slave_address; | |
67 | u32 data; | |
68 | u32 control; | |
69 | union { | |
49c801bf | 70 | u32 status; /* When reading */ |
71 | u32 baudrate; /* When writing */ | |
306563a7 AA |
72 | }; |
73 | u32 xtnd_slave_addr; | |
74 | u32 reserved[2]; | |
75 | u32 soft_reset; | |
4ce5a728 HS |
76 | }; |
77 | ||
6620377e HG |
78 | #endif |
79 | ||
14a6ff2c | 80 | #ifdef CONFIG_DM_I2C |
81 | struct mvtwsi_i2c_dev { | |
82 | /* TWSI Register base for the device */ | |
83 | struct mvtwsi_registers *base; | |
84 | /* Number of the device (determined from cell-index property) */ | |
85 | int index; | |
86 | /* The I2C slave address for the device */ | |
87 | u8 slaveadd; | |
88 | /* The configured I2C speed in Hz */ | |
89 | uint speed; | |
c68c6243 | 90 | /* The current length of a clock period (depending on speed) */ |
91 | uint tick; | |
14a6ff2c | 92 | }; |
93 | #endif /* CONFIG_DM_I2C */ | |
94 | ||
306563a7 | 95 | /* |
dfc3958c | 96 | * enum mvtwsi_ctrl_register_fields - Bit masks for flags in the control |
97 | * register | |
306563a7 | 98 | */ |
dfc3958c | 99 | enum mvtwsi_ctrl_register_fields { |
100 | /* Acknowledge bit */ | |
101 | MVTWSI_CONTROL_ACK = 0x00000004, | |
102 | /* Interrupt flag */ | |
103 | MVTWSI_CONTROL_IFLG = 0x00000008, | |
104 | /* Stop bit */ | |
105 | MVTWSI_CONTROL_STOP = 0x00000010, | |
106 | /* Start bit */ | |
107 | MVTWSI_CONTROL_START = 0x00000020, | |
108 | /* I2C enable */ | |
109 | MVTWSI_CONTROL_TWSIEN = 0x00000040, | |
110 | /* Interrupt enable */ | |
111 | MVTWSI_CONTROL_INTEN = 0x00000080, | |
112 | }; | |
4ce5a728 | 113 | |
904dfbfd | 114 | /* |
49c801bf | 115 | * On sun6i and newer, IFLG is a write-clear bit, which is cleared by writing 1; |
116 | * on other platforms, it is a normal r/w bit, which is cleared by writing 0. | |
904dfbfd HG |
117 | */ |
118 | ||
119 | #ifdef CONFIG_SUNXI_GEN_SUN6I | |
120 | #define MVTWSI_CONTROL_CLEAR_IFLG 0x00000008 | |
121 | #else | |
122 | #define MVTWSI_CONTROL_CLEAR_IFLG 0x00000000 | |
123 | #endif | |
124 | ||
306563a7 | 125 | /* |
dfc3958c | 126 | * enum mvstwsi_status_values - Possible values of I2C controller's status |
127 | * register | |
128 | * | |
129 | * Only those statuses expected in normal master operation on | |
130 | * non-10-bit-address devices are specified. | |
131 | * | |
132 | * Every status that's unexpected during normal operation (bus errors, | |
133 | * arbitration losses, missing ACKs...) is passed back to the caller as an error | |
306563a7 AA |
134 | * code. |
135 | */ | |
dfc3958c | 136 | enum mvstwsi_status_values { |
137 | /* START condition transmitted */ | |
138 | MVTWSI_STATUS_START = 0x08, | |
139 | /* Repeated START condition transmitted */ | |
140 | MVTWSI_STATUS_REPEATED_START = 0x10, | |
141 | /* Address + write bit transmitted, ACK received */ | |
142 | MVTWSI_STATUS_ADDR_W_ACK = 0x18, | |
143 | /* Data transmitted, ACK received */ | |
144 | MVTWSI_STATUS_DATA_W_ACK = 0x28, | |
145 | /* Address + read bit transmitted, ACK received */ | |
146 | MVTWSI_STATUS_ADDR_R_ACK = 0x40, | |
147 | /* Address + read bit transmitted, ACK not received */ | |
148 | MVTWSI_STATUS_ADDR_R_NAK = 0x48, | |
149 | /* Data received, ACK transmitted */ | |
150 | MVTWSI_STATUS_DATA_R_ACK = 0x50, | |
151 | /* Data received, ACK not transmitted */ | |
152 | MVTWSI_STATUS_DATA_R_NAK = 0x58, | |
153 | /* No relevant status */ | |
154 | MVTWSI_STATUS_IDLE = 0xF8, | |
155 | }; | |
306563a7 | 156 | |
670514f5 | 157 | /* |
158 | * enum mvstwsi_ack_flags - Determine whether a read byte should be | |
159 | * acknowledged or not. | |
160 | */ | |
161 | enum mvtwsi_ack_flags { | |
162 | /* Send NAK after received byte */ | |
163 | MVTWSI_READ_NAK = 0, | |
164 | /* Send ACK after received byte */ | |
165 | MVTWSI_READ_ACK = 1, | |
166 | }; | |
167 | ||
6e677caf | 168 | /* |
169 | * calc_tick() - Calculate the duration of a clock cycle from the I2C speed | |
170 | * | |
171 | * @speed: The speed in Hz to calculate the clock cycle duration for. | |
172 | * @return The duration of a clock cycle in ns. | |
173 | */ | |
c68c6243 | 174 | inline uint calc_tick(uint speed) |
175 | { | |
176 | /* One tick = the duration of a period at the specified speed in ns (we | |
177 | * add 100 ns to be on the safe side) */ | |
178 | return (1000000000u / speed) + 100; | |
179 | } | |
180 | ||
14a6ff2c | 181 | #ifndef CONFIG_DM_I2C |
c68c6243 | 182 | |
306563a7 | 183 | /* |
6e677caf | 184 | * twsi_get_base() - Get controller register base for specified adapter |
185 | * | |
186 | * @adap: Adapter to get the register base for. | |
187 | * @return Register base for the specified adapter. | |
306563a7 | 188 | */ |
dd82242b PK |
189 | static struct mvtwsi_registers *twsi_get_base(struct i2c_adapter *adap) |
190 | { | |
191 | switch (adap->hwadapnr) { | |
192 | #ifdef CONFIG_I2C_MVTWSI_BASE0 | |
193 | case 0: | |
9ec43b0c | 194 | return (struct mvtwsi_registers *)CONFIG_I2C_MVTWSI_BASE0; |
dd82242b PK |
195 | #endif |
196 | #ifdef CONFIG_I2C_MVTWSI_BASE1 | |
197 | case 1: | |
9ec43b0c | 198 | return (struct mvtwsi_registers *)CONFIG_I2C_MVTWSI_BASE1; |
dd82242b PK |
199 | #endif |
200 | #ifdef CONFIG_I2C_MVTWSI_BASE2 | |
201 | case 2: | |
9ec43b0c | 202 | return (struct mvtwsi_registers *)CONFIG_I2C_MVTWSI_BASE2; |
dd82242b PK |
203 | #endif |
204 | #ifdef CONFIG_I2C_MVTWSI_BASE3 | |
205 | case 3: | |
9ec43b0c | 206 | return (struct mvtwsi_registers *)CONFIG_I2C_MVTWSI_BASE3; |
dd82242b PK |
207 | #endif |
208 | #ifdef CONFIG_I2C_MVTWSI_BASE4 | |
209 | case 4: | |
9ec43b0c | 210 | return (struct mvtwsi_registers *)CONFIG_I2C_MVTWSI_BASE4; |
9d082687 JW |
211 | #endif |
212 | #ifdef CONFIG_I2C_MVTWSI_BASE5 | |
213 | case 5: | |
9ec43b0c | 214 | return (struct mvtwsi_registers *)CONFIG_I2C_MVTWSI_BASE5; |
dd82242b PK |
215 | #endif |
216 | default: | |
217 | printf("Missing mvtwsi controller %d base\n", adap->hwadapnr); | |
218 | break; | |
219 | } | |
220 | ||
221 | return NULL; | |
222 | } | |
14a6ff2c | 223 | #endif |
4ce5a728 HS |
224 | |
225 | /* | |
dfc3958c | 226 | * enum mvtwsi_error_class - types of I2C errors |
4ce5a728 | 227 | */ |
dfc3958c | 228 | enum mvtwsi_error_class { |
229 | /* The controller returned a different status than expected */ | |
230 | MVTWSI_ERROR_WRONG_STATUS = 0x01, | |
231 | /* The controller timed out */ | |
232 | MVTWSI_ERROR_TIMEOUT = 0x02, | |
233 | }; | |
4ce5a728 | 234 | |
dfc3958c | 235 | /* |
236 | * mvtwsi_error() - Build I2C return code from error information | |
237 | * | |
238 | * For debugging purposes, this function packs some information of an occurred | |
239 | * error into a return code. These error codes are returned from I2C API | |
240 | * functions (i2c_{read,write}, dm_i2c_{read,write}, etc.). | |
241 | * | |
242 | * @ec: The error class of the error (enum mvtwsi_error_class). | |
243 | * @lc: The last value of the control register. | |
244 | * @ls: The last value of the status register. | |
245 | * @es: The expected value of the status register. | |
246 | * @return The generated error code. | |
247 | */ | |
248 | inline uint mvtwsi_error(uint ec, uint lc, uint ls, uint es) | |
249 | { | |
250 | return ((ec << 24) & 0xFF000000) | |
251 | | ((lc << 16) & 0x00FF0000) | |
252 | | ((ls << 8) & 0x0000FF00) | |
253 | | (es & 0xFF); | |
254 | } | |
4ce5a728 | 255 | |
306563a7 | 256 | /* |
6e677caf | 257 | * twsi_wait() - Wait for I2C bus interrupt flag and check status, or time out. |
258 | * | |
259 | * @return Zero if status is as expected, or a non-zero code if either a time | |
260 | * out occurred, or the status was not the expected one. | |
306563a7 | 261 | */ |
c68c6243 | 262 | static int twsi_wait(struct mvtwsi_registers *twsi, int expected_status, |
263 | uint tick) | |
306563a7 AA |
264 | { |
265 | int control, status; | |
266 | int timeout = 1000; | |
267 | ||
268 | do { | |
269 | control = readl(&twsi->control); | |
270 | if (control & MVTWSI_CONTROL_IFLG) { | |
271 | status = readl(&twsi->status); | |
272 | if (status == expected_status) | |
273 | return 0; | |
274 | else | |
dfc3958c | 275 | return mvtwsi_error( |
306563a7 AA |
276 | MVTWSI_ERROR_WRONG_STATUS, |
277 | control, status, expected_status); | |
4ce5a728 | 278 | } |
c68c6243 | 279 | ndelay(tick); /* One clock cycle */ |
306563a7 AA |
280 | } while (timeout--); |
281 | status = readl(&twsi->status); | |
dfc3958c | 282 | return mvtwsi_error(MVTWSI_ERROR_TIMEOUT, control, status, |
283 | expected_status); | |
4ce5a728 HS |
284 | } |
285 | ||
306563a7 | 286 | /* |
6e677caf | 287 | * twsi_start() - Assert a START condition on the bus. |
288 | * | |
289 | * This function is used in both single I2C transactions and inside | |
290 | * back-to-back transactions (repeated starts). | |
291 | * | |
292 | * @twsi: The MVTWSI register structure to use. | |
293 | * @expected_status: The I2C bus status expected to be asserted after the | |
294 | * operation completion. | |
295 | * @tick: The duration of a clock cycle at the current I2C speed. | |
296 | * @return Zero if status is as expected, or a non-zero code if either a time | |
297 | * out occurred or the status was not the expected one. | |
306563a7 | 298 | */ |
c68c6243 | 299 | static int twsi_start(struct mvtwsi_registers *twsi, int expected_status, |
300 | uint tick) | |
4ce5a728 | 301 | { |
49c801bf | 302 | /* Assert START */ |
670514f5 | 303 | writel(MVTWSI_CONTROL_TWSIEN | MVTWSI_CONTROL_START | |
49c801bf | 304 | MVTWSI_CONTROL_CLEAR_IFLG, &twsi->control); |
305 | /* Wait for controller to process START */ | |
c68c6243 | 306 | return twsi_wait(twsi, expected_status, tick); |
4ce5a728 HS |
307 | } |
308 | ||
306563a7 | 309 | /* |
6e677caf | 310 | * twsi_send() - Send a byte on the I2C bus. |
311 | * | |
312 | * The byte may be part of an address byte or data. | |
313 | * | |
314 | * @twsi: The MVTWSI register structure to use. | |
315 | * @byte: The byte to send. | |
316 | * @expected_status: The I2C bus status expected to be asserted after the | |
317 | * operation completion. | |
318 | * @tick: The duration of a clock cycle at the current I2C speed. | |
319 | * @return Zero if status is as expected, or a non-zero code if either a time | |
320 | * out occurred or the status was not the expected one. | |
306563a7 | 321 | */ |
3c4db636 | 322 | static int twsi_send(struct mvtwsi_registers *twsi, u8 byte, |
c68c6243 | 323 | int expected_status, uint tick) |
4ce5a728 | 324 | { |
49c801bf | 325 | /* Write byte to data register for sending */ |
306563a7 | 326 | writel(byte, &twsi->data); |
49c801bf | 327 | /* Clear any pending interrupt -- that will cause sending */ |
670514f5 | 328 | writel(MVTWSI_CONTROL_TWSIEN | MVTWSI_CONTROL_CLEAR_IFLG, |
329 | &twsi->control); | |
49c801bf | 330 | /* Wait for controller to receive byte, and check ACK */ |
c68c6243 | 331 | return twsi_wait(twsi, expected_status, tick); |
4ce5a728 HS |
332 | } |
333 | ||
306563a7 | 334 | /* |
6e677caf | 335 | * twsi_recv() - Receive a byte on the I2C bus. |
336 | * | |
337 | * The static variable mvtwsi_control_flags controls whether we ack or nak. | |
338 | * | |
339 | * @twsi: The MVTWSI register structure to use. | |
340 | * @byte: The byte to send. | |
341 | * @ack_flag: Flag that determines whether the received byte should | |
342 | * be acknowledged by the controller or not (sent ACK/NAK). | |
343 | * @tick: The duration of a clock cycle at the current I2C speed. | |
344 | * @return Zero if status is as expected, or a non-zero code if either a time | |
345 | * out occurred or the status was not the expected one. | |
306563a7 | 346 | */ |
c68c6243 | 347 | static int twsi_recv(struct mvtwsi_registers *twsi, u8 *byte, int ack_flag, |
348 | uint tick) | |
4ce5a728 | 349 | { |
670514f5 | 350 | int expected_status, status, control; |
306563a7 | 351 | |
670514f5 | 352 | /* Compute expected status based on passed ACK flag */ |
353 | expected_status = ack_flag ? MVTWSI_STATUS_DATA_R_ACK : | |
354 | MVTWSI_STATUS_DATA_R_NAK; | |
49c801bf | 355 | /* Acknowledge *previous state*, and launch receive */ |
670514f5 | 356 | control = MVTWSI_CONTROL_TWSIEN; |
357 | control |= ack_flag == MVTWSI_READ_ACK ? MVTWSI_CONTROL_ACK : 0; | |
358 | writel(control | MVTWSI_CONTROL_CLEAR_IFLG, &twsi->control); | |
49c801bf | 359 | /* Wait for controller to receive byte, and assert ACK or NAK */ |
c68c6243 | 360 | status = twsi_wait(twsi, expected_status, tick); |
49c801bf | 361 | /* If we did receive the expected byte, store it */ |
306563a7 AA |
362 | if (status == 0) |
363 | *byte = readl(&twsi->data); | |
306563a7 | 364 | return status; |
4ce5a728 HS |
365 | } |
366 | ||
306563a7 | 367 | /* |
6e677caf | 368 | * twsi_stop() - Assert a STOP condition on the bus. |
369 | * | |
370 | * This function is also used to force the bus back to idle state (SDA = | |
371 | * SCL = 1). | |
372 | * | |
373 | * @twsi: The MVTWSI register structure to use. | |
374 | * @tick: The duration of a clock cycle at the current I2C speed. | |
375 | * @return Zero if the operation succeeded, or a non-zero code if a time out | |
376 | * occurred. | |
306563a7 | 377 | */ |
c68c6243 | 378 | static int twsi_stop(struct mvtwsi_registers *twsi, uint tick) |
4ce5a728 | 379 | { |
306563a7 | 380 | int control, stop_status; |
059fce9f | 381 | int status = 0; |
306563a7 AA |
382 | int timeout = 1000; |
383 | ||
49c801bf | 384 | /* Assert STOP */ |
306563a7 | 385 | control = MVTWSI_CONTROL_TWSIEN | MVTWSI_CONTROL_STOP; |
904dfbfd | 386 | writel(control | MVTWSI_CONTROL_CLEAR_IFLG, &twsi->control); |
49c801bf | 387 | /* Wait for IDLE; IFLG won't rise, so we can't use twsi_wait() */ |
306563a7 AA |
388 | do { |
389 | stop_status = readl(&twsi->status); | |
390 | if (stop_status == MVTWSI_STATUS_IDLE) | |
391 | break; | |
c68c6243 | 392 | ndelay(tick); /* One clock cycle */ |
306563a7 AA |
393 | } while (timeout--); |
394 | control = readl(&twsi->control); | |
395 | if (stop_status != MVTWSI_STATUS_IDLE) | |
059fce9f | 396 | status = mvtwsi_error(MVTWSI_ERROR_TIMEOUT, |
397 | control, status, MVTWSI_STATUS_IDLE); | |
306563a7 | 398 | return status; |
4ce5a728 HS |
399 | } |
400 | ||
6e677caf | 401 | /* |
402 | * twsi_calc_freq() - Compute I2C frequency depending on m and n parameters. | |
403 | * | |
404 | * @n: Parameter 'n' for the frequency calculation algorithm. | |
405 | * @m: Parameter 'm' for the frequency calculation algorithm. | |
406 | * @return The I2C frequency corresponding to the passed m and n parameters. | |
407 | */ | |
e0758281 | 408 | static uint twsi_calc_freq(const int n, const int m) |
f582a158 | 409 | { |
aec9a0f1 | 410 | #ifdef CONFIG_ARCH_SUNXI |
f582a158 SR |
411 | return CONFIG_SYS_TCLK / (10 * (m + 1) * (1 << n)); |
412 | #else | |
413 | return CONFIG_SYS_TCLK / (10 * (m + 1) * (2 << n)); | |
414 | #endif | |
415 | } | |
306563a7 | 416 | |
306563a7 | 417 | /* |
6e677caf | 418 | * twsi_reset() - Reset the I2C controller. |
419 | * | |
420 | * Resetting the controller also resets the baud rate and slave address, hence | |
421 | * they must be re-established after the reset. | |
422 | * | |
423 | * @twsi: The MVTWSI register structure to use. | |
306563a7 | 424 | */ |
3c4db636 | 425 | static void twsi_reset(struct mvtwsi_registers *twsi) |
306563a7 | 426 | { |
49c801bf | 427 | /* Reset controller */ |
306563a7 | 428 | writel(0, &twsi->soft_reset); |
49c801bf | 429 | /* Wait 2 ms -- this is what the Marvell LSP does */ |
306563a7 | 430 | udelay(20000); |
4ce5a728 HS |
431 | } |
432 | ||
306563a7 | 433 | /* |
6e677caf | 434 | * __twsi_i2c_set_bus_speed() - Set the speed of the I2C controller. |
435 | * | |
436 | * This function sets baud rate to the highest possible value that does not | |
437 | * exceed the requested rate. | |
438 | * | |
439 | * @twsi: The MVTWSI register structure to use. | |
440 | * @requested_speed: The desired frequency the controller should run at | |
441 | * in Hz. | |
442 | * @return The actual frequency the controller was configured to. | |
306563a7 | 443 | */ |
3c4db636 | 444 | static uint __twsi_i2c_set_bus_speed(struct mvtwsi_registers *twsi, |
61bc02b2 | 445 | uint requested_speed) |
4ce5a728 | 446 | { |
e0758281 | 447 | uint tmp_speed, highest_speed, n, m; |
448 | uint baud = 0x44; /* Baud rate after controller reset */ | |
306563a7 | 449 | |
306563a7 | 450 | highest_speed = 0; |
49c801bf | 451 | /* Successively try m, n combinations, and use the combination |
452 | * resulting in the largest speed that's not above the requested | |
453 | * speed */ | |
306563a7 AA |
454 | for (n = 0; n < 8; n++) { |
455 | for (m = 0; m < 16; m++) { | |
f582a158 | 456 | tmp_speed = twsi_calc_freq(n, m); |
9ec43b0c | 457 | if ((tmp_speed <= requested_speed) && |
458 | (tmp_speed > highest_speed)) { | |
306563a7 AA |
459 | highest_speed = tmp_speed; |
460 | baud = (m << 3) | n; | |
461 | } | |
462 | } | |
4ce5a728 | 463 | } |
0db2bbdc | 464 | writel(baud, &twsi->baudrate); |
c68c6243 | 465 | |
466 | /* Wait for controller for one tick */ | |
467 | #ifdef CONFIG_DM_I2C | |
468 | ndelay(calc_tick(highest_speed)); | |
469 | #else | |
470 | ndelay(10000); | |
471 | #endif | |
472 | return highest_speed; | |
0db2bbdc HG |
473 | } |
474 | ||
6e677caf | 475 | /* |
476 | * __twsi_i2c_init() - Initialize the I2C controller. | |
477 | * | |
478 | * @twsi: The MVTWSI register structure to use. | |
479 | * @speed: The initial frequency the controller should run at | |
480 | * in Hz. | |
481 | * @slaveadd: The I2C address to be set for the I2C master. | |
482 | * @actual_speed: A output parameter that receives the actual frequency | |
483 | * in Hz the controller was set to by the function. | |
484 | * @return Zero if the operation succeeded, or a non-zero code if a time out | |
485 | * occurred. | |
486 | */ | |
3c4db636 | 487 | static void __twsi_i2c_init(struct mvtwsi_registers *twsi, int speed, |
c68c6243 | 488 | int slaveadd, uint *actual_speed) |
0db2bbdc | 489 | { |
004b4cda SM |
490 | uint tmp_speed; |
491 | ||
49c801bf | 492 | /* Reset controller */ |
3c4db636 | 493 | twsi_reset(twsi); |
49c801bf | 494 | /* Set speed */ |
004b4cda | 495 | tmp_speed = __twsi_i2c_set_bus_speed(twsi, speed); |
8bcf12cc | 496 | if (actual_speed) |
004b4cda | 497 | *actual_speed = tmp_speed; |
49c801bf | 498 | /* Set slave address; even though we don't use it */ |
0db2bbdc HG |
499 | writel(slaveadd, &twsi->slave_address); |
500 | writel(0, &twsi->xtnd_slave_addr); | |
49c801bf | 501 | /* Assert STOP, but don't care for the result */ |
c68c6243 | 502 | #ifdef CONFIG_DM_I2C |
503 | (void) twsi_stop(twsi, calc_tick(*actual_speed)); | |
504 | #else | |
505 | (void) twsi_stop(twsi, 10000); | |
506 | #endif | |
4ce5a728 HS |
507 | } |
508 | ||
306563a7 | 509 | /* |
6e677caf | 510 | * i2c_begin() - Start a I2C transaction. |
511 | * | |
512 | * Begin a I2C transaction with a given expected start status and chip address. | |
513 | * A START is asserted, and the address byte is sent to the I2C controller. The | |
514 | * expected address status will be derived from the direction bit (bit 0) of | |
515 | * the address byte. | |
516 | * | |
517 | * @twsi: The MVTWSI register structure to use. | |
518 | * @expected_start_status: The I2C status the controller is expected to | |
519 | * assert after the address byte was sent. | |
520 | * @addr: The address byte to be sent. | |
521 | * @tick: The duration of a clock cycle at the current | |
522 | * I2C speed. | |
523 | * @return Zero if the operation succeeded, or a non-zero code if a time out or | |
524 | * unexpected I2C status occurred. | |
306563a7 | 525 | */ |
3c4db636 | 526 | static int i2c_begin(struct mvtwsi_registers *twsi, int expected_start_status, |
c68c6243 | 527 | u8 addr, uint tick) |
4ce5a728 | 528 | { |
306563a7 AA |
529 | int status, expected_addr_status; |
530 | ||
49c801bf | 531 | /* Compute the expected address status from the direction bit in |
532 | * the address byte */ | |
533 | if (addr & 1) /* Reading */ | |
306563a7 | 534 | expected_addr_status = MVTWSI_STATUS_ADDR_R_ACK; |
49c801bf | 535 | else /* Writing */ |
306563a7 | 536 | expected_addr_status = MVTWSI_STATUS_ADDR_W_ACK; |
49c801bf | 537 | /* Assert START */ |
c68c6243 | 538 | status = twsi_start(twsi, expected_start_status, tick); |
49c801bf | 539 | /* Send out the address if the start went well */ |
306563a7 | 540 | if (status == 0) |
c68c6243 | 541 | status = twsi_send(twsi, addr, expected_addr_status, tick); |
49c801bf | 542 | /* Return 0, or the status of the first failure */ |
306563a7 | 543 | return status; |
4ce5a728 HS |
544 | } |
545 | ||
306563a7 | 546 | /* |
6e677caf | 547 | * __twsi_i2c_probe_chip() - Probe the given I2C chip address. |
548 | * | |
549 | * This function begins a I2C read transaction, does a dummy read and NAKs; if | |
550 | * the procedure succeeds, the chip is considered to be present. | |
551 | * | |
552 | * @twsi: The MVTWSI register structure to use. | |
553 | * @chip: The chip address to probe. | |
554 | * @tick: The duration of a clock cycle at the current I2C speed. | |
555 | * @return Zero if the operation succeeded, or a non-zero code if a time out or | |
556 | * unexpected I2C status occurred. | |
306563a7 | 557 | */ |
c68c6243 | 558 | static int __twsi_i2c_probe_chip(struct mvtwsi_registers *twsi, uchar chip, |
559 | uint tick) | |
4ce5a728 | 560 | { |
306563a7 AA |
561 | u8 dummy_byte; |
562 | int status; | |
563 | ||
49c801bf | 564 | /* Begin i2c read */ |
c68c6243 | 565 | status = i2c_begin(twsi, MVTWSI_STATUS_START, (chip << 1) | 1, tick); |
49c801bf | 566 | /* Dummy read was accepted: receive byte, but NAK it. */ |
306563a7 | 567 | if (status == 0) |
c68c6243 | 568 | status = twsi_recv(twsi, &dummy_byte, MVTWSI_READ_NAK, tick); |
306563a7 | 569 | /* Stop transaction */ |
c68c6243 | 570 | twsi_stop(twsi, tick); |
49c801bf | 571 | /* Return 0, or the status of the first failure */ |
306563a7 | 572 | return status; |
4ce5a728 HS |
573 | } |
574 | ||
306563a7 | 575 | /* |
6e677caf | 576 | * __twsi_i2c_read() - Read data from a I2C chip. |
577 | * | |
578 | * This function begins a I2C write transaction, and transmits the address | |
579 | * bytes; then begins a I2C read transaction, and receives the data bytes. | |
306563a7 | 580 | * |
49c801bf | 581 | * NOTE: Some devices want a stop right before the second start, while some |
582 | * will choke if it is there. Since deciding this is not yet supported in | |
583 | * higher level APIs, we need to make a decision here, and for the moment that | |
584 | * will be a repeated start without a preceding stop. | |
6e677caf | 585 | * |
586 | * @twsi: The MVTWSI register structure to use. | |
587 | * @chip: The chip address to read from. | |
588 | * @addr: The address bytes to send. | |
589 | * @alen: The length of the address bytes in bytes. | |
590 | * @data: The buffer to receive the data read from the chip (has to have | |
591 | * a size of at least 'length' bytes). | |
592 | * @length: The amount of data to be read from the chip in bytes. | |
593 | * @tick: The duration of a clock cycle at the current I2C speed. | |
594 | * @return Zero if the operation succeeded, or a non-zero code if a time out or | |
595 | * unexpected I2C status occurred. | |
306563a7 | 596 | */ |
3c4db636 | 597 | static int __twsi_i2c_read(struct mvtwsi_registers *twsi, uchar chip, |
c68c6243 | 598 | u8 *addr, int alen, uchar *data, int length, |
599 | uint tick) | |
4ce5a728 | 600 | { |
059fce9f | 601 | int status = 0; |
602 | int stop_status; | |
24f9c6bb | 603 | int expected_start = MVTWSI_STATUS_START; |
604 | ||
605 | if (alen > 0) { | |
606 | /* Begin i2c write to send the address bytes */ | |
c68c6243 | 607 | status = i2c_begin(twsi, expected_start, (chip << 1), tick); |
24f9c6bb | 608 | /* Send address bytes */ |
609 | while ((status == 0) && alen--) | |
03d6cd97 | 610 | status = twsi_send(twsi, addr[alen], |
c68c6243 | 611 | MVTWSI_STATUS_DATA_W_ACK, tick); |
24f9c6bb | 612 | /* Send repeated STARTs after the initial START */ |
613 | expected_start = MVTWSI_STATUS_REPEATED_START; | |
614 | } | |
49c801bf | 615 | /* Begin i2c read to receive data bytes */ |
306563a7 | 616 | if (status == 0) |
c68c6243 | 617 | status = i2c_begin(twsi, expected_start, (chip << 1) | 1, tick); |
670514f5 | 618 | /* Receive actual data bytes; set NAK if we if we have nothing more to |
619 | * read */ | |
620 | while ((status == 0) && length--) | |
3c4db636 | 621 | status = twsi_recv(twsi, data++, |
670514f5 | 622 | length > 0 ? |
c68c6243 | 623 | MVTWSI_READ_ACK : MVTWSI_READ_NAK, tick); |
306563a7 | 624 | /* Stop transaction */ |
c68c6243 | 625 | stop_status = twsi_stop(twsi, tick); |
49c801bf | 626 | /* Return 0, or the status of the first failure */ |
059fce9f | 627 | return status != 0 ? status : stop_status; |
4ce5a728 HS |
628 | } |
629 | ||
306563a7 | 630 | /* |
6e677caf | 631 | * __twsi_i2c_write() - Send data to a I2C chip. |
632 | * | |
633 | * This function begins a I2C write transaction, and transmits the address | |
634 | * bytes; then begins a new I2C write transaction, and sends the data bytes. | |
635 | * | |
636 | * @twsi: The MVTWSI register structure to use. | |
637 | * @chip: The chip address to read from. | |
638 | * @addr: The address bytes to send. | |
639 | * @alen: The length of the address bytes in bytes. | |
640 | * @data: The buffer containing the data to be sent to the chip. | |
641 | * @length: The length of data to be sent to the chip in bytes. | |
642 | * @tick: The duration of a clock cycle at the current I2C speed. | |
643 | * @return Zero if the operation succeeded, or a non-zero code if a time out or | |
644 | * unexpected I2C status occurred. | |
306563a7 | 645 | */ |
3c4db636 | 646 | static int __twsi_i2c_write(struct mvtwsi_registers *twsi, uchar chip, |
c68c6243 | 647 | u8 *addr, int alen, uchar *data, int length, |
648 | uint tick) | |
4ce5a728 | 649 | { |
059fce9f | 650 | int status, stop_status; |
306563a7 | 651 | |
49c801bf | 652 | /* Begin i2c write to send first the address bytes, then the |
653 | * data bytes */ | |
c68c6243 | 654 | status = i2c_begin(twsi, MVTWSI_STATUS_START, (chip << 1), tick); |
49c801bf | 655 | /* Send address bytes */ |
f8a10ed1 | 656 | while ((status == 0) && (alen-- > 0)) |
03d6cd97 | 657 | status = twsi_send(twsi, addr[alen], MVTWSI_STATUS_DATA_W_ACK, |
c68c6243 | 658 | tick); |
49c801bf | 659 | /* Send data bytes */ |
306563a7 | 660 | while ((status == 0) && (length-- > 0)) |
c68c6243 | 661 | status = twsi_send(twsi, *(data++), MVTWSI_STATUS_DATA_W_ACK, |
662 | tick); | |
306563a7 | 663 | /* Stop transaction */ |
c68c6243 | 664 | stop_status = twsi_stop(twsi, tick); |
49c801bf | 665 | /* Return 0, or the status of the first failure */ |
059fce9f | 666 | return status != 0 ? status : stop_status; |
4ce5a728 HS |
667 | } |
668 | ||
14a6ff2c | 669 | #ifndef CONFIG_DM_I2C |
61bc02b2 | 670 | static void twsi_i2c_init(struct i2c_adapter *adap, int speed, |
671 | int slaveadd) | |
672 | { | |
3c4db636 | 673 | struct mvtwsi_registers *twsi = twsi_get_base(adap); |
c68c6243 | 674 | __twsi_i2c_init(twsi, speed, slaveadd, NULL); |
61bc02b2 | 675 | } |
676 | ||
677 | static uint twsi_i2c_set_bus_speed(struct i2c_adapter *adap, | |
678 | uint requested_speed) | |
679 | { | |
3c4db636 | 680 | struct mvtwsi_registers *twsi = twsi_get_base(adap); |
c68c6243 | 681 | __twsi_i2c_set_bus_speed(twsi, requested_speed); |
682 | return 0; | |
61bc02b2 | 683 | } |
684 | ||
685 | static int twsi_i2c_probe(struct i2c_adapter *adap, uchar chip) | |
686 | { | |
3c4db636 | 687 | struct mvtwsi_registers *twsi = twsi_get_base(adap); |
c68c6243 | 688 | return __twsi_i2c_probe_chip(twsi, chip, 10000); |
61bc02b2 | 689 | } |
690 | ||
691 | static int twsi_i2c_read(struct i2c_adapter *adap, uchar chip, uint addr, | |
692 | int alen, uchar *data, int length) | |
693 | { | |
3c4db636 | 694 | struct mvtwsi_registers *twsi = twsi_get_base(adap); |
f8a10ed1 | 695 | u8 addr_bytes[4]; |
696 | ||
697 | addr_bytes[0] = (addr >> 0) & 0xFF; | |
698 | addr_bytes[1] = (addr >> 8) & 0xFF; | |
699 | addr_bytes[2] = (addr >> 16) & 0xFF; | |
700 | addr_bytes[3] = (addr >> 24) & 0xFF; | |
701 | ||
c68c6243 | 702 | return __twsi_i2c_read(twsi, chip, addr_bytes, alen, data, length, |
703 | 10000); | |
61bc02b2 | 704 | } |
705 | ||
706 | static int twsi_i2c_write(struct i2c_adapter *adap, uchar chip, uint addr, | |
707 | int alen, uchar *data, int length) | |
708 | { | |
3c4db636 | 709 | struct mvtwsi_registers *twsi = twsi_get_base(adap); |
f8a10ed1 | 710 | u8 addr_bytes[4]; |
711 | ||
712 | addr_bytes[0] = (addr >> 0) & 0xFF; | |
713 | addr_bytes[1] = (addr >> 8) & 0xFF; | |
714 | addr_bytes[2] = (addr >> 16) & 0xFF; | |
715 | addr_bytes[3] = (addr >> 24) & 0xFF; | |
716 | ||
c68c6243 | 717 | return __twsi_i2c_write(twsi, chip, addr_bytes, alen, data, length, |
718 | 10000); | |
61bc02b2 | 719 | } |
720 | ||
dd82242b | 721 | #ifdef CONFIG_I2C_MVTWSI_BASE0 |
0db2bbdc HG |
722 | U_BOOT_I2C_ADAP_COMPLETE(twsi0, twsi_i2c_init, twsi_i2c_probe, |
723 | twsi_i2c_read, twsi_i2c_write, | |
724 | twsi_i2c_set_bus_speed, | |
725 | CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE, 0) | |
dd82242b PK |
726 | #endif |
727 | #ifdef CONFIG_I2C_MVTWSI_BASE1 | |
728 | U_BOOT_I2C_ADAP_COMPLETE(twsi1, twsi_i2c_init, twsi_i2c_probe, | |
729 | twsi_i2c_read, twsi_i2c_write, | |
730 | twsi_i2c_set_bus_speed, | |
731 | CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE, 1) | |
732 | ||
733 | #endif | |
734 | #ifdef CONFIG_I2C_MVTWSI_BASE2 | |
735 | U_BOOT_I2C_ADAP_COMPLETE(twsi2, twsi_i2c_init, twsi_i2c_probe, | |
736 | twsi_i2c_read, twsi_i2c_write, | |
737 | twsi_i2c_set_bus_speed, | |
738 | CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE, 2) | |
739 | ||
740 | #endif | |
741 | #ifdef CONFIG_I2C_MVTWSI_BASE3 | |
742 | U_BOOT_I2C_ADAP_COMPLETE(twsi3, twsi_i2c_init, twsi_i2c_probe, | |
743 | twsi_i2c_read, twsi_i2c_write, | |
744 | twsi_i2c_set_bus_speed, | |
745 | CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE, 3) | |
746 | ||
747 | #endif | |
748 | #ifdef CONFIG_I2C_MVTWSI_BASE4 | |
749 | U_BOOT_I2C_ADAP_COMPLETE(twsi4, twsi_i2c_init, twsi_i2c_probe, | |
750 | twsi_i2c_read, twsi_i2c_write, | |
751 | twsi_i2c_set_bus_speed, | |
752 | CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE, 4) | |
753 | ||
754 | #endif | |
9d082687 JW |
755 | #ifdef CONFIG_I2C_MVTWSI_BASE5 |
756 | U_BOOT_I2C_ADAP_COMPLETE(twsi5, twsi_i2c_init, twsi_i2c_probe, | |
757 | twsi_i2c_read, twsi_i2c_write, | |
758 | twsi_i2c_set_bus_speed, | |
759 | CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE, 5) | |
760 | ||
761 | #endif | |
14a6ff2c | 762 | #else /* CONFIG_DM_I2C */ |
763 | ||
764 | static int mvtwsi_i2c_probe_chip(struct udevice *bus, u32 chip_addr, | |
765 | u32 chip_flags) | |
766 | { | |
767 | struct mvtwsi_i2c_dev *dev = dev_get_priv(bus); | |
c68c6243 | 768 | return __twsi_i2c_probe_chip(dev->base, chip_addr, dev->tick); |
14a6ff2c | 769 | } |
770 | ||
771 | static int mvtwsi_i2c_set_bus_speed(struct udevice *bus, uint speed) | |
772 | { | |
773 | struct mvtwsi_i2c_dev *dev = dev_get_priv(bus); | |
c68c6243 | 774 | |
775 | dev->speed = __twsi_i2c_set_bus_speed(dev->base, speed); | |
776 | dev->tick = calc_tick(dev->speed); | |
777 | ||
778 | return 0; | |
14a6ff2c | 779 | } |
780 | ||
781 | static int mvtwsi_i2c_ofdata_to_platdata(struct udevice *bus) | |
782 | { | |
783 | struct mvtwsi_i2c_dev *dev = dev_get_priv(bus); | |
784 | ||
a821c4af | 785 | dev->base = devfdt_get_addr_ptr(bus); |
14a6ff2c | 786 | |
787 | if (!dev->base) | |
788 | return -ENOMEM; | |
789 | ||
e160f7d4 | 790 | dev->index = fdtdec_get_int(gd->fdt_blob, dev_of_offset(bus), |
14a6ff2c | 791 | "cell-index", -1); |
e160f7d4 | 792 | dev->slaveadd = fdtdec_get_int(gd->fdt_blob, dev_of_offset(bus), |
14a6ff2c | 793 | "u-boot,i2c-slave-addr", 0x0); |
e160f7d4 | 794 | dev->speed = fdtdec_get_int(gd->fdt_blob, dev_of_offset(bus), |
14a6ff2c | 795 | "clock-frequency", 100000); |
796 | return 0; | |
797 | } | |
798 | ||
799 | static int mvtwsi_i2c_probe(struct udevice *bus) | |
800 | { | |
801 | struct mvtwsi_i2c_dev *dev = dev_get_priv(bus); | |
c68c6243 | 802 | uint actual_speed; |
803 | ||
804 | __twsi_i2c_init(dev->base, dev->speed, dev->slaveadd, &actual_speed); | |
805 | dev->speed = actual_speed; | |
806 | dev->tick = calc_tick(dev->speed); | |
14a6ff2c | 807 | return 0; |
808 | } | |
809 | ||
810 | static int mvtwsi_i2c_xfer(struct udevice *bus, struct i2c_msg *msg, int nmsgs) | |
811 | { | |
812 | struct mvtwsi_i2c_dev *dev = dev_get_priv(bus); | |
813 | struct i2c_msg *dmsg, *omsg, dummy; | |
814 | ||
815 | memset(&dummy, 0, sizeof(struct i2c_msg)); | |
816 | ||
817 | /* We expect either two messages (one with an offset and one with the | |
818 | * actual data) or one message (just data or offset/data combined) */ | |
819 | if (nmsgs > 2 || nmsgs == 0) { | |
820 | debug("%s: Only one or two messages are supported.", __func__); | |
821 | return -1; | |
822 | } | |
823 | ||
824 | omsg = nmsgs == 1 ? &dummy : msg; | |
825 | dmsg = nmsgs == 1 ? msg : msg + 1; | |
826 | ||
827 | if (dmsg->flags & I2C_M_RD) | |
828 | return __twsi_i2c_read(dev->base, dmsg->addr, omsg->buf, | |
c68c6243 | 829 | omsg->len, dmsg->buf, dmsg->len, |
830 | dev->tick); | |
14a6ff2c | 831 | else |
832 | return __twsi_i2c_write(dev->base, dmsg->addr, omsg->buf, | |
c68c6243 | 833 | omsg->len, dmsg->buf, dmsg->len, |
834 | dev->tick); | |
14a6ff2c | 835 | } |
836 | ||
837 | static const struct dm_i2c_ops mvtwsi_i2c_ops = { | |
838 | .xfer = mvtwsi_i2c_xfer, | |
839 | .probe_chip = mvtwsi_i2c_probe_chip, | |
840 | .set_bus_speed = mvtwsi_i2c_set_bus_speed, | |
841 | }; | |
842 | ||
843 | static const struct udevice_id mvtwsi_i2c_ids[] = { | |
844 | { .compatible = "marvell,mv64xxx-i2c", }, | |
87de0eb3 | 845 | { .compatible = "marvell,mv78230-i2c", }, |
a8f01ccf | 846 | { .compatible = "allwinner,sun6i-a31-i2c", }, |
14a6ff2c | 847 | { /* sentinel */ } |
848 | }; | |
849 | ||
850 | U_BOOT_DRIVER(i2c_mvtwsi) = { | |
851 | .name = "i2c_mvtwsi", | |
852 | .id = UCLASS_I2C, | |
853 | .of_match = mvtwsi_i2c_ids, | |
854 | .probe = mvtwsi_i2c_probe, | |
855 | .ofdata_to_platdata = mvtwsi_i2c_ofdata_to_platdata, | |
856 | .priv_auto_alloc_size = sizeof(struct mvtwsi_i2c_dev), | |
857 | .ops = &mvtwsi_i2c_ops, | |
858 | }; | |
859 | #endif /* CONFIG_DM_I2C */ |