]>
Commit | Line | Data |
---|---|---|
c609719b WD |
1 | /* |
2 | * (C) Copyright 2001, 2002 | |
3 | * Wolfgang Denk, DENX Software Engineering, wd@denx.de. | |
4 | * | |
5 | * See file CREDITS for list of people who contributed to this | |
6 | * project. | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or | |
9 | * modify it under the terms of the GNU General Public License as | |
10 | * published by the Free Software Foundation; either version 2 of | |
11 | * the License, or (at your option) any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program; if not, write to the Free Software | |
20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
21 | * MA 02111-1307 USA | |
22 | * | |
23 | * This has been changed substantially by Gerald Van Baren, Custom IDEAS, | |
24 | * vanbaren@cideas.com. It was heavily influenced by LiMon, written by | |
25 | * Neil Russell. | |
26 | */ | |
27 | ||
28 | #include <common.h> | |
29 | #ifdef CONFIG_MPC8260 /* only valid for MPC8260 */ | |
30 | #include <ioports.h> | |
a21ca95f | 31 | #include <asm/io.h> |
c609719b | 32 | #endif |
eabd5d8d AB |
33 | #if defined(CONFIG_AVR32) |
34 | #include <asm/arch/portmux.h> | |
35 | #endif | |
f3100ff7 | 36 | #if defined(CONFIG_AT91FAMILY) |
9d5028c2 WD |
37 | #include <asm/io.h> |
38 | #include <asm/arch/hardware.h> | |
0cf0b931 JS |
39 | #include <asm/arch/at91_pio.h> |
40 | #ifdef CONFIG_AT91_LEGACY | |
4e574c4e | 41 | #include <asm/arch/gpio.h> |
0cf0b931 | 42 | #endif |
4e574c4e | 43 | #endif |
ba94a1bb WD |
44 | #ifdef CONFIG_IXP425 /* only valid for IXP425 */ |
45 | #include <asm/arch/ixp425.h> | |
46 | #endif | |
1b6275df | 47 | #if defined(CONFIG_MPC852T) || defined(CONFIG_MPC866) |
a21ca95f HS |
48 | #include <asm/io.h> |
49 | #endif | |
c609719b WD |
50 | #include <i2c.h> |
51 | ||
793b5726 MF |
52 | #if defined(CONFIG_SOFT_I2C_GPIO_SCL) |
53 | # include <asm/gpio.h> | |
54 | ||
55 | # ifndef I2C_GPIO_SYNC | |
56 | # define I2C_GPIO_SYNC | |
57 | # endif | |
58 | ||
59 | # ifndef I2C_INIT | |
60 | # define I2C_INIT \ | |
61 | do { \ | |
62 | gpio_request(CONFIG_SOFT_I2C_GPIO_SCL, "soft_i2c"); \ | |
63 | gpio_request(CONFIG_SOFT_I2C_GPIO_SDA, "soft_i2c"); \ | |
64 | } while (0) | |
65 | # endif | |
66 | ||
67 | # ifndef I2C_ACTIVE | |
68 | # define I2C_ACTIVE do { } while (0) | |
69 | # endif | |
70 | ||
71 | # ifndef I2C_TRISTATE | |
72 | # define I2C_TRISTATE do { } while (0) | |
73 | # endif | |
74 | ||
75 | # ifndef I2C_READ | |
76 | # define I2C_READ gpio_get_value(CONFIG_SOFT_I2C_GPIO_SDA) | |
77 | # endif | |
78 | ||
79 | # ifndef I2C_SDA | |
80 | # define I2C_SDA(bit) \ | |
81 | do { \ | |
82 | if (bit) \ | |
83 | gpio_direction_input(CONFIG_SOFT_I2C_GPIO_SDA); \ | |
84 | else \ | |
85 | gpio_direction_output(CONFIG_SOFT_I2C_GPIO_SDA, 0); \ | |
86 | I2C_GPIO_SYNC; \ | |
87 | } while (0) | |
88 | # endif | |
89 | ||
90 | # ifndef I2C_SCL | |
91 | # define I2C_SCL(bit) \ | |
92 | do { \ | |
93 | gpio_direction_output(CONFIG_SOFT_I2C_GPIO_SCL, bit); \ | |
94 | I2C_GPIO_SYNC; \ | |
95 | } while (0) | |
96 | # endif | |
97 | ||
98 | # ifndef I2C_DELAY | |
99 | # define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */ | |
100 | # endif | |
101 | ||
102 | #endif | |
103 | ||
c609719b WD |
104 | /* #define DEBUG_I2C */ |
105 | ||
d87080b7 WD |
106 | #ifdef DEBUG_I2C |
107 | DECLARE_GLOBAL_DATA_PTR; | |
108 | #endif | |
109 | ||
c609719b WD |
110 | /*----------------------------------------------------------------------- |
111 | * Definitions | |
112 | */ | |
113 | ||
114 | #define RETRIES 0 | |
115 | ||
c609719b WD |
116 | #define I2C_ACK 0 /* PD_SDA level to ack a byte */ |
117 | #define I2C_NOACK 1 /* PD_SDA level to noack a byte */ | |
118 | ||
119 | ||
120 | #ifdef DEBUG_I2C | |
121 | #define PRINTD(fmt,args...) do { \ | |
c609719b WD |
122 | printf (fmt ,##args); \ |
123 | } while (0) | |
124 | #else | |
125 | #define PRINTD(fmt,args...) | |
126 | #endif | |
127 | ||
799b784a | 128 | #if defined(CONFIG_I2C_MULTI_BUS) |
5e3ab68e | 129 | static unsigned int i2c_bus_num __attribute__ ((section (".data"))) = 0; |
799b784a HS |
130 | #endif /* CONFIG_I2C_MULTI_BUS */ |
131 | ||
c609719b WD |
132 | /*----------------------------------------------------------------------- |
133 | * Local functions | |
134 | */ | |
6d0f6bcf | 135 | #if !defined(CONFIG_SYS_I2C_INIT_BOARD) |
c609719b | 136 | static void send_reset (void); |
4ca107ef | 137 | #endif |
c609719b WD |
138 | static void send_start (void); |
139 | static void send_stop (void); | |
140 | static void send_ack (int); | |
141 | static int write_byte (uchar byte); | |
142 | static uchar read_byte (int); | |
143 | ||
6d0f6bcf | 144 | #if !defined(CONFIG_SYS_I2C_INIT_BOARD) |
c609719b WD |
145 | /*----------------------------------------------------------------------- |
146 | * Send a reset sequence consisting of 9 clocks with the data signal high | |
147 | * to clock any confused device back into an idle state. Also send a | |
148 | * <stop> at the end of the sequence for belts & suspenders. | |
149 | */ | |
150 | static void send_reset(void) | |
151 | { | |
98aed379 | 152 | I2C_SOFT_DECLARATIONS /* intentional without ';' */ |
c609719b WD |
153 | int j; |
154 | ||
60fbe254 | 155 | I2C_SCL(1); |
c609719b | 156 | I2C_SDA(1); |
60fbe254 WD |
157 | #ifdef I2C_INIT |
158 | I2C_INIT; | |
159 | #endif | |
160 | I2C_TRISTATE; | |
c609719b WD |
161 | for(j = 0; j < 9; j++) { |
162 | I2C_SCL(0); | |
163 | I2C_DELAY; | |
164 | I2C_DELAY; | |
165 | I2C_SCL(1); | |
166 | I2C_DELAY; | |
167 | I2C_DELAY; | |
168 | } | |
169 | send_stop(); | |
170 | I2C_TRISTATE; | |
171 | } | |
4ca107ef | 172 | #endif |
c609719b WD |
173 | |
174 | /*----------------------------------------------------------------------- | |
175 | * START: High -> Low on SDA while SCL is High | |
176 | */ | |
177 | static void send_start(void) | |
178 | { | |
98aed379 | 179 | I2C_SOFT_DECLARATIONS /* intentional without ';' */ |
c609719b WD |
180 | |
181 | I2C_DELAY; | |
182 | I2C_SDA(1); | |
183 | I2C_ACTIVE; | |
184 | I2C_DELAY; | |
185 | I2C_SCL(1); | |
186 | I2C_DELAY; | |
187 | I2C_SDA(0); | |
188 | I2C_DELAY; | |
189 | } | |
190 | ||
191 | /*----------------------------------------------------------------------- | |
192 | * STOP: Low -> High on SDA while SCL is High | |
193 | */ | |
194 | static void send_stop(void) | |
195 | { | |
98aed379 | 196 | I2C_SOFT_DECLARATIONS /* intentional without ';' */ |
c609719b WD |
197 | |
198 | I2C_SCL(0); | |
199 | I2C_DELAY; | |
200 | I2C_SDA(0); | |
201 | I2C_ACTIVE; | |
202 | I2C_DELAY; | |
203 | I2C_SCL(1); | |
204 | I2C_DELAY; | |
205 | I2C_SDA(1); | |
206 | I2C_DELAY; | |
207 | I2C_TRISTATE; | |
208 | } | |
209 | ||
c609719b WD |
210 | /*----------------------------------------------------------------------- |
211 | * ack should be I2C_ACK or I2C_NOACK | |
212 | */ | |
213 | static void send_ack(int ack) | |
214 | { | |
98aed379 | 215 | I2C_SOFT_DECLARATIONS /* intentional without ';' */ |
c609719b | 216 | |
c609719b WD |
217 | I2C_SCL(0); |
218 | I2C_DELAY; | |
c609719b | 219 | I2C_ACTIVE; |
c15f80ea | 220 | I2C_SDA(ack); |
c609719b WD |
221 | I2C_DELAY; |
222 | I2C_SCL(1); | |
223 | I2C_DELAY; | |
224 | I2C_DELAY; | |
225 | I2C_SCL(0); | |
226 | I2C_DELAY; | |
227 | } | |
228 | ||
c609719b WD |
229 | /*----------------------------------------------------------------------- |
230 | * Send 8 bits and look for an acknowledgement. | |
231 | */ | |
232 | static int write_byte(uchar data) | |
233 | { | |
98aed379 | 234 | I2C_SOFT_DECLARATIONS /* intentional without ';' */ |
c609719b WD |
235 | int j; |
236 | int nack; | |
237 | ||
238 | I2C_ACTIVE; | |
239 | for(j = 0; j < 8; j++) { | |
240 | I2C_SCL(0); | |
241 | I2C_DELAY; | |
242 | I2C_SDA(data & 0x80); | |
243 | I2C_DELAY; | |
244 | I2C_SCL(1); | |
245 | I2C_DELAY; | |
246 | I2C_DELAY; | |
247 | ||
248 | data <<= 1; | |
249 | } | |
250 | ||
251 | /* | |
252 | * Look for an <ACK>(negative logic) and return it. | |
253 | */ | |
254 | I2C_SCL(0); | |
255 | I2C_DELAY; | |
256 | I2C_SDA(1); | |
257 | I2C_TRISTATE; | |
258 | I2C_DELAY; | |
259 | I2C_SCL(1); | |
260 | I2C_DELAY; | |
261 | I2C_DELAY; | |
262 | nack = I2C_READ; | |
263 | I2C_SCL(0); | |
264 | I2C_DELAY; | |
265 | I2C_ACTIVE; | |
266 | ||
267 | return(nack); /* not a nack is an ack */ | |
268 | } | |
269 | ||
799b784a HS |
270 | #if defined(CONFIG_I2C_MULTI_BUS) |
271 | /* | |
272 | * Functions for multiple I2C bus handling | |
273 | */ | |
274 | unsigned int i2c_get_bus_num(void) | |
275 | { | |
276 | return i2c_bus_num; | |
277 | } | |
278 | ||
279 | int i2c_set_bus_num(unsigned int bus) | |
280 | { | |
67b23a32 | 281 | #if defined(CONFIG_I2C_MUX) |
6d0f6bcf | 282 | if (bus < CONFIG_SYS_MAX_I2C_BUS) { |
67b23a32 HS |
283 | i2c_bus_num = bus; |
284 | } else { | |
285 | int ret; | |
286 | ||
287 | ret = i2x_mux_select_mux(bus); | |
4bd5566e | 288 | i2c_init_board(); |
67b23a32 HS |
289 | if (ret == 0) |
290 | i2c_bus_num = bus; | |
291 | else | |
292 | return ret; | |
293 | } | |
294 | #else | |
6d0f6bcf | 295 | if (bus >= CONFIG_SYS_MAX_I2C_BUS) |
799b784a HS |
296 | return -1; |
297 | i2c_bus_num = bus; | |
67b23a32 | 298 | #endif |
799b784a HS |
299 | return 0; |
300 | } | |
d144f94d | 301 | #endif |
799b784a | 302 | |
c609719b WD |
303 | /*----------------------------------------------------------------------- |
304 | * if ack == I2C_ACK, ACK the byte so can continue reading, else | |
305 | * send I2C_NOACK to end the read. | |
306 | */ | |
307 | static uchar read_byte(int ack) | |
308 | { | |
98aed379 | 309 | I2C_SOFT_DECLARATIONS /* intentional without ';' */ |
c609719b WD |
310 | int data; |
311 | int j; | |
312 | ||
313 | /* | |
314 | * Read 8 bits, MSB first. | |
315 | */ | |
316 | I2C_TRISTATE; | |
110e006f | 317 | I2C_SDA(1); |
c609719b WD |
318 | data = 0; |
319 | for(j = 0; j < 8; j++) { | |
320 | I2C_SCL(0); | |
321 | I2C_DELAY; | |
322 | I2C_SCL(1); | |
323 | I2C_DELAY; | |
324 | data <<= 1; | |
325 | data |= I2C_READ; | |
326 | I2C_DELAY; | |
327 | } | |
328 | send_ack(ack); | |
329 | ||
330 | return(data); | |
331 | } | |
332 | ||
333 | /*=====================================================================*/ | |
334 | /* Public Functions */ | |
335 | /*=====================================================================*/ | |
336 | ||
337 | /*----------------------------------------------------------------------- | |
338 | * Initialization | |
339 | */ | |
340 | void i2c_init (int speed, int slaveaddr) | |
341 | { | |
6d0f6bcf | 342 | #if defined(CONFIG_SYS_I2C_INIT_BOARD) |
4ca107ef HS |
343 | /* call board specific i2c bus reset routine before accessing the */ |
344 | /* environment, which might be in a chip on that bus. For details */ | |
345 | /* about this problem see doc/I2C_Edge_Conditions. */ | |
346 | i2c_init_board(); | |
347 | #else | |
c609719b | 348 | /* |
8bde7f77 WD |
349 | * WARNING: Do NOT save speed in a static variable: if the |
350 | * I2C routines are called before RAM is initialized (to read | |
351 | * the DIMM SPD, for instance), RAM won't be usable and your | |
352 | * system will crash. | |
c609719b WD |
353 | */ |
354 | send_reset (); | |
4ca107ef | 355 | #endif |
c609719b WD |
356 | } |
357 | ||
358 | /*----------------------------------------------------------------------- | |
359 | * Probe to see if a chip is present. Also good for checking for the | |
360 | * completion of EEPROM writes since the chip stops responding until | |
361 | * the write completes (typically 10mSec). | |
362 | */ | |
363 | int i2c_probe(uchar addr) | |
364 | { | |
365 | int rc; | |
366 | ||
82d716fd | 367 | /* |
8e7b703a | 368 | * perform 1 byte write transaction with just address byte |
82d716fd WD |
369 | * (fake write) |
370 | */ | |
c609719b | 371 | send_start(); |
6aff3115 | 372 | rc = write_byte ((addr << 1) | 0); |
c609719b WD |
373 | send_stop(); |
374 | ||
375 | return (rc ? 1 : 0); | |
376 | } | |
377 | ||
378 | /*----------------------------------------------------------------------- | |
379 | * Read bytes | |
380 | */ | |
381 | int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len) | |
382 | { | |
383 | int shift; | |
384 | PRINTD("i2c_read: chip %02X addr %02X alen %d buffer %p len %d\n", | |
385 | chip, addr, alen, buffer, len); | |
386 | ||
6d0f6bcf | 387 | #ifdef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW |
c609719b WD |
388 | /* |
389 | * EEPROM chips that implement "address overflow" are ones | |
390 | * like Catalyst 24WC04/08/16 which has 9/10/11 bits of | |
391 | * address and the extra bits end up in the "chip address" | |
392 | * bit slots. This makes a 24WC08 (1Kbyte) chip look like | |
393 | * four 256 byte chips. | |
394 | * | |
395 | * Note that we consider the length of the address field to | |
396 | * still be one byte because the extra address bits are | |
397 | * hidden in the chip address. | |
398 | */ | |
6d0f6bcf | 399 | chip |= ((addr >> (alen * 8)) & CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW); |
c609719b WD |
400 | |
401 | PRINTD("i2c_read: fix addr_overflow: chip %02X addr %02X\n", | |
402 | chip, addr); | |
403 | #endif | |
404 | ||
405 | /* | |
406 | * Do the addressing portion of a write cycle to set the | |
407 | * chip's address pointer. If the address length is zero, | |
408 | * don't do the normal write cycle to set the address pointer, | |
409 | * there is no address pointer in this chip. | |
410 | */ | |
411 | send_start(); | |
412 | if(alen > 0) { | |
413 | if(write_byte(chip << 1)) { /* write cycle */ | |
414 | send_stop(); | |
415 | PRINTD("i2c_read, no chip responded %02X\n", chip); | |
416 | return(1); | |
417 | } | |
418 | shift = (alen-1) * 8; | |
419 | while(alen-- > 0) { | |
420 | if(write_byte(addr >> shift)) { | |
421 | PRINTD("i2c_read, address not <ACK>ed\n"); | |
422 | return(1); | |
423 | } | |
424 | shift -= 8; | |
425 | } | |
2ac6985a AD |
426 | |
427 | /* Some I2C chips need a stop/start sequence here, | |
428 | * other chips don't work with a full stop and need | |
429 | * only a start. Default behaviour is to send the | |
430 | * stop/start sequence. | |
431 | */ | |
432 | #ifdef CONFIG_SOFT_I2C_READ_REPEATED_START | |
433 | send_start(); | |
434 | #else | |
435 | send_stop(); | |
c609719b | 436 | send_start(); |
2ac6985a | 437 | #endif |
c609719b WD |
438 | } |
439 | /* | |
440 | * Send the chip address again, this time for a read cycle. | |
441 | * Then read the data. On the last byte, we do a NACK instead | |
442 | * of an ACK(len == 0) to terminate the read. | |
443 | */ | |
444 | write_byte((chip << 1) | 1); /* read cycle */ | |
445 | while(len-- > 0) { | |
446 | *buffer++ = read_byte(len == 0); | |
447 | } | |
448 | send_stop(); | |
449 | return(0); | |
450 | } | |
451 | ||
452 | /*----------------------------------------------------------------------- | |
453 | * Write bytes | |
454 | */ | |
455 | int i2c_write(uchar chip, uint addr, int alen, uchar *buffer, int len) | |
456 | { | |
457 | int shift, failures = 0; | |
458 | ||
459 | PRINTD("i2c_write: chip %02X addr %02X alen %d buffer %p len %d\n", | |
460 | chip, addr, alen, buffer, len); | |
461 | ||
462 | send_start(); | |
463 | if(write_byte(chip << 1)) { /* write cycle */ | |
464 | send_stop(); | |
465 | PRINTD("i2c_write, no chip responded %02X\n", chip); | |
466 | return(1); | |
467 | } | |
468 | shift = (alen-1) * 8; | |
469 | while(alen-- > 0) { | |
470 | if(write_byte(addr >> shift)) { | |
471 | PRINTD("i2c_write, address not <ACK>ed\n"); | |
472 | return(1); | |
473 | } | |
474 | shift -= 8; | |
475 | } | |
476 | ||
477 | while(len-- > 0) { | |
478 | if(write_byte(*buffer++)) { | |
479 | failures++; | |
480 | } | |
481 | } | |
482 | send_stop(); | |
483 | return(failures); | |
484 | } |