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media: dvb: clean up redundant break statements
[thirdparty/kernel/stable.git] / drivers / media / dvb-frontends / drxd_hard.c
CommitLineData
126f1e61
RM		 1/*
2 * drxd_hard.c: DVB-T Demodulator Micronas DRX3975D-A2,DRX397xD-B1
3 *
4 * Copyright (C) 2003-2007 Micronas
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * version 2 only, as published by the Free Software Foundation.
9 *
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
bcb63314
SA		 16 * To obtain the license, point your browser to
17 * http://www.gnu.org/copyleft/gpl.html
126f1e61
RM		 18 */
19
20#include <linux/kernel.h>
21#include <linux/module.h>
22#include <linux/moduleparam.h>
23#include <linux/init.h>
24#include <linux/delay.h>
25#include <linux/firmware.h>
26#include <linux/i2c.h>
126f1e61
RM		 27#include <asm/div64.h>
28
fada1935 29#include <media/dvb_frontend.h>
126f1e61
RM		 30#include "drxd.h"
31#include "drxd_firm.h"
32
8f19f27e
DH		 33#define DRX_FW_FILENAME_A2 "drxd-a2-1.1.fw"
34#define DRX_FW_FILENAME_B1 "drxd-b1-1.1.fw"
35
126f1e61
RM		 36#define CHUNK_SIZE 48
37
38#define DRX_I2C_RMW 0x10
39#define DRX_I2C_BROADCAST 0x20
40#define DRX_I2C_CLEARCRC 0x80
41#define DRX_I2C_SINGLE_MASTER 0xC0
42#define DRX_I2C_MODEFLAGS 0xC0
43#define DRX_I2C_FLAGS 0xF0
44
126f1e61
RM		 45#define DEFAULT_LOCK_TIMEOUT 1100
46
47#define DRX_CHANNEL_AUTO 0
48#define DRX_CHANNEL_HIGH 1
49#define DRX_CHANNEL_LOW 2
50
51#define DRX_LOCK_MPEG 1
52#define DRX_LOCK_FEC 2
53#define DRX_LOCK_DEMOD 4
54
126f1e61
RM		 55/****************************************************************************/
56
57enum CSCDState {
58 CSCD_INIT = 0,
59 CSCD_SET,
60 CSCD_SAVED
61};
62
63enum CDrxdState {
64 DRXD_UNINITIALIZED = 0,
65 DRXD_STOPPED,
66 DRXD_STARTED
67};
68
69enum AGC_CTRL_MODE {
70 AGC_CTRL_AUTO = 0,
71 AGC_CTRL_USER,
72 AGC_CTRL_OFF
73};
74
75enum OperationMode {
76 OM_Default,
77 OM_DVBT_Diversity_Front,
78 OM_DVBT_Diversity_End
79};
80
81struct SCfgAgc {
82 enum AGC_CTRL_MODE ctrlMode;
6cacdd46
DH		 83 u16 outputLevel; /* range [0, ... , 1023], 1/n of fullscale range */
84 u16 settleLevel; /* range [0, ... , 1023], 1/n of fullscale range */
85 u16 minOutputLevel; /* range [0, ... , 1023], 1/n of fullscale range */
86 u16 maxOutputLevel; /* range [0, ... , 1023], 1/n of fullscale range */
87 u16 speed; /* range [0, ... , 1023], 1/n of fullscale range */
126f1e61
RM		 88
89 u16 R1;
90 u16 R2;
91 u16 R3;
92};
93
94struct SNoiseCal {
95 int cpOpt;
3caaa201
SN		 96 short cpNexpOfs;
97 short tdCal2k;
98 short tdCal8k;
126f1e61
RM		 99};
100
101enum app_env {
102 APPENV_STATIC = 0,
103 APPENV_PORTABLE = 1,
6cacdd46 104 APPENV_MOBILE = 2
126f1e61
RM		 105};
106
107enum EIFFilter {
108 IFFILTER_SAW = 0,
109 IFFILTER_DISCRETE = 1
110};
111
112struct drxd_state {
113 struct dvb_frontend frontend;
114 struct dvb_frontend_ops ops;
9f97c288 115 struct dtv_frontend_properties props;
126f1e61
RM		 116
117 const struct firmware *fw;
118 struct device *dev;
119
120 struct i2c_adapter *i2c;
121 void *priv;
122 struct drxd_config config;
123
124 int i2c_access;
125 int init_done;
834751d4 126 struct mutex mutex;
126f1e61 127
6cacdd46 128 u8 chip_adr;
126f1e61
RM		 129 u16 hi_cfg_timing_div;
130 u16 hi_cfg_bridge_delay;
131 u16 hi_cfg_wakeup_key;
132 u16 hi_cfg_ctrl;
133
134 u16 intermediate_freq;
135 u16 osc_clock_freq;
136
137 enum CSCDState cscd_state;
138 enum CDrxdState drxd_state;
139
140 u16 sys_clock_freq;
141 s16 osc_clock_deviation;
142 u16 expected_sys_clock_freq;
143
144 u16 insert_rs_byte;
145 u16 enable_parallel;
146
147 int operation_mode;
148
149 struct SCfgAgc if_agc_cfg;
150 struct SCfgAgc rf_agc_cfg;
151
152 struct SNoiseCal noise_cal;
153
154 u32 fe_fs_add_incr;
155 u32 org_fe_fs_add_incr;
156 u16 current_fe_if_incr;
157
158 u16 m_FeAgRegAgPwd;
159 u16 m_FeAgRegAgAgcSio;
160
161 u16 m_EcOcRegOcModeLop;
162 u16 m_EcOcRegSncSncLvl;
163 u8 *m_InitAtomicRead;
164 u8 *m_HiI2cPatch;
165
166 u8 *m_ResetCEFR;
167 u8 *m_InitFE_1;
168 u8 *m_InitFE_2;
169 u8 *m_InitCP;
170 u8 *m_InitCE;
171 u8 *m_InitEQ;
172 u8 *m_InitSC;
173 u8 *m_InitEC;
174 u8 *m_ResetECRAM;
175 u8 *m_InitDiversityFront;
176 u8 *m_InitDiversityEnd;
177 u8 *m_DisableDiversity;
178 u8 *m_StartDiversityFront;
179 u8 *m_StartDiversityEnd;
180
181 u8 *m_DiversityDelay8MHZ;
182 u8 *m_DiversityDelay6MHZ;
183
184 u8 *microcode;
185 u32 microcode_length;
186
187 int type_A;
188 int PGA;
189 int diversity;
190 int tuner_mirrors;
191
192 enum app_env app_env_default;
193 enum app_env app_env_diversity;
194
195};
196
126f1e61
RM		 197/****************************************************************************/
198/* I2C **********************************************************************/
199/****************************************************************************/
200
6cacdd46 201static int i2c_write(struct i2c_adapter *adap, u8 adr, u8 * data, int len)
126f1e61 202{
9999daf4 203 struct i2c_msg msg = {.addr = adr, .flags = 0, .buf = data, .len = len };
126f1e61
RM		 204
205 if (i2c_transfer(adap, &msg, 1) != 1)
206 return -1;
207 return 0;
208}
209
210static int i2c_read(struct i2c_adapter *adap,
9999daf4 211 u8 adr, u8 *msg, int len, u8 *answ, int alen)
126f1e61 212{
9999daf4
MCC		 213 struct i2c_msg msgs[2] = {
214 {
215 .addr = adr, .flags = 0,
216 .buf = msg, .len = len
217 }, {
218 .addr = adr, .flags = I2C_M_RD,
219 .buf = answ, .len = alen
220 }
6cacdd46 221 };
126f1e61
RM		 222 if (i2c_transfer(adap, msgs, 2) != 2)
223 return -1;
224 return 0;
225}
226
b01fbc10 227static inline u32 MulDiv32(u32 a, u32 b, u32 c)
126f1e61
RM		 228{
229 u64 tmp64;
230
9999daf4 231 tmp64 = (u64)a * (u64)b;
126f1e61
RM		 232 do_div(tmp64, c);
233
234 return (u32) tmp64;
235}
236
9999daf4 237static int Read16(struct drxd_state *state, u32 reg, u16 *data, u8 flags)
126f1e61 238{
6cacdd46
DH		 239 u8 adr = state->config.demod_address;
240 u8 mm1[4] = { reg & 0xff, (reg >> 16) & 0xff,
241 flags | ((reg >> 24) & 0xff), (reg >> 8) & 0xff
242 };
126f1e61 243 u8 mm2[2];
6cacdd46 244 if (i2c_read(state->i2c, adr, mm1, 4, mm2, 2) < 0)
126f1e61
RM		 245 return -1;
246 if (data)
6cacdd46
DH		 247 *data = mm2[0] | (mm2[1] << 8);
248 return mm2[0] | (mm2[1] << 8);
126f1e61
RM		 249}
250
9999daf4 251static int Read32(struct drxd_state *state, u32 reg, u32 *data, u8 flags)
126f1e61 252{
6cacdd46
DH		 253 u8 adr = state->config.demod_address;
254 u8 mm1[4] = { reg & 0xff, (reg >> 16) & 0xff,
255 flags | ((reg >> 24) & 0xff), (reg >> 8) & 0xff
256 };
126f1e61
RM		 257 u8 mm2[4];
258
6cacdd46 259 if (i2c_read(state->i2c, adr, mm1, 4, mm2, 4) < 0)
126f1e61
RM		 260 return -1;
261 if (data)
6cacdd46
DH		 262 *data =
263 mm2[0] | (mm2[1] << 8) | (mm2[2] << 16) | (mm2[3] << 24);
126f1e61
RM		 264 return 0;
265}
266
267static int Write16(struct drxd_state *state, u32 reg, u16 data, u8 flags)
268{
6cacdd46
DH		 269 u8 adr = state->config.demod_address;
270 u8 mm[6] = { reg & 0xff, (reg >> 16) & 0xff,
271 flags | ((reg >> 24) & 0xff), (reg >> 8) & 0xff,
272 data & 0xff, (data >> 8) & 0xff
273 };
126f1e61 274
6cacdd46 275 if (i2c_write(state->i2c, adr, mm, 6) < 0)
126f1e61
RM		 276 return -1;
277 return 0;
278}
279
280static int Write32(struct drxd_state *state, u32 reg, u32 data, u8 flags)
281{
6cacdd46
DH		 282 u8 adr = state->config.demod_address;
283 u8 mm[8] = { reg & 0xff, (reg >> 16) & 0xff,
284 flags | ((reg >> 24) & 0xff), (reg >> 8) & 0xff,
285 data & 0xff, (data >> 8) & 0xff,
286 (data >> 16) & 0xff, (data >> 24) & 0xff
287 };
126f1e61 288
6cacdd46 289 if (i2c_write(state->i2c, adr, mm, 8) < 0)
126f1e61
RM		 290 return -1;
291 return 0;
292}
293
294static int write_chunk(struct drxd_state *state,
9999daf4 295 u32 reg, u8 *data, u32 len, u8 flags)
126f1e61 296{
6cacdd46
DH		 297 u8 adr = state->config.demod_address;
298 u8 mm[CHUNK_SIZE + 4] = { reg & 0xff, (reg >> 16) & 0xff,
299 flags | ((reg >> 24) & 0xff), (reg >> 8) & 0xff
300 };
126f1e61
RM		 301 int i;
302
6cacdd46
DH		 303 for (i = 0; i < len; i++)
304 mm[4 + i] = data[i];
305 if (i2c_write(state->i2c, adr, mm, 4 + len) < 0) {
9999daf4 306 printk(KERN_ERR "error in write_chunk\n");
126f1e61
RM		 307 return -1;
308 }
309 return 0;
310}
311
312static int WriteBlock(struct drxd_state *state,
9999daf4 313 u32 Address, u16 BlockSize, u8 *pBlock, u8 Flags)
126f1e61 314{
6cacdd46 315 while (BlockSize > 0) {
126f1e61
RM		 316 u16 Chunk = BlockSize > CHUNK_SIZE ? CHUNK_SIZE : BlockSize;
317
6cacdd46 318 if (write_chunk(state, Address, pBlock, Chunk, Flags) < 0)
126f1e61
RM		 319 return -1;
320 pBlock += Chunk;
321 Address += (Chunk >> 1);
322 BlockSize -= Chunk;
323 }
324 return 0;
325}
326
6cacdd46 327static int WriteTable(struct drxd_state *state, u8 * pTable)
126f1e61
RM		 328{
329 int status = 0;
330
af28c996 331 if (!pTable)
126f1e61
RM		 332 return 0;
333
6cacdd46 334 while (!status) {
126f1e61 335 u16 Length;
6cacdd46
DH		 336 u32 Address = pTable[0] | (pTable[1] << 8) |
337 (pTable[2] << 16) | (pTable[3] << 24);
126f1e61 338
6cacdd46 339 if (Address == 0xFFFFFFFF)
126f1e61
RM		 340 break;
341 pTable += sizeof(u32);
342
6cacdd46 343 Length = pTable[0] | (pTable[1] << 8);
126f1e61
RM		 344 pTable += sizeof(u16);
345 if (!Length)
346 break;
6cacdd46
DH		 347 status = WriteBlock(state, Address, Length * 2, pTable, 0);
348 pTable += (Length * 2);
126f1e61
RM		 349 }
350 return status;
351}
352
126f1e61
RM		 353/****************************************************************************/
354/****************************************************************************/
355/****************************************************************************/
356
357static int ResetCEFR(struct drxd_state *state)
358{
359 return WriteTable(state, state->m_ResetCEFR);
360}
361
362static int InitCP(struct drxd_state *state)
363{
364 return WriteTable(state, state->m_InitCP);
365}
366
367static int InitCE(struct drxd_state *state)
368{
369 int status;
370 enum app_env AppEnv = state->app_env_default;
371
372 do {
58d5eaec
MCC		 373 status = WriteTable(state, state->m_InitCE);
374 if (status < 0)
375 break;
126f1e61
RM		 376
377 if (state->operation_mode == OM_DVBT_Diversity_Front ||
6cacdd46 378 state->operation_mode == OM_DVBT_Diversity_End) {
126f1e61
RM		 379 AppEnv = state->app_env_diversity;
380 }
6cacdd46 381 if (AppEnv == APPENV_STATIC) {
58d5eaec
MCC		 382 status = Write16(state, CE_REG_TAPSET__A, 0x0000, 0);
383 if (status < 0)
384 break;
6cacdd46 385 } else if (AppEnv == APPENV_PORTABLE) {
58d5eaec
MCC		 386 status = Write16(state, CE_REG_TAPSET__A, 0x0001, 0);
387 if (status < 0)
388 break;
6cacdd46 389 } else if (AppEnv == APPENV_MOBILE && state->type_A) {
58d5eaec
MCC		 390 status = Write16(state, CE_REG_TAPSET__A, 0x0002, 0);
391 if (status < 0)
392 break;
6cacdd46 393 } else if (AppEnv == APPENV_MOBILE && !state->type_A) {
58d5eaec
MCC		 394 status = Write16(state, CE_REG_TAPSET__A, 0x0006, 0);
395 if (status < 0)
396 break;
126f1e61
RM		 397 }
398
399 /* start ce */
58d5eaec
MCC		 400 status = Write16(state, B_CE_REG_COMM_EXEC__A, 0x0001, 0);
401 if (status < 0)
402 break;
6cacdd46 403 } while (0);
126f1e61
RM		 404 return status;
405}
406
407static int StopOC(struct drxd_state *state)
408{
409 int status = 0;
6cacdd46
DH		 410 u16 ocSyncLvl = 0;
411 u16 ocModeLop = state->m_EcOcRegOcModeLop;
412 u16 dtoIncLop = 0;
413 u16 dtoIncHip = 0;
126f1e61
RM		 414
415 do {
416 /* Store output configuration */
58d5eaec
MCC		 417 status = Read16(state, EC_OC_REG_SNC_ISC_LVL__A, &ocSyncLvl, 0);
418 if (status < 0)
9999daf4 419 break;
58d5eaec 420 /* CHK_ERROR(Read16(EC_OC_REG_OC_MODE_LOP__A, &ocModeLop)); */
126f1e61
RM		 421 state->m_EcOcRegSncSncLvl = ocSyncLvl;
422 /* m_EcOcRegOcModeLop = ocModeLop; */
423
424 /* Flush FIFO (byte-boundary) at fixed rate */
58d5eaec
MCC		 425 status = Read16(state, EC_OC_REG_RCN_MAP_LOP__A, &dtoIncLop, 0);
426 if (status < 0)
427 break;
428 status = Read16(state, EC_OC_REG_RCN_MAP_HIP__A, &dtoIncHip, 0);
429 if (status < 0)
430 break;
431 status = Write16(state, EC_OC_REG_DTO_INC_LOP__A, dtoIncLop, 0);
432 if (status < 0)
433 break;
434 status = Write16(state, EC_OC_REG_DTO_INC_HIP__A, dtoIncHip, 0);
435 if (status < 0)
436 break;
126f1e61 437 ocModeLop &= ~(EC_OC_REG_OC_MODE_LOP_DTO_CTR_SRC__M);
6cacdd46 438 ocModeLop |= EC_OC_REG_OC_MODE_LOP_DTO_CTR_SRC_STATIC;
58d5eaec
MCC		 439 status = Write16(state, EC_OC_REG_OC_MODE_LOP__A, ocModeLop, 0);
440 if (status < 0)
441 break;
442 status = Write16(state, EC_OC_REG_COMM_EXEC__A, EC_OC_REG_COMM_EXEC_CTL_HOLD, 0);
443 if (status < 0)
444 break;
126f1e61
RM		 445
446 msleep(1);
447 /* Output pins to '0' */
58d5eaec
MCC		 448 status = Write16(state, EC_OC_REG_OCR_MPG_UOS__A, EC_OC_REG_OCR_MPG_UOS__M, 0);
449 if (status < 0)
450 break;
126f1e61
RM		 451
452 /* Force the OC out of sync */
453 ocSyncLvl &= ~(EC_OC_REG_SNC_ISC_LVL_OSC__M);
58d5eaec
MCC		 454 status = Write16(state, EC_OC_REG_SNC_ISC_LVL__A, ocSyncLvl, 0);
455 if (status < 0)
456 break;
126f1e61 457 ocModeLop &= ~(EC_OC_REG_OC_MODE_LOP_PAR_ENA__M);
6cacdd46
DH		 458 ocModeLop |= EC_OC_REG_OC_MODE_LOP_PAR_ENA_ENABLE;
459 ocModeLop |= 0x2; /* Magically-out-of-sync */
58d5eaec
MCC		 460 status = Write16(state, EC_OC_REG_OC_MODE_LOP__A, ocModeLop, 0);
461 if (status < 0)
462 break;
463 status = Write16(state, EC_OC_REG_COMM_INT_STA__A, 0x0, 0);
464 if (status < 0)
465 break;
466 status = Write16(state, EC_OC_REG_COMM_EXEC__A, EC_OC_REG_COMM_EXEC_CTL_ACTIVE, 0);
467 if (status < 0)
468 break;
6cacdd46 469 } while (0);
126f1e61
RM		 470
471 return status;
472}
473
474static int StartOC(struct drxd_state *state)
475{
6cacdd46 476 int status = 0;
126f1e61
RM		 477
478 do {
479 /* Stop OC */
58d5eaec
MCC		 480 status = Write16(state, EC_OC_REG_COMM_EXEC__A, EC_OC_REG_COMM_EXEC_CTL_HOLD, 0);
481 if (status < 0)
482 break;
126f1e61
RM		 483
484 /* Restore output configuration */
58d5eaec
MCC		 485 status = Write16(state, EC_OC_REG_SNC_ISC_LVL__A, state->m_EcOcRegSncSncLvl, 0);
486 if (status < 0)
487 break;
488 status = Write16(state, EC_OC_REG_OC_MODE_LOP__A, state->m_EcOcRegOcModeLop, 0);
489 if (status < 0)
490 break;
126f1e61
RM		 491
492 /* Output pins active again */
58d5eaec
MCC		 493 status = Write16(state, EC_OC_REG_OCR_MPG_UOS__A, EC_OC_REG_OCR_MPG_UOS_INIT, 0);
494 if (status < 0)
495 break;
126f1e61
RM		 496
497 /* Start OC */
58d5eaec
MCC		 498 status = Write16(state, EC_OC_REG_COMM_EXEC__A, EC_OC_REG_COMM_EXEC_CTL_ACTIVE, 0);
499 if (status < 0)
500 break;
6cacdd46 501 } while (0);
126f1e61
RM		 502 return status;
503}
504
505static int InitEQ(struct drxd_state *state)
506{
507 return WriteTable(state, state->m_InitEQ);
508}
509
510static int InitEC(struct drxd_state *state)
511{
512 return WriteTable(state, state->m_InitEC);
513}
514
515static int InitSC(struct drxd_state *state)
516{
517 return WriteTable(state, state->m_InitSC);
518}
519
520static int InitAtomicRead(struct drxd_state *state)
521{
522 return WriteTable(state, state->m_InitAtomicRead);
523}
524
525static int CorrectSysClockDeviation(struct drxd_state *state);
526
6cacdd46 527static int DRX_GetLockStatus(struct drxd_state *state, u32 * pLockStatus)
126f1e61
RM		 528{
529 u16 ScRaRamLock = 0;
6cacdd46
DH		 530 const u16 mpeg_lock_mask = (SC_RA_RAM_LOCK_MPEG__M |
531 SC_RA_RAM_LOCK_FEC__M |
532 SC_RA_RAM_LOCK_DEMOD__M);
533 const u16 fec_lock_mask = (SC_RA_RAM_LOCK_FEC__M |
534 SC_RA_RAM_LOCK_DEMOD__M);
535 const u16 demod_lock_mask = SC_RA_RAM_LOCK_DEMOD__M;
126f1e61
RM		 536
537 int status;
538
6cacdd46 539 *pLockStatus = 0;
126f1e61 540
6cacdd46
DH		 541 status = Read16(state, SC_RA_RAM_LOCK__A, &ScRaRamLock, 0x0000);
542 if (status < 0) {
9999daf4 543 printk(KERN_ERR "Can't read SC_RA_RAM_LOCK__A status = %08x\n", status);
126f1e61
RM		 544 return status;
545 }
546
6cacdd46 547 if (state->drxd_state != DRXD_STARTED)
126f1e61
RM		 548 return 0;
549
6cacdd46
DH		 550 if ((ScRaRamLock & mpeg_lock_mask) == mpeg_lock_mask) {
551 *pLockStatus |= DRX_LOCK_MPEG;
126f1e61
RM		 552 CorrectSysClockDeviation(state);
553 }
554
6cacdd46
DH		 555 if ((ScRaRamLock & fec_lock_mask) == fec_lock_mask)
556 *pLockStatus |= DRX_LOCK_FEC;
126f1e61 557
6cacdd46
DH		 558 if ((ScRaRamLock & demod_lock_mask) == demod_lock_mask)
559 *pLockStatus |= DRX_LOCK_DEMOD;
126f1e61
RM		 560 return 0;
561}
562
563/****************************************************************************/
564
565static int SetCfgIfAgc(struct drxd_state *state, struct SCfgAgc *cfg)
566{
567 int status;
568
6cacdd46
DH		 569 if (cfg->outputLevel > DRXD_FE_CTRL_MAX)
570 return -1;
126f1e61 571
6cacdd46 572 if (cfg->ctrlMode == AGC_CTRL_USER) {
126f1e61
RM		 573 do {
574 u16 FeAgRegPm1AgcWri;
575 u16 FeAgRegAgModeLop;
576
58d5eaec
MCC		 577 status = Read16(state, FE_AG_REG_AG_MODE_LOP__A, &FeAgRegAgModeLop, 0);
578 if (status < 0)
579 break;
6cacdd46
DH		 580 FeAgRegAgModeLop &= (~FE_AG_REG_AG_MODE_LOP_MODE_4__M);
581 FeAgRegAgModeLop |= FE_AG_REG_AG_MODE_LOP_MODE_4_STATIC;
58d5eaec
MCC		 582 status = Write16(state, FE_AG_REG_AG_MODE_LOP__A, FeAgRegAgModeLop, 0);
583 if (status < 0)
584 break;
6cacdd46
DH		 585
586 FeAgRegPm1AgcWri = (u16) (cfg->outputLevel &
587 FE_AG_REG_PM1_AGC_WRI__M);
58d5eaec
MCC		 588 status = Write16(state, FE_AG_REG_PM1_AGC_WRI__A, FeAgRegPm1AgcWri, 0);
589 if (status < 0)
590 break;
9999daf4 591 } while (0);
6cacdd46
DH		 592 } else if (cfg->ctrlMode == AGC_CTRL_AUTO) {
593 if (((cfg->maxOutputLevel) < (cfg->minOutputLevel)) ||
594 ((cfg->maxOutputLevel) > DRXD_FE_CTRL_MAX) ||
595 ((cfg->speed) > DRXD_FE_CTRL_MAX) ||
596 ((cfg->settleLevel) > DRXD_FE_CTRL_MAX)
597 )
9999daf4 598 return -1;
126f1e61
RM		 599 do {
600 u16 FeAgRegAgModeLop;
601 u16 FeAgRegEgcSetLvl;
602 u16 slope, offset;
603
604 /* == Mode == */
605
58d5eaec
MCC		 606 status = Read16(state, FE_AG_REG_AG_MODE_LOP__A, &FeAgRegAgModeLop, 0);
607 if (status < 0)
608 break;
6cacdd46 609 FeAgRegAgModeLop &= (~FE_AG_REG_AG_MODE_LOP_MODE_4__M);
126f1e61 610 FeAgRegAgModeLop |=
6cacdd46 611 FE_AG_REG_AG_MODE_LOP_MODE_4_DYNAMIC;
58d5eaec
MCC		 612 status = Write16(state, FE_AG_REG_AG_MODE_LOP__A, FeAgRegAgModeLop, 0);
613 if (status < 0)
614 break;
126f1e61
RM		 615
616 /* == Settle level == */
617
6cacdd46
DH		 618 FeAgRegEgcSetLvl = (u16) ((cfg->settleLevel >> 1) &
619 FE_AG_REG_EGC_SET_LVL__M);
58d5eaec
MCC		 620 status = Write16(state, FE_AG_REG_EGC_SET_LVL__A, FeAgRegEgcSetLvl, 0);
621 if (status < 0)
622 break;
126f1e61
RM		 623
624 /* == Min/Max == */
625
6cacdd46
DH		 626 slope = (u16) ((cfg->maxOutputLevel -
627 cfg->minOutputLevel) / 2);
628 offset = (u16) ((cfg->maxOutputLevel +
629 cfg->minOutputLevel) / 2 - 511);
126f1e61 630
58d5eaec
MCC		 631 status = Write16(state, FE_AG_REG_GC1_AGC_RIC__A, slope, 0);
632 if (status < 0)
633 break;
634 status = Write16(state, FE_AG_REG_GC1_AGC_OFF__A, offset, 0);
635 if (status < 0)
636 break;
126f1e61
RM		 637
638 /* == Speed == */
639 {
640 const u16 maxRur = 8;
7f033708
CIK		 641 static const u16 slowIncrDecLUT[] = {
642 3, 4, 4, 5, 6 };
eaa8c79e 643 static const u16 fastIncrDecLUT[] = {
7f033708 644 14, 15, 15, 16,
6cacdd46
DH		 645 17, 18, 18, 19,
646 20, 21, 22, 23,
647 24, 26, 27, 28,
648 29, 31
649 };
650
651 u16 fineSteps = (DRXD_FE_CTRL_MAX + 1) /
652 (maxRur + 1);
653 u16 fineSpeed = (u16) (cfg->speed -
654 ((cfg->speed /
655 fineSteps) *
126f1e61 656 fineSteps));
6cacdd46
DH		 657 u16 invRurCount = (u16) (cfg->speed /
658 fineSteps);
126f1e61 659 u16 rurCount;
6cacdd46
DH		 660 if (invRurCount > maxRur) {
661 rurCount = 0;
126f1e61
RM		 662 fineSpeed += fineSteps;
663 } else {
6cacdd46 664 rurCount = maxRur - invRurCount;
126f1e61
RM		 665 }
666
667 /*
6cacdd46
DH		 668 fastInc = default *
669 (2^(fineSpeed/fineSteps))
670 => range[default...2*default>
671 slowInc = default *
672 (2^(fineSpeed/fineSteps))
673 */
126f1e61
RM		 674 {
675 u16 fastIncrDec =
6cacdd46
DH		 676 fastIncrDecLUT[fineSpeed /
677 ((fineSteps /
678 (14 + 1)) + 1)];
679 u16 slowIncrDec =
680 slowIncrDecLUT[fineSpeed /
681 (fineSteps /
682 (3 + 1))];
126f1e61 683
58d5eaec
MCC		 684 status = Write16(state, FE_AG_REG_EGC_RUR_CNT__A, rurCount, 0);
685 if (status < 0)
686 break;
687 status = Write16(state, FE_AG_REG_EGC_FAS_INC__A, fastIncrDec, 0);
688 if (status < 0)
689 break;
690 status = Write16(state, FE_AG_REG_EGC_FAS_DEC__A, fastIncrDec, 0);
691 if (status < 0)
692 break;
693 status = Write16(state, FE_AG_REG_EGC_SLO_INC__A, slowIncrDec, 0);
694 if (status < 0)
695 break;
696 status = Write16(state, FE_AG_REG_EGC_SLO_DEC__A, slowIncrDec, 0);
697 if (status < 0)
698 break;
126f1e61
RM		 699 }
700 }
6cacdd46 701 } while (0);
126f1e61
RM		 702
703 } else {
704 /* No OFF mode for IF control */
9999daf4 705 return -1;
126f1e61
RM		 706 }
707 return status;
708}
709
126f1e61
RM		 710static int SetCfgRfAgc(struct drxd_state *state, struct SCfgAgc *cfg)
711{
712 int status = 0;
713
6cacdd46 714 if (cfg->outputLevel > DRXD_FE_CTRL_MAX)
126f1e61
RM		 715 return -1;
716
6cacdd46 717 if (cfg->ctrlMode == AGC_CTRL_USER) {
126f1e61 718 do {
6cacdd46
DH		 719 u16 AgModeLop = 0;
720 u16 level = (cfg->outputLevel);
126f1e61 721
6cacdd46 722 if (level == DRXD_FE_CTRL_MAX)
126f1e61
RM		 723 level++;
724
58d5eaec
MCC		 725 status = Write16(state, FE_AG_REG_PM2_AGC_WRI__A, level, 0x0000);
726 if (status < 0)
727 break;
126f1e61
RM		 728
729 /*==== Mode ====*/
730
731 /* Powerdown PD2, WRI source */
6cacdd46 732 state->m_FeAgRegAgPwd &= ~(FE_AG_REG_AG_PWD_PWD_PD2__M);
126f1e61 733 state->m_FeAgRegAgPwd |=
6cacdd46 734 FE_AG_REG_AG_PWD_PWD_PD2_DISABLE;
58d5eaec
MCC		 735 status = Write16(state, FE_AG_REG_AG_PWD__A, state->m_FeAgRegAgPwd, 0x0000);
736 if (status < 0)
737 break;
126f1e61 738
58d5eaec
MCC		 739 status = Read16(state, FE_AG_REG_AG_MODE_LOP__A, &AgModeLop, 0x0000);
740 if (status < 0)
741 break;
6cacdd46
DH		 742 AgModeLop &= (~(FE_AG_REG_AG_MODE_LOP_MODE_5__M |
743 FE_AG_REG_AG_MODE_LOP_MODE_E__M));
744 AgModeLop |= (FE_AG_REG_AG_MODE_LOP_MODE_5_STATIC |
745 FE_AG_REG_AG_MODE_LOP_MODE_E_STATIC);
58d5eaec
MCC		 746 status = Write16(state, FE_AG_REG_AG_MODE_LOP__A, AgModeLop, 0x0000);
747 if (status < 0)
748 break;
126f1e61
RM		 749
750 /* enable AGC2 pin */
751 {
752 u16 FeAgRegAgAgcSio = 0;
58d5eaec
MCC		 753 status = Read16(state, FE_AG_REG_AG_AGC_SIO__A, &FeAgRegAgAgcSio, 0x0000);
754 if (status < 0)
755 break;
126f1e61 756 FeAgRegAgAgcSio &=
6cacdd46 757 ~(FE_AG_REG_AG_AGC_SIO_AGC_SIO_2__M);
126f1e61 758 FeAgRegAgAgcSio |=
6cacdd46 759 FE_AG_REG_AG_AGC_SIO_AGC_SIO_2_OUTPUT;
58d5eaec
MCC		 760 status = Write16(state, FE_AG_REG_AG_AGC_SIO__A, FeAgRegAgAgcSio, 0x0000);
761 if (status < 0)
762 break;
126f1e61
RM		 763 }
764
6cacdd46
DH		 765 } while (0);
766 } else if (cfg->ctrlMode == AGC_CTRL_AUTO) {
767 u16 AgModeLop = 0;
126f1e61
RM		 768
769 do {
770 u16 level;
771 /* Automatic control */
772 /* Powerup PD2, AGC2 as output, TGC source */
773 (state->m_FeAgRegAgPwd) &=
6cacdd46 774 ~(FE_AG_REG_AG_PWD_PWD_PD2__M);
126f1e61 775 (state->m_FeAgRegAgPwd) |=
6cacdd46 776 FE_AG_REG_AG_PWD_PWD_PD2_DISABLE;
58d5eaec
MCC		 777 status = Write16(state, FE_AG_REG_AG_PWD__A, (state->m_FeAgRegAgPwd), 0x0000);
778 if (status < 0)
779 break;
6cacdd46 780
58d5eaec
MCC		 781 status = Read16(state, FE_AG_REG_AG_MODE_LOP__A, &AgModeLop, 0x0000);
782 if (status < 0)
783 break;
6cacdd46
DH		 784 AgModeLop &= (~(FE_AG_REG_AG_MODE_LOP_MODE_5__M |
785 FE_AG_REG_AG_MODE_LOP_MODE_E__M));
786 AgModeLop |= (FE_AG_REG_AG_MODE_LOP_MODE_5_STATIC |
787 FE_AG_REG_AG_MODE_LOP_MODE_E_DYNAMIC);
58d5eaec
MCC		 788 status = Write16(state, FE_AG_REG_AG_MODE_LOP__A, AgModeLop, 0x0000);
789 if (status < 0)
790 break;
126f1e61 791 /* Settle level */
6cacdd46
DH		 792 level = (((cfg->settleLevel) >> 4) &
793 FE_AG_REG_TGC_SET_LVL__M);
58d5eaec
MCC		 794 status = Write16(state, FE_AG_REG_TGC_SET_LVL__A, level, 0x0000);
795 if (status < 0)
796 break;
126f1e61
RM		 797
798 /* Min/max: don't care */
799
800 /* Speed: TODO */
801
802 /* enable AGC2 pin */
803 {
804 u16 FeAgRegAgAgcSio = 0;
58d5eaec
MCC		 805 status = Read16(state, FE_AG_REG_AG_AGC_SIO__A, &FeAgRegAgAgcSio, 0x0000);
806 if (status < 0)
807 break;
126f1e61 808 FeAgRegAgAgcSio &=
6cacdd46 809 ~(FE_AG_REG_AG_AGC_SIO_AGC_SIO_2__M);
126f1e61 810 FeAgRegAgAgcSio |=
6cacdd46 811 FE_AG_REG_AG_AGC_SIO_AGC_SIO_2_OUTPUT;
58d5eaec
MCC		 812 status = Write16(state, FE_AG_REG_AG_AGC_SIO__A, FeAgRegAgAgcSio, 0x0000);
813 if (status < 0)
814 break;
126f1e61
RM		 815 }
816
6cacdd46 817 } while (0);
126f1e61 818 } else {
6cacdd46 819 u16 AgModeLop = 0;
126f1e61
RM		 820
821 do {
822 /* No RF AGC control */
823 /* Powerdown PD2, AGC2 as output, WRI source */
824 (state->m_FeAgRegAgPwd) &=
6cacdd46 825 ~(FE_AG_REG_AG_PWD_PWD_PD2__M);
126f1e61 826 (state->m_FeAgRegAgPwd) |=
6cacdd46 827 FE_AG_REG_AG_PWD_PWD_PD2_ENABLE;
58d5eaec
MCC		 828 status = Write16(state, FE_AG_REG_AG_PWD__A, (state->m_FeAgRegAgPwd), 0x0000);
829 if (status < 0)
830 break;
126f1e61 831
58d5eaec
MCC		 832 status = Read16(state, FE_AG_REG_AG_MODE_LOP__A, &AgModeLop, 0x0000);
833 if (status < 0)
834 break;
6cacdd46
DH		 835 AgModeLop &= (~(FE_AG_REG_AG_MODE_LOP_MODE_5__M |
836 FE_AG_REG_AG_MODE_LOP_MODE_E__M));
837 AgModeLop |= (FE_AG_REG_AG_MODE_LOP_MODE_5_STATIC |
838 FE_AG_REG_AG_MODE_LOP_MODE_E_STATIC);
58d5eaec
MCC		 839 status = Write16(state, FE_AG_REG_AG_MODE_LOP__A, AgModeLop, 0x0000);
840 if (status < 0)
841 break;
126f1e61
RM		 842
843 /* set FeAgRegAgAgcSio AGC2 (RF) as input */
844 {
845 u16 FeAgRegAgAgcSio = 0;
58d5eaec
MCC		 846 status = Read16(state, FE_AG_REG_AG_AGC_SIO__A, &FeAgRegAgAgcSio, 0x0000);
847 if (status < 0)
848 break;
126f1e61 849 FeAgRegAgAgcSio &=
6cacdd46 850 ~(FE_AG_REG_AG_AGC_SIO_AGC_SIO_2__M);
126f1e61 851 FeAgRegAgAgcSio |=
6cacdd46 852 FE_AG_REG_AG_AGC_SIO_AGC_SIO_2_INPUT;
58d5eaec
MCC		 853 status = Write16(state, FE_AG_REG_AG_AGC_SIO__A, FeAgRegAgAgcSio, 0x0000);
854 if (status < 0)
855 break;
126f1e61 856 }
6cacdd46 857 } while (0);
126f1e61
RM		 858 }
859 return status;
860}
861
6cacdd46 862static int ReadIFAgc(struct drxd_state *state, u32 * pValue)
126f1e61
RM		 863{
864 int status = 0;
865
866 *pValue = 0;
6cacdd46 867 if (state->if_agc_cfg.ctrlMode != AGC_CTRL_OFF) {
126f1e61 868 u16 Value;
6cacdd46 869 status = Read16(state, FE_AG_REG_GC1_AGC_DAT__A, &Value, 0);
126f1e61 870 Value &= FE_AG_REG_GC1_AGC_DAT__M;
6cacdd46 871 if (status >= 0) {
126f1e61 872 /* 3.3V
6cacdd46
DH		 873 |
874 R1
875 |
126f1e61 876 Vin - R3 - * -- Vout
6cacdd46
DH		 877 |
878 R2
879 |
880 GND
881 */
126f1e61
RM		 882 u32 R1 = state->if_agc_cfg.R1;
883 u32 R2 = state->if_agc_cfg.R2;
884 u32 R3 = state->if_agc_cfg.R3;
885
f8a26f05
ES		 886 u32 Vmax, Rpar, Vmin, Vout;
887
888 if (R2 == 0 && (R1 == 0 || R3 == 0))
889 return 0;
890
891 Vmax = (3300 * R2) / (R1 + R2);
892 Rpar = (R2 * R3) / (R3 + R2);
893 Vmin = (3300 * Rpar) / (R1 + Rpar);
894 Vout = Vmin + ((Vmax - Vmin) * Value) / 1024;
126f1e61
RM		 895
896 *pValue = Vout;
897 }
898 }
899 return status;
900}
901
8f19f27e
DH		 902static int load_firmware(struct drxd_state *state, const char *fw_name)
903{
904 const struct firmware *fw;
905
906 if (request_firmware(&fw, fw_name, state->dev) < 0) {
907 printk(KERN_ERR "drxd: firmware load failure [%s]\n", fw_name);
908 return -EIO;
909 }
910
53090aad 911 state->microcode = kmemdup(fw->data, fw->size, GFP_KERNEL);
af28c996 912 if (!state->microcode) {
8afe9119 913 release_firmware(fw);
8f19f27e
DH		 914 return -ENOMEM;
915 }
916
8f19f27e 917 state->microcode_length = fw->size;
8afe9119 918 release_firmware(fw);
8f19f27e
DH		 919 return 0;
920}
921
126f1e61 922static int DownloadMicrocode(struct drxd_state *state,
9999daf4 923 const u8 *pMCImage, u32 Length)
126f1e61
RM		 924{
925 u8 *pSrc;
126f1e61
RM		 926 u32 Address;
927 u16 nBlocks;
928 u16 BlockSize;
6cacdd46
DH		 929 u32 offset = 0;
930 int i, status = 0;
126f1e61 931
6cacdd46 932 pSrc = (u8 *) pMCImage;
23aefb7e
HV		 933 /* We're not using Flags */
934 /* Flags = (pSrc[0] << 8) | pSrc[1]; */
6cacdd46
DH		 935 pSrc += sizeof(u16);
936 offset += sizeof(u16);
126f1e61 937 nBlocks = (pSrc[0] << 8) | pSrc[1];
6cacdd46
DH		 938 pSrc += sizeof(u16);
939 offset += sizeof(u16);
126f1e61 940
6cacdd46
DH		 941 for (i = 0; i < nBlocks; i++) {
942 Address = (pSrc[0] << 24) | (pSrc[1] << 16) |
943 (pSrc[2] << 8) | pSrc[3];
944 pSrc += sizeof(u32);
945 offset += sizeof(u32);
126f1e61 946
6cacdd46
DH		 947 BlockSize = ((pSrc[0] << 8) | pSrc[1]) * sizeof(u16);
948 pSrc += sizeof(u16);
949 offset += sizeof(u16);
126f1e61 950
23aefb7e
HV		 951 /* We're not using Flags */
952 /* u16 Flags = (pSrc[0] << 8) | pSrc[1]; */
6cacdd46
DH		 953 pSrc += sizeof(u16);
954 offset += sizeof(u16);
126f1e61 955
23aefb7e
HV		 956 /* We're not using BlockCRC */
957 /* u16 BlockCRC = (pSrc[0] << 8) | pSrc[1]; */
6cacdd46
DH		 958 pSrc += sizeof(u16);
959 offset += sizeof(u16);
126f1e61 960
6cacdd46
DH		 961 status = WriteBlock(state, Address, BlockSize,
962 pSrc, DRX_I2C_CLEARCRC);
963 if (status < 0)
126f1e61
RM		 964 break;
965 pSrc += BlockSize;
966 offset += BlockSize;
967 }
968
969 return status;
970}
971
6cacdd46 972static int HI_Command(struct drxd_state *state, u16 cmd, u16 * pResult)
126f1e61
RM		 973{
974 u32 nrRetries = 0;
126f1e61
RM		 975 int status;
976
9999daf4
MCC		 977 status = Write16(state, HI_RA_RAM_SRV_CMD__A, cmd, 0);
978 if (status < 0)
126f1e61
RM		 979 return status;
980
981 do {
6cacdd46
DH		 982 nrRetries += 1;
983 if (nrRetries > DRXD_MAX_RETRIES) {
984 status = -1;
126f1e61 985 break;
c2c1b415 986 }
f161544d
MCC		 987 status = Read16(state, HI_RA_RAM_SRV_CMD__A, NULL, 0);
988 } while (status != 0);
126f1e61 989
6cacdd46
DH		 990 if (status >= 0)
991 status = Read16(state, HI_RA_RAM_SRV_RES__A, pResult, 0);
126f1e61
RM		 992 return status;
993}
994
995static int HI_CfgCommand(struct drxd_state *state)
996{
6cacdd46 997 int status = 0;
126f1e61 998
834751d4 999 mutex_lock(&state->mutex);
6cacdd46 1000 Write16(state, HI_RA_RAM_SRV_CFG_KEY__A, HI_RA_RAM_SRV_RST_KEY_ACT, 0);
126f1e61 1001 Write16(state, HI_RA_RAM_SRV_CFG_DIV__A, state->hi_cfg_timing_div, 0);
6cacdd46 1002 Write16(state, HI_RA_RAM_SRV_CFG_BDL__A, state->hi_cfg_bridge_delay, 0);
126f1e61
RM		 1003 Write16(state, HI_RA_RAM_SRV_CFG_WUP__A, state->hi_cfg_wakeup_key, 0);
1004 Write16(state, HI_RA_RAM_SRV_CFG_ACT__A, state->hi_cfg_ctrl, 0);
1005
6cacdd46 1006 Write16(state, HI_RA_RAM_SRV_CFG_KEY__A, HI_RA_RAM_SRV_RST_KEY_ACT, 0);
126f1e61 1007
6cacdd46 1008 if ((state->hi_cfg_ctrl & HI_RA_RAM_SRV_CFG_ACT_PWD_EXE) ==
126f1e61 1009 HI_RA_RAM_SRV_CFG_ACT_PWD_EXE)
6cacdd46
DH		 1010 status = Write16(state, HI_RA_RAM_SRV_CMD__A,
1011 HI_RA_RAM_SRV_CMD_CONFIG, 0);
126f1e61 1012 else
843e44a1 1013 status = HI_Command(state, HI_RA_RAM_SRV_CMD_CONFIG, NULL);
834751d4 1014 mutex_unlock(&state->mutex);
126f1e61
RM		 1015 return status;
1016}
1017
1018static int InitHI(struct drxd_state *state)
1019{
1020 state->hi_cfg_wakeup_key = (state->chip_adr);
1021 /* port/bridge/power down ctrl */
1022 state->hi_cfg_ctrl = HI_RA_RAM_SRV_CFG_ACT_SLV0_ON;
6cacdd46 1023 return HI_CfgCommand(state);
126f1e61
RM		 1024}
1025
1026static int HI_ResetCommand(struct drxd_state *state)
1027{
1028 int status;
1029
834751d4 1030 mutex_lock(&state->mutex);
6cacdd46
DH		 1031 status = Write16(state, HI_RA_RAM_SRV_RST_KEY__A,
1032 HI_RA_RAM_SRV_RST_KEY_ACT, 0);
1033 if (status == 0)
843e44a1 1034 status = HI_Command(state, HI_RA_RAM_SRV_CMD_RESET, NULL);
834751d4 1035 mutex_unlock(&state->mutex);
126f1e61
RM		 1036 msleep(1);
1037 return status;
1038}
1039
6cacdd46 1040static int DRX_ConfigureI2CBridge(struct drxd_state *state, int bEnableBridge)
126f1e61
RM		 1041{
1042 state->hi_cfg_ctrl &= (~HI_RA_RAM_SRV_CFG_ACT_BRD__M);
6cacdd46 1043 if (bEnableBridge)
126f1e61
RM		 1044 state->hi_cfg_ctrl |= HI_RA_RAM_SRV_CFG_ACT_BRD_ON;
1045 else
1046 state->hi_cfg_ctrl |= HI_RA_RAM_SRV_CFG_ACT_BRD_OFF;
1047
1048 return HI_CfgCommand(state);
1049}
1050
1051#define HI_TR_WRITE 0x9
1052#define HI_TR_READ 0xA
1053#define HI_TR_READ_WRITE 0xB
1054#define HI_TR_BROADCAST 0x4
1055
1056#if 0
1057static int AtomicReadBlock(struct drxd_state *state,
9999daf4 1058 u32 Addr, u16 DataSize, u8 *pData, u8 Flags)
126f1e61
RM		 1059{
1060 int status;
6cacdd46 1061 int i = 0;
126f1e61
RM		 1062
1063 /* Parameter check */
6cacdd46 1064 if ((!pData) || ((DataSize & 1) != 0))
126f1e61
RM		 1065 return -1;
1066
834751d4 1067 mutex_lock(&state->mutex);
126f1e61
RM		 1068
1069 do {
1070 /* Instruct HI to read n bytes */
1071 /* TODO use proper names forthese egisters */
58d5eaec
MCC		 1072 status = Write16(state, HI_RA_RAM_SRV_CFG_KEY__A, (HI_TR_FUNC_ADDR & 0xFFFF), 0);
1073 if (status < 0)
1074 break;
1075 status = Write16(state, HI_RA_RAM_SRV_CFG_DIV__A, (u16) (Addr >> 16), 0);
1076 if (status < 0)
1077 break;
1078 status = Write16(state, HI_RA_RAM_SRV_CFG_BDL__A, (u16) (Addr & 0xFFFF), 0);
1079 if (status < 0)
1080 break;
1081 status = Write16(state, HI_RA_RAM_SRV_CFG_WUP__A, (u16) ((DataSize / 2) - 1), 0);
1082 if (status < 0)
1083 break;
1084 status = Write16(state, HI_RA_RAM_SRV_CFG_ACT__A, HI_TR_READ, 0);
1085 if (status < 0)
1086 break;
1087
1088 status = HI_Command(state, HI_RA_RAM_SRV_CMD_EXECUTE, 0);
1089 if (status < 0)
1090 break;
6cacdd46
DH		 1091
1092 } while (0);
1093
1094 if (status >= 0) {
1095 for (i = 0; i < (DataSize / 2); i += 1) {
126f1e61
RM		 1096 u16 word;
1097
1098 status = Read16(state, (HI_RA_RAM_USR_BEGIN__A + i),
1099 &word, 0);
6cacdd46 1100 if (status < 0)
126f1e61 1101 break;
6cacdd46
DH		 1102 pData[2 * i] = (u8) (word & 0xFF);
1103 pData[(2 * i) + 1] = (u8) (word >> 8);
126f1e61
RM		 1104 }
1105 }
834751d4 1106 mutex_unlock(&state->mutex);
126f1e61
RM		 1107 return status;
1108}
1109
1110static int AtomicReadReg32(struct drxd_state *state,
9999daf4 1111 u32 Addr, u32 *pData, u8 Flags)
126f1e61 1112{
6cacdd46 1113 u8 buf[sizeof(u32)];
126f1e61
RM		 1114 int status;
1115
1116 if (!pData)
1117 return -1;
6cacdd46
DH		 1118 status = AtomicReadBlock(state, Addr, sizeof(u32), buf, Flags);
1119 *pData = (((u32) buf[0]) << 0) +
1120 (((u32) buf[1]) << 8) +
1121 (((u32) buf[2]) << 16) + (((u32) buf[3]) << 24);
126f1e61
RM		 1122 return status;
1123}
1124#endif
1125
1126static int StopAllProcessors(struct drxd_state *state)
1127{
1128 return Write16(state, HI_COMM_EXEC__A,
1129 SC_COMM_EXEC_CTL_STOP, DRX_I2C_BROADCAST);
1130}
1131
1132static int EnableAndResetMB(struct drxd_state *state)
1133{
1134 if (state->type_A) {
1135 /* disable? monitor bus observe @ EC_OC */
1136 Write16(state, EC_OC_REG_OC_MON_SIO__A, 0x0000, 0x0000);
1137 }
1138
1139 /* do inverse broadcast, followed by explicit write to HI */
1140 Write16(state, HI_COMM_MB__A, 0x0000, DRX_I2C_BROADCAST);
1141 Write16(state, HI_COMM_MB__A, 0x0000, 0x0000);
1142 return 0;
1143}
1144
1145static int InitCC(struct drxd_state *state)
1146{
0f787c12
AP		 1147 int status = 0;
1148
126f1e61
RM		 1149 if (state->osc_clock_freq == 0 ||
1150 state->osc_clock_freq > 20000 ||
6cacdd46 1151 (state->osc_clock_freq % 4000) != 0) {
9999daf4 1152 printk(KERN_ERR "invalid osc frequency %d\n", state->osc_clock_freq);
126f1e61
RM		 1153 return -1;
1154 }
1155
0f787c12
AP		 1156 status |= Write16(state, CC_REG_OSC_MODE__A, CC_REG_OSC_MODE_M20, 0);
1157 status |= Write16(state, CC_REG_PLL_MODE__A,
1158 CC_REG_PLL_MODE_BYPASS_PLL |
1159 CC_REG_PLL_MODE_PUMP_CUR_12, 0);
1160 status |= Write16(state, CC_REG_REF_DIVIDE__A,
1161 state->osc_clock_freq / 4000, 0);
1162 status |= Write16(state, CC_REG_PWD_MODE__A, CC_REG_PWD_MODE_DOWN_PLL,
1163 0);
1164 status |= Write16(state, CC_REG_UPDATE__A, CC_REG_UPDATE_KEY, 0);
126f1e61 1165
0f787c12 1166 return status;
126f1e61
RM		 1167}
1168
1169static int ResetECOD(struct drxd_state *state)
1170{
1171 int status = 0;
1172
6cacdd46 1173 if (state->type_A)
126f1e61
RM		 1174 status = Write16(state, EC_OD_REG_SYNC__A, 0x0664, 0);
1175 else
1176 status = Write16(state, B_EC_OD_REG_SYNC__A, 0x0664, 0);
1177
6cacdd46 1178 if (!(status < 0))
126f1e61 1179 status = WriteTable(state, state->m_ResetECRAM);
6cacdd46 1180 if (!(status < 0))
126f1e61
RM		 1181 status = Write16(state, EC_OD_REG_COMM_EXEC__A, 0x0001, 0);
1182 return status;
1183}
1184
126f1e61
RM		 1185/* Configure PGA switch */
1186
1187static int SetCfgPga(struct drxd_state *state, int pgaSwitch)
1188{
1189 int status;
1190 u16 AgModeLop = 0;
1191 u16 AgModeHip = 0;
1192 do {
6cacdd46 1193 if (pgaSwitch) {
126f1e61
RM		 1194 /* PGA on */
1195 /* fine gain */
58d5eaec
MCC		 1196 status = Read16(state, B_FE_AG_REG_AG_MODE_LOP__A, &AgModeLop, 0x0000);
1197 if (status < 0)
1198 break;
6cacdd46
DH		 1199 AgModeLop &= (~(B_FE_AG_REG_AG_MODE_LOP_MODE_C__M));
1200 AgModeLop |= B_FE_AG_REG_AG_MODE_LOP_MODE_C_DYNAMIC;
58d5eaec
MCC		 1201 status = Write16(state, B_FE_AG_REG_AG_MODE_LOP__A, AgModeLop, 0x0000);
1202 if (status < 0)
1203 break;
126f1e61
RM		 1204
1205 /* coarse gain */
58d5eaec
MCC		 1206 status = Read16(state, B_FE_AG_REG_AG_MODE_HIP__A, &AgModeHip, 0x0000);
1207 if (status < 0)
1208 break;
6cacdd46
DH		 1209 AgModeHip &= (~(B_FE_AG_REG_AG_MODE_HIP_MODE_J__M));
1210 AgModeHip |= B_FE_AG_REG_AG_MODE_HIP_MODE_J_DYNAMIC;
58d5eaec
MCC		 1211 status = Write16(state, B_FE_AG_REG_AG_MODE_HIP__A, AgModeHip, 0x0000);
1212 if (status < 0)
1213 break;
126f1e61
RM		 1214
1215 /* enable fine and coarse gain, enable AAF,
1216 no ext resistor */
58d5eaec
MCC		 1217 status = Write16(state, B_FE_AG_REG_AG_PGA_MODE__A, B_FE_AG_REG_AG_PGA_MODE_PFY_PCY_AFY_REN, 0x0000);
1218 if (status < 0)
1219 break;
126f1e61
RM		 1220 } else {
1221 /* PGA off, bypass */
1222
1223 /* fine gain */
58d5eaec
MCC		 1224 status = Read16(state, B_FE_AG_REG_AG_MODE_LOP__A, &AgModeLop, 0x0000);
1225 if (status < 0)
1226 break;
6cacdd46
DH		 1227 AgModeLop &= (~(B_FE_AG_REG_AG_MODE_LOP_MODE_C__M));
1228 AgModeLop |= B_FE_AG_REG_AG_MODE_LOP_MODE_C_STATIC;
58d5eaec
MCC		 1229 status = Write16(state, B_FE_AG_REG_AG_MODE_LOP__A, AgModeLop, 0x0000);
1230 if (status < 0)
1231 break;
126f1e61
RM		 1232
1233 /* coarse gain */
58d5eaec
MCC		 1234 status = Read16(state, B_FE_AG_REG_AG_MODE_HIP__A, &AgModeHip, 0x0000);
1235 if (status < 0)
1236 break;
6cacdd46
DH		 1237 AgModeHip &= (~(B_FE_AG_REG_AG_MODE_HIP_MODE_J__M));
1238 AgModeHip |= B_FE_AG_REG_AG_MODE_HIP_MODE_J_STATIC;
58d5eaec
MCC		 1239 status = Write16(state, B_FE_AG_REG_AG_MODE_HIP__A, AgModeHip, 0x0000);
1240 if (status < 0)
1241 break;
126f1e61
RM		 1242
1243 /* disable fine and coarse gain, enable AAF,
1244 no ext resistor */
58d5eaec
MCC		 1245 status = Write16(state, B_FE_AG_REG_AG_PGA_MODE__A, B_FE_AG_REG_AG_PGA_MODE_PFN_PCN_AFY_REN, 0x0000);
1246 if (status < 0)
1247 break;
126f1e61 1248 }
9999daf4 1249 } while (0);
126f1e61
RM		 1250 return status;
1251}
1252
1253static int InitFE(struct drxd_state *state)
1254{
6cacdd46 1255 int status;
126f1e61 1256
6cacdd46 1257 do {
58d5eaec
MCC		 1258 status = WriteTable(state, state->m_InitFE_1);
1259 if (status < 0)
1260 break;
126f1e61 1261
6cacdd46
DH		 1262 if (state->type_A) {
1263 status = Write16(state, FE_AG_REG_AG_PGA_MODE__A,
1264 FE_AG_REG_AG_PGA_MODE_PFN_PCN_AFY_REN,
1265 0);
1266 } else {
1267 if (state->PGA)
1268 status = SetCfgPga(state, 0);
1269 else
1270 status =
1271 Write16(state, B_FE_AG_REG_AG_PGA_MODE__A,
1272 B_FE_AG_REG_AG_PGA_MODE_PFN_PCN_AFY_REN,
1273 0);
1274 }
126f1e61 1275
6cacdd46
DH		 1276 if (status < 0)
1277 break;
58d5eaec
MCC		 1278 status = Write16(state, FE_AG_REG_AG_AGC_SIO__A, state->m_FeAgRegAgAgcSio, 0x0000);
1279 if (status < 0)
1280 break;
1281 status = Write16(state, FE_AG_REG_AG_PWD__A, state->m_FeAgRegAgPwd, 0x0000);
1282 if (status < 0)
1283 break;
126f1e61 1284
58d5eaec
MCC		 1285 status = WriteTable(state, state->m_InitFE_2);
1286 if (status < 0)
1287 break;
126f1e61 1288
6cacdd46 1289 } while (0);
126f1e61 1290
6cacdd46 1291 return status;
126f1e61
RM		 1292}
1293
1294static int InitFT(struct drxd_state *state)
1295{
1296 /*
6cacdd46
DH		 1297 norm OFFSET, MB says =2 voor 8K en =3 voor 2K waarschijnlijk
1298 SC stuff
1299 */
1300 return Write16(state, FT_REG_COMM_EXEC__A, 0x0001, 0x0000);
126f1e61
RM		 1301}
1302
1303static int SC_WaitForReady(struct drxd_state *state)
1304{
126f1e61
RM		 1305 int i;
1306
6cacdd46 1307 for (i = 0; i < DRXD_MAX_RETRIES; i += 1) {
f161544d
MCC		 1308 int status = Read16(state, SC_RA_RAM_CMD__A, NULL, 0);
1309 if (status == 0)
126f1e61
RM		 1310 return status;
1311 }
1312 return -1;
1313}
1314
1315static int SC_SendCommand(struct drxd_state *state, u16 cmd)
1316{
f161544d 1317 int status = 0, ret;
126f1e61
RM		 1318 u16 errCode;
1319
0f787c12
AP		 1320 status = Write16(state, SC_RA_RAM_CMD__A, cmd, 0);
1321 if (status < 0)
1322 return status;
1323
126f1e61
RM		 1324 SC_WaitForReady(state);
1325
f161544d 1326 ret = Read16(state, SC_RA_RAM_CMD_ADDR__A, &errCode, 0);
126f1e61 1327
f161544d 1328 if (ret < 0 || errCode == 0xFFFF) {
9999daf4 1329 printk(KERN_ERR "Command Error\n");
6cacdd46 1330 status = -1;
126f1e61
RM		 1331 }
1332
1333 return status;
1334}
1335
1336static int SC_ProcStartCommand(struct drxd_state *state,
6cacdd46 1337 u16 subCmd, u16 param0, u16 param1)
126f1e61 1338{
f161544d 1339 int ret, status = 0;
126f1e61
RM		 1340 u16 scExec;
1341
834751d4 1342 mutex_lock(&state->mutex);
126f1e61 1343 do {
f161544d
MCC		 1344 ret = Read16(state, SC_COMM_EXEC__A, &scExec, 0);
1345 if (ret < 0 || scExec != 1) {
6cacdd46 1346 status = -1;
126f1e61
RM		 1347 break;
1348 }
1349 SC_WaitForReady(state);
0f787c12
AP		 1350 status |= Write16(state, SC_RA_RAM_CMD_ADDR__A, subCmd, 0);
1351 status |= Write16(state, SC_RA_RAM_PARAM1__A, param1, 0);
1352 status |= Write16(state, SC_RA_RAM_PARAM0__A, param0, 0);
126f1e61
RM		 1353
1354 SC_SendCommand(state, SC_RA_RAM_CMD_PROC_START);
6cacdd46 1355 } while (0);
834751d4 1356 mutex_unlock(&state->mutex);
126f1e61
RM		 1357 return status;
1358}
1359
126f1e61 1360static int SC_SetPrefParamCommand(struct drxd_state *state,
6cacdd46 1361 u16 subCmd, u16 param0, u16 param1)
126f1e61
RM		 1362{
1363 int status;
1364
834751d4 1365 mutex_lock(&state->mutex);
126f1e61 1366 do {
58d5eaec
MCC		 1367 status = SC_WaitForReady(state);
1368 if (status < 0)
1369 break;
1370 status = Write16(state, SC_RA_RAM_CMD_ADDR__A, subCmd, 0);
1371 if (status < 0)
1372 break;
1373 status = Write16(state, SC_RA_RAM_PARAM1__A, param1, 0);
1374 if (status < 0)
1375 break;
1376 status = Write16(state, SC_RA_RAM_PARAM0__A, param0, 0);
1377 if (status < 0)
1378 break;
6cacdd46 1379
58d5eaec
MCC		 1380 status = SC_SendCommand(state, SC_RA_RAM_CMD_SET_PREF_PARAM);
1381 if (status < 0)
1382 break;
6cacdd46 1383 } while (0);
834751d4 1384 mutex_unlock(&state->mutex);
126f1e61
RM		 1385 return status;
1386}
1387
1388#if 0
6cacdd46 1389static int SC_GetOpParamCommand(struct drxd_state *state, u16 * result)
126f1e61 1390{
6cacdd46 1391 int status = 0;
126f1e61 1392
834751d4 1393 mutex_lock(&state->mutex);
126f1e61 1394 do {
58d5eaec
MCC		 1395 status = SC_WaitForReady(state);
1396 if (status < 0)
1397 break;
1398 status = SC_SendCommand(state, SC_RA_RAM_CMD_GET_OP_PARAM);
1399 if (status < 0)
1400 break;
1401 status = Read16(state, SC_RA_RAM_PARAM0__A, result, 0);
1402 if (status < 0)
1403 break;
6cacdd46 1404 } while (0);
834751d4 1405 mutex_unlock(&state->mutex);
126f1e61
RM		 1406 return status;
1407}
1408#endif
1409
1410static int ConfigureMPEGOutput(struct drxd_state *state, int bEnableOutput)
1411{
1412 int status;
1413
1414 do {
1415 u16 EcOcRegIprInvMpg = 0;
1416 u16 EcOcRegOcModeLop = 0;
1417 u16 EcOcRegOcModeHip = 0;
6cacdd46 1418 u16 EcOcRegOcMpgSio = 0;
126f1e61 1419
58d5eaec 1420 /*CHK_ERROR(Read16(state, EC_OC_REG_OC_MODE_LOP__A, &EcOcRegOcModeLop, 0)); */
126f1e61 1421
6cacdd46
DH		 1422 if (state->operation_mode == OM_DVBT_Diversity_Front) {
1423 if (bEnableOutput) {
126f1e61 1424 EcOcRegOcModeHip |=
6cacdd46
DH		 1425 B_EC_OC_REG_OC_MODE_HIP_MPG_BUS_SRC_MONITOR;
1426 } else
126f1e61
RM		 1427 EcOcRegOcMpgSio |= EC_OC_REG_OC_MPG_SIO__M;
1428 EcOcRegOcModeLop |=
6cacdd46
DH		 1429 EC_OC_REG_OC_MODE_LOP_PAR_ENA_DISABLE;
1430 } else {
126f1e61
RM		 1431 EcOcRegOcModeLop = state->m_EcOcRegOcModeLop;
1432
1433 if (bEnableOutput)
6cacdd46 1434 EcOcRegOcMpgSio &= (~(EC_OC_REG_OC_MPG_SIO__M));
126f1e61
RM		 1435 else
1436 EcOcRegOcMpgSio |= EC_OC_REG_OC_MPG_SIO__M;
1437
1438 /* Don't Insert RS Byte */
6cacdd46 1439 if (state->insert_rs_byte) {
126f1e61 1440 EcOcRegOcModeLop &=
6cacdd46 1441 (~(EC_OC_REG_OC_MODE_LOP_PAR_ENA__M));
126f1e61 1442 EcOcRegOcModeHip &=
6cacdd46 1443 (~EC_OC_REG_OC_MODE_HIP_MPG_PAR_VAL__M);
126f1e61
RM		 1444 EcOcRegOcModeHip |=
1445 EC_OC_REG_OC_MODE_HIP_MPG_PAR_VAL_ENABLE;
1446 } else {
1447 EcOcRegOcModeLop |=
6cacdd46 1448 EC_OC_REG_OC_MODE_LOP_PAR_ENA_DISABLE;
126f1e61
RM		 1449 EcOcRegOcModeHip &=
1450 (~EC_OC_REG_OC_MODE_HIP_MPG_PAR_VAL__M);
1451 EcOcRegOcModeHip |=
1452 EC_OC_REG_OC_MODE_HIP_MPG_PAR_VAL_DISABLE;
1453 }
1454
1455 /* Mode = Parallel */
6cacdd46 1456 if (state->enable_parallel)
126f1e61
RM		 1457 EcOcRegOcModeLop &=
1458 (~(EC_OC_REG_OC_MODE_LOP_MPG_TRM_MDE__M));
1459 else
1460 EcOcRegOcModeLop |=
1461 EC_OC_REG_OC_MODE_LOP_MPG_TRM_MDE_SERIAL;
1462 }
1463 /* Invert Data */
1464 /* EcOcRegIprInvMpg |= 0x00FF; */
1465 EcOcRegIprInvMpg &= (~(0x00FF));
1466
1467 /* Invert Error ( we don't use the pin ) */
1468 /* EcOcRegIprInvMpg |= 0x0100; */
1469 EcOcRegIprInvMpg &= (~(0x0100));
1470
1471 /* Invert Start ( we don't use the pin ) */
1472 /* EcOcRegIprInvMpg |= 0x0200; */
1473 EcOcRegIprInvMpg &= (~(0x0200));
1474
1475 /* Invert Valid ( we don't use the pin ) */
1476 /* EcOcRegIprInvMpg |= 0x0400; */
1477 EcOcRegIprInvMpg &= (~(0x0400));
1478
1479 /* Invert Clock */
1480 /* EcOcRegIprInvMpg |= 0x0800; */
1481 EcOcRegIprInvMpg &= (~(0x0800));
1482
1483 /* EcOcRegOcModeLop =0x05; */
58d5eaec
MCC		 1484 status = Write16(state, EC_OC_REG_IPR_INV_MPG__A, EcOcRegIprInvMpg, 0);
1485 if (status < 0)
1486 break;
1487 status = Write16(state, EC_OC_REG_OC_MODE_LOP__A, EcOcRegOcModeLop, 0);
1488 if (status < 0)
1489 break;
1490 status = Write16(state, EC_OC_REG_OC_MODE_HIP__A, EcOcRegOcModeHip, 0x0000);
1491 if (status < 0)
1492 break;
1493 status = Write16(state, EC_OC_REG_OC_MPG_SIO__A, EcOcRegOcMpgSio, 0);
1494 if (status < 0)
1495 break;
6cacdd46 1496 } while (0);
126f1e61
RM		 1497 return status;
1498}
1499
1500static int SetDeviceTypeId(struct drxd_state *state)
1501{
6cacdd46
DH		 1502 int status = 0;
1503 u16 deviceId = 0;
1504
1505 do {
58d5eaec
MCC		 1506 status = Read16(state, CC_REG_JTAGID_L__A, &deviceId, 0);
1507 if (status < 0)
1508 break;
6cacdd46 1509 /* TODO: why twice? */
58d5eaec
MCC		 1510 status = Read16(state, CC_REG_JTAGID_L__A, &deviceId, 0);
1511 if (status < 0)
1512 break;
9999daf4 1513 printk(KERN_INFO "drxd: deviceId = %04x\n", deviceId);
6cacdd46
DH		 1514
1515 state->type_A = 0;
1516 state->PGA = 0;
1517 state->diversity = 0;
1518 if (deviceId == 0) { /* on A2 only 3975 available */
1519 state->type_A = 1;
9999daf4 1520 printk(KERN_INFO "DRX3975D-A2\n");
6cacdd46
DH		 1521 } else {
1522 deviceId >>= 12;
9999daf4 1523 printk(KERN_INFO "DRX397%dD-B1\n", deviceId);
6cacdd46
DH		 1524 switch (deviceId) {
1525 case 4:
1526 state->diversity = 1;
06eeefe8 1527 /* fall through */
6cacdd46
DH		 1528 case 3:
1529 case 7:
1530 state->PGA = 1;
1531 break;
1532 case 6:
1533 state->diversity = 1;
06eeefe8 1534 /* fall through */
6cacdd46
DH		 1535 case 5:
1536 case 8:
1537 break;
1538 default:
1539 status = -1;
1540 break;
1541 }
1542 }
1543 } while (0);
1544
1545 if (status < 0)
1546 return status;
1547
1548 /* Init Table selection */
1549 state->m_InitAtomicRead = DRXD_InitAtomicRead;
1550 state->m_InitSC = DRXD_InitSC;
1551 state->m_ResetECRAM = DRXD_ResetECRAM;
1552 if (state->type_A) {
1553 state->m_ResetCEFR = DRXD_ResetCEFR;
1554 state->m_InitFE_1 = DRXD_InitFEA2_1;
1555 state->m_InitFE_2 = DRXD_InitFEA2_2;
1556 state->m_InitCP = DRXD_InitCPA2;
1557 state->m_InitCE = DRXD_InitCEA2;
1558 state->m_InitEQ = DRXD_InitEQA2;
1559 state->m_InitEC = DRXD_InitECA2;
1560 if (load_firmware(state, DRX_FW_FILENAME_A2))
1561 return -EIO;
1562 } else {
1563 state->m_ResetCEFR = NULL;
1564 state->m_InitFE_1 = DRXD_InitFEB1_1;
1565 state->m_InitFE_2 = DRXD_InitFEB1_2;
1566 state->m_InitCP = DRXD_InitCPB1;
1567 state->m_InitCE = DRXD_InitCEB1;
1568 state->m_InitEQ = DRXD_InitEQB1;
1569 state->m_InitEC = DRXD_InitECB1;
1570 if (load_firmware(state, DRX_FW_FILENAME_B1))
1571 return -EIO;
1572 }
1573 if (state->diversity) {
1574 state->m_InitDiversityFront = DRXD_InitDiversityFront;
1575 state->m_InitDiversityEnd = DRXD_InitDiversityEnd;
1576 state->m_DisableDiversity = DRXD_DisableDiversity;
1577 state->m_StartDiversityFront = DRXD_StartDiversityFront;
1578 state->m_StartDiversityEnd = DRXD_StartDiversityEnd;
1579 state->m_DiversityDelay8MHZ = DRXD_DiversityDelay8MHZ;
1580 state->m_DiversityDelay6MHZ = DRXD_DiversityDelay6MHZ;
1581 } else {
1582 state->m_InitDiversityFront = NULL;
1583 state->m_InitDiversityEnd = NULL;
1584 state->m_DisableDiversity = NULL;
1585 state->m_StartDiversityFront = NULL;
1586 state->m_StartDiversityEnd = NULL;
1587 state->m_DiversityDelay8MHZ = NULL;
1588 state->m_DiversityDelay6MHZ = NULL;
1589 }
1590
1591 return status;
126f1e61
RM		 1592}
1593
1594static int CorrectSysClockDeviation(struct drxd_state *state)
1595{
1596 int status;
6cacdd46
DH		 1597 s32 incr = 0;
1598 s32 nomincr = 0;
1599 u32 bandwidth = 0;
1600 u32 sysClockInHz = 0;
1601 u32 sysClockFreq = 0; /* in kHz */
126f1e61
RM		 1602 s16 oscClockDeviation;
1603 s16 Diff;
1604
1605 do {
1606 /* Retrieve bandwidth and incr, sanity check */
1607
1608 /* These accesses should be AtomicReadReg32, but that
1609 causes trouble (at least for diversity */
9999daf4 1610 status = Read32(state, LC_RA_RAM_IFINCR_NOM_L__A, ((u32 *) &nomincr), 0);
58d5eaec
MCC		 1611 if (status < 0)
1612 break;
9999daf4 1613 status = Read32(state, FE_IF_REG_INCR0__A, (u32 *) &incr, 0);
58d5eaec
MCC		 1614 if (status < 0)
1615 break;
6cacdd46
DH		 1616
1617 if (state->type_A) {
1618 if ((nomincr - incr < -500) || (nomincr - incr > 500))
126f1e61
RM		 1619 break;
1620 } else {
6cacdd46 1621 if ((nomincr - incr < -2000) || (nomincr - incr > 2000))
126f1e61
RM		 1622 break;
1623 }
1624
9f97c288
MCC		 1625 switch (state->props.bandwidth_hz) {
1626 case 8000000:
126f1e61
RM		 1627 bandwidth = DRXD_BANDWIDTH_8MHZ_IN_HZ;
1628 break;
9f97c288 1629 case 7000000:
126f1e61
RM		 1630 bandwidth = DRXD_BANDWIDTH_7MHZ_IN_HZ;
1631 break;
9f97c288 1632 case 6000000:
126f1e61
RM		 1633 bandwidth = DRXD_BANDWIDTH_6MHZ_IN_HZ;
1634 break;
6cacdd46 1635 default:
126f1e61
RM		 1636 return -1;
1637 break;
1638 }
1639
1640 /* Compute new sysclock value
1641 sysClockFreq = (((incr + 2^23)*bandwidth)/2^21)/1000 */
6cacdd46
DH		 1642 incr += (1 << 23);
1643 sysClockInHz = MulDiv32(incr, bandwidth, 1 << 21);
1644 sysClockFreq = (u32) (sysClockInHz / 1000);
126f1e61 1645 /* rounding */
9999daf4 1646 if ((sysClockInHz % 1000) > 500)
126f1e61 1647 sysClockFreq++;
126f1e61
RM		 1648
1649 /* Compute clock deviation in ppm */
6cacdd46
DH		 1650 oscClockDeviation = (u16) ((((s32) (sysClockFreq) -
1651 (s32)
1652 (state->expected_sys_clock_freq)) *
1653 1000000L) /
1654 (s32)
1655 (state->expected_sys_clock_freq));
126f1e61
RM		 1656
1657 Diff = oscClockDeviation - state->osc_clock_deviation;
9999daf4 1658 /*printk(KERN_INFO "sysclockdiff=%d\n", Diff); */
6cacdd46 1659 if (Diff >= -200 && Diff <= 200) {
126f1e61 1660 state->sys_clock_freq = (u16) sysClockFreq;
6cacdd46 1661 if (oscClockDeviation != state->osc_clock_deviation) {
126f1e61 1662 if (state->config.osc_deviation) {
6cacdd46
DH		 1663 state->config.osc_deviation(state->priv,
1664 oscClockDeviation,
1665 1);
1666 state->osc_clock_deviation =
1667 oscClockDeviation;
126f1e61
RM		 1668 }
1669 }
1670 /* switch OFF SRMM scan in SC */
58d5eaec
MCC		 1671 status = Write16(state, SC_RA_RAM_SAMPLE_RATE_COUNT__A, DRXD_OSCDEV_DONT_SCAN, 0);
1672 if (status < 0)
1673 break;
126f1e61
RM		 1674 /* overrule FE_IF internal value for
1675 proper re-locking */
58d5eaec
MCC		 1676 status = Write16(state, SC_RA_RAM_IF_SAVE__AX, state->current_fe_if_incr, 0);
1677 if (status < 0)
1678 break;
126f1e61
RM		 1679 state->cscd_state = CSCD_SAVED;
1680 }
6cacdd46 1681 } while (0);
126f1e61 1682
9999daf4 1683 return status;
126f1e61
RM		 1684}
1685
1686static int DRX_Stop(struct drxd_state *state)
1687{
1688 int status;
1689
6cacdd46 1690 if (state->drxd_state != DRXD_STARTED)
126f1e61
RM		 1691 return 0;
1692
1693 do {
6cacdd46 1694 if (state->cscd_state != CSCD_SAVED) {
126f1e61 1695 u32 lock;
58d5eaec
MCC		 1696 status = DRX_GetLockStatus(state, &lock);
1697 if (status < 0)
1698 break;
126f1e61
RM		 1699 }
1700
58d5eaec
MCC		 1701 status = StopOC(state);
1702 if (status < 0)
1703 break;
126f1e61
RM		 1704
1705 state->drxd_state = DRXD_STOPPED;
1706
58d5eaec
MCC		 1707 status = ConfigureMPEGOutput(state, 0);
1708 if (status < 0)
1709 break;
126f1e61 1710
6cacdd46 1711 if (state->type_A) {
126f1e61 1712 /* Stop relevant processors off the device */
58d5eaec
MCC		 1713 status = Write16(state, EC_OD_REG_COMM_EXEC__A, 0x0000, 0x0000);
1714 if (status < 0)
1715 break;
126f1e61 1716
58d5eaec
MCC		 1717 status = Write16(state, SC_COMM_EXEC__A, SC_COMM_EXEC_CTL_STOP, 0);
1718 if (status < 0)
1719 break;
1720 status = Write16(state, LC_COMM_EXEC__A, SC_COMM_EXEC_CTL_STOP, 0);
1721 if (status < 0)
1722 break;
126f1e61
RM		 1723 } else {
1724 /* Stop all processors except HI & CC & FE */
58d5eaec
MCC		 1725 status = Write16(state, B_SC_COMM_EXEC__A, SC_COMM_EXEC_CTL_STOP, 0);
1726 if (status < 0)
1727 break;
1728 status = Write16(state, B_LC_COMM_EXEC__A, SC_COMM_EXEC_CTL_STOP, 0);
1729 if (status < 0)
1730 break;
1731 status = Write16(state, B_FT_COMM_EXEC__A, SC_COMM_EXEC_CTL_STOP, 0);
1732 if (status < 0)
1733 break;
1734 status = Write16(state, B_CP_COMM_EXEC__A, SC_COMM_EXEC_CTL_STOP, 0);
1735 if (status < 0)
1736 break;
1737 status = Write16(state, B_CE_COMM_EXEC__A, SC_COMM_EXEC_CTL_STOP, 0);
1738 if (status < 0)
1739 break;
1740 status = Write16(state, B_EQ_COMM_EXEC__A, SC_COMM_EXEC_CTL_STOP, 0);
1741 if (status < 0)
1742 break;
1743 status = Write16(state, EC_OD_REG_COMM_EXEC__A, 0x0000, 0);
1744 if (status < 0)
1745 break;
126f1e61
RM		 1746 }
1747
6cacdd46 1748 } while (0);
126f1e61
RM		 1749 return status;
1750}
1751
8b35c2fe
MCC		 1752#if 0 /* Currently unused */
1753static int SetOperationMode(struct drxd_state *state, int oMode)
126f1e61
RM		 1754{
1755 int status;
1756
1757 do {
1758 if (state->drxd_state != DRXD_STOPPED) {
1759 status = -1;
1760 break;
1761 }
1762
1763 if (oMode == state->operation_mode) {
1764 status = 0;
1765 break;
1766 }
1767
1768 if (oMode != OM_Default && !state->diversity) {
1769 status = -1;
1770 break;
1771 }
1772
6cacdd46 1773 switch (oMode) {
126f1e61 1774 case OM_DVBT_Diversity_Front:
6cacdd46 1775 status = WriteTable(state, state->m_InitDiversityFront);
126f1e61
RM		 1776 break;
1777 case OM_DVBT_Diversity_End:
6cacdd46 1778 status = WriteTable(state, state->m_InitDiversityEnd);
126f1e61
RM		 1779 break;
1780 case OM_Default:
1781 /* We need to check how to
1782 get DRXD out of diversity */
1783 default:
1784 status = WriteTable(state, state->m_DisableDiversity);
1785 break;
1786 }
6cacdd46 1787 } while (0);
126f1e61
RM		 1788
1789 if (!status)
1790 state->operation_mode = oMode;
1791 return status;
1792}
8b35c2fe 1793#endif
126f1e61 1794
126f1e61
RM		 1795static int StartDiversity(struct drxd_state *state)
1796{
6cacdd46 1797 int status = 0;
126f1e61
RM		 1798 u16 rcControl;
1799
1800 do {
1801 if (state->operation_mode == OM_DVBT_Diversity_Front) {
58d5eaec
MCC		 1802 status = WriteTable(state, state->m_StartDiversityFront);
1803 if (status < 0)
1804 break;
6cacdd46 1805 } else if (state->operation_mode == OM_DVBT_Diversity_End) {
58d5eaec
MCC		 1806 status = WriteTable(state, state->m_StartDiversityEnd);
1807 if (status < 0)
1808 break;
9f97c288 1809 if (state->props.bandwidth_hz == 8000000) {
58d5eaec
MCC		 1810 status = WriteTable(state, state->m_DiversityDelay8MHZ);
1811 if (status < 0)
1812 break;
126f1e61 1813 } else {
58d5eaec
MCC		 1814 status = WriteTable(state, state->m_DiversityDelay6MHZ);
1815 if (status < 0)
1816 break;
126f1e61
RM		 1817 }
1818
58d5eaec
MCC		 1819 status = Read16(state, B_EQ_REG_RC_SEL_CAR__A, &rcControl, 0);
1820 if (status < 0)
1821 break;
126f1e61
RM		 1822 rcControl &= ~(B_EQ_REG_RC_SEL_CAR_FFTMODE__M);
1823 rcControl |= B_EQ_REG_RC_SEL_CAR_DIV_ON |
6cacdd46
DH		 1824 /* combining enabled */
1825 B_EQ_REG_RC_SEL_CAR_MEAS_A_CC |
1826 B_EQ_REG_RC_SEL_CAR_PASS_A_CC |
1827 B_EQ_REG_RC_SEL_CAR_LOCAL_A_CC;
58d5eaec
MCC		 1828 status = Write16(state, B_EQ_REG_RC_SEL_CAR__A, rcControl, 0);
1829 if (status < 0)
1830 break;
126f1e61 1831 }
6cacdd46 1832 } while (0);
126f1e61
RM		 1833 return status;
1834}
1835
126f1e61
RM		 1836static int SetFrequencyShift(struct drxd_state *state,
1837 u32 offsetFreq, int channelMirrored)
1838{
1839 int negativeShift = (state->tuner_mirrors == channelMirrored);
1840
1841 /* Handle all mirroring
1842 *
1843 * Note: ADC mirroring (aliasing) is implictly handled by limiting
1844 * feFsRegAddInc to 28 bits below
1845 * (if the result before masking is more than 28 bits, this means
1846 * that the ADC is mirroring.
1847 * The masking is in fact the aliasing of the ADC)
1848 *
1849 */
1850
1851 /* Compute register value, unsigned computation */
6cacdd46 1852 state->fe_fs_add_incr = MulDiv32(state->intermediate_freq +
126f1e61 1853 offsetFreq,
6cacdd46 1854 1 << 28, state->sys_clock_freq);
126f1e61
RM		 1855 /* Remove integer part */
1856 state->fe_fs_add_incr &= 0x0FFFFFFFL;
9999daf4 1857 if (negativeShift)
6cacdd46 1858 state->fe_fs_add_incr = ((1 << 28) - state->fe_fs_add_incr);
126f1e61
RM		 1859
1860 /* Save the frequency shift without tunerOffset compensation
1861 for CtrlGetChannel. */
6cacdd46
DH		 1862 state->org_fe_fs_add_incr = MulDiv32(state->intermediate_freq,
1863 1 << 28, state->sys_clock_freq);
126f1e61
RM		 1864 /* Remove integer part */
1865 state->org_fe_fs_add_incr &= 0x0FFFFFFFL;
1866 if (negativeShift)
6cacdd46 1867 state->org_fe_fs_add_incr = ((1L << 28) -
126f1e61
RM		 1868 state->org_fe_fs_add_incr);
1869
1870 return Write32(state, FE_FS_REG_ADD_INC_LOP__A,
1871 state->fe_fs_add_incr, 0);
1872}
1873
6cacdd46
DH		 1874static int SetCfgNoiseCalibration(struct drxd_state *state,
1875 struct SNoiseCal *noiseCal)
126f1e61
RM		 1876{
1877 u16 beOptEna;
6cacdd46 1878 int status = 0;
126f1e61
RM		 1879
1880 do {
58d5eaec
MCC		 1881 status = Read16(state, SC_RA_RAM_BE_OPT_ENA__A, &beOptEna, 0);
1882 if (status < 0)
1883 break;
6cacdd46 1884 if (noiseCal->cpOpt) {
126f1e61
RM		 1885 beOptEna |= (1 << SC_RA_RAM_BE_OPT_ENA_CP_OPT);
1886 } else {
1887 beOptEna &= ~(1 << SC_RA_RAM_BE_OPT_ENA_CP_OPT);
58d5eaec
MCC		 1888 status = Write16(state, CP_REG_AC_NEXP_OFFS__A, noiseCal->cpNexpOfs, 0);
1889 if (status < 0)
1890 break;
126f1e61 1891 }
58d5eaec
MCC		 1892 status = Write16(state, SC_RA_RAM_BE_OPT_ENA__A, beOptEna, 0);
1893 if (status < 0)
1894 break;
126f1e61 1895
6cacdd46 1896 if (!state->type_A) {
58d5eaec
MCC		 1897 status = Write16(state, B_SC_RA_RAM_CO_TD_CAL_2K__A, noiseCal->tdCal2k, 0);
1898 if (status < 0)
1899 break;
1900 status = Write16(state, B_SC_RA_RAM_CO_TD_CAL_8K__A, noiseCal->tdCal8k, 0);
1901 if (status < 0)
1902 break;
126f1e61 1903 }
6cacdd46 1904 } while (0);
126f1e61
RM		 1905
1906 return status;
1907}
1908
1909static int DRX_Start(struct drxd_state *state, s32 off)
1910{
9f97c288 1911 struct dtv_frontend_properties *p = &state->props;
126f1e61
RM		 1912 int status;
1913
6cacdd46
DH		 1914 u16 transmissionParams = 0;
1915 u16 operationMode = 0;
1916 u16 qpskTdTpsPwr = 0;
1917 u16 qam16TdTpsPwr = 0;
1918 u16 qam64TdTpsPwr = 0;
1919 u32 feIfIncr = 0;
1920 u32 bandwidth = 0;
126f1e61
RM		 1921 int mirrorFreqSpect;
1922
6cacdd46
DH		 1923 u16 qpskSnCeGain = 0;
1924 u16 qam16SnCeGain = 0;
1925 u16 qam64SnCeGain = 0;
1926 u16 qpskIsGainMan = 0;
1927 u16 qam16IsGainMan = 0;
1928 u16 qam64IsGainMan = 0;
1929 u16 qpskIsGainExp = 0;
1930 u16 qam16IsGainExp = 0;
1931 u16 qam64IsGainExp = 0;
1932 u16 bandwidthParam = 0;
1933
1934 if (off < 0)
1935 off = (off - 500) / 1000;
126f1e61 1936 else
6cacdd46 1937 off = (off + 500) / 1000;
126f1e61
RM		 1938
1939 do {
1940 if (state->drxd_state != DRXD_STOPPED)
1941 return -1;
58d5eaec
MCC		 1942 status = ResetECOD(state);
1943 if (status < 0)
1944 break;
126f1e61 1945 if (state->type_A) {
58d5eaec
MCC		 1946 status = InitSC(state);
1947 if (status < 0)
1948 break;
126f1e61 1949 } else {
58d5eaec
MCC		 1950 status = InitFT(state);
1951 if (status < 0)
1952 break;
1953 status = InitCP(state);
1954 if (status < 0)
1955 break;
1956 status = InitCE(state);
1957 if (status < 0)
1958 break;
1959 status = InitEQ(state);
1960 if (status < 0)
1961 break;
1962 status = InitSC(state);
1963 if (status < 0)
1964 break;
126f1e61
RM		 1965 }
1966
1967 /* Restore current IF & RF AGC settings */
1968
58d5eaec
MCC		 1969 status = SetCfgIfAgc(state, &state->if_agc_cfg);
1970 if (status < 0)
1971 break;
1972 status = SetCfgRfAgc(state, &state->rf_agc_cfg);
1973 if (status < 0)
1974 break;
126f1e61 1975
9f97c288 1976 mirrorFreqSpect = (state->props.inversion == INVERSION_ON);
126f1e61
RM		 1977
1978 switch (p->transmission_mode) {
6cacdd46 1979 default: /* Not set, detect it automatically */
126f1e61 1980 operationMode |= SC_RA_RAM_OP_AUTO_MODE__M;
40e43111 1981 /* fall through - try first guess DRX_FFTMODE_8K */
6cacdd46 1982 case TRANSMISSION_MODE_8K:
126f1e61
RM		 1983 transmissionParams |= SC_RA_RAM_OP_PARAM_MODE_8K;
1984 if (state->type_A) {
58d5eaec
MCC		 1985 status = Write16(state, EC_SB_REG_TR_MODE__A, EC_SB_REG_TR_MODE_8K, 0x0000);
1986 if (status < 0)
1987 break;
6cacdd46 1988 qpskSnCeGain = 99;
126f1e61
RM		 1989 qam16SnCeGain = 83;
1990 qam64SnCeGain = 67;
1991 }
1992 break;
6cacdd46 1993 case TRANSMISSION_MODE_2K:
126f1e61
RM		 1994 transmissionParams |= SC_RA_RAM_OP_PARAM_MODE_2K;
1995 if (state->type_A) {
58d5eaec
MCC		 1996 status = Write16(state, EC_SB_REG_TR_MODE__A, EC_SB_REG_TR_MODE_2K, 0x0000);
1997 if (status < 0)
1998 break;
6cacdd46 1999 qpskSnCeGain = 97;
126f1e61
RM		 2000 qam16SnCeGain = 71;
2001 qam64SnCeGain = 65;
2002 }
2003 break;
2004 }
2005
6cacdd46 2006 switch (p->guard_interval) {
126f1e61
RM		 2007 case GUARD_INTERVAL_1_4:
2008 transmissionParams |= SC_RA_RAM_OP_PARAM_GUARD_4;
2009 break;
2010 case GUARD_INTERVAL_1_8:
2011 transmissionParams |= SC_RA_RAM_OP_PARAM_GUARD_8;
2012 break;
2013 case GUARD_INTERVAL_1_16:
2014 transmissionParams |= SC_RA_RAM_OP_PARAM_GUARD_16;
2015 break;
2016 case GUARD_INTERVAL_1_32:
2017 transmissionParams |= SC_RA_RAM_OP_PARAM_GUARD_32;
2018 break;
6cacdd46 2019 default: /* Not set, detect it automatically */
126f1e61
RM		 2020 operationMode |= SC_RA_RAM_OP_AUTO_GUARD__M;
2021 /* try first guess 1/4 */
2022 transmissionParams |= SC_RA_RAM_OP_PARAM_GUARD_4;
2023 break;
2024 }
2025
9f97c288 2026 switch (p->hierarchy) {
126f1e61
RM		 2027 case HIERARCHY_1:
2028 transmissionParams |= SC_RA_RAM_OP_PARAM_HIER_A1;
2029 if (state->type_A) {
58d5eaec
MCC		 2030 status = Write16(state, EQ_REG_OT_ALPHA__A, 0x0001, 0x0000);
2031 if (status < 0)
2032 break;
2033 status = Write16(state, EC_SB_REG_ALPHA__A, 0x0001, 0x0000);
2034 if (status < 0)
2035 break;
126f1e61 2036
6cacdd46 2037 qpskTdTpsPwr = EQ_TD_TPS_PWR_UNKNOWN;
126f1e61
RM		 2038 qam16TdTpsPwr = EQ_TD_TPS_PWR_QAM16_ALPHA1;
2039 qam64TdTpsPwr = EQ_TD_TPS_PWR_QAM64_ALPHA1;
2040
6cacdd46
DH		 2041 qpskIsGainMan =
2042 SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_MAN__PRE;
126f1e61 2043 qam16IsGainMan =
6cacdd46 2044 SC_RA_RAM_EQ_IS_GAIN_16QAM_MAN__PRE;
126f1e61 2045 qam64IsGainMan =
6cacdd46 2046 SC_RA_RAM_EQ_IS_GAIN_64QAM_MAN__PRE;
126f1e61 2047
6cacdd46
DH		 2048 qpskIsGainExp =
2049 SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_EXP__PRE;
126f1e61 2050 qam16IsGainExp =
6cacdd46 2051 SC_RA_RAM_EQ_IS_GAIN_16QAM_EXP__PRE;
126f1e61 2052 qam64IsGainExp =
6cacdd46 2053 SC_RA_RAM_EQ_IS_GAIN_64QAM_EXP__PRE;
126f1e61
RM		 2054 }
2055 break;
2056
2057 case HIERARCHY_2:
2058 transmissionParams |= SC_RA_RAM_OP_PARAM_HIER_A2;
2059 if (state->type_A) {
58d5eaec
MCC		 2060 status = Write16(state, EQ_REG_OT_ALPHA__A, 0x0002, 0x0000);
2061 if (status < 0)
2062 break;
2063 status = Write16(state, EC_SB_REG_ALPHA__A, 0x0002, 0x0000);
2064 if (status < 0)
2065 break;
126f1e61 2066
6cacdd46 2067 qpskTdTpsPwr = EQ_TD_TPS_PWR_UNKNOWN;
126f1e61
RM		 2068 qam16TdTpsPwr = EQ_TD_TPS_PWR_QAM16_ALPHA2;
2069 qam64TdTpsPwr = EQ_TD_TPS_PWR_QAM64_ALPHA2;
2070
2071 qpskIsGainMan =
6cacdd46 2072 SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_MAN__PRE;
126f1e61 2073 qam16IsGainMan =
6cacdd46 2074 SC_RA_RAM_EQ_IS_GAIN_16QAM_A2_MAN__PRE;
126f1e61 2075 qam64IsGainMan =
6cacdd46 2076 SC_RA_RAM_EQ_IS_GAIN_64QAM_A2_MAN__PRE;
126f1e61 2077
6cacdd46
DH		 2078 qpskIsGainExp =
2079 SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_EXP__PRE;
126f1e61 2080 qam16IsGainExp =
6cacdd46 2081 SC_RA_RAM_EQ_IS_GAIN_16QAM_A2_EXP__PRE;
126f1e61 2082 qam64IsGainExp =
6cacdd46 2083 SC_RA_RAM_EQ_IS_GAIN_64QAM_A2_EXP__PRE;
126f1e61
RM		 2084 }
2085 break;
2086 case HIERARCHY_4:
2087 transmissionParams |= SC_RA_RAM_OP_PARAM_HIER_A4;
2088 if (state->type_A) {
58d5eaec
MCC		 2089 status = Write16(state, EQ_REG_OT_ALPHA__A, 0x0003, 0x0000);
2090 if (status < 0)
2091 break;
2092 status = Write16(state, EC_SB_REG_ALPHA__A, 0x0003, 0x0000);
2093 if (status < 0)
2094 break;
126f1e61 2095
6cacdd46 2096 qpskTdTpsPwr = EQ_TD_TPS_PWR_UNKNOWN;
126f1e61
RM		 2097 qam16TdTpsPwr = EQ_TD_TPS_PWR_QAM16_ALPHA4;
2098 qam64TdTpsPwr = EQ_TD_TPS_PWR_QAM64_ALPHA4;
2099
6cacdd46
DH		 2100 qpskIsGainMan =
2101 SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_MAN__PRE;
126f1e61 2102 qam16IsGainMan =
6cacdd46 2103 SC_RA_RAM_EQ_IS_GAIN_16QAM_A4_MAN__PRE;
126f1e61 2104 qam64IsGainMan =
6cacdd46 2105 SC_RA_RAM_EQ_IS_GAIN_64QAM_A4_MAN__PRE;
126f1e61 2106
6cacdd46
DH		 2107 qpskIsGainExp =
2108 SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_EXP__PRE;
126f1e61 2109 qam16IsGainExp =
6cacdd46 2110 SC_RA_RAM_EQ_IS_GAIN_16QAM_A4_EXP__PRE;
126f1e61 2111 qam64IsGainExp =
6cacdd46 2112 SC_RA_RAM_EQ_IS_GAIN_64QAM_A4_EXP__PRE;
126f1e61
RM		 2113 }
2114 break;
2115 case HIERARCHY_AUTO:
2116 default:
2117 /* Not set, detect it automatically, start with none */
2118 operationMode |= SC_RA_RAM_OP_AUTO_HIER__M;
2119 transmissionParams |= SC_RA_RAM_OP_PARAM_HIER_NO;
2120 if (state->type_A) {
58d5eaec
MCC		 2121 status = Write16(state, EQ_REG_OT_ALPHA__A, 0x0000, 0x0000);
2122 if (status < 0)
2123 break;
2124 status = Write16(state, EC_SB_REG_ALPHA__A, 0x0000, 0x0000);
2125 if (status < 0)
2126 break;
126f1e61 2127
6cacdd46 2128 qpskTdTpsPwr = EQ_TD_TPS_PWR_QPSK;
126f1e61
RM		 2129 qam16TdTpsPwr = EQ_TD_TPS_PWR_QAM16_ALPHAN;
2130 qam64TdTpsPwr = EQ_TD_TPS_PWR_QAM64_ALPHAN;
2131
6cacdd46
DH		 2132 qpskIsGainMan =
2133 SC_RA_RAM_EQ_IS_GAIN_QPSK_MAN__PRE;
126f1e61 2134 qam16IsGainMan =
6cacdd46 2135 SC_RA_RAM_EQ_IS_GAIN_16QAM_MAN__PRE;
126f1e61 2136 qam64IsGainMan =
6cacdd46 2137 SC_RA_RAM_EQ_IS_GAIN_64QAM_MAN__PRE;
126f1e61 2138
6cacdd46
DH		 2139 qpskIsGainExp =
2140 SC_RA_RAM_EQ_IS_GAIN_QPSK_EXP__PRE;
126f1e61 2141 qam16IsGainExp =
6cacdd46 2142 SC_RA_RAM_EQ_IS_GAIN_16QAM_EXP__PRE;
126f1e61 2143 qam64IsGainExp =
6cacdd46 2144 SC_RA_RAM_EQ_IS_GAIN_64QAM_EXP__PRE;
126f1e61
RM		 2145 }
2146 break;
2147 }
58d5eaec
MCC		 2148 if (status < 0)
2149 break;
126f1e61 2150
9f97c288 2151 switch (p->modulation) {
126f1e61
RM		 2152 default:
2153 operationMode |= SC_RA_RAM_OP_AUTO_CONST__M;
40e43111 2154 /* fall through - try first guess DRX_CONSTELLATION_QAM64 */
126f1e61
RM		 2155 case QAM_64:
2156 transmissionParams |= SC_RA_RAM_OP_PARAM_CONST_QAM64;
2157 if (state->type_A) {
58d5eaec
MCC		 2158 status = Write16(state, EQ_REG_OT_CONST__A, 0x0002, 0x0000);
2159 if (status < 0)
2160 break;
2161 status = Write16(state, EC_SB_REG_CONST__A, EC_SB_REG_CONST_64QAM, 0x0000);
2162 if (status < 0)
2163 break;
2164 status = Write16(state, EC_SB_REG_SCALE_MSB__A, 0x0020, 0x0000);
2165 if (status < 0)
2166 break;
2167 status = Write16(state, EC_SB_REG_SCALE_BIT2__A, 0x0008, 0x0000);
2168 if (status < 0)
2169 break;
2170 status = Write16(state, EC_SB_REG_SCALE_LSB__A, 0x0002, 0x0000);
2171 if (status < 0)
2172 break;
2173
2174 status = Write16(state, EQ_REG_TD_TPS_PWR_OFS__A, qam64TdTpsPwr, 0x0000);
2175 if (status < 0)
2176 break;
2177 status = Write16(state, EQ_REG_SN_CEGAIN__A, qam64SnCeGain, 0x0000);
2178 if (status < 0)
2179 break;
2180 status = Write16(state, EQ_REG_IS_GAIN_MAN__A, qam64IsGainMan, 0x0000);
2181 if (status < 0)
2182 break;
2183 status = Write16(state, EQ_REG_IS_GAIN_EXP__A, qam64IsGainExp, 0x0000);
2184 if (status < 0)
2185 break;
126f1e61
RM		 2186 }
2187 break;
6cacdd46 2188 case QPSK:
126f1e61
RM		 2189 transmissionParams |= SC_RA_RAM_OP_PARAM_CONST_QPSK;
2190 if (state->type_A) {
58d5eaec
MCC		 2191 status = Write16(state, EQ_REG_OT_CONST__A, 0x0000, 0x0000);
2192 if (status < 0)
2193 break;
2194 status = Write16(state, EC_SB_REG_CONST__A, EC_SB_REG_CONST_QPSK, 0x0000);
2195 if (status < 0)
2196 break;
2197 status = Write16(state, EC_SB_REG_SCALE_MSB__A, 0x0010, 0x0000);
2198 if (status < 0)
2199 break;
2200 status = Write16(state, EC_SB_REG_SCALE_BIT2__A, 0x0000, 0x0000);
2201 if (status < 0)
2202 break;
2203 status = Write16(state, EC_SB_REG_SCALE_LSB__A, 0x0000, 0x0000);
2204 if (status < 0)
2205 break;
2206
2207 status = Write16(state, EQ_REG_TD_TPS_PWR_OFS__A, qpskTdTpsPwr, 0x0000);
2208 if (status < 0)
2209 break;
2210 status = Write16(state, EQ_REG_SN_CEGAIN__A, qpskSnCeGain, 0x0000);
2211 if (status < 0)
2212 break;
2213 status = Write16(state, EQ_REG_IS_GAIN_MAN__A, qpskIsGainMan, 0x0000);
2214 if (status < 0)
2215 break;
2216 status = Write16(state, EQ_REG_IS_GAIN_EXP__A, qpskIsGainExp, 0x0000);
2217 if (status < 0)
2218 break;
126f1e61
RM		 2219 }
2220 break;
2221
2222 case QAM_16:
2223 transmissionParams |= SC_RA_RAM_OP_PARAM_CONST_QAM16;
2224 if (state->type_A) {
58d5eaec
MCC		 2225 status = Write16(state, EQ_REG_OT_CONST__A, 0x0001, 0x0000);
2226 if (status < 0)
2227 break;
2228 status = Write16(state, EC_SB_REG_CONST__A, EC_SB_REG_CONST_16QAM, 0x0000);
2229 if (status < 0)
2230 break;
2231 status = Write16(state, EC_SB_REG_SCALE_MSB__A, 0x0010, 0x0000);
2232 if (status < 0)
2233 break;
2234 status = Write16(state, EC_SB_REG_SCALE_BIT2__A, 0x0004, 0x0000);
2235 if (status < 0)
2236 break;
2237 status = Write16(state, EC_SB_REG_SCALE_LSB__A, 0x0000, 0x0000);
2238 if (status < 0)
2239 break;
2240
2241 status = Write16(state, EQ_REG_TD_TPS_PWR_OFS__A, qam16TdTpsPwr, 0x0000);
2242 if (status < 0)
2243 break;
2244 status = Write16(state, EQ_REG_SN_CEGAIN__A, qam16SnCeGain, 0x0000);
2245 if (status < 0)
2246 break;
2247 status = Write16(state, EQ_REG_IS_GAIN_MAN__A, qam16IsGainMan, 0x0000);
2248 if (status < 0)
2249 break;
2250 status = Write16(state, EQ_REG_IS_GAIN_EXP__A, qam16IsGainExp, 0x0000);
2251 if (status < 0)
2252 break;
126f1e61
RM		 2253 }
2254 break;
2255
2256 }
58d5eaec
MCC		 2257 if (status < 0)
2258 break;
126f1e61
RM		 2259
2260 switch (DRX_CHANNEL_HIGH) {
2261 default:
2262 case DRX_CHANNEL_AUTO:
2263 case DRX_CHANNEL_LOW:
2264 transmissionParams |= SC_RA_RAM_OP_PARAM_PRIO_LO;
58d5eaec 2265 status = Write16(state, EC_SB_REG_PRIOR__A, EC_SB_REG_PRIOR_LO, 0x0000);
126f1e61
RM		 2266 break;
2267 case DRX_CHANNEL_HIGH:
2268 transmissionParams |= SC_RA_RAM_OP_PARAM_PRIO_HI;
58d5eaec 2269 status = Write16(state, EC_SB_REG_PRIOR__A, EC_SB_REG_PRIOR_HI, 0x0000);
126f1e61 2270 break;
126f1e61
RM		 2271 }
2272
6cacdd46 2273 switch (p->code_rate_HP) {
126f1e61
RM		 2274 case FEC_1_2:
2275 transmissionParams |= SC_RA_RAM_OP_PARAM_RATE_1_2;
0646d347 2276 if (state->type_A)
58d5eaec 2277 status = Write16(state, EC_VD_REG_SET_CODERATE__A, EC_VD_REG_SET_CODERATE_C1_2, 0x0000);
126f1e61
RM		 2278 break;
2279 default:
2280 operationMode |= SC_RA_RAM_OP_AUTO_RATE__M;
06eeefe8 2281 /* fall through */
6cacdd46 2282 case FEC_2_3:
126f1e61 2283 transmissionParams |= SC_RA_RAM_OP_PARAM_RATE_2_3;
0646d347 2284 if (state->type_A)
58d5eaec 2285 status = Write16(state, EC_VD_REG_SET_CODERATE__A, EC_VD_REG_SET_CODERATE_C2_3, 0x0000);
126f1e61 2286 break;
6cacdd46 2287 case FEC_3_4:
126f1e61 2288 transmissionParams |= SC_RA_RAM_OP_PARAM_RATE_3_4;
0646d347 2289 if (state->type_A)
58d5eaec 2290 status = Write16(state, EC_VD_REG_SET_CODERATE__A, EC_VD_REG_SET_CODERATE_C3_4, 0x0000);
126f1e61 2291 break;
6cacdd46 2292 case FEC_5_6:
126f1e61 2293 transmissionParams |= SC_RA_RAM_OP_PARAM_RATE_5_6;
0646d347 2294 if (state->type_A)
58d5eaec 2295 status = Write16(state, EC_VD_REG_SET_CODERATE__A, EC_VD_REG_SET_CODERATE_C5_6, 0x0000);
126f1e61 2296 break;
6cacdd46 2297 case FEC_7_8:
126f1e61 2298 transmissionParams |= SC_RA_RAM_OP_PARAM_RATE_7_8;
0646d347 2299 if (state->type_A)
58d5eaec 2300 status = Write16(state, EC_VD_REG_SET_CODERATE__A, EC_VD_REG_SET_CODERATE_C7_8, 0x0000);
126f1e61
RM		 2301 break;
2302 }
58d5eaec
MCC		 2303 if (status < 0)
2304 break;
126f1e61
RM		 2305
2306 /* First determine real bandwidth (Hz) */
2307 /* Also set delay for impulse noise cruncher (only A2) */
2308 /* Also set parameters for EC_OC fix, note
2309 EC_OC_REG_TMD_HIL_MAR is changed
2310 by SC for fix for some 8K,1/8 guard but is restored by
2311 InitEC and ResetEC
2312 functions */
9f97c288
MCC		 2313 switch (p->bandwidth_hz) {
2314 case 0:
2315 p->bandwidth_hz = 8000000;
2316 /* fall through */
2317 case 8000000:
126f1e61
RM		 2318 /* (64/7)*(8/8)*1000000 */
2319 bandwidth = DRXD_BANDWIDTH_8MHZ_IN_HZ;
2320
2321 bandwidthParam = 0;
2322 status = Write16(state,
6cacdd46 2323 FE_AG_REG_IND_DEL__A, 50, 0x0000);
126f1e61 2324 break;
9f97c288 2325 case 7000000:
126f1e61
RM		 2326 /* (64/7)*(7/8)*1000000 */
2327 bandwidth = DRXD_BANDWIDTH_7MHZ_IN_HZ;
6cacdd46 2328 bandwidthParam = 0x4807; /*binary:0100 1000 0000 0111 */
126f1e61 2329 status = Write16(state,
6cacdd46 2330 FE_AG_REG_IND_DEL__A, 59, 0x0000);
126f1e61 2331 break;
9f97c288 2332 case 6000000:
126f1e61
RM		 2333 /* (64/7)*(6/8)*1000000 */
2334 bandwidth = DRXD_BANDWIDTH_6MHZ_IN_HZ;
6cacdd46 2335 bandwidthParam = 0x0F07; /*binary: 0000 1111 0000 0111 */
126f1e61 2336 status = Write16(state,
6cacdd46 2337 FE_AG_REG_IND_DEL__A, 71, 0x0000);
126f1e61 2338 break;
63952e8c
AO		 2339 default:
2340 status = -EINVAL;
126f1e61 2341 }
58d5eaec
MCC		 2342 if (status < 0)
2343 break;
126f1e61 2344
58d5eaec
MCC		 2345 status = Write16(state, SC_RA_RAM_BAND__A, bandwidthParam, 0x0000);
2346 if (status < 0)
2347 break;
126f1e61
RM		 2348
2349 {
2350 u16 sc_config;
58d5eaec
MCC		 2351 status = Read16(state, SC_RA_RAM_CONFIG__A, &sc_config, 0);
2352 if (status < 0)
2353 break;
126f1e61
RM		 2354
2355 /* enable SLAVE mode in 2k 1/32 to
2356 prevent timing change glitches */
6cacdd46
DH		 2357 if ((p->transmission_mode == TRANSMISSION_MODE_2K) &&
2358 (p->guard_interval == GUARD_INTERVAL_1_32)) {
126f1e61
RM		 2359 /* enable slave */
2360 sc_config |= SC_RA_RAM_CONFIG_SLAVE__M;
2361 } else {
2362 /* disable slave */
2363 sc_config &= ~SC_RA_RAM_CONFIG_SLAVE__M;
2364 }
58d5eaec
MCC		 2365 status = Write16(state, SC_RA_RAM_CONFIG__A, sc_config, 0);
2366 if (status < 0)
2367 break;
126f1e61
RM		 2368 }
2369
58d5eaec
MCC		 2370 status = SetCfgNoiseCalibration(state, &state->noise_cal);
2371 if (status < 0)
2372 break;
126f1e61 2373
6cacdd46 2374 if (state->cscd_state == CSCD_INIT) {
126f1e61 2375 /* switch on SRMM scan in SC */
58d5eaec
MCC		 2376 status = Write16(state, SC_RA_RAM_SAMPLE_RATE_COUNT__A, DRXD_OSCDEV_DO_SCAN, 0x0000);
2377 if (status < 0)
2378 break;
2379/* CHK_ERROR(Write16(SC_RA_RAM_SAMPLE_RATE_STEP__A, DRXD_OSCDEV_STEP, 0x0000));*/
126f1e61
RM		 2380 state->cscd_state = CSCD_SET;
2381 }
2382
126f1e61
RM		 2383 /* Now compute FE_IF_REG_INCR */
2384 /*((( SysFreq/BandWidth)/2)/2) -1) * 2^23) =>
6cacdd46
DH		 2385 ((SysFreq / BandWidth) * (2^21) ) - (2^23) */
2386 feIfIncr = MulDiv32(state->sys_clock_freq * 1000,
2387 (1ULL << 21), bandwidth) - (1 << 23);
58d5eaec
MCC		 2388 status = Write16(state, FE_IF_REG_INCR0__A, (u16) (feIfIncr & FE_IF_REG_INCR0__M), 0x0000);
2389 if (status < 0)
2390 break;
2391 status = Write16(state, FE_IF_REG_INCR1__A, (u16) ((feIfIncr >> FE_IF_REG_INCR0__W) & FE_IF_REG_INCR1__M), 0x0000);
2392 if (status < 0)
2393 break;
126f1e61
RM		 2394 /* Bandwidth setting done */
2395
2396 /* Mirror & frequency offset */
2397 SetFrequencyShift(state, off, mirrorFreqSpect);
2398
2399 /* Start SC, write channel settings to SC */
2400
2401 /* Enable SC after setting all other parameters */
58d5eaec
MCC		 2402 status = Write16(state, SC_COMM_STATE__A, 0, 0x0000);
2403 if (status < 0)
2404 break;
2405 status = Write16(state, SC_COMM_EXEC__A, 1, 0x0000);
2406 if (status < 0)
2407 break;
126f1e61
RM		 2408
2409 /* Write SC parameter registers, operation mode */
2410#if 1
6cacdd46
DH		 2411 operationMode = (SC_RA_RAM_OP_AUTO_MODE__M |
2412 SC_RA_RAM_OP_AUTO_GUARD__M |
2413 SC_RA_RAM_OP_AUTO_CONST__M |
2414 SC_RA_RAM_OP_AUTO_HIER__M |
2415 SC_RA_RAM_OP_AUTO_RATE__M);
126f1e61 2416#endif
58d5eaec
MCC		 2417 status = SC_SetPrefParamCommand(state, 0x0000, transmissionParams, operationMode);
2418 if (status < 0)
2419 break;
126f1e61
RM		 2420
2421 /* Start correct processes to get in lock */
58d5eaec
MCC		 2422 status = SC_ProcStartCommand(state, SC_RA_RAM_PROC_LOCKTRACK, SC_RA_RAM_SW_EVENT_RUN_NMASK__M, SC_RA_RAM_LOCKTRACK_MIN);
2423 if (status < 0)
2424 break;
126f1e61 2425
58d5eaec
MCC		 2426 status = StartOC(state);
2427 if (status < 0)
2428 break;
126f1e61 2429
6cacdd46 2430 if (state->operation_mode != OM_Default) {
58d5eaec
MCC		 2431 status = StartDiversity(state);
2432 if (status < 0)
2433 break;
126f1e61
RM		 2434 }
2435
2436 state->drxd_state = DRXD_STARTED;
6cacdd46 2437 } while (0);
126f1e61
RM		 2438
2439 return status;
2440}
2441
2442static int CDRXD(struct drxd_state *state, u32 IntermediateFrequency)
2443{
2444 u32 ulRfAgcOutputLevel = 0xffffffff;
6cacdd46
DH		 2445 u32 ulRfAgcSettleLevel = 528; /* Optimum value for MT2060 */
2446 u32 ulRfAgcMinLevel = 0; /* Currently unused */
2447 u32 ulRfAgcMaxLevel = DRXD_FE_CTRL_MAX; /* Currently unused */
2448 u32 ulRfAgcSpeed = 0; /* Currently unused */
2449 u32 ulRfAgcMode = 0; /*2; Off */
2450 u32 ulRfAgcR1 = 820;
126f1e61 2451 u32 ulRfAgcR2 = 2200;
6cacdd46
DH		 2452 u32 ulRfAgcR3 = 150;
2453 u32 ulIfAgcMode = 0; /* Auto */
126f1e61
RM		 2454 u32 ulIfAgcOutputLevel = 0xffffffff;
2455 u32 ulIfAgcSettleLevel = 0xffffffff;
2456 u32 ulIfAgcMinLevel = 0xffffffff;
2457 u32 ulIfAgcMaxLevel = 0xffffffff;
2458 u32 ulIfAgcSpeed = 0xffffffff;
6cacdd46 2459 u32 ulIfAgcR1 = 820;
126f1e61 2460 u32 ulIfAgcR2 = 2200;
6cacdd46 2461 u32 ulIfAgcR3 = 150;
126f1e61
RM		 2462 u32 ulClock = state->config.clock;
2463 u32 ulSerialMode = 0;
6cacdd46 2464 u32 ulEcOcRegOcModeLop = 4; /* Dynamic DTO source */
126f1e61
RM		 2465 u32 ulHiI2cDelay = HI_I2C_DELAY;
2466 u32 ulHiI2cBridgeDelay = HI_I2C_BRIDGE_DELAY;
2467 u32 ulHiI2cPatch = 0;
6cacdd46 2468 u32 ulEnvironment = APPENV_PORTABLE;
126f1e61
RM		 2469 u32 ulEnvironmentDiversity = APPENV_MOBILE;
2470 u32 ulIFFilter = IFFILTER_SAW;
2471
6cacdd46 2472 state->if_agc_cfg.ctrlMode = AGC_CTRL_AUTO;
126f1e61
RM		 2473 state->if_agc_cfg.outputLevel = 0;
2474 state->if_agc_cfg.settleLevel = 140;
2475 state->if_agc_cfg.minOutputLevel = 0;
2476 state->if_agc_cfg.maxOutputLevel = 1023;
2477 state->if_agc_cfg.speed = 904;
2478
6cacdd46
DH		 2479 if (ulIfAgcMode == 1 && ulIfAgcOutputLevel <= DRXD_FE_CTRL_MAX) {
2480 state->if_agc_cfg.ctrlMode = AGC_CTRL_USER;
2481 state->if_agc_cfg.outputLevel = (u16) (ulIfAgcOutputLevel);
126f1e61
RM		 2482 }
2483
6cacdd46 2484 if (ulIfAgcMode == 0 &&
126f1e61
RM		 2485 ulIfAgcSettleLevel <= DRXD_FE_CTRL_MAX &&
2486 ulIfAgcMinLevel <= DRXD_FE_CTRL_MAX &&
2487 ulIfAgcMaxLevel <= DRXD_FE_CTRL_MAX &&
6cacdd46
DH		 2488 ulIfAgcSpeed <= DRXD_FE_CTRL_MAX) {
2489 state->if_agc_cfg.ctrlMode = AGC_CTRL_AUTO;
2490 state->if_agc_cfg.settleLevel = (u16) (ulIfAgcSettleLevel);
2491 state->if_agc_cfg.minOutputLevel = (u16) (ulIfAgcMinLevel);
2492 state->if_agc_cfg.maxOutputLevel = (u16) (ulIfAgcMaxLevel);
2493 state->if_agc_cfg.speed = (u16) (ulIfAgcSpeed);
126f1e61
RM		 2494 }
2495
6cacdd46
DH		 2496 state->if_agc_cfg.R1 = (u16) (ulIfAgcR1);
2497 state->if_agc_cfg.R2 = (u16) (ulIfAgcR2);
2498 state->if_agc_cfg.R3 = (u16) (ulIfAgcR3);
126f1e61 2499
6cacdd46
DH		 2500 state->rf_agc_cfg.R1 = (u16) (ulRfAgcR1);
2501 state->rf_agc_cfg.R2 = (u16) (ulRfAgcR2);
2502 state->rf_agc_cfg.R3 = (u16) (ulRfAgcR3);
126f1e61 2503
6cacdd46 2504 state->rf_agc_cfg.ctrlMode = AGC_CTRL_AUTO;
126f1e61 2505 /* rest of the RFAgcCfg structure currently unused */
6cacdd46
DH		 2506 if (ulRfAgcMode == 1 && ulRfAgcOutputLevel <= DRXD_FE_CTRL_MAX) {
2507 state->rf_agc_cfg.ctrlMode = AGC_CTRL_USER;
2508 state->rf_agc_cfg.outputLevel = (u16) (ulRfAgcOutputLevel);
126f1e61
RM		 2509 }
2510
6cacdd46 2511 if (ulRfAgcMode == 0 &&
126f1e61
RM		 2512 ulRfAgcSettleLevel <= DRXD_FE_CTRL_MAX &&
2513 ulRfAgcMinLevel <= DRXD_FE_CTRL_MAX &&
2514 ulRfAgcMaxLevel <= DRXD_FE_CTRL_MAX &&
6cacdd46
DH		 2515 ulRfAgcSpeed <= DRXD_FE_CTRL_MAX) {
2516 state->rf_agc_cfg.ctrlMode = AGC_CTRL_AUTO;
2517 state->rf_agc_cfg.settleLevel = (u16) (ulRfAgcSettleLevel);
2518 state->rf_agc_cfg.minOutputLevel = (u16) (ulRfAgcMinLevel);
2519 state->rf_agc_cfg.maxOutputLevel = (u16) (ulRfAgcMaxLevel);
2520 state->rf_agc_cfg.speed = (u16) (ulRfAgcSpeed);
126f1e61
RM		 2521 }
2522
9999daf4 2523 if (ulRfAgcMode == 2)
6cacdd46 2524 state->rf_agc_cfg.ctrlMode = AGC_CTRL_OFF;
126f1e61
RM		 2525
2526 if (ulEnvironment <= 2)
6cacdd46
DH		 2527 state->app_env_default = (enum app_env)
2528 (ulEnvironment);
126f1e61
RM		 2529 if (ulEnvironmentDiversity <= 2)
2530 state->app_env_diversity = (enum app_env)
6cacdd46 2531 (ulEnvironmentDiversity);
126f1e61 2532
6cacdd46 2533 if (ulIFFilter == IFFILTER_DISCRETE) {
126f1e61 2534 /* discrete filter */
6cacdd46
DH		 2535 state->noise_cal.cpOpt = 0;
2536 state->noise_cal.cpNexpOfs = 40;
2537 state->noise_cal.tdCal2k = -40;
2538 state->noise_cal.tdCal8k = -24;
126f1e61
RM		 2539 } else {
2540 /* SAW filter */
6cacdd46
DH		 2541 state->noise_cal.cpOpt = 1;
2542 state->noise_cal.cpNexpOfs = 0;
2543 state->noise_cal.tdCal2k = -21;
2544 state->noise_cal.tdCal8k = -24;
126f1e61 2545 }
6cacdd46
DH		 2546 state->m_EcOcRegOcModeLop = (u16) (ulEcOcRegOcModeLop);
2547
2548 state->chip_adr = (state->config.demod_address << 1) | 1;
2549 switch (ulHiI2cPatch) {
2550 case 1:
2551 state->m_HiI2cPatch = DRXD_HiI2cPatch_1;
2552 break;
2553 case 3:
2554 state->m_HiI2cPatch = DRXD_HiI2cPatch_3;
2555 break;
126f1e61
RM		 2556 default:
2557 state->m_HiI2cPatch = NULL;
2558 }
2559
2560 /* modify tuner and clock attributes */
6cacdd46 2561 state->intermediate_freq = (u16) (IntermediateFrequency / 1000);
126f1e61
RM		 2562 /* expected system clock frequency in kHz */
2563 state->expected_sys_clock_freq = 48000;
2564 /* real system clock frequency in kHz */
2565 state->sys_clock_freq = 48000;
6cacdd46 2566 state->osc_clock_freq = (u16) ulClock;
126f1e61
RM		 2567 state->osc_clock_deviation = 0;
2568 state->cscd_state = CSCD_INIT;
2569 state->drxd_state = DRXD_UNINITIALIZED;
2570
6cacdd46
DH		 2571 state->PGA = 0;
2572 state->type_A = 0;
2573 state->tuner_mirrors = 0;
126f1e61
RM		 2574
2575 /* modify MPEG output attributes */
ba967965 2576 state->insert_rs_byte = state->config.insert_rs_byte;
126f1e61
RM		 2577 state->enable_parallel = (ulSerialMode != 1);
2578
2579 /* Timing div, 250ns/Psys */
2580 /* Timing div, = ( delay (nano seconds) * sysclk (kHz) )/ 1000 */
2581
6cacdd46
DH		 2582 state->hi_cfg_timing_div = (u16) ((state->sys_clock_freq / 1000) *
2583 ulHiI2cDelay) / 1000;
126f1e61
RM		 2584 /* Bridge delay, uses oscilator clock */
2585 /* Delay = ( delay (nano seconds) * oscclk (kHz) )/ 1000 */
6cacdd46
DH		 2586 state->hi_cfg_bridge_delay = (u16) ((state->osc_clock_freq / 1000) *
2587 ulHiI2cBridgeDelay) / 1000;
126f1e61
RM		 2588
2589 state->m_FeAgRegAgPwd = DRXD_DEF_AG_PWD_CONSUMER;
2590 /* state->m_FeAgRegAgPwd = DRXD_DEF_AG_PWD_PRO; */
2591 state->m_FeAgRegAgAgcSio = DRXD_DEF_AG_AGC_SIO;
2592 return 0;
2593}
2594
8b35c2fe 2595static int DRXD_init(struct drxd_state *state, const u8 *fw, u32 fw_size)
126f1e61 2596{
6cacdd46 2597 int status = 0;
126f1e61
RM		 2598 u32 driverVersion;
2599
2600 if (state->init_done)
2601 return 0;
2602
2603 CDRXD(state, state->config.IF ? state->config.IF : 36000000);
2604
2605 do {
2606 state->operation_mode = OM_Default;
2607
58d5eaec
MCC		 2608 status = SetDeviceTypeId(state);
2609 if (status < 0)
2610 break;
126f1e61
RM		 2611
2612 /* Apply I2c address patch to B1 */
af28c996 2613 if (!state->type_A && state->m_HiI2cPatch) {
58d5eaec
MCC		 2614 status = WriteTable(state, state->m_HiI2cPatch);
2615 if (status < 0)
2616 break;
cea13002 2617 }
126f1e61
RM		 2618
2619 if (state->type_A) {
2620 /* HI firmware patch for UIO readout,
2621 avoid clearing of result register */
58d5eaec
MCC		 2622 status = Write16(state, 0x43012D, 0x047f, 0);
2623 if (status < 0)
2624 break;
126f1e61
RM		 2625 }
2626
58d5eaec
MCC		 2627 status = HI_ResetCommand(state);
2628 if (status < 0)
2629 break;
126f1e61 2630
58d5eaec
MCC		 2631 status = StopAllProcessors(state);
2632 if (status < 0)
2633 break;
2634 status = InitCC(state);
2635 if (status < 0)
2636 break;
126f1e61
RM		 2637
2638 state->osc_clock_deviation = 0;
2639
2640 if (state->config.osc_deviation)
2641 state->osc_clock_deviation =
6cacdd46 2642 state->config.osc_deviation(state->priv, 0, 0);
126f1e61
RM		 2643 {
2644 /* Handle clock deviation */
2645 s32 devB;
6cacdd46
DH		 2646 s32 devA = (s32) (state->osc_clock_deviation) *
2647 (s32) (state->expected_sys_clock_freq);
126f1e61 2648 /* deviation in kHz */
6cacdd46 2649 s32 deviation = (devA / (1000000L));
126f1e61 2650 /* rounding, signed */
6cacdd46
DH		 2651 if (devA > 0)
2652 devB = (2);
126f1e61 2653 else
6cacdd46
DH		 2654 devB = (-2);
2655 if ((devB * (devA % 1000000L) > 1000000L)) {
126f1e61 2656 /* add +1 or -1 */
6cacdd46 2657 deviation += (devB / 2);
126f1e61
RM		 2658 }
2659
6cacdd46
DH		 2660 state->sys_clock_freq =
2661 (u16) ((state->expected_sys_clock_freq) +
2662 deviation);
126f1e61 2663 }
58d5eaec
MCC		 2664 status = InitHI(state);
2665 if (status < 0)
2666 break;
2667 status = InitAtomicRead(state);
2668 if (status < 0)
2669 break;
126f1e61 2670
58d5eaec
MCC		 2671 status = EnableAndResetMB(state);
2672 if (status < 0)
2673 break;
73b8922f 2674 if (state->type_A) {
58d5eaec
MCC		 2675 status = ResetCEFR(state);
2676 if (status < 0)
2677 break;
73b8922f 2678 }
126f1e61 2679 if (fw) {
58d5eaec
MCC		 2680 status = DownloadMicrocode(state, fw, fw_size);
2681 if (status < 0)
2682 break;
126f1e61 2683 } else {
58d5eaec
MCC		 2684 status = DownloadMicrocode(state, state->microcode, state->microcode_length);
2685 if (status < 0)
2686 break;
126f1e61
RM		 2687 }
2688
2689 if (state->PGA) {
2690 state->m_FeAgRegAgPwd = DRXD_DEF_AG_PWD_PRO;
6cacdd46 2691 SetCfgPga(state, 0); /* PGA = 0 dB */
126f1e61
RM		 2692 } else {
2693 state->m_FeAgRegAgPwd = DRXD_DEF_AG_PWD_CONSUMER;
2694 }
2695
2696 state->m_FeAgRegAgAgcSio = DRXD_DEF_AG_AGC_SIO;
2697
58d5eaec
MCC		 2698 status = InitFE(state);
2699 if (status < 0)
2700 break;
2701 status = InitFT(state);
2702 if (status < 0)
2703 break;
2704 status = InitCP(state);
2705 if (status < 0)
2706 break;
2707 status = InitCE(state);
2708 if (status < 0)
2709 break;
2710 status = InitEQ(state);
2711 if (status < 0)
2712 break;
2713 status = InitEC(state);
2714 if (status < 0)
2715 break;
2716 status = InitSC(state);
2717 if (status < 0)
2718 break;
126f1e61 2719
58d5eaec
MCC		 2720 status = SetCfgIfAgc(state, &state->if_agc_cfg);
2721 if (status < 0)
2722 break;
2723 status = SetCfgRfAgc(state, &state->rf_agc_cfg);
2724 if (status < 0)
2725 break;
126f1e61
RM		 2726
2727 state->cscd_state = CSCD_INIT;
58d5eaec
MCC		 2728 status = Write16(state, SC_COMM_EXEC__A, SC_COMM_EXEC_CTL_STOP, 0);
2729 if (status < 0)
2730 break;
2731 status = Write16(state, LC_COMM_EXEC__A, SC_COMM_EXEC_CTL_STOP, 0);
2732 if (status < 0)
2733 break;
126f1e61 2734
6cacdd46
DH		 2735 driverVersion = (((VERSION_MAJOR / 10) << 4) +
2736 (VERSION_MAJOR % 10)) << 24;
2737 driverVersion += (((VERSION_MINOR / 10) << 4) +
2738 (VERSION_MINOR % 10)) << 16;
2739 driverVersion += ((VERSION_PATCH / 1000) << 12) +
2740 ((VERSION_PATCH / 100) << 8) +
2741 ((VERSION_PATCH / 10) << 4) + (VERSION_PATCH % 10);
126f1e61 2742
58d5eaec
MCC		 2743 status = Write32(state, SC_RA_RAM_DRIVER_VERSION__AX, driverVersion, 0);
2744 if (status < 0)
2745 break;
126f1e61 2746
58d5eaec
MCC		 2747 status = StopOC(state);
2748 if (status < 0)
2749 break;
126f1e61
RM		 2750
2751 state->drxd_state = DRXD_STOPPED;
6cacdd46
DH		 2752 state->init_done = 1;
2753 status = 0;
126f1e61
RM		 2754 } while (0);
2755 return status;
2756}
2757
8b35c2fe 2758static int DRXD_status(struct drxd_state *state, u32 *pLockStatus)
126f1e61
RM		 2759{
2760 DRX_GetLockStatus(state, pLockStatus);
2761
6cacdd46
DH		 2762 /*if (*pLockStatus&DRX_LOCK_MPEG) */
2763 if (*pLockStatus & DRX_LOCK_FEC) {
126f1e61
RM		 2764 ConfigureMPEGOutput(state, 1);
2765 /* Get status again, in case we have MPEG lock now */
6cacdd46 2766 /*DRX_GetLockStatus(state, pLockStatus); */
126f1e61
RM		 2767 }
2768
2769 return 0;
2770}
2771
2772/****************************************************************************/
2773/****************************************************************************/
2774/****************************************************************************/
2775
6cacdd46 2776static int drxd_read_signal_strength(struct dvb_frontend *fe, u16 * strength)
126f1e61
RM		 2777{
2778 struct drxd_state *state = fe->demodulator_priv;
2779 u32 value;
2780 int res;
2781
6cacdd46
DH		 2782 res = ReadIFAgc(state, &value);
2783 if (res < 0)
2784 *strength = 0;
126f1e61 2785 else
6cacdd46 2786 *strength = 0xffff - (value << 4);
126f1e61
RM		 2787 return 0;
2788}
2789
0df289a2 2790static int drxd_read_status(struct dvb_frontend *fe, enum fe_status *status)
126f1e61
RM		 2791{
2792 struct drxd_state *state = fe->demodulator_priv;
2793 u32 lock;
2794
2795 DRXD_status(state, &lock);
6cacdd46 2796 *status = 0;
126f1e61
RM		 2797 /* No MPEG lock in V255 firmware, bug ? */
2798#if 1
6cacdd46
DH		 2799 if (lock & DRX_LOCK_MPEG)
2800 *status |= FE_HAS_LOCK;
126f1e61 2801#else
6cacdd46
DH		 2802 if (lock & DRX_LOCK_FEC)
2803 *status |= FE_HAS_LOCK;
126f1e61 2804#endif
6cacdd46
DH		 2805 if (lock & DRX_LOCK_FEC)
2806 *status |= FE_HAS_VITERBI | FE_HAS_SYNC;
2807 if (lock & DRX_LOCK_DEMOD)
2808 *status |= FE_HAS_CARRIER | FE_HAS_SIGNAL;
126f1e61
RM		 2809
2810 return 0;
2811}
2812
2813static int drxd_init(struct dvb_frontend *fe)
2814{
6cacdd46 2815 struct drxd_state *state = fe->demodulator_priv;
126f1e61 2816
843e44a1 2817 return DRXD_init(state, NULL, 0);
126f1e61
RM		 2818}
2819
619c027d 2820static int drxd_config_i2c(struct dvb_frontend *fe, int onoff)
126f1e61 2821{
6cacdd46 2822 struct drxd_state *state = fe->demodulator_priv;
126f1e61 2823
6b142b3c
DH		 2824 if (state->config.disable_i2c_gate_ctrl == 1)
2825 return 0;
2826
126f1e61
RM		 2827 return DRX_ConfigureI2CBridge(state, onoff);
2828}
2829
2830static int drxd_get_tune_settings(struct dvb_frontend *fe,
6cacdd46 2831 struct dvb_frontend_tune_settings *sets)
126f1e61 2832{
6cacdd46
DH		 2833 sets->min_delay_ms = 10000;
2834 sets->max_drift = 0;
2835 sets->step_size = 0;
126f1e61
RM		 2836 return 0;
2837}
2838
6cacdd46 2839static int drxd_read_ber(struct dvb_frontend *fe, u32 * ber)
126f1e61
RM		 2840{
2841 *ber = 0;
2842 return 0;
2843}
2844
6cacdd46 2845static int drxd_read_snr(struct dvb_frontend *fe, u16 * snr)
126f1e61 2846{
6cacdd46 2847 *snr = 0;
126f1e61
RM		 2848 return 0;
2849}
2850
6cacdd46 2851static int drxd_read_ucblocks(struct dvb_frontend *fe, u32 * ucblocks)
126f1e61 2852{
6cacdd46 2853 *ucblocks = 0;
126f1e61
RM		 2854 return 0;
2855}
2856
6cacdd46 2857static int drxd_sleep(struct dvb_frontend *fe)
126f1e61 2858{
6cacdd46 2859 struct drxd_state *state = fe->demodulator_priv;
126f1e61
RM		 2860
2861 ConfigureMPEGOutput(state, 0);
2862 return 0;
2863}
2864
6cacdd46 2865static int drxd_i2c_gate_ctrl(struct dvb_frontend *fe, int enable)
126f1e61
RM		 2866{
2867 return drxd_config_i2c(fe, enable);
2868}
2869
9f97c288 2870static int drxd_set_frontend(struct dvb_frontend *fe)
126f1e61 2871{
9f97c288 2872 struct dtv_frontend_properties *p = &fe->dtv_property_cache;
6cacdd46
DH		 2873 struct drxd_state *state = fe->demodulator_priv;
2874 s32 off = 0;
126f1e61 2875
9f97c288 2876 state->props = *p;
126f1e61
RM		 2877 DRX_Stop(state);
2878
2879 if (fe->ops.tuner_ops.set_params) {
14d24d14 2880 fe->ops.tuner_ops.set_params(fe);
126f1e61
RM		 2881 if (fe->ops.i2c_gate_ctrl)
2882 fe->ops.i2c_gate_ctrl(fe, 0);
2883 }
2884
126f1e61
RM		 2885 msleep(200);
2886
2887 return DRX_Start(state, off);
2888}
2889
126f1e61
RM		 2890static void drxd_release(struct dvb_frontend *fe)
2891{
2892 struct drxd_state *state = fe->demodulator_priv;
2893
2894 kfree(state);
2895}
2896
bd336e63 2897static const struct dvb_frontend_ops drxd_ops = {
9f97c288 2898 .delsys = { SYS_DVBT},
126f1e61 2899 .info = {
6cacdd46 2900 .name = "Micronas DRXD DVB-T",
f1b1eabf
MCC		 2901 .frequency_min_hz = 47125 * kHz,
2902 .frequency_max_hz = 855250 * kHz,
2903 .frequency_stepsize_hz = 166667,
6cacdd46
DH		 2904 .caps = FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 |
2905 FE_CAN_FEC_3_4 | FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 |
2906 FE_CAN_FEC_AUTO |
2907 FE_CAN_QAM_16 | FE_CAN_QAM_64 |
2908 FE_CAN_QAM_AUTO |
2909 FE_CAN_TRANSMISSION_MODE_AUTO |
2910 FE_CAN_GUARD_INTERVAL_AUTO |
2911 FE_CAN_HIERARCHY_AUTO | FE_CAN_RECOVER | FE_CAN_MUTE_TS},
126f1e61
RM		 2912
2913 .release = drxd_release,
2914 .init = drxd_init,
2915 .sleep = drxd_sleep,
2916 .i2c_gate_ctrl = drxd_i2c_gate_ctrl,
2917
9f97c288 2918 .set_frontend = drxd_set_frontend,
126f1e61
RM		 2919 .get_tune_settings = drxd_get_tune_settings,
2920
2921 .read_status = drxd_read_status,
2922 .read_ber = drxd_read_ber,
2923 .read_signal_strength = drxd_read_signal_strength,
2924 .read_snr = drxd_read_snr,
2925 .read_ucblocks = drxd_read_ucblocks,
2926};
2927
2928struct dvb_frontend *drxd_attach(const struct drxd_config *config,
2929 void *priv, struct i2c_adapter *i2c,
2930 struct device *dev)
2931{
2932 struct drxd_state *state = NULL;
2933
f4f24d1f 2934 state = kzalloc(sizeof(*state), GFP_KERNEL);
126f1e61
RM		 2935 if (!state)
2936 return NULL;
126f1e61 2937
ee45ddc1 2938 state->ops = drxd_ops;
6cacdd46
DH		 2939 state->dev = dev;
2940 state->config = *config;
2941 state->i2c = i2c;
2942 state->priv = priv;
126f1e61 2943
834751d4 2944 mutex_init(&state->mutex);
126f1e61 2945
843e44a1 2946 if (Read16(state, 0, NULL, 0) < 0)
126f1e61
RM		 2947 goto error;
2948
ee45ddc1 2949 state->frontend.ops = drxd_ops;
6cacdd46 2950 state->frontend.demodulator_priv = state;
126f1e61 2951 ConfigureMPEGOutput(state, 0);
e7c953d2
PC		 2952 /* add few initialization to allow gate control */
2953 CDRXD(state, state->config.IF ? state->config.IF : 36000000);
2954 InitHI(state);
2955
126f1e61
RM		 2956 return &state->frontend;
2957
2958error:
9999daf4 2959 printk(KERN_ERR "drxd: not found\n");
126f1e61
RM		 2960 kfree(state);
2961 return NULL;
2962}
9999daf4 2963EXPORT_SYMBOL(drxd_attach);
126f1e61
RM		 2964
2965MODULE_DESCRIPTION("DRXD driver");
2966MODULE_AUTHOR("Micronas");
2967MODULE_LICENSE("GPL");
Mirror https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git