[people/ms/u-boot.git] / drivers / misc / mxc_ocotp.c

/*
 * (C) Copyright 2013 ADVANSEE
 * Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
 *
 * Based on Dirk Behme's
 * https://github.com/dirkbehme/u-boot-imx6/blob/28b17e9/drivers/misc/imx_otp.c,
 * which is based on Freescale's
 * http://git.freescale.com/git/cgit.cgi/imx/uboot-imx.git/tree/drivers/misc/imx_otp.c?h=imx_v2009.08_1.1.0&id=9aa74e6,
 * which is:
 * Copyright (C) 2011 Freescale Semiconductor, Inc.
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#include <common.h>
#include <fuse.h>
#include <asm/errno.h>
#include <asm/io.h>
#include <asm/arch/clock.h>
#include <asm/arch/imx-regs.h>

#define BO_CTRL_WR_UNLOCK		16
#define BM_CTRL_WR_UNLOCK		0xffff0000
#define BV_CTRL_WR_UNLOCK_KEY		0x3e77
#define BM_CTRL_ERROR			0x00000200
#define BM_CTRL_BUSY			0x00000100
#define BO_CTRL_ADDR			0
#define BM_CTRL_ADDR			0x0000007f

#define BO_TIMING_STROBE_READ		16
#define BM_TIMING_STROBE_READ		0x003f0000
#define BV_TIMING_STROBE_READ_NS	37
#define BO_TIMING_RELAX			12
#define BM_TIMING_RELAX			0x0000f000
#define BV_TIMING_RELAX_NS		17
#define BO_TIMING_STROBE_PROG		0
#define BM_TIMING_STROBE_PROG		0x00000fff
#define BV_TIMING_STROBE_PROG_US	10

#define BM_READ_CTRL_READ_FUSE		0x00000001

#define BF(value, field)		(((value) << BO_##field) & BM_##field)

#define WRITE_POSTAMBLE_US		2

static void wait_busy(struct ocotp_regs *regs, unsigned int delay_us)
{
	while (readl(&regs->ctrl) & BM_CTRL_BUSY)
		udelay(delay_us);
}

static void clear_error(struct ocotp_regs *regs)
{
	writel(BM_CTRL_ERROR, &regs->ctrl_clr);
}

static int prepare_access(struct ocotp_regs **regs, u32 bank, u32 word,
				int assert, const char *caller)
{
	*regs = (struct ocotp_regs *)OCOTP_BASE_ADDR;

	if (bank >= ARRAY_SIZE((*regs)->bank) ||
			word >= ARRAY_SIZE((*regs)->bank[0].fuse_regs) >> 2 ||
			!assert) {
		printf("mxc_ocotp %s(): Invalid argument\n", caller);
		return -EINVAL;
	}

	enable_ocotp_clk(1);

	wait_busy(*regs, 1);
	clear_error(*regs);

	return 0;
}

static int finish_access(struct ocotp_regs *regs, const char *caller)
{
	u32 err;

	err = !!(readl(&regs->ctrl) & BM_CTRL_ERROR);
	clear_error(regs);

	enable_ocotp_clk(0);

	if (err) {
		printf("mxc_ocotp %s(): Access protect error\n", caller);
		return -EIO;
	}

	return 0;
}

static int prepare_read(struct ocotp_regs **regs, u32 bank, u32 word, u32 *val,
			const char *caller)
{
	return prepare_access(regs, bank, word, val != NULL, caller);
}

int fuse_read(u32 bank, u32 word, u32 *val)
{
	struct ocotp_regs *regs;
	int ret;

	ret = prepare_read(&regs, bank, word, val, __func__);
	if (ret)
		return ret;

	*val = readl(&regs->bank[bank].fuse_regs[word << 2]);

	return finish_access(regs, __func__);
}

static void set_timing(struct ocotp_regs *regs)
{
	u32 ipg_clk;
	u32 relax, strobe_read, strobe_prog;
	u32 timing;

	ipg_clk = mxc_get_clock(MXC_IPG_CLK);

	relax = DIV_ROUND_UP(ipg_clk * BV_TIMING_RELAX_NS, 1000000000) - 1;
	strobe_read = DIV_ROUND_UP(ipg_clk * BV_TIMING_STROBE_READ_NS,
					1000000000) + 2 * (relax + 1) - 1;
	strobe_prog = DIV_ROUND(ipg_clk * BV_TIMING_STROBE_PROG_US, 1000000) +
			2 * (relax + 1) - 1;

	timing = BF(strobe_read, TIMING_STROBE_READ) |
			BF(relax, TIMING_RELAX) |
			BF(strobe_prog, TIMING_STROBE_PROG);

	clrsetbits_le32(&regs->timing, BM_TIMING_STROBE_READ | BM_TIMING_RELAX |
			BM_TIMING_STROBE_PROG, timing);
}

static void setup_direct_access(struct ocotp_regs *regs, u32 bank, u32 word,
				int write)
{
	u32 wr_unlock = write ? BV_CTRL_WR_UNLOCK_KEY : 0;
	u32 addr = bank << 3 | word;

	set_timing(regs);
	clrsetbits_le32(&regs->ctrl, BM_CTRL_WR_UNLOCK | BM_CTRL_ADDR,
			BF(wr_unlock, CTRL_WR_UNLOCK) |
			BF(addr, CTRL_ADDR));
}

int fuse_sense(u32 bank, u32 word, u32 *val)
{
	struct ocotp_regs *regs;
	int ret;

	ret = prepare_read(&regs, bank, word, val, __func__);
	if (ret)
		return ret;

	setup_direct_access(regs, bank, word, false);
	writel(BM_READ_CTRL_READ_FUSE, &regs->read_ctrl);
	wait_busy(regs, 1);
	*val = readl(&regs->read_fuse_data);

	return finish_access(regs, __func__);
}

static int prepare_write(struct ocotp_regs **regs, u32 bank, u32 word,
				const char *caller)
{
	return prepare_access(regs, bank, word, true, caller);
}

int fuse_prog(u32 bank, u32 word, u32 val)
{
	struct ocotp_regs *regs;
	int ret;

	ret = prepare_write(&regs, bank, word, __func__);
	if (ret)
		return ret;

	setup_direct_access(regs, bank, word, true);
	writel(val, &regs->data);
	wait_busy(regs, BV_TIMING_STROBE_PROG_US);
	udelay(WRITE_POSTAMBLE_US);

	return finish_access(regs, __func__);
}

int fuse_override(u32 bank, u32 word, u32 val)
{
	struct ocotp_regs *regs;
	int ret;

	ret = prepare_write(&regs, bank, word, __func__);
	if (ret)
		return ret;

	writel(val, &regs->bank[bank].fuse_regs[word << 2]);

	return finish_access(regs, __func__);
}
Commit	Line	Data
112fd2ec BT	1	/*
	2	* (C) Copyright 2013 ADVANSEE
	3	* Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
	4	*
	5	* Based on Dirk Behme's
	6	* https://github.com/dirkbehme/u-boot-imx6/blob/28b17e9/drivers/misc/imx_otp.c,
	7	* which is based on Freescale's
	8	* http://git.freescale.com/git/cgit.cgi/imx/uboot-imx.git/tree/drivers/misc/imx_otp.c?h=imx_v2009.08_1.1.0&id=9aa74e6,
	9	* which is:
	10	* Copyright (C) 2011 Freescale Semiconductor, Inc.
	11	*
1a459660	12	* SPDX-License-Identifier: GPL-2.0+
112fd2ec BT	13	*/
	14
	15	#include <common.h>
	16	#include <fuse.h>
	17	#include <asm/errno.h>
	18	#include <asm/io.h>
	19	#include <asm/arch/clock.h>
	20	#include <asm/arch/imx-regs.h>
	21
	22	#define BO_CTRL_WR_UNLOCK 16
	23	#define BM_CTRL_WR_UNLOCK 0xffff0000
	24	#define BV_CTRL_WR_UNLOCK_KEY 0x3e77
	25	#define BM_CTRL_ERROR 0x00000200
	26	#define BM_CTRL_BUSY 0x00000100
	27	#define BO_CTRL_ADDR 0
	28	#define BM_CTRL_ADDR 0x0000007f
	29
	30	#define BO_TIMING_STROBE_READ 16
	31	#define BM_TIMING_STROBE_READ 0x003f0000
	32	#define BV_TIMING_STROBE_READ_NS 37
	33	#define BO_TIMING_RELAX 12
	34	#define BM_TIMING_RELAX 0x0000f000
	35	#define BV_TIMING_RELAX_NS 17
	36	#define BO_TIMING_STROBE_PROG 0
	37	#define BM_TIMING_STROBE_PROG 0x00000fff
	38	#define BV_TIMING_STROBE_PROG_US 10
	39
	40	#define BM_READ_CTRL_READ_FUSE 0x00000001
	41
	42	#define BF(value, field) (((value) << BO_##field) & BM_##field)
	43
	44	#define WRITE_POSTAMBLE_US 2
	45
	46	static void wait_busy(struct ocotp_regs *regs, unsigned int delay_us)
	47	{
	48	while (readl(&regs->ctrl) & BM_CTRL_BUSY)
	49	udelay(delay_us);
	50	}
	51
	52	static void clear_error(struct ocotp_regs *regs)
	53	{
	54	writel(BM_CTRL_ERROR, &regs->ctrl_clr);
	55	}
	56
	57	static int prepare_access(struct ocotp_regs **regs, u32 bank, u32 word,
	58	int assert, const char *caller)
	59	{
	60	regs = (struct ocotp_regs )OCOTP_BASE_ADDR;
	61
	62	if (bank >= ARRAY_SIZE((*regs)->bank) \|\|
	63	word >= ARRAY_SIZE((*regs)->bank[0].fuse_regs) >> 2 \|\|
	64	!assert) {
	65	printf("mxc_ocotp %s(): Invalid argument\n", caller);
	66	return -EINVAL;
	67	}
	68
	69	enable_ocotp_clk(1);
	70
	71	wait_busy(*regs, 1);
	72	clear_error(*regs);
	73
	74	return 0;
	75	}
	76
77	static int finish_access(struct ocotp_regs regs, const char caller)
78	{
79	u32 err;
80
81	err = !!(readl(&regs->ctrl) & BM_CTRL_ERROR);
82	clear_error(regs);
83
84	enable_ocotp_clk(0);
85
86	if (err) {
87	printf("mxc_ocotp %s(): Access protect error\n", caller);
88	return -EIO;
89	}
90
91	return 0;
92	}
93
94	static int prepare_read(struct ocotp_regs *regs, u32 bank, u32 word, u32 val,
95	const char *caller)
96	{
97	return prepare_access(regs, bank, word, val != NULL, caller);
98	}
99
100	int fuse_read(u32 bank, u32 word, u32 *val)
101	{
102	struct ocotp_regs *regs;
103	int ret;
104
105	ret = prepare_read(&regs, bank, word, val, __func__);
106	if (ret)
107	return ret;
108
109	*val = readl(&regs->bank[bank].fuse_regs[word << 2]);
110
111	return finish_access(regs, __func__);
112	}
113
114	static void set_timing(struct ocotp_regs *regs)
115	{
116	u32 ipg_clk;
117	u32 relax, strobe_read, strobe_prog;
118	u32 timing;
119
120	ipg_clk = mxc_get_clock(MXC_IPG_CLK);
121
122	relax = DIV_ROUND_UP(ipg_clk * BV_TIMING_RELAX_NS, 1000000000) - 1;
123	strobe_read = DIV_ROUND_UP(ipg_clk * BV_TIMING_STROBE_READ_NS,
124	1000000000) + 2 * (relax + 1) - 1;
125	strobe_prog = DIV_ROUND(ipg_clk * BV_TIMING_STROBE_PROG_US, 1000000) +
126	2 * (relax + 1) - 1;
127
128	timing = BF(strobe_read, TIMING_STROBE_READ) \|
129	BF(relax, TIMING_RELAX) \|
130	BF(strobe_prog, TIMING_STROBE_PROG);
131
132	clrsetbits_le32(&regs->timing, BM_TIMING_STROBE_READ \| BM_TIMING_RELAX \|
133	BM_TIMING_STROBE_PROG, timing);
134	}
135
136	static void setup_direct_access(struct ocotp_regs *regs, u32 bank, u32 word,
137	int write)
138	{
139	u32 wr_unlock = write ? BV_CTRL_WR_UNLOCK_KEY : 0;
140	u32 addr = bank << 3 \| word;
141
142	set_timing(regs);
143	clrsetbits_le32(&regs->ctrl, BM_CTRL_WR_UNLOCK \| BM_CTRL_ADDR,
144	BF(wr_unlock, CTRL_WR_UNLOCK) \|
145	BF(addr, CTRL_ADDR));
146	}
147
148	int fuse_sense(u32 bank, u32 word, u32 *val)
149	{
150	struct ocotp_regs *regs;
151	int ret;
152
153	ret = prepare_read(&regs, bank, word, val, __func__);
154	if (ret)
155	return ret;
156
157	setup_direct_access(regs, bank, word, false);
158	writel(BM_READ_CTRL_READ_FUSE, &regs->read_ctrl);
159	wait_busy(regs, 1);
160	*val = readl(&regs->read_fuse_data);
161
162	return finish_access(regs, __func__);
163	}
164
165	static int prepare_write(struct ocotp_regs **regs, u32 bank, u32 word,
166	const char *caller)
167	{
168	return prepare_access(regs, bank, word, true, caller);
169	}
170
171	int fuse_prog(u32 bank, u32 word, u32 val)
172	{
173	struct ocotp_regs *regs;
174	int ret;
175
176	ret = prepare_write(&regs, bank, word, __func__);
177	if (ret)
178	return ret;
179
180	setup_direct_access(regs, bank, word, true);
181	writel(val, &regs->data);
182	wait_busy(regs, BV_TIMING_STROBE_PROG_US);
183	udelay(WRITE_POSTAMBLE_US);
184
185	return finish_access(regs, __func__);
186	}
187
188	int fuse_override(u32 bank, u32 word, u32 val)
189	{
190	struct ocotp_regs *regs;
191	int ret;
192
193	ret = prepare_write(&regs, bank, word, __func__);
194	if (ret)
195	return ret;
196
197	writel(val, &regs->bank[bank].fuse_regs[word << 2]);
198
199	return finish_access(regs, __func__);
200	}