[thirdparty/u-boot.git] / drivers / misc / mxc_ocotp.c

// SPDX-License-Identifier: GPL-2.0+
/*
 * (C) Copyright 2013 ADVANSEE
 * Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
 *
 * Based on Dirk Behme's
 * https://github.com/dirkbehme/u-boot-imx6/blob/28b17e9/drivers/misc/imx_otp.c,
 * which is based on Freescale's
 * https://source.codeaurora.org/external/imx/uboot-imx/tree/drivers/misc/imx_otp.c?id=9aa74e6,
 * which is:
 * Copyright (C) 2011 Freescale Semiconductor, Inc.
 */

#include <common.h>
#include <fuse.h>
#include <linux/delay.h>
#include <linux/errno.h>
#include <asm/io.h>
#include <asm/arch/clock.h>
#include <asm/arch/imx-regs.h>
#include <asm/mach-imx/sys_proto.h>

#define BO_CTRL_WR_UNLOCK		16
#define BM_CTRL_WR_UNLOCK		0xffff0000
#define BV_CTRL_WR_UNLOCK_KEY		0x3e77
#define BM_CTRL_ERROR			0x00000200
#define BM_CTRL_BUSY			0x00000100
#define BO_CTRL_ADDR			0
#ifdef CONFIG_MX7
#define BM_CTRL_ADDR                    0x0000000f
#define BM_CTRL_RELOAD                  0x00000400
#elif defined(CONFIG_MX7ULP)
#define BM_CTRL_ADDR                    0x000000FF
#define BM_CTRL_RELOAD                  0x00000400
#define BM_OUT_STATUS_DED				0x00000400
#define BM_OUT_STATUS_LOCKED			0x00000800
#define BM_OUT_STATUS_PROGFAIL			0x00001000
#elif defined(CONFIG_IMX8M)
#ifdef CONFIG_IMX8MP
#undef BM_CTRL_ADDR
#undef BM_CTRL_ERROR
#undef BM_CTRL_BUSY
#define BM_CTRL_ADDR			0x000001ff
#define BM_CTRL_ERROR			0x00000400
#define BM_CTRL_BUSY			0x00000200
#else
#define BM_CTRL_ADDR			0x000000ff
#endif
#else
#define BM_CTRL_ADDR			0x0000007f
#endif

#ifdef CONFIG_MX7
#define BO_TIMING_FSOURCE               12
#define BM_TIMING_FSOURCE               0x0007f000
#define BV_TIMING_FSOURCE_NS            1001
#define BO_TIMING_PROG                  0
#define BM_TIMING_PROG                  0x00000fff
#define BV_TIMING_PROG_US               10
#else
#define BO_TIMING_STROBE_READ		16
#define BM_TIMING_STROBE_READ		0x003f0000
#define BV_TIMING_STROBE_READ_NS	37
#define BO_TIMING_RELAX			12
#define BM_TIMING_RELAX			0x0000f000
#define BV_TIMING_RELAX_NS		17
#define BO_TIMING_STROBE_PROG		0
#define BM_TIMING_STROBE_PROG		0x00000fff
#define BV_TIMING_STROBE_PROG_US	10
#endif

#define BM_READ_CTRL_READ_FUSE		0x00000001

#define BF(value, field)		(((value) << BO_##field) & BM_##field)

#define WRITE_POSTAMBLE_US		2

#if defined(CONFIG_MX6) || defined(CONFIG_VF610)
#define FUSE_BANK_SIZE	0x80
#ifdef CONFIG_MX6SL
#define FUSE_BANKS	8
#elif defined(CONFIG_MX6ULL) || defined(CONFIG_MX6SLL)
#define FUSE_BANKS	9
#else
#define FUSE_BANKS	16
#endif
#elif defined CONFIG_MX7
#define FUSE_BANK_SIZE	0x40
#define FUSE_BANKS	16
#elif defined(CONFIG_MX7ULP)
#define FUSE_BANK_SIZE	0x80
#define FUSE_BANKS	31
#elif defined(CONFIG_IMX8M)
#define FUSE_BANK_SIZE	0x40
#ifdef CONFIG_IMX8MP
#define FUSE_BANKS	96
#else
#define FUSE_BANKS	64
#endif
#else
#error "Unsupported architecture\n"
#endif

#if defined(CONFIG_MX6)

/*
 * There is a hole in shadow registers address map of size 0x100
 * between bank 5 and bank 6 on iMX6QP, iMX6DQ, iMX6SDL, iMX6SX,
 * iMX6UL, i.MX6ULL and i.MX6SLL.
 * Bank 5 ends at 0x6F0 and Bank 6 starts at 0x800. When reading the fuses,
 * we should account for this hole in address space.
 *
 * Similar hole exists between bank 14 and bank 15 of size
 * 0x80 on iMX6QP, iMX6DQ, iMX6SDL and iMX6SX.
 * Note: iMX6SL has only 0-7 banks and there is no hole.
 * Note: iMX6UL doesn't have this one.
 *
 * This function is to covert user input to physical bank index.
 * Only needed when read fuse, because we use register offset, so
 * need to calculate real register offset.
 * When write, no need to consider hole, always use the bank/word
 * index from fuse map.
 */
u32 fuse_bank_physical(int index)
{
	u32 phy_index;

	if (is_mx6sl() || is_mx7ulp()) {
		phy_index = index;
	} else if (is_mx6ul() || is_mx6ull() || is_mx6sll()) {
		if ((is_mx6ull() || is_mx6sll()) && index == 8)
			index = 7;

		if (index >= 6)
			phy_index = fuse_bank_physical(5) + (index - 6) + 3;
		else
			phy_index = index;
	} else {
		if (index >= 15)
			phy_index = fuse_bank_physical(14) + (index - 15) + 2;
		else if (index >= 6)
			phy_index = fuse_bank_physical(5) + (index - 6) + 3;
		else
			phy_index = index;
	}
	return phy_index;
}

u32 fuse_word_physical(u32 bank, u32 word_index)
{
	if (is_mx6ull() || is_mx6sll()) {
		if (bank == 8)
			word_index = word_index + 4;
	}

	return word_index;
}
#else
u32 fuse_bank_physical(int index)
{
	return index;
}

u32 fuse_word_physical(u32 bank, u32 word_index)
{
	return word_index;
}

#endif

static void wait_busy(struct ocotp_regs *regs, unsigned int delay_us)
{
	while (readl(&regs->ctrl) & BM_CTRL_BUSY)
		udelay(delay_us);
}

static void clear_error(struct ocotp_regs *regs)
{
	writel(BM_CTRL_ERROR, &regs->ctrl_clr);
}

static int prepare_access(struct ocotp_regs **regs, u32 bank, u32 word,
				int assert, const char *caller)
{
	*regs = (struct ocotp_regs *)OCOTP_BASE_ADDR;

	if (bank >= FUSE_BANKS ||
	    word >= ARRAY_SIZE((*regs)->bank[0].fuse_regs) >> 2 ||
	    !assert) {
		printf("mxc_ocotp %s(): Invalid argument\n", caller);
		return -EINVAL;
	}

	if (is_mx6ull() || is_mx6sll()) {
		if ((bank == 7 || bank == 8) &&
		    word >= ARRAY_SIZE((*regs)->bank[0].fuse_regs) >> 3) {
			printf("mxc_ocotp %s(): Invalid argument\n", caller);
			return -EINVAL;
		}
	}

	enable_ocotp_clk(1);

	wait_busy(*regs, 1);
	clear_error(*regs);

	return 0;
}

static int finish_access(struct ocotp_regs *regs, const char *caller)
{
	u32 err;

	err = !!(readl(&regs->ctrl) & BM_CTRL_ERROR);
	clear_error(regs);

#ifdef CONFIG_MX7ULP
	/* Need to power down the OTP memory */
	writel(1, &regs->pdn);
#endif
	if (err) {
		printf("mxc_ocotp %s(): Access protect error\n", caller);
		return -EIO;
	}

	return 0;
}

static int prepare_read(struct ocotp_regs **regs, u32 bank, u32 word, u32 *val,
			const char *caller)
{
	return prepare_access(regs, bank, word, val != NULL, caller);
}

int fuse_read(u32 bank, u32 word, u32 *val)
{
	struct ocotp_regs *regs;
	int ret;
	u32 phy_bank;
	u32 phy_word;

	ret = prepare_read(&regs, bank, word, val, __func__);
	if (ret)
		return ret;

	phy_bank = fuse_bank_physical(bank);
	phy_word = fuse_word_physical(bank, word);

	*val = readl(&regs->bank[phy_bank].fuse_regs[phy_word << 2]);

#ifdef CONFIG_MX7ULP
	if (readl(&regs->out_status) & BM_OUT_STATUS_DED) {
		writel(BM_OUT_STATUS_DED, &regs->out_status_clr);
		printf("mxc_ocotp %s(): fuse read wrong\n", __func__);
		return -EIO;
	}
#endif
	return finish_access(regs, __func__);
}

#ifdef CONFIG_MX7
static void set_timing(struct ocotp_regs *regs)
{
	u32 ipg_clk;
	u32 fsource, prog;
	u32 timing;

	ipg_clk = mxc_get_clock(MXC_IPG_CLK);

	fsource = DIV_ROUND_UP((ipg_clk / 1000) * BV_TIMING_FSOURCE_NS,
			+       1000000) + 1;
	prog = DIV_ROUND_CLOSEST(ipg_clk * BV_TIMING_PROG_US, 1000000) + 1;

	timing = BF(fsource, TIMING_FSOURCE) | BF(prog, TIMING_PROG);

	clrsetbits_le32(&regs->timing, BM_TIMING_FSOURCE | BM_TIMING_PROG,
			timing);
}
#elif defined(CONFIG_MX7ULP)
static void set_timing(struct ocotp_regs *regs)
{
	/* No timing set for MX7ULP */
}

#else
static void set_timing(struct ocotp_regs *regs)
{
	u32 ipg_clk;
	u32 relax, strobe_read, strobe_prog;
	u32 timing;

	ipg_clk = mxc_get_clock(MXC_IPG_CLK);

	relax = DIV_ROUND_UP(ipg_clk * BV_TIMING_RELAX_NS, 1000000000) - 1;
	strobe_read = DIV_ROUND_UP(ipg_clk * BV_TIMING_STROBE_READ_NS,
					1000000000) + 2 * (relax + 1) - 1;
	strobe_prog = DIV_ROUND_CLOSEST(ipg_clk * BV_TIMING_STROBE_PROG_US,
						1000000) + 2 * (relax + 1) - 1;

	timing = BF(strobe_read, TIMING_STROBE_READ) |
			BF(relax, TIMING_RELAX) |
			BF(strobe_prog, TIMING_STROBE_PROG);

	clrsetbits_le32(&regs->timing, BM_TIMING_STROBE_READ | BM_TIMING_RELAX |
			BM_TIMING_STROBE_PROG, timing);
}
#endif

static void setup_direct_access(struct ocotp_regs *regs, u32 bank, u32 word,
				int write)
{
	u32 wr_unlock = write ? BV_CTRL_WR_UNLOCK_KEY : 0;
#ifdef CONFIG_MX7
	u32 addr = bank;
#elif defined CONFIG_IMX8M
	u32 addr = bank << 2 | word;
#else
	u32 addr;
	/* Bank 7 and Bank 8 only supports 4 words each for i.MX6ULL */
	if ((is_mx6ull() || is_mx6sll()) && (bank > 7)) {
		bank = bank - 1;
		word += 4;
	}
	addr = bank << 3 | word;
#endif

	set_timing(regs);
	clrsetbits_le32(&regs->ctrl, BM_CTRL_WR_UNLOCK | BM_CTRL_ADDR,
			BF(wr_unlock, CTRL_WR_UNLOCK) |
			BF(addr, CTRL_ADDR));
}

int fuse_sense(u32 bank, u32 word, u32 *val)
{
	struct ocotp_regs *regs;
	int ret;

	if (is_imx8mq() && (soc_rev() >= CHIP_REV_2_1)) {
		printf("mxc_ocotp %s(): fuse sense is disabled\n", __func__);
		return -EPERM;
	}

	ret = prepare_read(&regs, bank, word, val, __func__);
	if (ret)
		return ret;

	setup_direct_access(regs, bank, word, false);
	writel(BM_READ_CTRL_READ_FUSE, &regs->read_ctrl);
	wait_busy(regs, 1);
#ifdef CONFIG_MX7
	*val = readl((&regs->read_fuse_data0) + (word << 2));
#else
	*val = readl(&regs->read_fuse_data);
#endif

#ifdef CONFIG_MX7ULP
	if (readl(&regs->out_status) & BM_OUT_STATUS_DED) {
		writel(BM_OUT_STATUS_DED, &regs->out_status_clr);
		printf("mxc_ocotp %s(): fuse read wrong\n", __func__);
		return -EIO;
	}
#endif

	return finish_access(regs, __func__);
}

static int prepare_write(struct ocotp_regs **regs, u32 bank, u32 word,
				const char *caller)
{
#ifdef CONFIG_MX7ULP
	u32 val;
	int ret;

	/* Only bank 0 and 1 are redundancy mode, others are ECC mode */
	if (bank != 0 && bank != 1) {
		if ((soc_rev() < CHIP_REV_2_0) ||
		    ((soc_rev() >= CHIP_REV_2_0) &&
		    bank != 9 && bank != 10 && bank != 28)) {
			ret = fuse_sense(bank, word, &val);
			if (ret)
				return ret;

			if (val != 0) {
				printf("mxc_ocotp: The word has been programmed, no more write\n");
				return -EPERM;
			}
		}
	}
#endif

	return prepare_access(regs, bank, word, true, caller);
}

int fuse_prog(u32 bank, u32 word, u32 val)
{
	struct ocotp_regs *regs;
	int ret;

	ret = prepare_write(&regs, bank, word, __func__);
	if (ret)
		return ret;

	setup_direct_access(regs, bank, word, true);
#ifdef CONFIG_MX7
	switch (word) {
	case 0:
		writel(0, &regs->data1);
		writel(0, &regs->data2);
		writel(0, &regs->data3);
		writel(val, &regs->data0);
		break;
	case 1:
		writel(val, &regs->data1);
		writel(0, &regs->data2);
		writel(0, &regs->data3);
		writel(0, &regs->data0);
		break;
	case 2:
		writel(0, &regs->data1);
		writel(val, &regs->data2);
		writel(0, &regs->data3);
		writel(0, &regs->data0);
		break;
	case 3:
		writel(0, &regs->data1);
		writel(0, &regs->data2);
		writel(val, &regs->data3);
		writel(0, &regs->data0);
		break;
	}
	wait_busy(regs, BV_TIMING_PROG_US);
#else
	writel(val, &regs->data);
	wait_busy(regs, BV_TIMING_STROBE_PROG_US);
#endif
	udelay(WRITE_POSTAMBLE_US);

#ifdef CONFIG_MX7ULP
	if (readl(&regs->out_status) & (BM_OUT_STATUS_PROGFAIL | BM_OUT_STATUS_LOCKED)) {
		writel((BM_OUT_STATUS_PROGFAIL | BM_OUT_STATUS_LOCKED), &regs->out_status_clr);
		printf("mxc_ocotp %s(): fuse write is failed\n", __func__);
		return -EIO;
	}
#endif

	return finish_access(regs, __func__);
}

int fuse_override(u32 bank, u32 word, u32 val)
{
	struct ocotp_regs *regs;
	int ret;
	u32 phy_bank;
	u32 phy_word;

	ret = prepare_write(&regs, bank, word, __func__);
	if (ret)
		return ret;

	phy_bank = fuse_bank_physical(bank);
	phy_word = fuse_word_physical(bank, word);

	writel(val, &regs->bank[phy_bank].fuse_regs[phy_word << 2]);

#ifdef CONFIG_MX7ULP
	if (readl(&regs->out_status) & (BM_OUT_STATUS_PROGFAIL | BM_OUT_STATUS_LOCKED)) {
		writel((BM_OUT_STATUS_PROGFAIL | BM_OUT_STATUS_LOCKED), &regs->out_status_clr);
		printf("mxc_ocotp %s(): fuse write is failed\n", __func__);
		return -EIO;
	}
#endif

	return finish_access(regs, __func__);
}
Commit	Line	Data
83d290c5	1	// SPDX-License-Identifier: GPL-2.0+
112fd2ec BT	2	/*
	3	* (C) Copyright 2013 ADVANSEE
	4	* Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
	5	*
	6	* Based on Dirk Behme's
	7	* https://github.com/dirkbehme/u-boot-imx6/blob/28b17e9/drivers/misc/imx_otp.c,
	8	* which is based on Freescale's
d66b0f5d	9	* https://source.codeaurora.org/external/imx/uboot-imx/tree/drivers/misc/imx_otp.c?id=9aa74e6,
112fd2ec BT	10	* which is:
112fd2ec BT	11	* Copyright (C) 2011 Freescale Semiconductor, Inc.
112fd2ec BT	12	*/
112fd2ec BT	13
d678a59d	14	#include <common.h>
112fd2ec	15	#include <fuse.h>
c05ed00a	16	#include <linux/delay.h>
1221ce45	17	#include <linux/errno.h>
112fd2ec BT	18	#include <asm/io.h>
	19	#include <asm/arch/clock.h>
	20	#include <asm/arch/imx-regs.h>
552a848e	21	#include <asm/mach-imx/sys_proto.h>
112fd2ec BT	22
	23	#define BO_CTRL_WR_UNLOCK 16
	24	#define BM_CTRL_WR_UNLOCK 0xffff0000
	25	#define BV_CTRL_WR_UNLOCK_KEY 0x3e77
	26	#define BM_CTRL_ERROR 0x00000200
	27	#define BM_CTRL_BUSY 0x00000100
	28	#define BO_CTRL_ADDR 0
42c91c10 AA	29	#ifdef CONFIG_MX7
	30	#define BM_CTRL_ADDR 0x0000000f
	31	#define BM_CTRL_RELOAD 0x00000400
3ca0f0d2 PF	32	#elif defined(CONFIG_MX7ULP)
	33	#define BM_CTRL_ADDR 0x000000FF
	34	#define BM_CTRL_RELOAD 0x00000400
	35	#define BM_OUT_STATUS_DED 0x00000400
	36	#define BM_OUT_STATUS_LOCKED 0x00000800
	37	#define BM_OUT_STATUS_PROGFAIL 0x00001000
cd357ad1	38	#elif defined(CONFIG_IMX8M)
67f3f32c PF	39	#ifdef CONFIG_IMX8MP
	40	#undef BM_CTRL_ADDR
	41	#undef BM_CTRL_ERROR
	42	#undef BM_CTRL_BUSY
	43	#define BM_CTRL_ADDR 0x000001ff
	44	#define BM_CTRL_ERROR 0x00000400
	45	#define BM_CTRL_BUSY 0x00000200
	46	#else
8a099b68	47	#define BM_CTRL_ADDR 0x000000ff
67f3f32c	48	#endif
42c91c10	49	#else
112fd2ec	50	#define BM_CTRL_ADDR 0x0000007f
42c91c10 AA	51	#endif
	52
	53	#ifdef CONFIG_MX7
	54	#define BO_TIMING_FSOURCE 12
	55	#define BM_TIMING_FSOURCE 0x0007f000
	56	#define BV_TIMING_FSOURCE_NS 1001
	57	#define BO_TIMING_PROG 0
	58	#define BM_TIMING_PROG 0x00000fff
	59	#define BV_TIMING_PROG_US 10
	60	#else
112fd2ec BT	61	#define BO_TIMING_STROBE_READ 16
	62	#define BM_TIMING_STROBE_READ 0x003f0000
	63	#define BV_TIMING_STROBE_READ_NS 37
	64	#define BO_TIMING_RELAX 12
	65	#define BM_TIMING_RELAX 0x0000f000
	66	#define BV_TIMING_RELAX_NS 17
	67	#define BO_TIMING_STROBE_PROG 0
	68	#define BM_TIMING_STROBE_PROG 0x00000fff
	69	#define BV_TIMING_STROBE_PROG_US 10
42c91c10	70	#endif
112fd2ec BT	71
	72	#define BM_READ_CTRL_READ_FUSE 0x00000001
	73
	74	#define BF(value, field) (((value) << BO_##field) & BM_##field)
	75
	76	#define WRITE_POSTAMBLE_US 2
	77
7296a023 PF	78	#if defined(CONFIG_MX6) \|\| defined(CONFIG_VF610)
	79	#define FUSE_BANK_SIZE 0x80
	80	#ifdef CONFIG_MX6SL
	81	#define FUSE_BANKS 8
b2ebdd85	82	#elif defined(CONFIG_MX6ULL) \|\| defined(CONFIG_MX6SLL)
f8b95731	83	#define FUSE_BANKS 9
7296a023 PF	84	#else
	85	#define FUSE_BANKS 16
	86	#endif
	87	#elif defined CONFIG_MX7
	88	#define FUSE_BANK_SIZE 0x40
	89	#define FUSE_BANKS 16
3ca0f0d2 PF	90	#elif defined(CONFIG_MX7ULP)
	91	#define FUSE_BANK_SIZE 0x80
	92	#define FUSE_BANKS 31
cd357ad1	93	#elif defined(CONFIG_IMX8M)
8a099b68	94	#define FUSE_BANK_SIZE 0x40
67f3f32c PF	95	#ifdef CONFIG_IMX8MP
	96	#define FUSE_BANKS 96
	97	#else
8a099b68	98	#define FUSE_BANKS 64
67f3f32c	99	#endif
7296a023 PF	100	#else
	101	#error "Unsupported architecture\n"
	102	#endif
	103
	104	#if defined(CONFIG_MX6)
7296a023 PF	105
	106	/*
	107	* There is a hole in shadow registers address map of size 0x100
f8b95731	108	* between bank 5 and bank 6 on iMX6QP, iMX6DQ, iMX6SDL, iMX6SX,
b2ebdd85	109	* iMX6UL, i.MX6ULL and i.MX6SLL.
7296a023 PF	110	* Bank 5 ends at 0x6F0 and Bank 6 starts at 0x800. When reading the fuses,
	111	* we should account for this hole in address space.
	112	*
	113	* Similar hole exists between bank 14 and bank 15 of size
	114	* 0x80 on iMX6QP, iMX6DQ, iMX6SDL and iMX6SX.
	115	* Note: iMX6SL has only 0-7 banks and there is no hole.
	116	* Note: iMX6UL doesn't have this one.
	117	*
	118	* This function is to covert user input to physical bank index.
	119	* Only needed when read fuse, because we use register offset, so
	120	* need to calculate real register offset.
	121	* When write, no need to consider hole, always use the bank/word
	122	* index from fuse map.
	123	*/
	124	u32 fuse_bank_physical(int index)
	125	{
	126	u32 phy_index;
	127
3ca0f0d2	128	if (is_mx6sl() \|\| is_mx7ulp()) {
7296a023	129	phy_index = index;
b2ebdd85 PF	130	} else if (is_mx6ul() \|\| is_mx6ull() \|\| is_mx6sll()) {
b2ebdd85 PF	131	if ((is_mx6ull() \|\| is_mx6sll()) && index == 8)
f8b95731 PF	132	index = 7;
f8b95731 PF	133
7296a023 PF	134	if (index >= 6)
	135	phy_index = fuse_bank_physical(5) + (index - 6) + 3;
	136	else
	137	phy_index = index;
	138	} else {
	139	if (index >= 15)
	140	phy_index = fuse_bank_physical(14) + (index - 15) + 2;
	141	else if (index >= 6)
	142	phy_index = fuse_bank_physical(5) + (index - 6) + 3;
	143	else
	144	phy_index = index;
	145	}
	146	return phy_index;
	147	}
f8b95731 PF	148
	149	u32 fuse_word_physical(u32 bank, u32 word_index)
	150	{
b2ebdd85	151	if (is_mx6ull() \|\| is_mx6sll()) {
f8b95731 PF	152	if (bank == 8)
	153	word_index = word_index + 4;
	154	}
	155
	156	return word_index;
	157	}
7296a023 PF	158	#else
	159	u32 fuse_bank_physical(int index)
	160	{
	161	return index;
	162	}
f8b95731 PF	163
	164	u32 fuse_word_physical(u32 bank, u32 word_index)
	165	{
	166	return word_index;
	167	}
	168
7296a023 PF	169	#endif
7296a023 PF	170
112fd2ec BT	171	static void wait_busy(struct ocotp_regs *regs, unsigned int delay_us)
	172	{
	173	while (readl(&regs->ctrl) & BM_CTRL_BUSY)
	174	udelay(delay_us);
	175	}
	176
	177	static void clear_error(struct ocotp_regs *regs)
	178	{
	179	writel(BM_CTRL_ERROR, &regs->ctrl_clr);
	180	}
	181
	182	static int prepare_access(struct ocotp_regs **regs, u32 bank, u32 word,
	183	int assert, const char *caller)
	184	{
	185	regs = (struct ocotp_regs )OCOTP_BASE_ADDR;
	186
7296a023 PF	187	if (bank >= FUSE_BANKS \|\|
	188	word >= ARRAY_SIZE((*regs)->bank[0].fuse_regs) >> 2 \|\|
	189	!assert) {
112fd2ec BT	190	printf("mxc_ocotp %s(): Invalid argument\n", caller);
	191	return -EINVAL;
	192	}
	193
b2ebdd85	194	if (is_mx6ull() \|\| is_mx6sll()) {
f8b95731 PF	195	if ((bank == 7 \|\| bank == 8) &&
f8b95731 PF	196	word >= ARRAY_SIZE((*regs)->bank[0].fuse_regs) >> 3) {
b2ebdd85	197	printf("mxc_ocotp %s(): Invalid argument\n", caller);
f8b95731 PF	198	return -EINVAL;
	199	}
	200	}
	201
112fd2ec BT	202	enable_ocotp_clk(1);
	203
	204	wait_busy(*regs, 1);
	205	clear_error(*regs);
	206
	207	return 0;
	208	}
	209
	210	static int finish_access(struct ocotp_regs regs, const char caller)
	211	{
	212	u32 err;
	213
	214	err = !!(readl(&regs->ctrl) & BM_CTRL_ERROR);
	215	clear_error(regs);
	216
3ca0f0d2 PF	217	#ifdef CONFIG_MX7ULP
	218	/* Need to power down the OTP memory */
	219	writel(1, &regs->pdn);
	220	#endif
112fd2ec BT	221	if (err) {
	222	printf("mxc_ocotp %s(): Access protect error\n", caller);
	223	return -EIO;
	224	}
	225
	226	return 0;
	227	}
	228
	229	static int prepare_read(struct ocotp_regs *regs, u32 bank, u32 word, u32 val,
	230	const char *caller)
	231	{
	232	return prepare_access(regs, bank, word, val != NULL, caller);
	233	}
	234
	235	int fuse_read(u32 bank, u32 word, u32 *val)
	236	{
	237	struct ocotp_regs *regs;
	238	int ret;
7296a023	239	u32 phy_bank;
f8b95731	240	u32 phy_word;
112fd2ec BT	241
	242	ret = prepare_read(&regs, bank, word, val, __func__);
	243	if (ret)
	244	return ret;
	245
7296a023	246	phy_bank = fuse_bank_physical(bank);
f8b95731	247	phy_word = fuse_word_physical(bank, word);
7296a023	248
f8b95731	249	*val = readl(&regs->bank[phy_bank].fuse_regs[phy_word << 2]);
112fd2ec	250
3ca0f0d2 PF	251	#ifdef CONFIG_MX7ULP
	252	if (readl(&regs->out_status) & BM_OUT_STATUS_DED) {
	253	writel(BM_OUT_STATUS_DED, &regs->out_status_clr);
	254	printf("mxc_ocotp %s(): fuse read wrong\n", __func__);
	255	return -EIO;
	256	}
	257	#endif
112fd2ec BT	258	return finish_access(regs, __func__);
	259	}
	260
42c91c10 AA	261	#ifdef CONFIG_MX7
	262	static void set_timing(struct ocotp_regs *regs)
	263	{
	264	u32 ipg_clk;
	265	u32 fsource, prog;
	266	u32 timing;
	267
	268	ipg_clk = mxc_get_clock(MXC_IPG_CLK);
	269
	270	fsource = DIV_ROUND_UP((ipg_clk / 1000) * BV_TIMING_FSOURCE_NS,
	271	+ 1000000) + 1;
	272	prog = DIV_ROUND_CLOSEST(ipg_clk * BV_TIMING_PROG_US, 1000000) + 1;
	273
	274	timing = BF(fsource, TIMING_FSOURCE) \| BF(prog, TIMING_PROG);
	275
	276	clrsetbits_le32(&regs->timing, BM_TIMING_FSOURCE \| BM_TIMING_PROG,
	277	timing);
	278	}
3ca0f0d2 PF	279	#elif defined(CONFIG_MX7ULP)
	280	static void set_timing(struct ocotp_regs *regs)
	281	{
	282	/* No timing set for MX7ULP */
	283	}
	284
42c91c10	285	#else
112fd2ec BT	286	static void set_timing(struct ocotp_regs *regs)
	287	{
	288	u32 ipg_clk;
	289	u32 relax, strobe_read, strobe_prog;
	290	u32 timing;
	291
	292	ipg_clk = mxc_get_clock(MXC_IPG_CLK);
	293
	294	relax = DIV_ROUND_UP(ipg_clk * BV_TIMING_RELAX_NS, 1000000000) - 1;
	295	strobe_read = DIV_ROUND_UP(ipg_clk * BV_TIMING_STROBE_READ_NS,
	296	1000000000) + 2 * (relax + 1) - 1;
4515992f MY	297	strobe_prog = DIV_ROUND_CLOSEST(ipg_clk * BV_TIMING_STROBE_PROG_US,
4515992f MY	298	1000000) + 2 * (relax + 1) - 1;
112fd2ec BT	299
	300	timing = BF(strobe_read, TIMING_STROBE_READ) \|
	301	BF(relax, TIMING_RELAX) \|
	302	BF(strobe_prog, TIMING_STROBE_PROG);
	303
	304	clrsetbits_le32(&regs->timing, BM_TIMING_STROBE_READ \| BM_TIMING_RELAX \|
	305	BM_TIMING_STROBE_PROG, timing);
	306	}
42c91c10	307	#endif
112fd2ec BT	308
	309	static void setup_direct_access(struct ocotp_regs *regs, u32 bank, u32 word,
	310	int write)
	311	{
	312	u32 wr_unlock = write ? BV_CTRL_WR_UNLOCK_KEY : 0;
42c91c10 AA	313	#ifdef CONFIG_MX7
42c91c10 AA	314	u32 addr = bank;
cd357ad1	315	#elif defined CONFIG_IMX8M
8a099b68	316	u32 addr = bank << 2 \| word;
42c91c10	317	#else
f8b95731 PF	318	u32 addr;
f8b95731 PF	319	/* Bank 7 and Bank 8 only supports 4 words each for i.MX6ULL */
b2ebdd85	320	if ((is_mx6ull() \|\| is_mx6sll()) && (bank > 7)) {
f8b95731 PF	321	bank = bank - 1;
	322	word += 4;
	323	}
	324	addr = bank << 3 \| word;
42c91c10	325	#endif
112fd2ec BT	326
	327	set_timing(regs);
	328	clrsetbits_le32(&regs->ctrl, BM_CTRL_WR_UNLOCK \| BM_CTRL_ADDR,
	329	BF(wr_unlock, CTRL_WR_UNLOCK) \|
	330	BF(addr, CTRL_ADDR));
	331	}
	332
	333	int fuse_sense(u32 bank, u32 word, u32 *val)
	334	{
	335	struct ocotp_regs *regs;
	336	int ret;
	337
10867a0d	338	if (is_imx8mq() && (soc_rev() >= CHIP_REV_2_1)) {
b3cf86c8 YL	339	printf("mxc_ocotp %s(): fuse sense is disabled\n", __func__);
	340	return -EPERM;
	341	}
	342
112fd2ec BT	343	ret = prepare_read(&regs, bank, word, val, __func__);
	344	if (ret)
	345	return ret;
	346
	347	setup_direct_access(regs, bank, word, false);
	348	writel(BM_READ_CTRL_READ_FUSE, &regs->read_ctrl);
	349	wait_busy(regs, 1);
42c91c10 AA	350	#ifdef CONFIG_MX7
	351	*val = readl((&regs->read_fuse_data0) + (word << 2));
	352	#else
112fd2ec	353	*val = readl(&regs->read_fuse_data);
42c91c10	354	#endif
112fd2ec	355
3ca0f0d2 PF	356	#ifdef CONFIG_MX7ULP
	357	if (readl(&regs->out_status) & BM_OUT_STATUS_DED) {
	358	writel(BM_OUT_STATUS_DED, &regs->out_status_clr);
	359	printf("mxc_ocotp %s(): fuse read wrong\n", __func__);
	360	return -EIO;
	361	}
	362	#endif
	363
112fd2ec BT	364	return finish_access(regs, __func__);
	365	}
	366
	367	static int prepare_write(struct ocotp_regs **regs, u32 bank, u32 word,
	368	const char *caller)
	369	{
8df42bee PF	370	#ifdef CONFIG_MX7ULP
	371	u32 val;
	372	int ret;
	373
	374	/* Only bank 0 and 1 are redundancy mode, others are ECC mode */
	375	if (bank != 0 && bank != 1) {
112ad600 YL	376	if ((soc_rev() < CHIP_REV_2_0) \|\|
	377	((soc_rev() >= CHIP_REV_2_0) &&
	378	bank != 9 && bank != 10 && bank != 28)) {
	379	ret = fuse_sense(bank, word, &val);
	380	if (ret)
	381	return ret;
	382
	383	if (val != 0) {
	384	printf("mxc_ocotp: The word has been programmed, no more write\n");
	385	return -EPERM;
	386	}
8df42bee PF	387	}
	388	}
	389	#endif
	390
112fd2ec BT	391	return prepare_access(regs, bank, word, true, caller);
	392	}
	393
	394	int fuse_prog(u32 bank, u32 word, u32 val)
	395	{
	396	struct ocotp_regs *regs;
	397	int ret;
	398
	399	ret = prepare_write(&regs, bank, word, __func__);
	400	if (ret)
	401	return ret;
	402
	403	setup_direct_access(regs, bank, word, true);
42c91c10 AA	404	#ifdef CONFIG_MX7
	405	switch (word) {
	406	case 0:
	407	writel(0, &regs->data1);
	408	writel(0, &regs->data2);
	409	writel(0, &regs->data3);
	410	writel(val, &regs->data0);
	411	break;
	412	case 1:
	413	writel(val, &regs->data1);
	414	writel(0, &regs->data2);
	415	writel(0, &regs->data3);
	416	writel(0, &regs->data0);
	417	break;
	418	case 2:
	419	writel(0, &regs->data1);
	420	writel(val, &regs->data2);
	421	writel(0, &regs->data3);
	422	writel(0, &regs->data0);
	423	break;
	424	case 3:
	425	writel(0, &regs->data1);
	426	writel(0, &regs->data2);
	427	writel(val, &regs->data3);
	428	writel(0, &regs->data0);
	429	break;
	430	}
	431	wait_busy(regs, BV_TIMING_PROG_US);
	432	#else
112fd2ec BT	433	writel(val, &regs->data);
112fd2ec BT	434	wait_busy(regs, BV_TIMING_STROBE_PROG_US);
42c91c10	435	#endif
112fd2ec BT	436	udelay(WRITE_POSTAMBLE_US);
112fd2ec BT	437
3ca0f0d2 PF	438	#ifdef CONFIG_MX7ULP
	439	if (readl(&regs->out_status) & (BM_OUT_STATUS_PROGFAIL \| BM_OUT_STATUS_LOCKED)) {
	440	writel((BM_OUT_STATUS_PROGFAIL \| BM_OUT_STATUS_LOCKED), &regs->out_status_clr);
	441	printf("mxc_ocotp %s(): fuse write is failed\n", __func__);
	442	return -EIO;
	443	}
	444	#endif
	445
112fd2ec BT	446	return finish_access(regs, __func__);
	447	}
	448
	449	int fuse_override(u32 bank, u32 word, u32 val)
	450	{
	451	struct ocotp_regs *regs;
	452	int ret;
7296a023	453	u32 phy_bank;
f8b95731	454	u32 phy_word;
112fd2ec BT	455
	456	ret = prepare_write(&regs, bank, word, __func__);
	457	if (ret)
	458	return ret;
	459
7296a023	460	phy_bank = fuse_bank_physical(bank);
f8b95731	461	phy_word = fuse_word_physical(bank, word);
7296a023	462
f8b95731	463	writel(val, &regs->bank[phy_bank].fuse_regs[phy_word << 2]);
112fd2ec	464
3ca0f0d2 PF	465	#ifdef CONFIG_MX7ULP
	466	if (readl(&regs->out_status) & (BM_OUT_STATUS_PROGFAIL \| BM_OUT_STATUS_LOCKED)) {
	467	writel((BM_OUT_STATUS_PROGFAIL \| BM_OUT_STATUS_LOCKED), &regs->out_status_clr);
	468	printf("mxc_ocotp %s(): fuse write is failed\n", __func__);
	469	return -EIO;
	470	}
	471	#endif
	472
112fd2ec BT	473	return finish_access(regs, __func__);
112fd2ec BT	474	}