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73dd5c4c SW |
1 | /* |
2 | * Copyright (c) 2016, NVIDIA CORPORATION. | |
3 | * | |
4 | * SPDX-License-Identifier: GPL-2.0 | |
5 | */ | |
6 | ||
7 | #include <common.h> | |
8 | #include <dm.h> | |
9 | #include <dm/lists.h> | |
10 | #include <dm/root.h> | |
11 | #include <mailbox.h> | |
12 | #include <misc.h> | |
13 | #include <asm/arch-tegra/bpmp_abi.h> | |
14 | #include <asm/arch-tegra/ivc.h> | |
15 | ||
16 | #define BPMP_IVC_FRAME_COUNT 1 | |
17 | #define BPMP_IVC_FRAME_SIZE 128 | |
18 | ||
19 | #define BPMP_FLAG_DO_ACK BIT(0) | |
20 | #define BPMP_FLAG_RING_DOORBELL BIT(1) | |
21 | ||
22 | DECLARE_GLOBAL_DATA_PTR; | |
23 | ||
24 | struct tegra186_bpmp { | |
25 | struct mbox_chan mbox; | |
26 | struct tegra_ivc ivc; | |
27 | }; | |
28 | ||
29 | static int tegra186_bpmp_call(struct udevice *dev, int mrq, void *tx_msg, | |
30 | int tx_size, void *rx_msg, int rx_size) | |
31 | { | |
32 | struct tegra186_bpmp *priv = dev_get_priv(dev); | |
33 | int ret, err; | |
34 | void *ivc_frame; | |
35 | struct mrq_request *req; | |
36 | struct mrq_response *resp; | |
37 | ulong start_time; | |
38 | ||
39 | debug("%s(dev=%p, mrq=%u, tx_msg=%p, tx_size=%d, rx_msg=%p, rx_size=%d) (priv=%p)\n", | |
40 | __func__, dev, mrq, tx_msg, tx_size, rx_msg, rx_size, priv); | |
41 | ||
42 | if ((tx_size > BPMP_IVC_FRAME_SIZE) || (rx_size > BPMP_IVC_FRAME_SIZE)) | |
43 | return -EINVAL; | |
44 | ||
45 | ret = tegra_ivc_write_get_next_frame(&priv->ivc, &ivc_frame); | |
46 | if (ret) { | |
47 | error("tegra_ivc_write_get_next_frame() failed: %d\n", ret); | |
48 | return ret; | |
49 | } | |
50 | ||
51 | req = ivc_frame; | |
52 | req->mrq = mrq; | |
53 | req->flags = BPMP_FLAG_DO_ACK | BPMP_FLAG_RING_DOORBELL; | |
54 | memcpy(req + 1, tx_msg, tx_size); | |
55 | ||
56 | ret = tegra_ivc_write_advance(&priv->ivc); | |
57 | if (ret) { | |
58 | error("tegra_ivc_write_advance() failed: %d\n", ret); | |
59 | return ret; | |
60 | } | |
61 | ||
62 | start_time = timer_get_us(); | |
63 | for (;;) { | |
64 | ret = tegra_ivc_channel_notified(&priv->ivc); | |
65 | if (ret) { | |
66 | error("tegra_ivc_channel_notified() failed: %d\n", ret); | |
67 | return ret; | |
68 | } | |
69 | ||
70 | ret = tegra_ivc_read_get_next_frame(&priv->ivc, &ivc_frame); | |
71 | if (!ret) | |
72 | break; | |
73 | ||
74 | /* Timeout 20ms; roughly 10x current max observed duration */ | |
75 | if ((timer_get_us() - start_time) > 20 * 1000) { | |
76 | error("tegra_ivc_read_get_next_frame() timed out (%d)\n", | |
77 | ret); | |
78 | return -ETIMEDOUT; | |
79 | } | |
80 | } | |
81 | ||
82 | resp = ivc_frame; | |
83 | err = resp->err; | |
84 | if (!err && rx_msg && rx_size) | |
85 | memcpy(rx_msg, resp + 1, rx_size); | |
86 | ||
87 | ret = tegra_ivc_read_advance(&priv->ivc); | |
88 | if (ret) { | |
89 | error("tegra_ivc_write_advance() failed: %d\n", ret); | |
90 | return ret; | |
91 | } | |
92 | ||
93 | if (err) { | |
94 | error("BPMP responded with error %d\n", err); | |
95 | /* err isn't a U-Boot error code, so don't that */ | |
96 | return -EIO; | |
97 | } | |
98 | ||
99 | return rx_size; | |
100 | } | |
101 | ||
102 | /** | |
103 | * The BPMP exposes multiple different services. We create a sub-device for | |
104 | * each separate type of service, since each device must be of the appropriate | |
105 | * UCLASS. | |
106 | */ | |
107 | static int tegra186_bpmp_bind(struct udevice *dev) | |
108 | { | |
109 | int ret; | |
110 | struct udevice *child; | |
111 | ||
112 | debug("%s(dev=%p)\n", __func__, dev); | |
113 | ||
114 | ret = device_bind_driver_to_node(dev, "tegra186_clk", "tegra186_clk", | |
e160f7d4 | 115 | dev_of_offset(dev), &child); |
73dd5c4c SW |
116 | if (ret) |
117 | return ret; | |
118 | ||
119 | ret = device_bind_driver_to_node(dev, "tegra186_reset", | |
e160f7d4 | 120 | "tegra186_reset", dev_of_offset(dev), |
73dd5c4c SW |
121 | &child); |
122 | if (ret) | |
123 | return ret; | |
124 | ||
125 | ret = device_bind_driver_to_node(dev, "tegra186_power_domain", | |
126 | "tegra186_power_domain", | |
e160f7d4 | 127 | dev_of_offset(dev), &child); |
73dd5c4c SW |
128 | if (ret) |
129 | return ret; | |
130 | ||
131 | ret = dm_scan_fdt_dev(dev); | |
132 | if (ret) | |
133 | return ret; | |
134 | ||
135 | return 0; | |
136 | } | |
137 | ||
138 | static ulong tegra186_bpmp_get_shmem(struct udevice *dev, int index) | |
139 | { | |
140 | int ret; | |
141 | struct fdtdec_phandle_args args; | |
142 | fdt_addr_t reg; | |
143 | ||
e160f7d4 | 144 | ret = fdtdec_parse_phandle_with_args(gd->fdt_blob, dev_of_offset(dev), |
73dd5c4c SW |
145 | "shmem", NULL, 0, index, &args); |
146 | if (ret < 0) { | |
147 | error("fdtdec_parse_phandle_with_args() failed: %d\n", ret); | |
148 | return ret; | |
149 | } | |
150 | ||
151 | reg = fdtdec_get_addr_size_auto_noparent(gd->fdt_blob, args.node, | |
152 | "reg", 0, NULL, true); | |
153 | if (reg == FDT_ADDR_T_NONE) { | |
154 | error("fdtdec_get_addr_size_auto_noparent() failed\n"); | |
155 | return -ENODEV; | |
156 | } | |
157 | ||
158 | return reg; | |
159 | } | |
160 | ||
161 | static void tegra186_bpmp_ivc_notify(struct tegra_ivc *ivc) | |
162 | { | |
163 | struct tegra186_bpmp *priv = | |
164 | container_of(ivc, struct tegra186_bpmp, ivc); | |
165 | int ret; | |
166 | ||
167 | ret = mbox_send(&priv->mbox, NULL); | |
168 | if (ret) | |
169 | error("mbox_send() failed: %d\n", ret); | |
170 | } | |
171 | ||
172 | static int tegra186_bpmp_probe(struct udevice *dev) | |
173 | { | |
174 | struct tegra186_bpmp *priv = dev_get_priv(dev); | |
175 | int ret; | |
176 | ulong tx_base, rx_base, start_time; | |
177 | ||
178 | debug("%s(dev=%p) (priv=%p)\n", __func__, dev, priv); | |
179 | ||
180 | ret = mbox_get_by_index(dev, 0, &priv->mbox); | |
181 | if (ret) { | |
182 | error("mbox_get_by_index() failed: %d\n", ret); | |
183 | return ret; | |
184 | } | |
185 | ||
186 | tx_base = tegra186_bpmp_get_shmem(dev, 0); | |
187 | if (IS_ERR_VALUE(tx_base)) { | |
188 | error("tegra186_bpmp_get_shmem failed for tx_base\n"); | |
189 | return tx_base; | |
190 | } | |
191 | rx_base = tegra186_bpmp_get_shmem(dev, 1); | |
192 | if (IS_ERR_VALUE(rx_base)) { | |
193 | error("tegra186_bpmp_get_shmem failed for rx_base\n"); | |
194 | return rx_base; | |
195 | } | |
196 | debug("shmem: rx=%lx, tx=%lx\n", rx_base, tx_base); | |
197 | ||
198 | ret = tegra_ivc_init(&priv->ivc, rx_base, tx_base, BPMP_IVC_FRAME_COUNT, | |
199 | BPMP_IVC_FRAME_SIZE, tegra186_bpmp_ivc_notify); | |
200 | if (ret) { | |
201 | error("tegra_ivc_init() failed: %d\n", ret); | |
202 | return ret; | |
203 | } | |
204 | ||
205 | tegra_ivc_channel_reset(&priv->ivc); | |
206 | start_time = timer_get_us(); | |
207 | for (;;) { | |
208 | ret = tegra_ivc_channel_notified(&priv->ivc); | |
209 | if (!ret) | |
210 | break; | |
211 | ||
212 | /* Timeout 100ms */ | |
213 | if ((timer_get_us() - start_time) > 100 * 1000) { | |
214 | error("Initial IVC reset timed out (%d)\n", ret); | |
215 | ret = -ETIMEDOUT; | |
216 | goto err_free_mbox; | |
217 | } | |
218 | } | |
219 | ||
220 | return 0; | |
221 | ||
222 | err_free_mbox: | |
223 | mbox_free(&priv->mbox); | |
224 | ||
225 | return ret; | |
226 | } | |
227 | ||
228 | static int tegra186_bpmp_remove(struct udevice *dev) | |
229 | { | |
230 | struct tegra186_bpmp *priv = dev_get_priv(dev); | |
231 | ||
232 | debug("%s(dev=%p) (priv=%p)\n", __func__, dev, priv); | |
233 | ||
234 | mbox_free(&priv->mbox); | |
235 | ||
236 | return 0; | |
237 | } | |
238 | ||
239 | static struct misc_ops tegra186_bpmp_ops = { | |
240 | .call = tegra186_bpmp_call, | |
241 | }; | |
242 | ||
243 | static const struct udevice_id tegra186_bpmp_ids[] = { | |
244 | { .compatible = "nvidia,tegra186-bpmp" }, | |
245 | { } | |
246 | }; | |
247 | ||
248 | U_BOOT_DRIVER(tegra186_bpmp) = { | |
249 | .name = "tegra186_bpmp", | |
250 | .id = UCLASS_MISC, | |
251 | .of_match = tegra186_bpmp_ids, | |
252 | .bind = tegra186_bpmp_bind, | |
253 | .probe = tegra186_bpmp_probe, | |
254 | .remove = tegra186_bpmp_remove, | |
255 | .ops = &tegra186_bpmp_ops, | |
256 | .priv_auto_alloc_size = sizeof(struct tegra186_bpmp), | |
257 | }; |