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Commit | Line | Data |
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d0ebbb8d JC |
1 | /* |
2 | * (C) Copyright 2012 SAMSUNG Electronics | |
3 | * Jaehoon Chung <jh80.chung@samsung.com> | |
4 | * | |
1a459660 | 5 | * SPDX-License-Identifier: GPL-2.0+ |
d0ebbb8d JC |
6 | */ |
7 | ||
8 | #include <common.h> | |
d0ebbb8d | 9 | #include <dwmmc.h> |
a082a2dd A |
10 | #include <fdtdec.h> |
11 | #include <libfdt.h> | |
12 | #include <malloc.h> | |
ccd60a85 | 13 | #include <errno.h> |
d0ebbb8d JC |
14 | #include <asm/arch/dwmmc.h> |
15 | #include <asm/arch/clk.h> | |
a082a2dd | 16 | #include <asm/arch/pinmux.h> |
64029f7a | 17 | #include <asm/arch/power.h> |
959198f7 | 18 | #include <asm/gpio.h> |
d0ebbb8d | 19 | |
a082a2dd A |
20 | #define DWMMC_MAX_CH_NUM 4 |
21 | #define DWMMC_MAX_FREQ 52000000 | |
22 | #define DWMMC_MIN_FREQ 400000 | |
5dab81ce JC |
23 | #define DWMMC_MMC0_SDR_TIMING_VAL 0x03030001 |
24 | #define DWMMC_MMC2_SDR_TIMING_VAL 0x03020001 | |
25 | ||
3537ee87 JC |
26 | #ifdef CONFIG_DM_MMC |
27 | #include <dm.h> | |
28 | DECLARE_GLOBAL_DATA_PTR; | |
29 | ||
30 | struct exynos_mmc_plat { | |
31 | struct mmc_config cfg; | |
32 | struct mmc mmc; | |
33 | }; | |
34 | #endif | |
35 | ||
5dab81ce JC |
36 | /* Exynos implmentation specific drver private data */ |
37 | struct dwmci_exynos_priv_data { | |
3537ee87 JC |
38 | #ifdef CONFIG_DM_MMC |
39 | struct dwmci_host host; | |
40 | #endif | |
5dab81ce JC |
41 | u32 sdr_timing; |
42 | }; | |
d0ebbb8d | 43 | |
a082a2dd A |
44 | /* |
45 | * Function used as callback function to initialise the | |
46 | * CLKSEL register for every mmc channel. | |
47 | */ | |
d0ebbb8d JC |
48 | static void exynos_dwmci_clksel(struct dwmci_host *host) |
49 | { | |
5dab81ce JC |
50 | struct dwmci_exynos_priv_data *priv = host->priv; |
51 | ||
52 | dwmci_writel(host, DWMCI_CLKSEL, priv->sdr_timing); | |
a082a2dd | 53 | } |
d0ebbb8d | 54 | |
e3563f2e | 55 | unsigned int exynos_dwmci_get_clk(struct dwmci_host *host, uint freq) |
a082a2dd | 56 | { |
d3e016cc RS |
57 | unsigned long sclk; |
58 | int8_t clk_div; | |
59 | ||
60 | /* | |
61 | * Since SDCLKIN is divided inside controller by the DIVRATIO | |
62 | * value set in the CLKSEL register, we need to use the same output | |
63 | * clock value to calculate the CLKDIV value. | |
64 | * as per user manual:cclk_in = SDCLKIN / (DIVRATIO + 1) | |
65 | */ | |
66 | clk_div = ((dwmci_readl(host, DWMCI_CLKSEL) >> DWMCI_DIVRATIO_BIT) | |
67 | & DWMCI_DIVRATIO_MASK) + 1; | |
68 | sclk = get_mmc_clk(host->dev_index); | |
69 | ||
959198f7 JC |
70 | /* |
71 | * Assume to know divider value. | |
72 | * When clock unit is broken, need to set "host->div" | |
73 | */ | |
74 | return sclk / clk_div / (host->div + 1); | |
d0ebbb8d JC |
75 | } |
76 | ||
18ab6755 JC |
77 | static void exynos_dwmci_board_init(struct dwmci_host *host) |
78 | { | |
5dab81ce JC |
79 | struct dwmci_exynos_priv_data *priv = host->priv; |
80 | ||
18ab6755 JC |
81 | if (host->quirks & DWMCI_QUIRK_DISABLE_SMU) { |
82 | dwmci_writel(host, EMMCP_MPSBEGIN0, 0); | |
83 | dwmci_writel(host, EMMCP_SEND0, 0); | |
84 | dwmci_writel(host, EMMCP_CTRL0, | |
85 | MPSCTRL_SECURE_READ_BIT | | |
86 | MPSCTRL_SECURE_WRITE_BIT | | |
87 | MPSCTRL_NON_SECURE_READ_BIT | | |
88 | MPSCTRL_NON_SECURE_WRITE_BIT | MPSCTRL_VALID); | |
89 | } | |
3a33bb18 | 90 | |
5dab81ce JC |
91 | /* Set to timing value at initial time */ |
92 | if (priv->sdr_timing) | |
3a33bb18 | 93 | exynos_dwmci_clksel(host); |
18ab6755 JC |
94 | } |
95 | ||
d956a67e | 96 | static int exynos_dwmci_core_init(struct dwmci_host *host) |
d0ebbb8d | 97 | { |
a082a2dd A |
98 | unsigned int div; |
99 | unsigned long freq, sclk; | |
959198f7 JC |
100 | |
101 | if (host->bus_hz) | |
102 | freq = host->bus_hz; | |
103 | else | |
104 | freq = DWMMC_MAX_FREQ; | |
105 | ||
a082a2dd | 106 | /* request mmc clock vlaue of 52MHz. */ |
d956a67e | 107 | sclk = get_mmc_clk(host->dev_index); |
a082a2dd A |
108 | div = DIV_ROUND_UP(sclk, freq); |
109 | /* set the clock divisor for mmc */ | |
d956a67e | 110 | set_mmc_clk(host->dev_index, div); |
d0ebbb8d | 111 | |
a082a2dd | 112 | host->name = "EXYNOS DWMMC"; |
6f0b7caa RS |
113 | #ifdef CONFIG_EXYNOS5420 |
114 | host->quirks = DWMCI_QUIRK_DISABLE_SMU; | |
115 | #endif | |
18ab6755 | 116 | host->board_init = exynos_dwmci_board_init; |
a082a2dd | 117 | |
e09bd853 | 118 | host->caps = MMC_MODE_DDR_52MHz; |
d0ebbb8d | 119 | host->clksel = exynos_dwmci_clksel; |
b44fe83a | 120 | host->get_mmc_clk = exynos_dwmci_get_clk; |
3537ee87 JC |
121 | |
122 | #ifndef CONFIG_DM_MMC | |
a082a2dd A |
123 | /* Add the mmc channel to be registered with mmc core */ |
124 | if (add_dwmci(host, DWMMC_MAX_FREQ, DWMMC_MIN_FREQ)) { | |
d956a67e | 125 | printf("DWMMC%d registration failed\n", host->dev_index); |
a082a2dd A |
126 | return -1; |
127 | } | |
3537ee87 JC |
128 | #endif |
129 | ||
a082a2dd A |
130 | return 0; |
131 | } | |
132 | ||
959198f7 JC |
133 | static struct dwmci_host dwmci_host[DWMMC_MAX_CH_NUM]; |
134 | ||
135 | static int do_dwmci_init(struct dwmci_host *host) | |
a082a2dd | 136 | { |
d956a67e | 137 | int flag, err; |
a082a2dd | 138 | |
959198f7 JC |
139 | flag = host->buswidth == 8 ? PINMUX_FLAG_8BIT_MODE : PINMUX_FLAG_NONE; |
140 | err = exynos_pinmux_config(host->dev_id, flag); | |
141 | if (err) { | |
d956a67e | 142 | printf("DWMMC%d not configure\n", host->dev_index); |
959198f7 JC |
143 | return err; |
144 | } | |
a082a2dd | 145 | |
d956a67e | 146 | return exynos_dwmci_core_init(host); |
959198f7 | 147 | } |
d0ebbb8d | 148 | |
959198f7 JC |
149 | static int exynos_dwmci_get_config(const void *blob, int node, |
150 | struct dwmci_host *host) | |
151 | { | |
152 | int err = 0; | |
5dab81ce JC |
153 | u32 base, timing[3]; |
154 | struct dwmci_exynos_priv_data *priv; | |
155 | ||
156 | priv = malloc(sizeof(struct dwmci_exynos_priv_data)); | |
157 | if (!priv) { | |
158 | error("dwmci_exynos_priv_data malloc fail!\n"); | |
159 | return -ENOMEM; | |
160 | } | |
d0ebbb8d | 161 | |
959198f7 JC |
162 | /* Extract device id for each mmc channel */ |
163 | host->dev_id = pinmux_decode_periph_id(blob, node); | |
a082a2dd | 164 | |
dfcb683a JC |
165 | host->dev_index = fdtdec_get_int(blob, node, "index", host->dev_id); |
166 | if (host->dev_index == host->dev_id) | |
167 | host->dev_index = host->dev_id - PERIPH_ID_SDMMC0; | |
168 | ||
ce757b18 JC |
169 | if (host->dev_index > 4) { |
170 | printf("DWMMC%d: Can't get the dev index\n", host->dev_index); | |
171 | return -EINVAL; | |
172 | } | |
173 | ||
70f6d394 JC |
174 | /* Get the bus width from the device node (Default is 4bit buswidth) */ |
175 | host->buswidth = fdtdec_get_int(blob, node, "samsung,bus-width", 4); | |
a082a2dd | 176 | |
959198f7 JC |
177 | /* Set the base address from the device node */ |
178 | base = fdtdec_get_addr(blob, node, "reg"); | |
179 | if (!base) { | |
dfcb683a | 180 | printf("DWMMC%d: Can't get base address\n", host->dev_index); |
959198f7 JC |
181 | return -EINVAL; |
182 | } | |
183 | host->ioaddr = (void *)base; | |
184 | ||
185 | /* Extract the timing info from the node */ | |
186 | err = fdtdec_get_int_array(blob, node, "samsung,timing", timing, 3); | |
187 | if (err) { | |
dfcb683a JC |
188 | printf("DWMMC%d: Can't get sdr-timings for devider\n", |
189 | host->dev_index); | |
959198f7 JC |
190 | return -EINVAL; |
191 | } | |
192 | ||
5dab81ce | 193 | priv->sdr_timing = (DWMCI_SET_SAMPLE_CLK(timing[0]) | |
959198f7 JC |
194 | DWMCI_SET_DRV_CLK(timing[1]) | |
195 | DWMCI_SET_DIV_RATIO(timing[2])); | |
5dab81ce JC |
196 | |
197 | /* sdr_timing didn't assigned anything, use the default value */ | |
198 | if (!priv->sdr_timing) { | |
199 | if (host->dev_index == 0) | |
200 | priv->sdr_timing = DWMMC_MMC0_SDR_TIMING_VAL; | |
201 | else if (host->dev_index == 2) | |
202 | priv->sdr_timing = DWMMC_MMC2_SDR_TIMING_VAL; | |
203 | } | |
959198f7 JC |
204 | |
205 | host->fifoth_val = fdtdec_get_int(blob, node, "fifoth_val", 0); | |
206 | host->bus_hz = fdtdec_get_int(blob, node, "bus_hz", 0); | |
207 | host->div = fdtdec_get_int(blob, node, "div", 0); | |
208 | ||
5dab81ce JC |
209 | host->priv = priv; |
210 | ||
959198f7 JC |
211 | return 0; |
212 | } | |
213 | ||
214 | static int exynos_dwmci_process_node(const void *blob, | |
215 | int node_list[], int count) | |
216 | { | |
217 | struct dwmci_host *host; | |
218 | int i, node, err; | |
219 | ||
220 | for (i = 0; i < count; i++) { | |
221 | node = node_list[i]; | |
222 | if (node <= 0) | |
223 | continue; | |
224 | host = &dwmci_host[i]; | |
225 | err = exynos_dwmci_get_config(blob, node, host); | |
a082a2dd | 226 | if (err) { |
dfcb683a | 227 | printf("%s: failed to decode dev %d\n", __func__, i); |
959198f7 | 228 | return err; |
a082a2dd A |
229 | } |
230 | ||
959198f7 | 231 | do_dwmci_init(host); |
a082a2dd | 232 | } |
d0ebbb8d JC |
233 | return 0; |
234 | } | |
959198f7 JC |
235 | |
236 | int exynos_dwmmc_init(const void *blob) | |
237 | { | |
959198f7 | 238 | int node_list[DWMMC_MAX_CH_NUM]; |
64029f7a | 239 | int boot_dev_node; |
959198f7 JC |
240 | int err = 0, count; |
241 | ||
959198f7 | 242 | count = fdtdec_find_aliases_for_id(blob, "mmc", |
d956a67e JC |
243 | COMPAT_SAMSUNG_EXYNOS_DWMMC, node_list, |
244 | DWMMC_MAX_CH_NUM); | |
64029f7a PM |
245 | |
246 | /* For DWMMC always set boot device as mmc 0 */ | |
247 | if (count >= 3 && get_boot_mode() == BOOT_MODE_SD) { | |
248 | boot_dev_node = node_list[2]; | |
249 | node_list[2] = node_list[0]; | |
250 | node_list[0] = boot_dev_node; | |
251 | } | |
252 | ||
959198f7 JC |
253 | err = exynos_dwmci_process_node(blob, node_list, count); |
254 | ||
255 | return err; | |
256 | } | |
3537ee87 JC |
257 | |
258 | #ifdef CONFIG_DM_MMC | |
259 | static int exynos_dwmmc_probe(struct udevice *dev) | |
260 | { | |
261 | struct exynos_mmc_plat *plat = dev_get_platdata(dev); | |
262 | struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev); | |
263 | struct dwmci_exynos_priv_data *priv = dev_get_priv(dev); | |
264 | struct dwmci_host *host = &priv->host; | |
265 | int err; | |
266 | ||
e160f7d4 | 267 | err = exynos_dwmci_get_config(gd->fdt_blob, dev_of_offset(dev), host); |
3537ee87 JC |
268 | if (err) |
269 | return err; | |
270 | err = do_dwmci_init(host); | |
271 | if (err) | |
272 | return err; | |
273 | ||
e5113c33 | 274 | dwmci_setup_cfg(&plat->cfg, host, DWMMC_MAX_FREQ, DWMMC_MIN_FREQ); |
3537ee87 JC |
275 | host->mmc = &plat->mmc; |
276 | host->mmc->priv = &priv->host; | |
277 | host->priv = dev; | |
278 | upriv->mmc = host->mmc; | |
279 | ||
280 | return dwmci_probe(dev); | |
281 | } | |
282 | ||
283 | static int exynos_dwmmc_bind(struct udevice *dev) | |
284 | { | |
285 | struct exynos_mmc_plat *plat = dev_get_platdata(dev); | |
3537ee87 | 286 | |
24f5aec3 | 287 | return dwmci_bind(dev, &plat->mmc, &plat->cfg); |
3537ee87 JC |
288 | } |
289 | ||
290 | static const struct udevice_id exynos_dwmmc_ids[] = { | |
291 | { .compatible = "samsung,exynos4412-dw-mshc" }, | |
292 | { } | |
293 | }; | |
294 | ||
295 | U_BOOT_DRIVER(exynos_dwmmc_drv) = { | |
296 | .name = "exynos_dwmmc", | |
297 | .id = UCLASS_MMC, | |
298 | .of_match = exynos_dwmmc_ids, | |
299 | .bind = exynos_dwmmc_bind, | |
300 | .ops = &dm_dwmci_ops, | |
301 | .probe = exynos_dwmmc_probe, | |
302 | .priv_auto_alloc_size = sizeof(struct dwmci_exynos_priv_data), | |
303 | .platdata_auto_alloc_size = sizeof(struct exynos_mmc_plat), | |
304 | }; | |
305 | #endif |