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Commit | Line | Data |
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272cc70b AF |
1 | /* |
2 | * Copyright 2008, Freescale Semiconductor, Inc | |
3 | * Andy Fleming | |
4 | * | |
5 | * Based vaguely on the Linux code | |
6 | * | |
1a459660 | 7 | * SPDX-License-Identifier: GPL-2.0+ |
272cc70b AF |
8 | */ |
9 | ||
10 | #include <config.h> | |
11 | #include <common.h> | |
12 | #include <command.h> | |
8e3332e2 SS |
13 | #include <dm.h> |
14 | #include <dm/device-internal.h> | |
d4622df3 | 15 | #include <errno.h> |
272cc70b AF |
16 | #include <mmc.h> |
17 | #include <part.h> | |
18 | #include <malloc.h> | |
19 | #include <linux/list.h> | |
9b1f942c | 20 | #include <div64.h> |
da61fa5f | 21 | #include "mmc_private.h" |
272cc70b AF |
22 | |
23 | static struct list_head mmc_devices; | |
24 | static int cur_dev_num = -1; | |
25 | ||
750121c3 | 26 | __weak int board_mmc_getwp(struct mmc *mmc) |
d23d8d7e NK |
27 | { |
28 | return -1; | |
29 | } | |
30 | ||
31 | int mmc_getwp(struct mmc *mmc) | |
32 | { | |
33 | int wp; | |
34 | ||
35 | wp = board_mmc_getwp(mmc); | |
36 | ||
d4e1da4e | 37 | if (wp < 0) { |
93bfd616 PA |
38 | if (mmc->cfg->ops->getwp) |
39 | wp = mmc->cfg->ops->getwp(mmc); | |
d4e1da4e PK |
40 | else |
41 | wp = 0; | |
42 | } | |
d23d8d7e NK |
43 | |
44 | return wp; | |
45 | } | |
46 | ||
cee9ab7c JH |
47 | __weak int board_mmc_getcd(struct mmc *mmc) |
48 | { | |
11fdade2 SB |
49 | return -1; |
50 | } | |
51 | ||
da61fa5f | 52 | int mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data) |
272cc70b | 53 | { |
5db2fe3a | 54 | int ret; |
8635ff9e | 55 | |
8635ff9e | 56 | #ifdef CONFIG_MMC_TRACE |
5db2fe3a RR |
57 | int i; |
58 | u8 *ptr; | |
59 | ||
60 | printf("CMD_SEND:%d\n", cmd->cmdidx); | |
61 | printf("\t\tARG\t\t\t 0x%08X\n", cmd->cmdarg); | |
93bfd616 | 62 | ret = mmc->cfg->ops->send_cmd(mmc, cmd, data); |
5db2fe3a RR |
63 | switch (cmd->resp_type) { |
64 | case MMC_RSP_NONE: | |
65 | printf("\t\tMMC_RSP_NONE\n"); | |
66 | break; | |
67 | case MMC_RSP_R1: | |
68 | printf("\t\tMMC_RSP_R1,5,6,7 \t 0x%08X \n", | |
69 | cmd->response[0]); | |
70 | break; | |
71 | case MMC_RSP_R1b: | |
72 | printf("\t\tMMC_RSP_R1b\t\t 0x%08X \n", | |
73 | cmd->response[0]); | |
74 | break; | |
75 | case MMC_RSP_R2: | |
76 | printf("\t\tMMC_RSP_R2\t\t 0x%08X \n", | |
77 | cmd->response[0]); | |
78 | printf("\t\t \t\t 0x%08X \n", | |
79 | cmd->response[1]); | |
80 | printf("\t\t \t\t 0x%08X \n", | |
81 | cmd->response[2]); | |
82 | printf("\t\t \t\t 0x%08X \n", | |
83 | cmd->response[3]); | |
84 | printf("\n"); | |
85 | printf("\t\t\t\t\tDUMPING DATA\n"); | |
86 | for (i = 0; i < 4; i++) { | |
87 | int j; | |
88 | printf("\t\t\t\t\t%03d - ", i*4); | |
146bec79 | 89 | ptr = (u8 *)&cmd->response[i]; |
5db2fe3a RR |
90 | ptr += 3; |
91 | for (j = 0; j < 4; j++) | |
92 | printf("%02X ", *ptr--); | |
93 | printf("\n"); | |
94 | } | |
95 | break; | |
96 | case MMC_RSP_R3: | |
97 | printf("\t\tMMC_RSP_R3,4\t\t 0x%08X \n", | |
98 | cmd->response[0]); | |
99 | break; | |
100 | default: | |
101 | printf("\t\tERROR MMC rsp not supported\n"); | |
102 | break; | |
103 | } | |
5db2fe3a | 104 | #else |
93bfd616 | 105 | ret = mmc->cfg->ops->send_cmd(mmc, cmd, data); |
5db2fe3a | 106 | #endif |
8635ff9e | 107 | return ret; |
272cc70b AF |
108 | } |
109 | ||
da61fa5f | 110 | int mmc_send_status(struct mmc *mmc, int timeout) |
5d4fc8d9 RR |
111 | { |
112 | struct mmc_cmd cmd; | |
d617c426 | 113 | int err, retries = 5; |
5d4fc8d9 RR |
114 | #ifdef CONFIG_MMC_TRACE |
115 | int status; | |
116 | #endif | |
117 | ||
118 | cmd.cmdidx = MMC_CMD_SEND_STATUS; | |
119 | cmd.resp_type = MMC_RSP_R1; | |
aaf3d41a MV |
120 | if (!mmc_host_is_spi(mmc)) |
121 | cmd.cmdarg = mmc->rca << 16; | |
5d4fc8d9 | 122 | |
1677eef4 | 123 | while (1) { |
5d4fc8d9 | 124 | err = mmc_send_cmd(mmc, &cmd, NULL); |
d617c426 JK |
125 | if (!err) { |
126 | if ((cmd.response[0] & MMC_STATUS_RDY_FOR_DATA) && | |
127 | (cmd.response[0] & MMC_STATUS_CURR_STATE) != | |
128 | MMC_STATE_PRG) | |
129 | break; | |
130 | else if (cmd.response[0] & MMC_STATUS_MASK) { | |
56196826 | 131 | #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT) |
d617c426 JK |
132 | printf("Status Error: 0x%08X\n", |
133 | cmd.response[0]); | |
56196826 | 134 | #endif |
d617c426 JK |
135 | return COMM_ERR; |
136 | } | |
137 | } else if (--retries < 0) | |
5d4fc8d9 | 138 | return err; |
5d4fc8d9 | 139 | |
1677eef4 AG |
140 | if (timeout-- <= 0) |
141 | break; | |
5d4fc8d9 | 142 | |
1677eef4 AG |
143 | udelay(1000); |
144 | } | |
5d4fc8d9 | 145 | |
5db2fe3a RR |
146 | #ifdef CONFIG_MMC_TRACE |
147 | status = (cmd.response[0] & MMC_STATUS_CURR_STATE) >> 9; | |
148 | printf("CURR STATE:%d\n", status); | |
149 | #endif | |
5b0c942f | 150 | if (timeout <= 0) { |
56196826 | 151 | #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT) |
5d4fc8d9 | 152 | printf("Timeout waiting card ready\n"); |
56196826 | 153 | #endif |
5d4fc8d9 RR |
154 | return TIMEOUT; |
155 | } | |
6b2221b0 AG |
156 | if (cmd.response[0] & MMC_STATUS_SWITCH_ERROR) |
157 | return SWITCH_ERR; | |
5d4fc8d9 RR |
158 | |
159 | return 0; | |
160 | } | |
161 | ||
da61fa5f | 162 | int mmc_set_blocklen(struct mmc *mmc, int len) |
272cc70b AF |
163 | { |
164 | struct mmc_cmd cmd; | |
165 | ||
786e8f81 | 166 | if (mmc->ddr_mode) |
d22e3d46 JC |
167 | return 0; |
168 | ||
272cc70b AF |
169 | cmd.cmdidx = MMC_CMD_SET_BLOCKLEN; |
170 | cmd.resp_type = MMC_RSP_R1; | |
171 | cmd.cmdarg = len; | |
272cc70b AF |
172 | |
173 | return mmc_send_cmd(mmc, &cmd, NULL); | |
174 | } | |
175 | ||
176 | struct mmc *find_mmc_device(int dev_num) | |
177 | { | |
178 | struct mmc *m; | |
179 | struct list_head *entry; | |
180 | ||
181 | list_for_each(entry, &mmc_devices) { | |
182 | m = list_entry(entry, struct mmc, link); | |
183 | ||
184 | if (m->block_dev.dev == dev_num) | |
185 | return m; | |
186 | } | |
187 | ||
56196826 | 188 | #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT) |
272cc70b | 189 | printf("MMC Device %d not found\n", dev_num); |
56196826 | 190 | #endif |
272cc70b AF |
191 | |
192 | return NULL; | |
193 | } | |
194 | ||
ff8fef56 | 195 | static int mmc_read_blocks(struct mmc *mmc, void *dst, lbaint_t start, |
fdbb873e | 196 | lbaint_t blkcnt) |
272cc70b AF |
197 | { |
198 | struct mmc_cmd cmd; | |
199 | struct mmc_data data; | |
200 | ||
4a1a06bc AS |
201 | if (blkcnt > 1) |
202 | cmd.cmdidx = MMC_CMD_READ_MULTIPLE_BLOCK; | |
203 | else | |
204 | cmd.cmdidx = MMC_CMD_READ_SINGLE_BLOCK; | |
272cc70b AF |
205 | |
206 | if (mmc->high_capacity) | |
4a1a06bc | 207 | cmd.cmdarg = start; |
272cc70b | 208 | else |
4a1a06bc | 209 | cmd.cmdarg = start * mmc->read_bl_len; |
272cc70b AF |
210 | |
211 | cmd.resp_type = MMC_RSP_R1; | |
272cc70b AF |
212 | |
213 | data.dest = dst; | |
4a1a06bc | 214 | data.blocks = blkcnt; |
272cc70b AF |
215 | data.blocksize = mmc->read_bl_len; |
216 | data.flags = MMC_DATA_READ; | |
217 | ||
4a1a06bc AS |
218 | if (mmc_send_cmd(mmc, &cmd, &data)) |
219 | return 0; | |
272cc70b | 220 | |
4a1a06bc AS |
221 | if (blkcnt > 1) { |
222 | cmd.cmdidx = MMC_CMD_STOP_TRANSMISSION; | |
223 | cmd.cmdarg = 0; | |
224 | cmd.resp_type = MMC_RSP_R1b; | |
4a1a06bc | 225 | if (mmc_send_cmd(mmc, &cmd, NULL)) { |
56196826 | 226 | #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT) |
4a1a06bc | 227 | printf("mmc fail to send stop cmd\n"); |
56196826 | 228 | #endif |
4a1a06bc AS |
229 | return 0; |
230 | } | |
272cc70b AF |
231 | } |
232 | ||
4a1a06bc | 233 | return blkcnt; |
272cc70b AF |
234 | } |
235 | ||
ff8fef56 | 236 | static ulong mmc_bread(int dev_num, lbaint_t start, lbaint_t blkcnt, void *dst) |
272cc70b | 237 | { |
4a1a06bc AS |
238 | lbaint_t cur, blocks_todo = blkcnt; |
239 | ||
240 | if (blkcnt == 0) | |
241 | return 0; | |
272cc70b | 242 | |
4a1a06bc | 243 | struct mmc *mmc = find_mmc_device(dev_num); |
272cc70b AF |
244 | if (!mmc) |
245 | return 0; | |
246 | ||
d2bf29e3 | 247 | if ((start + blkcnt) > mmc->block_dev.lba) { |
56196826 | 248 | #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT) |
ff8fef56 | 249 | printf("MMC: block number 0x" LBAF " exceeds max(0x" LBAF ")\n", |
d2bf29e3 | 250 | start + blkcnt, mmc->block_dev.lba); |
56196826 | 251 | #endif |
d2bf29e3 LW |
252 | return 0; |
253 | } | |
272cc70b | 254 | |
11692991 SG |
255 | if (mmc_set_blocklen(mmc, mmc->read_bl_len)) { |
256 | debug("%s: Failed to set blocklen\n", __func__); | |
272cc70b | 257 | return 0; |
11692991 | 258 | } |
272cc70b | 259 | |
4a1a06bc | 260 | do { |
93bfd616 PA |
261 | cur = (blocks_todo > mmc->cfg->b_max) ? |
262 | mmc->cfg->b_max : blocks_todo; | |
11692991 SG |
263 | if (mmc_read_blocks(mmc, dst, start, cur) != cur) { |
264 | debug("%s: Failed to read blocks\n", __func__); | |
4a1a06bc | 265 | return 0; |
11692991 | 266 | } |
4a1a06bc AS |
267 | blocks_todo -= cur; |
268 | start += cur; | |
269 | dst += cur * mmc->read_bl_len; | |
270 | } while (blocks_todo > 0); | |
272cc70b AF |
271 | |
272 | return blkcnt; | |
273 | } | |
274 | ||
fdbb873e | 275 | static int mmc_go_idle(struct mmc *mmc) |
272cc70b AF |
276 | { |
277 | struct mmc_cmd cmd; | |
278 | int err; | |
279 | ||
280 | udelay(1000); | |
281 | ||
282 | cmd.cmdidx = MMC_CMD_GO_IDLE_STATE; | |
283 | cmd.cmdarg = 0; | |
284 | cmd.resp_type = MMC_RSP_NONE; | |
272cc70b AF |
285 | |
286 | err = mmc_send_cmd(mmc, &cmd, NULL); | |
287 | ||
288 | if (err) | |
289 | return err; | |
290 | ||
291 | udelay(2000); | |
292 | ||
293 | return 0; | |
294 | } | |
295 | ||
fdbb873e | 296 | static int sd_send_op_cond(struct mmc *mmc) |
272cc70b AF |
297 | { |
298 | int timeout = 1000; | |
299 | int err; | |
300 | struct mmc_cmd cmd; | |
301 | ||
1677eef4 | 302 | while (1) { |
272cc70b AF |
303 | cmd.cmdidx = MMC_CMD_APP_CMD; |
304 | cmd.resp_type = MMC_RSP_R1; | |
305 | cmd.cmdarg = 0; | |
272cc70b AF |
306 | |
307 | err = mmc_send_cmd(mmc, &cmd, NULL); | |
308 | ||
309 | if (err) | |
310 | return err; | |
311 | ||
312 | cmd.cmdidx = SD_CMD_APP_SEND_OP_COND; | |
313 | cmd.resp_type = MMC_RSP_R3; | |
250de12b SB |
314 | |
315 | /* | |
316 | * Most cards do not answer if some reserved bits | |
317 | * in the ocr are set. However, Some controller | |
318 | * can set bit 7 (reserved for low voltages), but | |
319 | * how to manage low voltages SD card is not yet | |
320 | * specified. | |
321 | */ | |
d52ebf10 | 322 | cmd.cmdarg = mmc_host_is_spi(mmc) ? 0 : |
93bfd616 | 323 | (mmc->cfg->voltages & 0xff8000); |
272cc70b AF |
324 | |
325 | if (mmc->version == SD_VERSION_2) | |
326 | cmd.cmdarg |= OCR_HCS; | |
327 | ||
328 | err = mmc_send_cmd(mmc, &cmd, NULL); | |
329 | ||
330 | if (err) | |
331 | return err; | |
332 | ||
1677eef4 AG |
333 | if (cmd.response[0] & OCR_BUSY) |
334 | break; | |
335 | ||
336 | if (timeout-- <= 0) | |
337 | return UNUSABLE_ERR; | |
272cc70b | 338 | |
1677eef4 AG |
339 | udelay(1000); |
340 | } | |
272cc70b AF |
341 | |
342 | if (mmc->version != SD_VERSION_2) | |
343 | mmc->version = SD_VERSION_1_0; | |
344 | ||
d52ebf10 TC |
345 | if (mmc_host_is_spi(mmc)) { /* read OCR for spi */ |
346 | cmd.cmdidx = MMC_CMD_SPI_READ_OCR; | |
347 | cmd.resp_type = MMC_RSP_R3; | |
348 | cmd.cmdarg = 0; | |
d52ebf10 TC |
349 | |
350 | err = mmc_send_cmd(mmc, &cmd, NULL); | |
351 | ||
352 | if (err) | |
353 | return err; | |
354 | } | |
355 | ||
998be3dd | 356 | mmc->ocr = cmd.response[0]; |
272cc70b AF |
357 | |
358 | mmc->high_capacity = ((mmc->ocr & OCR_HCS) == OCR_HCS); | |
359 | mmc->rca = 0; | |
360 | ||
361 | return 0; | |
362 | } | |
363 | ||
5289b535 | 364 | static int mmc_send_op_cond_iter(struct mmc *mmc, int use_arg) |
272cc70b | 365 | { |
5289b535 | 366 | struct mmc_cmd cmd; |
272cc70b AF |
367 | int err; |
368 | ||
5289b535 AG |
369 | cmd.cmdidx = MMC_CMD_SEND_OP_COND; |
370 | cmd.resp_type = MMC_RSP_R3; | |
371 | cmd.cmdarg = 0; | |
5a20397b RH |
372 | if (use_arg && !mmc_host_is_spi(mmc)) |
373 | cmd.cmdarg = OCR_HCS | | |
93bfd616 | 374 | (mmc->cfg->voltages & |
a626c8d4 AG |
375 | (mmc->ocr & OCR_VOLTAGE_MASK)) | |
376 | (mmc->ocr & OCR_ACCESS_MODE); | |
e9550449 | 377 | |
5289b535 | 378 | err = mmc_send_cmd(mmc, &cmd, NULL); |
e9550449 CLC |
379 | if (err) |
380 | return err; | |
5289b535 | 381 | mmc->ocr = cmd.response[0]; |
e9550449 CLC |
382 | return 0; |
383 | } | |
384 | ||
750121c3 | 385 | static int mmc_send_op_cond(struct mmc *mmc) |
e9550449 | 386 | { |
e9550449 CLC |
387 | int err, i; |
388 | ||
272cc70b AF |
389 | /* Some cards seem to need this */ |
390 | mmc_go_idle(mmc); | |
391 | ||
31cacbab | 392 | /* Asking to the card its capabilities */ |
e9550449 | 393 | for (i = 0; i < 2; i++) { |
5289b535 | 394 | err = mmc_send_op_cond_iter(mmc, i != 0); |
e9550449 CLC |
395 | if (err) |
396 | return err; | |
cd6881b5 | 397 | |
e9550449 | 398 | /* exit if not busy (flag seems to be inverted) */ |
a626c8d4 | 399 | if (mmc->ocr & OCR_BUSY) |
bd47c135 | 400 | break; |
e9550449 | 401 | } |
bd47c135 AG |
402 | mmc->op_cond_pending = 1; |
403 | return 0; | |
e9550449 | 404 | } |
cd6881b5 | 405 | |
750121c3 | 406 | static int mmc_complete_op_cond(struct mmc *mmc) |
e9550449 CLC |
407 | { |
408 | struct mmc_cmd cmd; | |
409 | int timeout = 1000; | |
410 | uint start; | |
411 | int err; | |
cd6881b5 | 412 | |
e9550449 | 413 | mmc->op_cond_pending = 0; |
cc17c01f AG |
414 | if (!(mmc->ocr & OCR_BUSY)) { |
415 | start = get_timer(0); | |
1677eef4 | 416 | while (1) { |
cc17c01f AG |
417 | err = mmc_send_op_cond_iter(mmc, 1); |
418 | if (err) | |
419 | return err; | |
1677eef4 AG |
420 | if (mmc->ocr & OCR_BUSY) |
421 | break; | |
cc17c01f AG |
422 | if (get_timer(start) > timeout) |
423 | return UNUSABLE_ERR; | |
424 | udelay(100); | |
1677eef4 | 425 | } |
cc17c01f | 426 | } |
272cc70b | 427 | |
d52ebf10 TC |
428 | if (mmc_host_is_spi(mmc)) { /* read OCR for spi */ |
429 | cmd.cmdidx = MMC_CMD_SPI_READ_OCR; | |
430 | cmd.resp_type = MMC_RSP_R3; | |
431 | cmd.cmdarg = 0; | |
d52ebf10 TC |
432 | |
433 | err = mmc_send_cmd(mmc, &cmd, NULL); | |
434 | ||
435 | if (err) | |
436 | return err; | |
a626c8d4 AG |
437 | |
438 | mmc->ocr = cmd.response[0]; | |
d52ebf10 TC |
439 | } |
440 | ||
272cc70b | 441 | mmc->version = MMC_VERSION_UNKNOWN; |
272cc70b AF |
442 | |
443 | mmc->high_capacity = ((mmc->ocr & OCR_HCS) == OCR_HCS); | |
def816a2 | 444 | mmc->rca = 1; |
272cc70b AF |
445 | |
446 | return 0; | |
447 | } | |
448 | ||
449 | ||
fdbb873e | 450 | static int mmc_send_ext_csd(struct mmc *mmc, u8 *ext_csd) |
272cc70b AF |
451 | { |
452 | struct mmc_cmd cmd; | |
453 | struct mmc_data data; | |
454 | int err; | |
455 | ||
456 | /* Get the Card Status Register */ | |
457 | cmd.cmdidx = MMC_CMD_SEND_EXT_CSD; | |
458 | cmd.resp_type = MMC_RSP_R1; | |
459 | cmd.cmdarg = 0; | |
272cc70b | 460 | |
cdfd1ac6 | 461 | data.dest = (char *)ext_csd; |
272cc70b | 462 | data.blocks = 1; |
8bfa195e | 463 | data.blocksize = MMC_MAX_BLOCK_LEN; |
272cc70b AF |
464 | data.flags = MMC_DATA_READ; |
465 | ||
466 | err = mmc_send_cmd(mmc, &cmd, &data); | |
467 | ||
468 | return err; | |
469 | } | |
470 | ||
471 | ||
fdbb873e | 472 | static int mmc_switch(struct mmc *mmc, u8 set, u8 index, u8 value) |
272cc70b AF |
473 | { |
474 | struct mmc_cmd cmd; | |
5d4fc8d9 RR |
475 | int timeout = 1000; |
476 | int ret; | |
272cc70b AF |
477 | |
478 | cmd.cmdidx = MMC_CMD_SWITCH; | |
479 | cmd.resp_type = MMC_RSP_R1b; | |
480 | cmd.cmdarg = (MMC_SWITCH_MODE_WRITE_BYTE << 24) | | |
5d4fc8d9 RR |
481 | (index << 16) | |
482 | (value << 8); | |
272cc70b | 483 | |
5d4fc8d9 RR |
484 | ret = mmc_send_cmd(mmc, &cmd, NULL); |
485 | ||
486 | /* Waiting for the ready status */ | |
93ad0d18 JK |
487 | if (!ret) |
488 | ret = mmc_send_status(mmc, timeout); | |
5d4fc8d9 RR |
489 | |
490 | return ret; | |
491 | ||
272cc70b AF |
492 | } |
493 | ||
fdbb873e | 494 | static int mmc_change_freq(struct mmc *mmc) |
272cc70b | 495 | { |
8bfa195e | 496 | ALLOC_CACHE_ALIGN_BUFFER(u8, ext_csd, MMC_MAX_BLOCK_LEN); |
272cc70b AF |
497 | char cardtype; |
498 | int err; | |
499 | ||
fc5b32fb | 500 | mmc->card_caps = 0; |
272cc70b | 501 | |
d52ebf10 TC |
502 | if (mmc_host_is_spi(mmc)) |
503 | return 0; | |
504 | ||
272cc70b AF |
505 | /* Only version 4 supports high-speed */ |
506 | if (mmc->version < MMC_VERSION_4) | |
507 | return 0; | |
508 | ||
fc5b32fb AG |
509 | mmc->card_caps |= MMC_MODE_4BIT | MMC_MODE_8BIT; |
510 | ||
272cc70b AF |
511 | err = mmc_send_ext_csd(mmc, ext_csd); |
512 | ||
513 | if (err) | |
514 | return err; | |
515 | ||
0560db18 | 516 | cardtype = ext_csd[EXT_CSD_CARD_TYPE] & 0xf; |
272cc70b AF |
517 | |
518 | err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_HS_TIMING, 1); | |
519 | ||
520 | if (err) | |
6b2221b0 | 521 | return err == SWITCH_ERR ? 0 : err; |
272cc70b AF |
522 | |
523 | /* Now check to see that it worked */ | |
524 | err = mmc_send_ext_csd(mmc, ext_csd); | |
525 | ||
526 | if (err) | |
527 | return err; | |
528 | ||
529 | /* No high-speed support */ | |
0560db18 | 530 | if (!ext_csd[EXT_CSD_HS_TIMING]) |
272cc70b AF |
531 | return 0; |
532 | ||
533 | /* High Speed is set, there are two types: 52MHz and 26MHz */ | |
d22e3d46 | 534 | if (cardtype & EXT_CSD_CARD_TYPE_52) { |
201d5ac4 | 535 | if (cardtype & EXT_CSD_CARD_TYPE_DDR_1_8V) |
d22e3d46 | 536 | mmc->card_caps |= MMC_MODE_DDR_52MHz; |
272cc70b | 537 | mmc->card_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS; |
d22e3d46 | 538 | } else { |
272cc70b | 539 | mmc->card_caps |= MMC_MODE_HS; |
d22e3d46 | 540 | } |
272cc70b AF |
541 | |
542 | return 0; | |
543 | } | |
544 | ||
f866a46d SW |
545 | static int mmc_set_capacity(struct mmc *mmc, int part_num) |
546 | { | |
547 | switch (part_num) { | |
548 | case 0: | |
549 | mmc->capacity = mmc->capacity_user; | |
550 | break; | |
551 | case 1: | |
552 | case 2: | |
553 | mmc->capacity = mmc->capacity_boot; | |
554 | break; | |
555 | case 3: | |
556 | mmc->capacity = mmc->capacity_rpmb; | |
557 | break; | |
558 | case 4: | |
559 | case 5: | |
560 | case 6: | |
561 | case 7: | |
562 | mmc->capacity = mmc->capacity_gp[part_num - 4]; | |
563 | break; | |
564 | default: | |
565 | return -1; | |
566 | } | |
567 | ||
568 | mmc->block_dev.lba = lldiv(mmc->capacity, mmc->read_bl_len); | |
569 | ||
570 | return 0; | |
571 | } | |
572 | ||
d2356284 SW |
573 | int mmc_select_hwpart(int dev_num, int hwpart) |
574 | { | |
575 | struct mmc *mmc = find_mmc_device(dev_num); | |
576 | int ret; | |
577 | ||
578 | if (!mmc) | |
d4622df3 | 579 | return -ENODEV; |
d2356284 SW |
580 | |
581 | if (mmc->part_num == hwpart) | |
582 | return 0; | |
583 | ||
584 | if (mmc->part_config == MMCPART_NOAVAILABLE) { | |
585 | printf("Card doesn't support part_switch\n"); | |
d4622df3 | 586 | return -EMEDIUMTYPE; |
d2356284 SW |
587 | } |
588 | ||
589 | ret = mmc_switch_part(dev_num, hwpart); | |
590 | if (ret) | |
d4622df3 | 591 | return ret; |
d2356284 SW |
592 | |
593 | mmc->part_num = hwpart; | |
594 | ||
595 | return 0; | |
596 | } | |
597 | ||
598 | ||
bc897b1d LW |
599 | int mmc_switch_part(int dev_num, unsigned int part_num) |
600 | { | |
601 | struct mmc *mmc = find_mmc_device(dev_num); | |
f866a46d | 602 | int ret; |
bc897b1d LW |
603 | |
604 | if (!mmc) | |
605 | return -1; | |
606 | ||
f866a46d SW |
607 | ret = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_PART_CONF, |
608 | (mmc->part_config & ~PART_ACCESS_MASK) | |
609 | | (part_num & PART_ACCESS_MASK)); | |
f866a46d | 610 | |
6dc93e70 PB |
611 | /* |
612 | * Set the capacity if the switch succeeded or was intended | |
613 | * to return to representing the raw device. | |
614 | */ | |
615 | if ((ret == 0) || ((ret == -ENODEV) && (part_num == 0))) | |
616 | ret = mmc_set_capacity(mmc, part_num); | |
617 | ||
618 | return ret; | |
bc897b1d LW |
619 | } |
620 | ||
ac9da0e0 DSC |
621 | int mmc_hwpart_config(struct mmc *mmc, |
622 | const struct mmc_hwpart_conf *conf, | |
623 | enum mmc_hwpart_conf_mode mode) | |
624 | { | |
625 | u8 part_attrs = 0; | |
626 | u32 enh_size_mult; | |
627 | u32 enh_start_addr; | |
628 | u32 gp_size_mult[4]; | |
629 | u32 max_enh_size_mult; | |
630 | u32 tot_enh_size_mult = 0; | |
8dda5b0e | 631 | u8 wr_rel_set; |
ac9da0e0 DSC |
632 | int i, pidx, err; |
633 | ALLOC_CACHE_ALIGN_BUFFER(u8, ext_csd, MMC_MAX_BLOCK_LEN); | |
634 | ||
635 | if (mode < MMC_HWPART_CONF_CHECK || mode > MMC_HWPART_CONF_COMPLETE) | |
636 | return -EINVAL; | |
637 | ||
638 | if (IS_SD(mmc) || (mmc->version < MMC_VERSION_4_41)) { | |
639 | printf("eMMC >= 4.4 required for enhanced user data area\n"); | |
640 | return -EMEDIUMTYPE; | |
641 | } | |
642 | ||
643 | if (!(mmc->part_support & PART_SUPPORT)) { | |
644 | printf("Card does not support partitioning\n"); | |
645 | return -EMEDIUMTYPE; | |
646 | } | |
647 | ||
648 | if (!mmc->hc_wp_grp_size) { | |
649 | printf("Card does not define HC WP group size\n"); | |
650 | return -EMEDIUMTYPE; | |
651 | } | |
652 | ||
653 | /* check partition alignment and total enhanced size */ | |
654 | if (conf->user.enh_size) { | |
655 | if (conf->user.enh_size % mmc->hc_wp_grp_size || | |
656 | conf->user.enh_start % mmc->hc_wp_grp_size) { | |
657 | printf("User data enhanced area not HC WP group " | |
658 | "size aligned\n"); | |
659 | return -EINVAL; | |
660 | } | |
661 | part_attrs |= EXT_CSD_ENH_USR; | |
662 | enh_size_mult = conf->user.enh_size / mmc->hc_wp_grp_size; | |
663 | if (mmc->high_capacity) { | |
664 | enh_start_addr = conf->user.enh_start; | |
665 | } else { | |
666 | enh_start_addr = (conf->user.enh_start << 9); | |
667 | } | |
668 | } else { | |
669 | enh_size_mult = 0; | |
670 | enh_start_addr = 0; | |
671 | } | |
672 | tot_enh_size_mult += enh_size_mult; | |
673 | ||
674 | for (pidx = 0; pidx < 4; pidx++) { | |
675 | if (conf->gp_part[pidx].size % mmc->hc_wp_grp_size) { | |
676 | printf("GP%i partition not HC WP group size " | |
677 | "aligned\n", pidx+1); | |
678 | return -EINVAL; | |
679 | } | |
680 | gp_size_mult[pidx] = conf->gp_part[pidx].size / mmc->hc_wp_grp_size; | |
681 | if (conf->gp_part[pidx].size && conf->gp_part[pidx].enhanced) { | |
682 | part_attrs |= EXT_CSD_ENH_GP(pidx); | |
683 | tot_enh_size_mult += gp_size_mult[pidx]; | |
684 | } | |
685 | } | |
686 | ||
687 | if (part_attrs && ! (mmc->part_support & ENHNCD_SUPPORT)) { | |
688 | printf("Card does not support enhanced attribute\n"); | |
689 | return -EMEDIUMTYPE; | |
690 | } | |
691 | ||
692 | err = mmc_send_ext_csd(mmc, ext_csd); | |
693 | if (err) | |
694 | return err; | |
695 | ||
696 | max_enh_size_mult = | |
697 | (ext_csd[EXT_CSD_MAX_ENH_SIZE_MULT+2] << 16) + | |
698 | (ext_csd[EXT_CSD_MAX_ENH_SIZE_MULT+1] << 8) + | |
699 | ext_csd[EXT_CSD_MAX_ENH_SIZE_MULT]; | |
700 | if (tot_enh_size_mult > max_enh_size_mult) { | |
701 | printf("Total enhanced size exceeds maximum (%u > %u)\n", | |
702 | tot_enh_size_mult, max_enh_size_mult); | |
703 | return -EMEDIUMTYPE; | |
704 | } | |
705 | ||
8dda5b0e DSC |
706 | /* The default value of EXT_CSD_WR_REL_SET is device |
707 | * dependent, the values can only be changed if the | |
708 | * EXT_CSD_HS_CTRL_REL bit is set. The values can be | |
709 | * changed only once and before partitioning is completed. */ | |
710 | wr_rel_set = ext_csd[EXT_CSD_WR_REL_SET]; | |
711 | if (conf->user.wr_rel_change) { | |
712 | if (conf->user.wr_rel_set) | |
713 | wr_rel_set |= EXT_CSD_WR_DATA_REL_USR; | |
714 | else | |
715 | wr_rel_set &= ~EXT_CSD_WR_DATA_REL_USR; | |
716 | } | |
717 | for (pidx = 0; pidx < 4; pidx++) { | |
718 | if (conf->gp_part[pidx].wr_rel_change) { | |
719 | if (conf->gp_part[pidx].wr_rel_set) | |
720 | wr_rel_set |= EXT_CSD_WR_DATA_REL_GP(pidx); | |
721 | else | |
722 | wr_rel_set &= ~EXT_CSD_WR_DATA_REL_GP(pidx); | |
723 | } | |
724 | } | |
725 | ||
726 | if (wr_rel_set != ext_csd[EXT_CSD_WR_REL_SET] && | |
727 | !(ext_csd[EXT_CSD_WR_REL_PARAM] & EXT_CSD_HS_CTRL_REL)) { | |
728 | puts("Card does not support host controlled partition write " | |
729 | "reliability settings\n"); | |
730 | return -EMEDIUMTYPE; | |
731 | } | |
732 | ||
ac9da0e0 DSC |
733 | if (ext_csd[EXT_CSD_PARTITION_SETTING] & |
734 | EXT_CSD_PARTITION_SETTING_COMPLETED) { | |
735 | printf("Card already partitioned\n"); | |
736 | return -EPERM; | |
737 | } | |
738 | ||
739 | if (mode == MMC_HWPART_CONF_CHECK) | |
740 | return 0; | |
741 | ||
742 | /* Partitioning requires high-capacity size definitions */ | |
743 | if (!(ext_csd[EXT_CSD_ERASE_GROUP_DEF] & 0x01)) { | |
744 | err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, | |
745 | EXT_CSD_ERASE_GROUP_DEF, 1); | |
746 | ||
747 | if (err) | |
748 | return err; | |
749 | ||
750 | ext_csd[EXT_CSD_ERASE_GROUP_DEF] = 1; | |
751 | ||
752 | /* update erase group size to be high-capacity */ | |
753 | mmc->erase_grp_size = | |
754 | ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE] * 1024; | |
755 | ||
756 | } | |
757 | ||
758 | /* all OK, write the configuration */ | |
759 | for (i = 0; i < 4; i++) { | |
760 | err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, | |
761 | EXT_CSD_ENH_START_ADDR+i, | |
762 | (enh_start_addr >> (i*8)) & 0xFF); | |
763 | if (err) | |
764 | return err; | |
765 | } | |
766 | for (i = 0; i < 3; i++) { | |
767 | err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, | |
768 | EXT_CSD_ENH_SIZE_MULT+i, | |
769 | (enh_size_mult >> (i*8)) & 0xFF); | |
770 | if (err) | |
771 | return err; | |
772 | } | |
773 | for (pidx = 0; pidx < 4; pidx++) { | |
774 | for (i = 0; i < 3; i++) { | |
775 | err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, | |
776 | EXT_CSD_GP_SIZE_MULT+pidx*3+i, | |
777 | (gp_size_mult[pidx] >> (i*8)) & 0xFF); | |
778 | if (err) | |
779 | return err; | |
780 | } | |
781 | } | |
782 | err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, | |
783 | EXT_CSD_PARTITIONS_ATTRIBUTE, part_attrs); | |
784 | if (err) | |
785 | return err; | |
786 | ||
787 | if (mode == MMC_HWPART_CONF_SET) | |
788 | return 0; | |
789 | ||
8dda5b0e DSC |
790 | /* The WR_REL_SET is a write-once register but shall be |
791 | * written before setting PART_SETTING_COMPLETED. As it is | |
792 | * write-once we can only write it when completing the | |
793 | * partitioning. */ | |
794 | if (wr_rel_set != ext_csd[EXT_CSD_WR_REL_SET]) { | |
795 | err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, | |
796 | EXT_CSD_WR_REL_SET, wr_rel_set); | |
797 | if (err) | |
798 | return err; | |
799 | } | |
800 | ||
ac9da0e0 DSC |
801 | /* Setting PART_SETTING_COMPLETED confirms the partition |
802 | * configuration but it only becomes effective after power | |
803 | * cycle, so we do not adjust the partition related settings | |
804 | * in the mmc struct. */ | |
805 | ||
806 | err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, | |
807 | EXT_CSD_PARTITION_SETTING, | |
808 | EXT_CSD_PARTITION_SETTING_COMPLETED); | |
809 | if (err) | |
810 | return err; | |
811 | ||
812 | return 0; | |
813 | } | |
814 | ||
48972d90 TR |
815 | int mmc_getcd(struct mmc *mmc) |
816 | { | |
817 | int cd; | |
818 | ||
819 | cd = board_mmc_getcd(mmc); | |
820 | ||
d4e1da4e | 821 | if (cd < 0) { |
93bfd616 PA |
822 | if (mmc->cfg->ops->getcd) |
823 | cd = mmc->cfg->ops->getcd(mmc); | |
d4e1da4e PK |
824 | else |
825 | cd = 1; | |
826 | } | |
48972d90 TR |
827 | |
828 | return cd; | |
829 | } | |
830 | ||
fdbb873e | 831 | static int sd_switch(struct mmc *mmc, int mode, int group, u8 value, u8 *resp) |
272cc70b AF |
832 | { |
833 | struct mmc_cmd cmd; | |
834 | struct mmc_data data; | |
835 | ||
836 | /* Switch the frequency */ | |
837 | cmd.cmdidx = SD_CMD_SWITCH_FUNC; | |
838 | cmd.resp_type = MMC_RSP_R1; | |
839 | cmd.cmdarg = (mode << 31) | 0xffffff; | |
840 | cmd.cmdarg &= ~(0xf << (group * 4)); | |
841 | cmd.cmdarg |= value << (group * 4); | |
272cc70b AF |
842 | |
843 | data.dest = (char *)resp; | |
844 | data.blocksize = 64; | |
845 | data.blocks = 1; | |
846 | data.flags = MMC_DATA_READ; | |
847 | ||
848 | return mmc_send_cmd(mmc, &cmd, &data); | |
849 | } | |
850 | ||
851 | ||
fdbb873e | 852 | static int sd_change_freq(struct mmc *mmc) |
272cc70b AF |
853 | { |
854 | int err; | |
855 | struct mmc_cmd cmd; | |
f781dd38 A |
856 | ALLOC_CACHE_ALIGN_BUFFER(uint, scr, 2); |
857 | ALLOC_CACHE_ALIGN_BUFFER(uint, switch_status, 16); | |
272cc70b AF |
858 | struct mmc_data data; |
859 | int timeout; | |
860 | ||
861 | mmc->card_caps = 0; | |
862 | ||
d52ebf10 TC |
863 | if (mmc_host_is_spi(mmc)) |
864 | return 0; | |
865 | ||
272cc70b AF |
866 | /* Read the SCR to find out if this card supports higher speeds */ |
867 | cmd.cmdidx = MMC_CMD_APP_CMD; | |
868 | cmd.resp_type = MMC_RSP_R1; | |
869 | cmd.cmdarg = mmc->rca << 16; | |
272cc70b AF |
870 | |
871 | err = mmc_send_cmd(mmc, &cmd, NULL); | |
872 | ||
873 | if (err) | |
874 | return err; | |
875 | ||
876 | cmd.cmdidx = SD_CMD_APP_SEND_SCR; | |
877 | cmd.resp_type = MMC_RSP_R1; | |
878 | cmd.cmdarg = 0; | |
272cc70b AF |
879 | |
880 | timeout = 3; | |
881 | ||
882 | retry_scr: | |
f781dd38 | 883 | data.dest = (char *)scr; |
272cc70b AF |
884 | data.blocksize = 8; |
885 | data.blocks = 1; | |
886 | data.flags = MMC_DATA_READ; | |
887 | ||
888 | err = mmc_send_cmd(mmc, &cmd, &data); | |
889 | ||
890 | if (err) { | |
891 | if (timeout--) | |
892 | goto retry_scr; | |
893 | ||
894 | return err; | |
895 | } | |
896 | ||
4e3d89ba YK |
897 | mmc->scr[0] = __be32_to_cpu(scr[0]); |
898 | mmc->scr[1] = __be32_to_cpu(scr[1]); | |
272cc70b AF |
899 | |
900 | switch ((mmc->scr[0] >> 24) & 0xf) { | |
901 | case 0: | |
902 | mmc->version = SD_VERSION_1_0; | |
903 | break; | |
904 | case 1: | |
905 | mmc->version = SD_VERSION_1_10; | |
906 | break; | |
907 | case 2: | |
908 | mmc->version = SD_VERSION_2; | |
1741c64d JC |
909 | if ((mmc->scr[0] >> 15) & 0x1) |
910 | mmc->version = SD_VERSION_3; | |
272cc70b AF |
911 | break; |
912 | default: | |
913 | mmc->version = SD_VERSION_1_0; | |
914 | break; | |
915 | } | |
916 | ||
b44c7083 AS |
917 | if (mmc->scr[0] & SD_DATA_4BIT) |
918 | mmc->card_caps |= MMC_MODE_4BIT; | |
919 | ||
272cc70b AF |
920 | /* Version 1.0 doesn't support switching */ |
921 | if (mmc->version == SD_VERSION_1_0) | |
922 | return 0; | |
923 | ||
924 | timeout = 4; | |
925 | while (timeout--) { | |
926 | err = sd_switch(mmc, SD_SWITCH_CHECK, 0, 1, | |
f781dd38 | 927 | (u8 *)switch_status); |
272cc70b AF |
928 | |
929 | if (err) | |
930 | return err; | |
931 | ||
932 | /* The high-speed function is busy. Try again */ | |
4e3d89ba | 933 | if (!(__be32_to_cpu(switch_status[7]) & SD_HIGHSPEED_BUSY)) |
272cc70b AF |
934 | break; |
935 | } | |
936 | ||
272cc70b | 937 | /* If high-speed isn't supported, we return */ |
4e3d89ba | 938 | if (!(__be32_to_cpu(switch_status[3]) & SD_HIGHSPEED_SUPPORTED)) |
272cc70b AF |
939 | return 0; |
940 | ||
2c3fbf4c ML |
941 | /* |
942 | * If the host doesn't support SD_HIGHSPEED, do not switch card to | |
943 | * HIGHSPEED mode even if the card support SD_HIGHSPPED. | |
944 | * This can avoid furthur problem when the card runs in different | |
945 | * mode between the host. | |
946 | */ | |
93bfd616 PA |
947 | if (!((mmc->cfg->host_caps & MMC_MODE_HS_52MHz) && |
948 | (mmc->cfg->host_caps & MMC_MODE_HS))) | |
2c3fbf4c ML |
949 | return 0; |
950 | ||
f781dd38 | 951 | err = sd_switch(mmc, SD_SWITCH_SWITCH, 0, 1, (u8 *)switch_status); |
272cc70b AF |
952 | |
953 | if (err) | |
954 | return err; | |
955 | ||
4e3d89ba | 956 | if ((__be32_to_cpu(switch_status[4]) & 0x0f000000) == 0x01000000) |
272cc70b AF |
957 | mmc->card_caps |= MMC_MODE_HS; |
958 | ||
959 | return 0; | |
960 | } | |
961 | ||
962 | /* frequency bases */ | |
963 | /* divided by 10 to be nice to platforms without floating point */ | |
5f837c2c | 964 | static const int fbase[] = { |
272cc70b AF |
965 | 10000, |
966 | 100000, | |
967 | 1000000, | |
968 | 10000000, | |
969 | }; | |
970 | ||
971 | /* Multiplier values for TRAN_SPEED. Multiplied by 10 to be nice | |
972 | * to platforms without floating point. | |
973 | */ | |
5f837c2c | 974 | static const int multipliers[] = { |
272cc70b AF |
975 | 0, /* reserved */ |
976 | 10, | |
977 | 12, | |
978 | 13, | |
979 | 15, | |
980 | 20, | |
981 | 25, | |
982 | 30, | |
983 | 35, | |
984 | 40, | |
985 | 45, | |
986 | 50, | |
987 | 55, | |
988 | 60, | |
989 | 70, | |
990 | 80, | |
991 | }; | |
992 | ||
fdbb873e | 993 | static void mmc_set_ios(struct mmc *mmc) |
272cc70b | 994 | { |
93bfd616 PA |
995 | if (mmc->cfg->ops->set_ios) |
996 | mmc->cfg->ops->set_ios(mmc); | |
272cc70b AF |
997 | } |
998 | ||
999 | void mmc_set_clock(struct mmc *mmc, uint clock) | |
1000 | { | |
93bfd616 PA |
1001 | if (clock > mmc->cfg->f_max) |
1002 | clock = mmc->cfg->f_max; | |
272cc70b | 1003 | |
93bfd616 PA |
1004 | if (clock < mmc->cfg->f_min) |
1005 | clock = mmc->cfg->f_min; | |
272cc70b AF |
1006 | |
1007 | mmc->clock = clock; | |
1008 | ||
1009 | mmc_set_ios(mmc); | |
1010 | } | |
1011 | ||
fdbb873e | 1012 | static void mmc_set_bus_width(struct mmc *mmc, uint width) |
272cc70b AF |
1013 | { |
1014 | mmc->bus_width = width; | |
1015 | ||
1016 | mmc_set_ios(mmc); | |
1017 | } | |
1018 | ||
fdbb873e | 1019 | static int mmc_startup(struct mmc *mmc) |
272cc70b | 1020 | { |
f866a46d | 1021 | int err, i; |
272cc70b | 1022 | uint mult, freq; |
639b7827 | 1023 | u64 cmult, csize, capacity; |
272cc70b | 1024 | struct mmc_cmd cmd; |
8bfa195e SG |
1025 | ALLOC_CACHE_ALIGN_BUFFER(u8, ext_csd, MMC_MAX_BLOCK_LEN); |
1026 | ALLOC_CACHE_ALIGN_BUFFER(u8, test_csd, MMC_MAX_BLOCK_LEN); | |
5d4fc8d9 | 1027 | int timeout = 1000; |
0c453bb7 | 1028 | bool has_parts = false; |
8a0cf490 | 1029 | bool part_completed; |
272cc70b | 1030 | |
d52ebf10 TC |
1031 | #ifdef CONFIG_MMC_SPI_CRC_ON |
1032 | if (mmc_host_is_spi(mmc)) { /* enable CRC check for spi */ | |
1033 | cmd.cmdidx = MMC_CMD_SPI_CRC_ON_OFF; | |
1034 | cmd.resp_type = MMC_RSP_R1; | |
1035 | cmd.cmdarg = 1; | |
d52ebf10 TC |
1036 | err = mmc_send_cmd(mmc, &cmd, NULL); |
1037 | ||
1038 | if (err) | |
1039 | return err; | |
1040 | } | |
1041 | #endif | |
1042 | ||
272cc70b | 1043 | /* Put the Card in Identify Mode */ |
d52ebf10 TC |
1044 | cmd.cmdidx = mmc_host_is_spi(mmc) ? MMC_CMD_SEND_CID : |
1045 | MMC_CMD_ALL_SEND_CID; /* cmd not supported in spi */ | |
272cc70b AF |
1046 | cmd.resp_type = MMC_RSP_R2; |
1047 | cmd.cmdarg = 0; | |
272cc70b AF |
1048 | |
1049 | err = mmc_send_cmd(mmc, &cmd, NULL); | |
1050 | ||
1051 | if (err) | |
1052 | return err; | |
1053 | ||
1054 | memcpy(mmc->cid, cmd.response, 16); | |
1055 | ||
1056 | /* | |
1057 | * For MMC cards, set the Relative Address. | |
1058 | * For SD cards, get the Relatvie Address. | |
1059 | * This also puts the cards into Standby State | |
1060 | */ | |
d52ebf10 TC |
1061 | if (!mmc_host_is_spi(mmc)) { /* cmd not supported in spi */ |
1062 | cmd.cmdidx = SD_CMD_SEND_RELATIVE_ADDR; | |
1063 | cmd.cmdarg = mmc->rca << 16; | |
1064 | cmd.resp_type = MMC_RSP_R6; | |
272cc70b | 1065 | |
d52ebf10 | 1066 | err = mmc_send_cmd(mmc, &cmd, NULL); |
272cc70b | 1067 | |
d52ebf10 TC |
1068 | if (err) |
1069 | return err; | |
272cc70b | 1070 | |
d52ebf10 TC |
1071 | if (IS_SD(mmc)) |
1072 | mmc->rca = (cmd.response[0] >> 16) & 0xffff; | |
1073 | } | |
272cc70b AF |
1074 | |
1075 | /* Get the Card-Specific Data */ | |
1076 | cmd.cmdidx = MMC_CMD_SEND_CSD; | |
1077 | cmd.resp_type = MMC_RSP_R2; | |
1078 | cmd.cmdarg = mmc->rca << 16; | |
272cc70b AF |
1079 | |
1080 | err = mmc_send_cmd(mmc, &cmd, NULL); | |
1081 | ||
5d4fc8d9 RR |
1082 | /* Waiting for the ready status */ |
1083 | mmc_send_status(mmc, timeout); | |
1084 | ||
272cc70b AF |
1085 | if (err) |
1086 | return err; | |
1087 | ||
998be3dd RV |
1088 | mmc->csd[0] = cmd.response[0]; |
1089 | mmc->csd[1] = cmd.response[1]; | |
1090 | mmc->csd[2] = cmd.response[2]; | |
1091 | mmc->csd[3] = cmd.response[3]; | |
272cc70b AF |
1092 | |
1093 | if (mmc->version == MMC_VERSION_UNKNOWN) { | |
0b453ffe | 1094 | int version = (cmd.response[0] >> 26) & 0xf; |
272cc70b AF |
1095 | |
1096 | switch (version) { | |
1097 | case 0: | |
1098 | mmc->version = MMC_VERSION_1_2; | |
1099 | break; | |
1100 | case 1: | |
1101 | mmc->version = MMC_VERSION_1_4; | |
1102 | break; | |
1103 | case 2: | |
1104 | mmc->version = MMC_VERSION_2_2; | |
1105 | break; | |
1106 | case 3: | |
1107 | mmc->version = MMC_VERSION_3; | |
1108 | break; | |
1109 | case 4: | |
1110 | mmc->version = MMC_VERSION_4; | |
1111 | break; | |
1112 | default: | |
1113 | mmc->version = MMC_VERSION_1_2; | |
1114 | break; | |
1115 | } | |
1116 | } | |
1117 | ||
1118 | /* divide frequency by 10, since the mults are 10x bigger */ | |
0b453ffe RV |
1119 | freq = fbase[(cmd.response[0] & 0x7)]; |
1120 | mult = multipliers[((cmd.response[0] >> 3) & 0xf)]; | |
272cc70b AF |
1121 | |
1122 | mmc->tran_speed = freq * mult; | |
1123 | ||
ab71188c | 1124 | mmc->dsr_imp = ((cmd.response[1] >> 12) & 0x1); |
998be3dd | 1125 | mmc->read_bl_len = 1 << ((cmd.response[1] >> 16) & 0xf); |
272cc70b AF |
1126 | |
1127 | if (IS_SD(mmc)) | |
1128 | mmc->write_bl_len = mmc->read_bl_len; | |
1129 | else | |
998be3dd | 1130 | mmc->write_bl_len = 1 << ((cmd.response[3] >> 22) & 0xf); |
272cc70b AF |
1131 | |
1132 | if (mmc->high_capacity) { | |
1133 | csize = (mmc->csd[1] & 0x3f) << 16 | |
1134 | | (mmc->csd[2] & 0xffff0000) >> 16; | |
1135 | cmult = 8; | |
1136 | } else { | |
1137 | csize = (mmc->csd[1] & 0x3ff) << 2 | |
1138 | | (mmc->csd[2] & 0xc0000000) >> 30; | |
1139 | cmult = (mmc->csd[2] & 0x00038000) >> 15; | |
1140 | } | |
1141 | ||
f866a46d SW |
1142 | mmc->capacity_user = (csize + 1) << (cmult + 2); |
1143 | mmc->capacity_user *= mmc->read_bl_len; | |
1144 | mmc->capacity_boot = 0; | |
1145 | mmc->capacity_rpmb = 0; | |
1146 | for (i = 0; i < 4; i++) | |
1147 | mmc->capacity_gp[i] = 0; | |
272cc70b | 1148 | |
8bfa195e SG |
1149 | if (mmc->read_bl_len > MMC_MAX_BLOCK_LEN) |
1150 | mmc->read_bl_len = MMC_MAX_BLOCK_LEN; | |
272cc70b | 1151 | |
8bfa195e SG |
1152 | if (mmc->write_bl_len > MMC_MAX_BLOCK_LEN) |
1153 | mmc->write_bl_len = MMC_MAX_BLOCK_LEN; | |
272cc70b | 1154 | |
ab71188c MN |
1155 | if ((mmc->dsr_imp) && (0xffffffff != mmc->dsr)) { |
1156 | cmd.cmdidx = MMC_CMD_SET_DSR; | |
1157 | cmd.cmdarg = (mmc->dsr & 0xffff) << 16; | |
1158 | cmd.resp_type = MMC_RSP_NONE; | |
1159 | if (mmc_send_cmd(mmc, &cmd, NULL)) | |
1160 | printf("MMC: SET_DSR failed\n"); | |
1161 | } | |
1162 | ||
272cc70b | 1163 | /* Select the card, and put it into Transfer Mode */ |
d52ebf10 TC |
1164 | if (!mmc_host_is_spi(mmc)) { /* cmd not supported in spi */ |
1165 | cmd.cmdidx = MMC_CMD_SELECT_CARD; | |
fe8f7066 | 1166 | cmd.resp_type = MMC_RSP_R1; |
d52ebf10 | 1167 | cmd.cmdarg = mmc->rca << 16; |
d52ebf10 | 1168 | err = mmc_send_cmd(mmc, &cmd, NULL); |
272cc70b | 1169 | |
d52ebf10 TC |
1170 | if (err) |
1171 | return err; | |
1172 | } | |
272cc70b | 1173 | |
e6f99a56 LW |
1174 | /* |
1175 | * For SD, its erase group is always one sector | |
1176 | */ | |
1177 | mmc->erase_grp_size = 1; | |
bc897b1d | 1178 | mmc->part_config = MMCPART_NOAVAILABLE; |
d23e2c09 SG |
1179 | if (!IS_SD(mmc) && (mmc->version >= MMC_VERSION_4)) { |
1180 | /* check ext_csd version and capacity */ | |
1181 | err = mmc_send_ext_csd(mmc, ext_csd); | |
9cf199eb DSC |
1182 | if (err) |
1183 | return err; | |
1184 | if (ext_csd[EXT_CSD_REV] >= 2) { | |
639b7827 YS |
1185 | /* |
1186 | * According to the JEDEC Standard, the value of | |
1187 | * ext_csd's capacity is valid if the value is more | |
1188 | * than 2GB | |
1189 | */ | |
0560db18 LW |
1190 | capacity = ext_csd[EXT_CSD_SEC_CNT] << 0 |
1191 | | ext_csd[EXT_CSD_SEC_CNT + 1] << 8 | |
1192 | | ext_csd[EXT_CSD_SEC_CNT + 2] << 16 | |
1193 | | ext_csd[EXT_CSD_SEC_CNT + 3] << 24; | |
8bfa195e | 1194 | capacity *= MMC_MAX_BLOCK_LEN; |
b1f1e821 | 1195 | if ((capacity >> 20) > 2 * 1024) |
f866a46d | 1196 | mmc->capacity_user = capacity; |
d23e2c09 | 1197 | } |
bc897b1d | 1198 | |
64f4a619 JC |
1199 | switch (ext_csd[EXT_CSD_REV]) { |
1200 | case 1: | |
1201 | mmc->version = MMC_VERSION_4_1; | |
1202 | break; | |
1203 | case 2: | |
1204 | mmc->version = MMC_VERSION_4_2; | |
1205 | break; | |
1206 | case 3: | |
1207 | mmc->version = MMC_VERSION_4_3; | |
1208 | break; | |
1209 | case 5: | |
1210 | mmc->version = MMC_VERSION_4_41; | |
1211 | break; | |
1212 | case 6: | |
1213 | mmc->version = MMC_VERSION_4_5; | |
1214 | break; | |
edab723b MN |
1215 | case 7: |
1216 | mmc->version = MMC_VERSION_5_0; | |
1217 | break; | |
64f4a619 JC |
1218 | } |
1219 | ||
8a0cf490 DSC |
1220 | /* The partition data may be non-zero but it is only |
1221 | * effective if PARTITION_SETTING_COMPLETED is set in | |
1222 | * EXT_CSD, so ignore any data if this bit is not set, | |
1223 | * except for enabling the high-capacity group size | |
1224 | * definition (see below). */ | |
1225 | part_completed = !!(ext_csd[EXT_CSD_PARTITION_SETTING] & | |
1226 | EXT_CSD_PARTITION_SETTING_COMPLETED); | |
1227 | ||
0c453bb7 DSC |
1228 | /* store the partition info of emmc */ |
1229 | mmc->part_support = ext_csd[EXT_CSD_PARTITIONING_SUPPORT]; | |
1230 | if ((ext_csd[EXT_CSD_PARTITIONING_SUPPORT] & PART_SUPPORT) || | |
1231 | ext_csd[EXT_CSD_BOOT_MULT]) | |
1232 | mmc->part_config = ext_csd[EXT_CSD_PART_CONF]; | |
8a0cf490 DSC |
1233 | if (part_completed && |
1234 | (ext_csd[EXT_CSD_PARTITIONING_SUPPORT] & ENHNCD_SUPPORT)) | |
0c453bb7 DSC |
1235 | mmc->part_attr = ext_csd[EXT_CSD_PARTITIONS_ATTRIBUTE]; |
1236 | ||
1237 | mmc->capacity_boot = ext_csd[EXT_CSD_BOOT_MULT] << 17; | |
1238 | ||
1239 | mmc->capacity_rpmb = ext_csd[EXT_CSD_RPMB_MULT] << 17; | |
1240 | ||
1241 | for (i = 0; i < 4; i++) { | |
1242 | int idx = EXT_CSD_GP_SIZE_MULT + i * 3; | |
8a0cf490 | 1243 | uint mult = (ext_csd[idx + 2] << 16) + |
0c453bb7 | 1244 | (ext_csd[idx + 1] << 8) + ext_csd[idx]; |
8a0cf490 DSC |
1245 | if (mult) |
1246 | has_parts = true; | |
1247 | if (!part_completed) | |
1248 | continue; | |
1249 | mmc->capacity_gp[i] = mult; | |
0c453bb7 DSC |
1250 | mmc->capacity_gp[i] *= |
1251 | ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE]; | |
1252 | mmc->capacity_gp[i] *= ext_csd[EXT_CSD_HC_WP_GRP_SIZE]; | |
f8e89d67 | 1253 | mmc->capacity_gp[i] <<= 19; |
0c453bb7 DSC |
1254 | } |
1255 | ||
8a0cf490 DSC |
1256 | if (part_completed) { |
1257 | mmc->enh_user_size = | |
1258 | (ext_csd[EXT_CSD_ENH_SIZE_MULT+2] << 16) + | |
1259 | (ext_csd[EXT_CSD_ENH_SIZE_MULT+1] << 8) + | |
1260 | ext_csd[EXT_CSD_ENH_SIZE_MULT]; | |
1261 | mmc->enh_user_size *= ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE]; | |
1262 | mmc->enh_user_size *= ext_csd[EXT_CSD_HC_WP_GRP_SIZE]; | |
1263 | mmc->enh_user_size <<= 19; | |
1264 | mmc->enh_user_start = | |
1265 | (ext_csd[EXT_CSD_ENH_START_ADDR+3] << 24) + | |
1266 | (ext_csd[EXT_CSD_ENH_START_ADDR+2] << 16) + | |
1267 | (ext_csd[EXT_CSD_ENH_START_ADDR+1] << 8) + | |
1268 | ext_csd[EXT_CSD_ENH_START_ADDR]; | |
1269 | if (mmc->high_capacity) | |
1270 | mmc->enh_user_start <<= 9; | |
1271 | } | |
a7f852b6 | 1272 | |
e6f99a56 | 1273 | /* |
1937e5aa OM |
1274 | * Host needs to enable ERASE_GRP_DEF bit if device is |
1275 | * partitioned. This bit will be lost every time after a reset | |
1276 | * or power off. This will affect erase size. | |
e6f99a56 | 1277 | */ |
8a0cf490 | 1278 | if (part_completed) |
0c453bb7 | 1279 | has_parts = true; |
1937e5aa | 1280 | if ((ext_csd[EXT_CSD_PARTITIONING_SUPPORT] & PART_SUPPORT) && |
0c453bb7 DSC |
1281 | (ext_csd[EXT_CSD_PARTITIONS_ATTRIBUTE] & PART_ENH_ATTRIB)) |
1282 | has_parts = true; | |
1283 | if (has_parts) { | |
1937e5aa OM |
1284 | err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, |
1285 | EXT_CSD_ERASE_GROUP_DEF, 1); | |
1286 | ||
1287 | if (err) | |
1288 | return err; | |
021a8055 HP |
1289 | else |
1290 | ext_csd[EXT_CSD_ERASE_GROUP_DEF] = 1; | |
037dc0ab | 1291 | } |
1937e5aa | 1292 | |
037dc0ab | 1293 | if (ext_csd[EXT_CSD_ERASE_GROUP_DEF] & 0x01) { |
1937e5aa | 1294 | /* Read out group size from ext_csd */ |
0560db18 | 1295 | mmc->erase_grp_size = |
a4ff9f83 | 1296 | ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE] * 1024; |
d7b29129 MN |
1297 | /* |
1298 | * if high capacity and partition setting completed | |
1299 | * SEC_COUNT is valid even if it is smaller than 2 GiB | |
1300 | * JEDEC Standard JESD84-B45, 6.2.4 | |
1301 | */ | |
8a0cf490 | 1302 | if (mmc->high_capacity && part_completed) { |
d7b29129 MN |
1303 | capacity = (ext_csd[EXT_CSD_SEC_CNT]) | |
1304 | (ext_csd[EXT_CSD_SEC_CNT + 1] << 8) | | |
1305 | (ext_csd[EXT_CSD_SEC_CNT + 2] << 16) | | |
1306 | (ext_csd[EXT_CSD_SEC_CNT + 3] << 24); | |
1307 | capacity *= MMC_MAX_BLOCK_LEN; | |
1308 | mmc->capacity_user = capacity; | |
1309 | } | |
8bfa195e | 1310 | } else { |
1937e5aa | 1311 | /* Calculate the group size from the csd value. */ |
e6f99a56 LW |
1312 | int erase_gsz, erase_gmul; |
1313 | erase_gsz = (mmc->csd[2] & 0x00007c00) >> 10; | |
1314 | erase_gmul = (mmc->csd[2] & 0x000003e0) >> 5; | |
1315 | mmc->erase_grp_size = (erase_gsz + 1) | |
1316 | * (erase_gmul + 1); | |
1317 | } | |
037dc0ab DSC |
1318 | |
1319 | mmc->hc_wp_grp_size = 1024 | |
1320 | * ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE] | |
1321 | * ext_csd[EXT_CSD_HC_WP_GRP_SIZE]; | |
9e41a00b DSC |
1322 | |
1323 | mmc->wr_rel_set = ext_csd[EXT_CSD_WR_REL_SET]; | |
d23e2c09 SG |
1324 | } |
1325 | ||
f866a46d SW |
1326 | err = mmc_set_capacity(mmc, mmc->part_num); |
1327 | if (err) | |
1328 | return err; | |
1329 | ||
272cc70b AF |
1330 | if (IS_SD(mmc)) |
1331 | err = sd_change_freq(mmc); | |
1332 | else | |
1333 | err = mmc_change_freq(mmc); | |
1334 | ||
1335 | if (err) | |
1336 | return err; | |
1337 | ||
1338 | /* Restrict card's capabilities by what the host can do */ | |
93bfd616 | 1339 | mmc->card_caps &= mmc->cfg->host_caps; |
272cc70b AF |
1340 | |
1341 | if (IS_SD(mmc)) { | |
1342 | if (mmc->card_caps & MMC_MODE_4BIT) { | |
1343 | cmd.cmdidx = MMC_CMD_APP_CMD; | |
1344 | cmd.resp_type = MMC_RSP_R1; | |
1345 | cmd.cmdarg = mmc->rca << 16; | |
272cc70b AF |
1346 | |
1347 | err = mmc_send_cmd(mmc, &cmd, NULL); | |
1348 | if (err) | |
1349 | return err; | |
1350 | ||
1351 | cmd.cmdidx = SD_CMD_APP_SET_BUS_WIDTH; | |
1352 | cmd.resp_type = MMC_RSP_R1; | |
1353 | cmd.cmdarg = 2; | |
272cc70b AF |
1354 | err = mmc_send_cmd(mmc, &cmd, NULL); |
1355 | if (err) | |
1356 | return err; | |
1357 | ||
1358 | mmc_set_bus_width(mmc, 4); | |
1359 | } | |
1360 | ||
1361 | if (mmc->card_caps & MMC_MODE_HS) | |
ad5fd922 | 1362 | mmc->tran_speed = 50000000; |
272cc70b | 1363 | else |
ad5fd922 | 1364 | mmc->tran_speed = 25000000; |
fc5b32fb AG |
1365 | } else if (mmc->version >= MMC_VERSION_4) { |
1366 | /* Only version 4 of MMC supports wider bus widths */ | |
7798f6db AF |
1367 | int idx; |
1368 | ||
1369 | /* An array of possible bus widths in order of preference */ | |
1370 | static unsigned ext_csd_bits[] = { | |
d22e3d46 JC |
1371 | EXT_CSD_DDR_BUS_WIDTH_8, |
1372 | EXT_CSD_DDR_BUS_WIDTH_4, | |
7798f6db AF |
1373 | EXT_CSD_BUS_WIDTH_8, |
1374 | EXT_CSD_BUS_WIDTH_4, | |
1375 | EXT_CSD_BUS_WIDTH_1, | |
1376 | }; | |
1377 | ||
1378 | /* An array to map CSD bus widths to host cap bits */ | |
1379 | static unsigned ext_to_hostcaps[] = { | |
786e8f81 AG |
1380 | [EXT_CSD_DDR_BUS_WIDTH_4] = |
1381 | MMC_MODE_DDR_52MHz | MMC_MODE_4BIT, | |
1382 | [EXT_CSD_DDR_BUS_WIDTH_8] = | |
1383 | MMC_MODE_DDR_52MHz | MMC_MODE_8BIT, | |
7798f6db AF |
1384 | [EXT_CSD_BUS_WIDTH_4] = MMC_MODE_4BIT, |
1385 | [EXT_CSD_BUS_WIDTH_8] = MMC_MODE_8BIT, | |
1386 | }; | |
1387 | ||
1388 | /* An array to map chosen bus width to an integer */ | |
1389 | static unsigned widths[] = { | |
d22e3d46 | 1390 | 8, 4, 8, 4, 1, |
7798f6db AF |
1391 | }; |
1392 | ||
1393 | for (idx=0; idx < ARRAY_SIZE(ext_csd_bits); idx++) { | |
1394 | unsigned int extw = ext_csd_bits[idx]; | |
786e8f81 | 1395 | unsigned int caps = ext_to_hostcaps[extw]; |
7798f6db | 1396 | |
bf477073 AG |
1397 | /* |
1398 | * If the bus width is still not changed, | |
1399 | * don't try to set the default again. | |
1400 | * Otherwise, recover from switch attempts | |
1401 | * by switching to 1-bit bus width. | |
1402 | */ | |
1403 | if (extw == EXT_CSD_BUS_WIDTH_1 && | |
1404 | mmc->bus_width == 1) { | |
1405 | err = 0; | |
1406 | break; | |
1407 | } | |
1408 | ||
7798f6db | 1409 | /* |
786e8f81 AG |
1410 | * Check to make sure the card and controller support |
1411 | * these capabilities | |
7798f6db | 1412 | */ |
786e8f81 | 1413 | if ((mmc->card_caps & caps) != caps) |
7798f6db AF |
1414 | continue; |
1415 | ||
272cc70b | 1416 | err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, |
7798f6db | 1417 | EXT_CSD_BUS_WIDTH, extw); |
272cc70b AF |
1418 | |
1419 | if (err) | |
4137894e | 1420 | continue; |
272cc70b | 1421 | |
786e8f81 | 1422 | mmc->ddr_mode = (caps & MMC_MODE_DDR_52MHz) ? 1 : 0; |
7798f6db | 1423 | mmc_set_bus_width(mmc, widths[idx]); |
4137894e LW |
1424 | |
1425 | err = mmc_send_ext_csd(mmc, test_csd); | |
786e8f81 AG |
1426 | |
1427 | if (err) | |
1428 | continue; | |
1429 | ||
786a27b7 | 1430 | /* Only compare read only fields */ |
786e8f81 AG |
1431 | if (ext_csd[EXT_CSD_PARTITIONING_SUPPORT] |
1432 | == test_csd[EXT_CSD_PARTITIONING_SUPPORT] && | |
1433 | ext_csd[EXT_CSD_HC_WP_GRP_SIZE] | |
1434 | == test_csd[EXT_CSD_HC_WP_GRP_SIZE] && | |
1435 | ext_csd[EXT_CSD_REV] | |
1436 | == test_csd[EXT_CSD_REV] && | |
1437 | ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE] | |
1438 | == test_csd[EXT_CSD_HC_ERASE_GRP_SIZE] && | |
1439 | memcmp(&ext_csd[EXT_CSD_SEC_CNT], | |
1440 | &test_csd[EXT_CSD_SEC_CNT], 4) == 0) | |
4137894e | 1441 | break; |
786e8f81 AG |
1442 | else |
1443 | err = SWITCH_ERR; | |
272cc70b AF |
1444 | } |
1445 | ||
786e8f81 AG |
1446 | if (err) |
1447 | return err; | |
1448 | ||
272cc70b AF |
1449 | if (mmc->card_caps & MMC_MODE_HS) { |
1450 | if (mmc->card_caps & MMC_MODE_HS_52MHz) | |
ad5fd922 | 1451 | mmc->tran_speed = 52000000; |
272cc70b | 1452 | else |
ad5fd922 JC |
1453 | mmc->tran_speed = 26000000; |
1454 | } | |
272cc70b AF |
1455 | } |
1456 | ||
ad5fd922 JC |
1457 | mmc_set_clock(mmc, mmc->tran_speed); |
1458 | ||
5af8f45c AG |
1459 | /* Fix the block length for DDR mode */ |
1460 | if (mmc->ddr_mode) { | |
1461 | mmc->read_bl_len = MMC_MAX_BLOCK_LEN; | |
1462 | mmc->write_bl_len = MMC_MAX_BLOCK_LEN; | |
1463 | } | |
1464 | ||
272cc70b AF |
1465 | /* fill in device description */ |
1466 | mmc->block_dev.lun = 0; | |
1467 | mmc->block_dev.type = 0; | |
1468 | mmc->block_dev.blksz = mmc->read_bl_len; | |
0472fbfd | 1469 | mmc->block_dev.log2blksz = LOG2(mmc->block_dev.blksz); |
9b1f942c | 1470 | mmc->block_dev.lba = lldiv(mmc->capacity, mmc->read_bl_len); |
56196826 | 1471 | #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT) |
babce5f6 TH |
1472 | sprintf(mmc->block_dev.vendor, "Man %06x Snr %04x%04x", |
1473 | mmc->cid[0] >> 24, (mmc->cid[2] & 0xffff), | |
1474 | (mmc->cid[3] >> 16) & 0xffff); | |
1475 | sprintf(mmc->block_dev.product, "%c%c%c%c%c%c", mmc->cid[0] & 0xff, | |
1476 | (mmc->cid[1] >> 24), (mmc->cid[1] >> 16) & 0xff, | |
1477 | (mmc->cid[1] >> 8) & 0xff, mmc->cid[1] & 0xff, | |
1478 | (mmc->cid[2] >> 24) & 0xff); | |
1479 | sprintf(mmc->block_dev.revision, "%d.%d", (mmc->cid[2] >> 20) & 0xf, | |
1480 | (mmc->cid[2] >> 16) & 0xf); | |
56196826 PB |
1481 | #else |
1482 | mmc->block_dev.vendor[0] = 0; | |
1483 | mmc->block_dev.product[0] = 0; | |
1484 | mmc->block_dev.revision[0] = 0; | |
1485 | #endif | |
122efd43 | 1486 | #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBDISK_SUPPORT) |
272cc70b | 1487 | init_part(&mmc->block_dev); |
122efd43 | 1488 | #endif |
272cc70b AF |
1489 | |
1490 | return 0; | |
1491 | } | |
1492 | ||
fdbb873e | 1493 | static int mmc_send_if_cond(struct mmc *mmc) |
272cc70b AF |
1494 | { |
1495 | struct mmc_cmd cmd; | |
1496 | int err; | |
1497 | ||
1498 | cmd.cmdidx = SD_CMD_SEND_IF_COND; | |
1499 | /* We set the bit if the host supports voltages between 2.7 and 3.6 V */ | |
93bfd616 | 1500 | cmd.cmdarg = ((mmc->cfg->voltages & 0xff8000) != 0) << 8 | 0xaa; |
272cc70b | 1501 | cmd.resp_type = MMC_RSP_R7; |
272cc70b AF |
1502 | |
1503 | err = mmc_send_cmd(mmc, &cmd, NULL); | |
1504 | ||
1505 | if (err) | |
1506 | return err; | |
1507 | ||
998be3dd | 1508 | if ((cmd.response[0] & 0xff) != 0xaa) |
272cc70b AF |
1509 | return UNUSABLE_ERR; |
1510 | else | |
1511 | mmc->version = SD_VERSION_2; | |
1512 | ||
1513 | return 0; | |
1514 | } | |
1515 | ||
93bfd616 PA |
1516 | /* not used any more */ |
1517 | int __deprecated mmc_register(struct mmc *mmc) | |
1518 | { | |
1519 | #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT) | |
1520 | printf("%s is deprecated! use mmc_create() instead.\n", __func__); | |
1521 | #endif | |
1522 | return -1; | |
1523 | } | |
1524 | ||
1525 | struct mmc *mmc_create(const struct mmc_config *cfg, void *priv) | |
272cc70b | 1526 | { |
93bfd616 PA |
1527 | struct mmc *mmc; |
1528 | ||
1529 | /* quick validation */ | |
1530 | if (cfg == NULL || cfg->ops == NULL || cfg->ops->send_cmd == NULL || | |
1531 | cfg->f_min == 0 || cfg->f_max == 0 || cfg->b_max == 0) | |
1532 | return NULL; | |
1533 | ||
1534 | mmc = calloc(1, sizeof(*mmc)); | |
1535 | if (mmc == NULL) | |
1536 | return NULL; | |
1537 | ||
1538 | mmc->cfg = cfg; | |
1539 | mmc->priv = priv; | |
1540 | ||
1541 | /* the following chunk was mmc_register() */ | |
1542 | ||
ab71188c MN |
1543 | /* Setup dsr related values */ |
1544 | mmc->dsr_imp = 0; | |
1545 | mmc->dsr = 0xffffffff; | |
272cc70b AF |
1546 | /* Setup the universal parts of the block interface just once */ |
1547 | mmc->block_dev.if_type = IF_TYPE_MMC; | |
1548 | mmc->block_dev.dev = cur_dev_num++; | |
1549 | mmc->block_dev.removable = 1; | |
1550 | mmc->block_dev.block_read = mmc_bread; | |
1551 | mmc->block_dev.block_write = mmc_bwrite; | |
e6f99a56 | 1552 | mmc->block_dev.block_erase = mmc_berase; |
272cc70b | 1553 | |
93bfd616 PA |
1554 | /* setup initial part type */ |
1555 | mmc->block_dev.part_type = mmc->cfg->part_type; | |
272cc70b | 1556 | |
93bfd616 | 1557 | INIT_LIST_HEAD(&mmc->link); |
272cc70b | 1558 | |
93bfd616 PA |
1559 | list_add_tail(&mmc->link, &mmc_devices); |
1560 | ||
1561 | return mmc; | |
1562 | } | |
1563 | ||
1564 | void mmc_destroy(struct mmc *mmc) | |
1565 | { | |
1566 | /* only freeing memory for now */ | |
1567 | free(mmc); | |
272cc70b AF |
1568 | } |
1569 | ||
df3fc526 | 1570 | #ifdef CONFIG_PARTITIONS |
272cc70b AF |
1571 | block_dev_desc_t *mmc_get_dev(int dev) |
1572 | { | |
1573 | struct mmc *mmc = find_mmc_device(dev); | |
6bb4b4bc | 1574 | if (!mmc || mmc_init(mmc)) |
40242bc3 | 1575 | return NULL; |
272cc70b | 1576 | |
40242bc3 | 1577 | return &mmc->block_dev; |
272cc70b | 1578 | } |
df3fc526 | 1579 | #endif |
272cc70b | 1580 | |
95de9ab2 PK |
1581 | /* board-specific MMC power initializations. */ |
1582 | __weak void board_mmc_power_init(void) | |
1583 | { | |
1584 | } | |
1585 | ||
e9550449 | 1586 | int mmc_start_init(struct mmc *mmc) |
272cc70b | 1587 | { |
afd5932b | 1588 | int err; |
272cc70b | 1589 | |
ab769f22 | 1590 | /* we pretend there's no card when init is NULL */ |
93bfd616 | 1591 | if (mmc_getcd(mmc) == 0 || mmc->cfg->ops->init == NULL) { |
48972d90 | 1592 | mmc->has_init = 0; |
56196826 | 1593 | #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT) |
48972d90 | 1594 | printf("MMC: no card present\n"); |
56196826 | 1595 | #endif |
48972d90 TR |
1596 | return NO_CARD_ERR; |
1597 | } | |
1598 | ||
bc897b1d LW |
1599 | if (mmc->has_init) |
1600 | return 0; | |
1601 | ||
5a8dbdc6 YL |
1602 | #ifdef CONFIG_FSL_ESDHC_ADAPTER_IDENT |
1603 | mmc_adapter_card_type_ident(); | |
1604 | #endif | |
95de9ab2 PK |
1605 | board_mmc_power_init(); |
1606 | ||
ab769f22 | 1607 | /* made sure it's not NULL earlier */ |
93bfd616 | 1608 | err = mmc->cfg->ops->init(mmc); |
272cc70b AF |
1609 | |
1610 | if (err) | |
1611 | return err; | |
1612 | ||
786e8f81 | 1613 | mmc->ddr_mode = 0; |
b86b85e2 IY |
1614 | mmc_set_bus_width(mmc, 1); |
1615 | mmc_set_clock(mmc, 1); | |
1616 | ||
272cc70b AF |
1617 | /* Reset the Card */ |
1618 | err = mmc_go_idle(mmc); | |
1619 | ||
1620 | if (err) | |
1621 | return err; | |
1622 | ||
bc897b1d LW |
1623 | /* The internal partition reset to user partition(0) at every CMD0*/ |
1624 | mmc->part_num = 0; | |
1625 | ||
272cc70b | 1626 | /* Test for SD version 2 */ |
afd5932b | 1627 | err = mmc_send_if_cond(mmc); |
272cc70b | 1628 | |
272cc70b AF |
1629 | /* Now try to get the SD card's operating condition */ |
1630 | err = sd_send_op_cond(mmc); | |
1631 | ||
1632 | /* If the command timed out, we check for an MMC card */ | |
1633 | if (err == TIMEOUT) { | |
1634 | err = mmc_send_op_cond(mmc); | |
1635 | ||
bd47c135 | 1636 | if (err) { |
56196826 | 1637 | #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT) |
272cc70b | 1638 | printf("Card did not respond to voltage select!\n"); |
56196826 | 1639 | #endif |
272cc70b AF |
1640 | return UNUSABLE_ERR; |
1641 | } | |
1642 | } | |
1643 | ||
bd47c135 | 1644 | if (!err) |
e9550449 CLC |
1645 | mmc->init_in_progress = 1; |
1646 | ||
1647 | return err; | |
1648 | } | |
1649 | ||
1650 | static int mmc_complete_init(struct mmc *mmc) | |
1651 | { | |
1652 | int err = 0; | |
1653 | ||
bd47c135 | 1654 | mmc->init_in_progress = 0; |
e9550449 CLC |
1655 | if (mmc->op_cond_pending) |
1656 | err = mmc_complete_op_cond(mmc); | |
1657 | ||
1658 | if (!err) | |
1659 | err = mmc_startup(mmc); | |
bc897b1d LW |
1660 | if (err) |
1661 | mmc->has_init = 0; | |
1662 | else | |
1663 | mmc->has_init = 1; | |
e9550449 CLC |
1664 | return err; |
1665 | } | |
1666 | ||
1667 | int mmc_init(struct mmc *mmc) | |
1668 | { | |
bd47c135 | 1669 | int err = 0; |
d803fea5 | 1670 | unsigned start; |
e9550449 CLC |
1671 | |
1672 | if (mmc->has_init) | |
1673 | return 0; | |
d803fea5 MZ |
1674 | |
1675 | start = get_timer(0); | |
1676 | ||
e9550449 CLC |
1677 | if (!mmc->init_in_progress) |
1678 | err = mmc_start_init(mmc); | |
1679 | ||
bd47c135 | 1680 | if (!err) |
e9550449 CLC |
1681 | err = mmc_complete_init(mmc); |
1682 | debug("%s: %d, time %lu\n", __func__, err, get_timer(start)); | |
bc897b1d | 1683 | return err; |
272cc70b AF |
1684 | } |
1685 | ||
ab71188c MN |
1686 | int mmc_set_dsr(struct mmc *mmc, u16 val) |
1687 | { | |
1688 | mmc->dsr = val; | |
1689 | return 0; | |
1690 | } | |
1691 | ||
cee9ab7c JH |
1692 | /* CPU-specific MMC initializations */ |
1693 | __weak int cpu_mmc_init(bd_t *bis) | |
272cc70b AF |
1694 | { |
1695 | return -1; | |
1696 | } | |
1697 | ||
cee9ab7c JH |
1698 | /* board-specific MMC initializations. */ |
1699 | __weak int board_mmc_init(bd_t *bis) | |
1700 | { | |
1701 | return -1; | |
1702 | } | |
272cc70b | 1703 | |
56196826 PB |
1704 | #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT) |
1705 | ||
272cc70b AF |
1706 | void print_mmc_devices(char separator) |
1707 | { | |
1708 | struct mmc *m; | |
1709 | struct list_head *entry; | |
34dd9284 | 1710 | char *mmc_type; |
272cc70b AF |
1711 | |
1712 | list_for_each(entry, &mmc_devices) { | |
1713 | m = list_entry(entry, struct mmc, link); | |
1714 | ||
34dd9284 PM |
1715 | if (m->has_init) |
1716 | mmc_type = IS_SD(m) ? "SD" : "eMMC"; | |
1717 | else | |
1718 | mmc_type = NULL; | |
1719 | ||
93bfd616 | 1720 | printf("%s: %d", m->cfg->name, m->block_dev.dev); |
34dd9284 PM |
1721 | if (mmc_type) |
1722 | printf(" (%s)", mmc_type); | |
272cc70b | 1723 | |
e75eaf10 LP |
1724 | if (entry->next != &mmc_devices) { |
1725 | printf("%c", separator); | |
1726 | if (separator != '\n') | |
1727 | puts (" "); | |
1728 | } | |
272cc70b AF |
1729 | } |
1730 | ||
1731 | printf("\n"); | |
1732 | } | |
1733 | ||
56196826 PB |
1734 | #else |
1735 | void print_mmc_devices(char separator) { } | |
1736 | #endif | |
1737 | ||
ea6ebe21 LW |
1738 | int get_mmc_num(void) |
1739 | { | |
1740 | return cur_dev_num; | |
1741 | } | |
1742 | ||
e9550449 CLC |
1743 | void mmc_set_preinit(struct mmc *mmc, int preinit) |
1744 | { | |
1745 | mmc->preinit = preinit; | |
1746 | } | |
1747 | ||
1748 | static void do_preinit(void) | |
1749 | { | |
1750 | struct mmc *m; | |
1751 | struct list_head *entry; | |
1752 | ||
1753 | list_for_each(entry, &mmc_devices) { | |
1754 | m = list_entry(entry, struct mmc, link); | |
1755 | ||
5a8dbdc6 YL |
1756 | #ifdef CONFIG_FSL_ESDHC_ADAPTER_IDENT |
1757 | mmc_set_preinit(m, 1); | |
1758 | #endif | |
e9550449 CLC |
1759 | if (m->preinit) |
1760 | mmc_start_init(m); | |
1761 | } | |
1762 | } | |
1763 | ||
8e3332e2 SS |
1764 | #if defined(CONFIG_DM_MMC) && defined(CONFIG_SPL_BUILD) |
1765 | static int mmc_probe(bd_t *bis) | |
1766 | { | |
1767 | return 0; | |
1768 | } | |
1769 | #elif defined(CONFIG_DM_MMC) | |
1770 | static int mmc_probe(bd_t *bis) | |
1771 | { | |
1772 | int ret; | |
1773 | struct uclass *uc; | |
1774 | struct udevice *m; | |
1775 | ||
1776 | ret = uclass_get(UCLASS_MMC, &uc); | |
1777 | if (ret) | |
1778 | return ret; | |
1779 | ||
1780 | uclass_foreach_dev(m, uc) { | |
1781 | ret = device_probe(m); | |
1782 | if (ret) | |
1783 | printf("%s - probe failed: %d\n", m->name, ret); | |
1784 | } | |
1785 | ||
1786 | return 0; | |
1787 | } | |
1788 | #else | |
1789 | static int mmc_probe(bd_t *bis) | |
1790 | { | |
1791 | if (board_mmc_init(bis) < 0) | |
1792 | cpu_mmc_init(bis); | |
1793 | ||
1794 | return 0; | |
1795 | } | |
1796 | #endif | |
e9550449 | 1797 | |
272cc70b AF |
1798 | int mmc_initialize(bd_t *bis) |
1799 | { | |
1b26bab1 | 1800 | static int initialized = 0; |
8e3332e2 | 1801 | int ret; |
1b26bab1 DK |
1802 | if (initialized) /* Avoid initializing mmc multiple times */ |
1803 | return 0; | |
1804 | initialized = 1; | |
1805 | ||
272cc70b AF |
1806 | INIT_LIST_HEAD (&mmc_devices); |
1807 | cur_dev_num = 0; | |
1808 | ||
8e3332e2 SS |
1809 | ret = mmc_probe(bis); |
1810 | if (ret) | |
1811 | return ret; | |
272cc70b | 1812 | |
bb0dc108 | 1813 | #ifndef CONFIG_SPL_BUILD |
272cc70b | 1814 | print_mmc_devices(','); |
bb0dc108 | 1815 | #endif |
272cc70b | 1816 | |
e9550449 | 1817 | do_preinit(); |
272cc70b AF |
1818 | return 0; |
1819 | } | |
3690d6d6 A |
1820 | |
1821 | #ifdef CONFIG_SUPPORT_EMMC_BOOT | |
1822 | /* | |
1823 | * This function changes the size of boot partition and the size of rpmb | |
1824 | * partition present on EMMC devices. | |
1825 | * | |
1826 | * Input Parameters: | |
1827 | * struct *mmc: pointer for the mmc device strcuture | |
1828 | * bootsize: size of boot partition | |
1829 | * rpmbsize: size of rpmb partition | |
1830 | * | |
1831 | * Returns 0 on success. | |
1832 | */ | |
1833 | ||
1834 | int mmc_boot_partition_size_change(struct mmc *mmc, unsigned long bootsize, | |
1835 | unsigned long rpmbsize) | |
1836 | { | |
1837 | int err; | |
1838 | struct mmc_cmd cmd; | |
1839 | ||
1840 | /* Only use this command for raw EMMC moviNAND. Enter backdoor mode */ | |
1841 | cmd.cmdidx = MMC_CMD_RES_MAN; | |
1842 | cmd.resp_type = MMC_RSP_R1b; | |
1843 | cmd.cmdarg = MMC_CMD62_ARG1; | |
1844 | ||
1845 | err = mmc_send_cmd(mmc, &cmd, NULL); | |
1846 | if (err) { | |
1847 | debug("mmc_boot_partition_size_change: Error1 = %d\n", err); | |
1848 | return err; | |
1849 | } | |
1850 | ||
1851 | /* Boot partition changing mode */ | |
1852 | cmd.cmdidx = MMC_CMD_RES_MAN; | |
1853 | cmd.resp_type = MMC_RSP_R1b; | |
1854 | cmd.cmdarg = MMC_CMD62_ARG2; | |
1855 | ||
1856 | err = mmc_send_cmd(mmc, &cmd, NULL); | |
1857 | if (err) { | |
1858 | debug("mmc_boot_partition_size_change: Error2 = %d\n", err); | |
1859 | return err; | |
1860 | } | |
1861 | /* boot partition size is multiple of 128KB */ | |
1862 | bootsize = (bootsize * 1024) / 128; | |
1863 | ||
1864 | /* Arg: boot partition size */ | |
1865 | cmd.cmdidx = MMC_CMD_RES_MAN; | |
1866 | cmd.resp_type = MMC_RSP_R1b; | |
1867 | cmd.cmdarg = bootsize; | |
1868 | ||
1869 | err = mmc_send_cmd(mmc, &cmd, NULL); | |
1870 | if (err) { | |
1871 | debug("mmc_boot_partition_size_change: Error3 = %d\n", err); | |
1872 | return err; | |
1873 | } | |
1874 | /* RPMB partition size is multiple of 128KB */ | |
1875 | rpmbsize = (rpmbsize * 1024) / 128; | |
1876 | /* Arg: RPMB partition size */ | |
1877 | cmd.cmdidx = MMC_CMD_RES_MAN; | |
1878 | cmd.resp_type = MMC_RSP_R1b; | |
1879 | cmd.cmdarg = rpmbsize; | |
1880 | ||
1881 | err = mmc_send_cmd(mmc, &cmd, NULL); | |
1882 | if (err) { | |
1883 | debug("mmc_boot_partition_size_change: Error4 = %d\n", err); | |
1884 | return err; | |
1885 | } | |
1886 | return 0; | |
1887 | } | |
1888 | ||
5a99b9de TR |
1889 | /* |
1890 | * Modify EXT_CSD[177] which is BOOT_BUS_WIDTH | |
1891 | * based on the passed in values for BOOT_BUS_WIDTH, RESET_BOOT_BUS_WIDTH | |
1892 | * and BOOT_MODE. | |
1893 | * | |
1894 | * Returns 0 on success. | |
1895 | */ | |
1896 | int mmc_set_boot_bus_width(struct mmc *mmc, u8 width, u8 reset, u8 mode) | |
1897 | { | |
1898 | int err; | |
1899 | ||
1900 | err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_BOOT_BUS_WIDTH, | |
1901 | EXT_CSD_BOOT_BUS_WIDTH_MODE(mode) | | |
1902 | EXT_CSD_BOOT_BUS_WIDTH_RESET(reset) | | |
1903 | EXT_CSD_BOOT_BUS_WIDTH_WIDTH(width)); | |
1904 | ||
1905 | if (err) | |
1906 | return err; | |
1907 | return 0; | |
1908 | } | |
1909 | ||
792970b0 TR |
1910 | /* |
1911 | * Modify EXT_CSD[179] which is PARTITION_CONFIG (formerly BOOT_CONFIG) | |
1912 | * based on the passed in values for BOOT_ACK, BOOT_PARTITION_ENABLE and | |
1913 | * PARTITION_ACCESS. | |
1914 | * | |
1915 | * Returns 0 on success. | |
1916 | */ | |
1917 | int mmc_set_part_conf(struct mmc *mmc, u8 ack, u8 part_num, u8 access) | |
1918 | { | |
1919 | int err; | |
1920 | ||
1921 | err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_PART_CONF, | |
1922 | EXT_CSD_BOOT_ACK(ack) | | |
1923 | EXT_CSD_BOOT_PART_NUM(part_num) | | |
1924 | EXT_CSD_PARTITION_ACCESS(access)); | |
1925 | ||
1926 | if (err) | |
1927 | return err; | |
1928 | return 0; | |
1929 | } | |
33ace362 TR |
1930 | |
1931 | /* | |
1932 | * Modify EXT_CSD[162] which is RST_n_FUNCTION based on the given value | |
1933 | * for enable. Note that this is a write-once field for non-zero values. | |
1934 | * | |
1935 | * Returns 0 on success. | |
1936 | */ | |
1937 | int mmc_set_rst_n_function(struct mmc *mmc, u8 enable) | |
1938 | { | |
1939 | return mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_RST_N_FUNCTION, | |
1940 | enable); | |
1941 | } | |
3690d6d6 | 1942 | #endif |