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board/t2080rdb: reset cs4315 phy
[u-boot.git] / drivers / mmc / mmc.c
CommitLineData
272cc70b
AF		 1/*
2 * Copyright 2008, Freescale Semiconductor, Inc
3 * Andy Fleming
4 *
5 * Based vaguely on the Linux code
6 *
1a459660 7 * SPDX-License-Identifier: GPL-2.0+
272cc70b
AF		 8 */
9
10#include <config.h>
11#include <common.h>
12#include <command.h>
d4622df3 13#include <errno.h>
272cc70b
AF		 14#include <mmc.h>
15#include <part.h>
16#include <malloc.h>
17#include <linux/list.h>
9b1f942c 18#include <div64.h>
da61fa5f 19#include "mmc_private.h"
272cc70b
AF		 20
21static struct list_head mmc_devices;
22static int cur_dev_num = -1;
23
750121c3 24__weak int board_mmc_getwp(struct mmc *mmc)
d23d8d7e
NK		 25{
26 return -1;
27}
28
29int mmc_getwp(struct mmc *mmc)
30{
31 int wp;
32
33 wp = board_mmc_getwp(mmc);
34
d4e1da4e 35 if (wp < 0) {
93bfd616
PA		 36 if (mmc->cfg->ops->getwp)
37 wp = mmc->cfg->ops->getwp(mmc);
d4e1da4e
PK		 38 else
39 wp = 0;
40 }
d23d8d7e
NK		 41
42 return wp;
43}
44
cee9ab7c
JH		 45__weak int board_mmc_getcd(struct mmc *mmc)
46{
11fdade2
SB		 47 return -1;
48}
49
da61fa5f 50int mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data)
272cc70b 51{
5db2fe3a 52 int ret;
8635ff9e 53
8635ff9e 54#ifdef CONFIG_MMC_TRACE
5db2fe3a
RR		 55 int i;
56 u8 *ptr;
57
58 printf("CMD_SEND:%d\n", cmd->cmdidx);
59 printf("\t\tARG\t\t\t 0x%08X\n", cmd->cmdarg);
93bfd616 60 ret = mmc->cfg->ops->send_cmd(mmc, cmd, data);
5db2fe3a
RR		 61 switch (cmd->resp_type) {
62 case MMC_RSP_NONE:
63 printf("\t\tMMC_RSP_NONE\n");
64 break;
65 case MMC_RSP_R1:
66 printf("\t\tMMC_RSP_R1,5,6,7 \t 0x%08X \n",
67 cmd->response[0]);
68 break;
69 case MMC_RSP_R1b:
70 printf("\t\tMMC_RSP_R1b\t\t 0x%08X \n",
71 cmd->response[0]);
72 break;
73 case MMC_RSP_R2:
74 printf("\t\tMMC_RSP_R2\t\t 0x%08X \n",
75 cmd->response[0]);
76 printf("\t\t \t\t 0x%08X \n",
77 cmd->response[1]);
78 printf("\t\t \t\t 0x%08X \n",
79 cmd->response[2]);
80 printf("\t\t \t\t 0x%08X \n",
81 cmd->response[3]);
82 printf("\n");
83 printf("\t\t\t\t\tDUMPING DATA\n");
84 for (i = 0; i < 4; i++) {
85 int j;
86 printf("\t\t\t\t\t%03d - ", i*4);
146bec79 87 ptr = (u8 *)&cmd->response[i];
5db2fe3a
RR		 88 ptr += 3;
89 for (j = 0; j < 4; j++)
90 printf("%02X ", *ptr--);
91 printf("\n");
92 }
93 break;
94 case MMC_RSP_R3:
95 printf("\t\tMMC_RSP_R3,4\t\t 0x%08X \n",
96 cmd->response[0]);
97 break;
98 default:
99 printf("\t\tERROR MMC rsp not supported\n");
100 break;
101 }
5db2fe3a 102#else
93bfd616 103 ret = mmc->cfg->ops->send_cmd(mmc, cmd, data);
5db2fe3a 104#endif
8635ff9e 105 return ret;
272cc70b
AF		 106}
107
da61fa5f 108int mmc_send_status(struct mmc *mmc, int timeout)
5d4fc8d9
RR		 109{
110 struct mmc_cmd cmd;
d617c426 111 int err, retries = 5;
5d4fc8d9
RR		 112#ifdef CONFIG_MMC_TRACE
113 int status;
114#endif
115
116 cmd.cmdidx = MMC_CMD_SEND_STATUS;
117 cmd.resp_type = MMC_RSP_R1;
aaf3d41a
MV		 118 if (!mmc_host_is_spi(mmc))
119 cmd.cmdarg = mmc->rca << 16;
5d4fc8d9
RR		 120
121 do {
122 err = mmc_send_cmd(mmc, &cmd, NULL);
d617c426
JK		 123 if (!err) {
124 if ((cmd.response[0] & MMC_STATUS_RDY_FOR_DATA) &&
125 (cmd.response[0] & MMC_STATUS_CURR_STATE) !=
126 MMC_STATE_PRG)
127 break;
128 else if (cmd.response[0] & MMC_STATUS_MASK) {
56196826 129#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
d617c426
JK		 130 printf("Status Error: 0x%08X\n",
131 cmd.response[0]);
56196826 132#endif
d617c426
JK		 133 return COMM_ERR;
134 }
135 } else if (--retries < 0)
5d4fc8d9 136 return err;
5d4fc8d9
RR		 137
138 udelay(1000);
139
5d4fc8d9
RR		 140 } while (timeout--);
141
5db2fe3a
RR		 142#ifdef CONFIG_MMC_TRACE
143 status = (cmd.response[0] & MMC_STATUS_CURR_STATE) >> 9;
144 printf("CURR STATE:%d\n", status);
145#endif
5b0c942f 146 if (timeout <= 0) {
56196826 147#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
5d4fc8d9 148 printf("Timeout waiting card ready\n");
56196826 149#endif
5d4fc8d9
RR		 150 return TIMEOUT;
151 }
6b2221b0
AG		 152 if (cmd.response[0] & MMC_STATUS_SWITCH_ERROR)
153 return SWITCH_ERR;
5d4fc8d9
RR		 154
155 return 0;
156}
157
da61fa5f 158int mmc_set_blocklen(struct mmc *mmc, int len)
272cc70b
AF		 159{
160 struct mmc_cmd cmd;
161
786e8f81 162 if (mmc->ddr_mode)
d22e3d46
JC		 163 return 0;
164
272cc70b
AF		 165 cmd.cmdidx = MMC_CMD_SET_BLOCKLEN;
166 cmd.resp_type = MMC_RSP_R1;
167 cmd.cmdarg = len;
272cc70b
AF		 168
169 return mmc_send_cmd(mmc, &cmd, NULL);
170}
171
172struct mmc *find_mmc_device(int dev_num)
173{
174 struct mmc *m;
175 struct list_head *entry;
176
177 list_for_each(entry, &mmc_devices) {
178 m = list_entry(entry, struct mmc, link);
179
180 if (m->block_dev.dev == dev_num)
181 return m;
182 }
183
56196826 184#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
272cc70b 185 printf("MMC Device %d not found\n", dev_num);
56196826 186#endif
272cc70b
AF		 187
188 return NULL;
189}
190
ff8fef56 191static int mmc_read_blocks(struct mmc *mmc, void *dst, lbaint_t start,
fdbb873e 192 lbaint_t blkcnt)
272cc70b
AF		 193{
194 struct mmc_cmd cmd;
195 struct mmc_data data;
196
4a1a06bc
AS		 197 if (blkcnt > 1)
198 cmd.cmdidx = MMC_CMD_READ_MULTIPLE_BLOCK;
199 else
200 cmd.cmdidx = MMC_CMD_READ_SINGLE_BLOCK;
272cc70b
AF		 201
202 if (mmc->high_capacity)
4a1a06bc 203 cmd.cmdarg = start;
272cc70b 204 else
4a1a06bc 205 cmd.cmdarg = start * mmc->read_bl_len;
272cc70b
AF		 206
207 cmd.resp_type = MMC_RSP_R1;
272cc70b
AF		 208
209 data.dest = dst;
4a1a06bc 210 data.blocks = blkcnt;
272cc70b
AF		 211 data.blocksize = mmc->read_bl_len;
212 data.flags = MMC_DATA_READ;
213
4a1a06bc
AS		 214 if (mmc_send_cmd(mmc, &cmd, &data))
215 return 0;
272cc70b 216
4a1a06bc
AS		 217 if (blkcnt > 1) {
218 cmd.cmdidx = MMC_CMD_STOP_TRANSMISSION;
219 cmd.cmdarg = 0;
220 cmd.resp_type = MMC_RSP_R1b;
4a1a06bc 221 if (mmc_send_cmd(mmc, &cmd, NULL)) {
56196826 222#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
4a1a06bc 223 printf("mmc fail to send stop cmd\n");
56196826 224#endif
4a1a06bc
AS		 225 return 0;
226 }
272cc70b
AF		 227 }
228
4a1a06bc 229 return blkcnt;
272cc70b
AF		 230}
231
ff8fef56 232static ulong mmc_bread(int dev_num, lbaint_t start, lbaint_t blkcnt, void *dst)
272cc70b 233{
4a1a06bc
AS		 234 lbaint_t cur, blocks_todo = blkcnt;
235
236 if (blkcnt == 0)
237 return 0;
272cc70b 238
4a1a06bc 239 struct mmc *mmc = find_mmc_device(dev_num);
272cc70b
AF		 240 if (!mmc)
241 return 0;
242
d2bf29e3 243 if ((start + blkcnt) > mmc->block_dev.lba) {
56196826 244#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
ff8fef56 245 printf("MMC: block number 0x" LBAF " exceeds max(0x" LBAF ")\n",
d2bf29e3 246 start + blkcnt, mmc->block_dev.lba);
56196826 247#endif
d2bf29e3
LW		 248 return 0;
249 }
272cc70b 250
4a1a06bc 251 if (mmc_set_blocklen(mmc, mmc->read_bl_len))
272cc70b 252 return 0;
272cc70b 253
4a1a06bc 254 do {
93bfd616
PA		 255 cur = (blocks_todo > mmc->cfg->b_max) ?
256 mmc->cfg->b_max : blocks_todo;
4a1a06bc
AS		 257 if(mmc_read_blocks(mmc, dst, start, cur) != cur)
258 return 0;
259 blocks_todo -= cur;
260 start += cur;
261 dst += cur * mmc->read_bl_len;
262 } while (blocks_todo > 0);
272cc70b
AF		 263
264 return blkcnt;
265}
266
fdbb873e 267static int mmc_go_idle(struct mmc *mmc)
272cc70b
AF		 268{
269 struct mmc_cmd cmd;
270 int err;
271
272 udelay(1000);
273
274 cmd.cmdidx = MMC_CMD_GO_IDLE_STATE;
275 cmd.cmdarg = 0;
276 cmd.resp_type = MMC_RSP_NONE;
272cc70b
AF		 277
278 err = mmc_send_cmd(mmc, &cmd, NULL);
279
280 if (err)
281 return err;
282
283 udelay(2000);
284
285 return 0;
286}
287
fdbb873e 288static int sd_send_op_cond(struct mmc *mmc)
272cc70b
AF		 289{
290 int timeout = 1000;
291 int err;
292 struct mmc_cmd cmd;
293
294 do {
295 cmd.cmdidx = MMC_CMD_APP_CMD;
296 cmd.resp_type = MMC_RSP_R1;
297 cmd.cmdarg = 0;
272cc70b
AF		 298
299 err = mmc_send_cmd(mmc, &cmd, NULL);
300
301 if (err)
302 return err;
303
304 cmd.cmdidx = SD_CMD_APP_SEND_OP_COND;
305 cmd.resp_type = MMC_RSP_R3;
250de12b
SB		 306
307 /*
308 * Most cards do not answer if some reserved bits
309 * in the ocr are set. However, Some controller
310 * can set bit 7 (reserved for low voltages), but
311 * how to manage low voltages SD card is not yet
312 * specified.
313 */
d52ebf10 314 cmd.cmdarg = mmc_host_is_spi(mmc) ? 0 :
93bfd616 315 (mmc->cfg->voltages & 0xff8000);
272cc70b
AF		 316
317 if (mmc->version == SD_VERSION_2)
318 cmd.cmdarg |= OCR_HCS;
319
320 err = mmc_send_cmd(mmc, &cmd, NULL);
321
322 if (err)
323 return err;
324
325 udelay(1000);
326 } while ((!(cmd.response[0] & OCR_BUSY)) && timeout--);
327
328 if (timeout <= 0)
329 return UNUSABLE_ERR;
330
331 if (mmc->version != SD_VERSION_2)
332 mmc->version = SD_VERSION_1_0;
333
d52ebf10
TC		 334 if (mmc_host_is_spi(mmc)) { /* read OCR for spi */
335 cmd.cmdidx = MMC_CMD_SPI_READ_OCR;
336 cmd.resp_type = MMC_RSP_R3;
337 cmd.cmdarg = 0;
d52ebf10
TC		 338
339 err = mmc_send_cmd(mmc, &cmd, NULL);
340
341 if (err)
342 return err;
343 }
344
998be3dd 345 mmc->ocr = cmd.response[0];
272cc70b
AF		 346
347 mmc->high_capacity = ((mmc->ocr & OCR_HCS) == OCR_HCS);
348 mmc->rca = 0;
349
350 return 0;
351}
352
e9550449
CLC		 353/* We pass in the cmd since otherwise the init seems to fail */
354static int mmc_send_op_cond_iter(struct mmc *mmc, struct mmc_cmd *cmd,
355 int use_arg)
272cc70b 356{
272cc70b
AF		 357 int err;
358
e9550449
CLC		 359 cmd->cmdidx = MMC_CMD_SEND_OP_COND;
360 cmd->resp_type = MMC_RSP_R3;
361 cmd->cmdarg = 0;
362 if (use_arg && !mmc_host_is_spi(mmc)) {
363 cmd->cmdarg =
93bfd616 364 (mmc->cfg->voltages &
e9550449
CLC		 365 (mmc->op_cond_response & OCR_VOLTAGE_MASK)) |
366 (mmc->op_cond_response & OCR_ACCESS_MODE);
367
93bfd616 368 if (mmc->cfg->host_caps & MMC_MODE_HC)
e9550449
CLC		 369 cmd->cmdarg |= OCR_HCS;
370 }
371 err = mmc_send_cmd(mmc, cmd, NULL);
372 if (err)
373 return err;
374 mmc->op_cond_response = cmd->response[0];
375 return 0;
376}
377
750121c3 378static int mmc_send_op_cond(struct mmc *mmc)
e9550449
CLC		 379{
380 struct mmc_cmd cmd;
381 int err, i;
382
272cc70b
AF		 383 /* Some cards seem to need this */
384 mmc_go_idle(mmc);
385
31cacbab 386 /* Asking to the card its capabilities */
e9550449
CLC		 387 mmc->op_cond_pending = 1;
388 for (i = 0; i < 2; i++) {
389 err = mmc_send_op_cond_iter(mmc, &cmd, i != 0);
390 if (err)
391 return err;
cd6881b5 392
e9550449
CLC		 393 /* exit if not busy (flag seems to be inverted) */
394 if (mmc->op_cond_response & OCR_BUSY)
395 return 0;
396 }
397 return IN_PROGRESS;
398}
cd6881b5 399
750121c3 400static int mmc_complete_op_cond(struct mmc *mmc)
e9550449
CLC		 401{
402 struct mmc_cmd cmd;
403 int timeout = 1000;
404 uint start;
405 int err;
cd6881b5 406
e9550449
CLC		 407 mmc->op_cond_pending = 0;
408 start = get_timer(0);
272cc70b 409 do {
e9550449 410 err = mmc_send_op_cond_iter(mmc, &cmd, 1);
272cc70b
AF		 411 if (err)
412 return err;
e9550449
CLC		 413 if (get_timer(start) > timeout)
414 return UNUSABLE_ERR;
415 udelay(100);
416 } while (!(mmc->op_cond_response & OCR_BUSY));
272cc70b 417
d52ebf10
TC		 418 if (mmc_host_is_spi(mmc)) { /* read OCR for spi */
419 cmd.cmdidx = MMC_CMD_SPI_READ_OCR;
420 cmd.resp_type = MMC_RSP_R3;
421 cmd.cmdarg = 0;
d52ebf10
TC		 422
423 err = mmc_send_cmd(mmc, &cmd, NULL);
424
425 if (err)
426 return err;
427 }
428
272cc70b 429 mmc->version = MMC_VERSION_UNKNOWN;
998be3dd 430 mmc->ocr = cmd.response[0];
272cc70b
AF		 431
432 mmc->high_capacity = ((mmc->ocr & OCR_HCS) == OCR_HCS);
def816a2 433 mmc->rca = 1;
272cc70b
AF		 434
435 return 0;
436}
437
438
fdbb873e 439static int mmc_send_ext_csd(struct mmc *mmc, u8 *ext_csd)
272cc70b
AF		 440{
441 struct mmc_cmd cmd;
442 struct mmc_data data;
443 int err;
444
445 /* Get the Card Status Register */
446 cmd.cmdidx = MMC_CMD_SEND_EXT_CSD;
447 cmd.resp_type = MMC_RSP_R1;
448 cmd.cmdarg = 0;
272cc70b 449
cdfd1ac6 450 data.dest = (char *)ext_csd;
272cc70b 451 data.blocks = 1;
8bfa195e 452 data.blocksize = MMC_MAX_BLOCK_LEN;
272cc70b
AF		 453 data.flags = MMC_DATA_READ;
454
455 err = mmc_send_cmd(mmc, &cmd, &data);
456
457 return err;
458}
459
460
fdbb873e 461static int mmc_switch(struct mmc *mmc, u8 set, u8 index, u8 value)
272cc70b
AF		 462{
463 struct mmc_cmd cmd;
5d4fc8d9
RR		 464 int timeout = 1000;
465 int ret;
272cc70b
AF		 466
467 cmd.cmdidx = MMC_CMD_SWITCH;
468 cmd.resp_type = MMC_RSP_R1b;
469 cmd.cmdarg = (MMC_SWITCH_MODE_WRITE_BYTE << 24) |
5d4fc8d9
RR		 470 (index << 16) |
471 (value << 8);
272cc70b 472
5d4fc8d9
RR		 473 ret = mmc_send_cmd(mmc, &cmd, NULL);
474
475 /* Waiting for the ready status */
93ad0d18
JK		 476 if (!ret)
477 ret = mmc_send_status(mmc, timeout);
5d4fc8d9
RR		 478
479 return ret;
480
272cc70b
AF		 481}
482
fdbb873e 483static int mmc_change_freq(struct mmc *mmc)
272cc70b 484{
8bfa195e 485 ALLOC_CACHE_ALIGN_BUFFER(u8, ext_csd, MMC_MAX_BLOCK_LEN);
272cc70b
AF		 486 char cardtype;
487 int err;
488
fc5b32fb 489 mmc->card_caps = 0;
272cc70b 490
d52ebf10
TC		 491 if (mmc_host_is_spi(mmc))
492 return 0;
493
272cc70b
AF		 494 /* Only version 4 supports high-speed */
495 if (mmc->version < MMC_VERSION_4)
496 return 0;
497
fc5b32fb
AG		 498 mmc->card_caps |= MMC_MODE_4BIT | MMC_MODE_8BIT;
499
272cc70b
AF		 500 err = mmc_send_ext_csd(mmc, ext_csd);
501
502 if (err)
503 return err;
504
0560db18 505 cardtype = ext_csd[EXT_CSD_CARD_TYPE] & 0xf;
272cc70b
AF		 506
507 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_HS_TIMING, 1);
508
509 if (err)
6b2221b0 510 return err == SWITCH_ERR ? 0 : err;
272cc70b
AF		 511
512 /* Now check to see that it worked */
513 err = mmc_send_ext_csd(mmc, ext_csd);
514
515 if (err)
516 return err;
517
518 /* No high-speed support */
0560db18 519 if (!ext_csd[EXT_CSD_HS_TIMING])
272cc70b
AF		 520 return 0;
521
522 /* High Speed is set, there are two types: 52MHz and 26MHz */
d22e3d46 523 if (cardtype & EXT_CSD_CARD_TYPE_52) {
201d5ac4 524 if (cardtype & EXT_CSD_CARD_TYPE_DDR_1_8V)
d22e3d46 525 mmc->card_caps |= MMC_MODE_DDR_52MHz;
272cc70b 526 mmc->card_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS;
d22e3d46 527 } else {
272cc70b 528 mmc->card_caps |= MMC_MODE_HS;
d22e3d46 529 }
272cc70b
AF		 530
531 return 0;
532}
533
f866a46d
SW		 534static int mmc_set_capacity(struct mmc *mmc, int part_num)
535{
536 switch (part_num) {
537 case 0:
538 mmc->capacity = mmc->capacity_user;
539 break;
540 case 1:
541 case 2:
542 mmc->capacity = mmc->capacity_boot;
543 break;
544 case 3:
545 mmc->capacity = mmc->capacity_rpmb;
546 break;
547 case 4:
548 case 5:
549 case 6:
550 case 7:
551 mmc->capacity = mmc->capacity_gp[part_num - 4];
552 break;
553 default:
554 return -1;
555 }
556
557 mmc->block_dev.lba = lldiv(mmc->capacity, mmc->read_bl_len);
558
559 return 0;
560}
561
d2356284
SW		 562int mmc_select_hwpart(int dev_num, int hwpart)
563{
564 struct mmc *mmc = find_mmc_device(dev_num);
565 int ret;
566
567 if (!mmc)
d4622df3 568 return -ENODEV;
d2356284
SW		 569
570 if (mmc->part_num == hwpart)
571 return 0;
572
573 if (mmc->part_config == MMCPART_NOAVAILABLE) {
574 printf("Card doesn't support part_switch\n");
d4622df3 575 return -EMEDIUMTYPE;
d2356284
SW		 576 }
577
578 ret = mmc_switch_part(dev_num, hwpart);
579 if (ret)
d4622df3 580 return ret;
d2356284
SW		 581
582 mmc->part_num = hwpart;
583
584 return 0;
585}
586
587
bc897b1d
LW		 588int mmc_switch_part(int dev_num, unsigned int part_num)
589{
590 struct mmc *mmc = find_mmc_device(dev_num);
f866a46d 591 int ret;
bc897b1d
LW		 592
593 if (!mmc)
594 return -1;
595
f866a46d
SW		 596 ret = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_PART_CONF,
597 (mmc->part_config & ~PART_ACCESS_MASK)
598 | (part_num & PART_ACCESS_MASK));
f866a46d 599
6dc93e70
PB		 600 /*
601 * Set the capacity if the switch succeeded or was intended
602 * to return to representing the raw device.
603 */
604 if ((ret == 0) || ((ret == -ENODEV) && (part_num == 0)))
605 ret = mmc_set_capacity(mmc, part_num);
606
607 return ret;
bc897b1d
LW		 608}
609
ac9da0e0
DSC		 610int mmc_hwpart_config(struct mmc *mmc,
611 const struct mmc_hwpart_conf *conf,
612 enum mmc_hwpart_conf_mode mode)
613{
614 u8 part_attrs = 0;
615 u32 enh_size_mult;
616 u32 enh_start_addr;
617 u32 gp_size_mult[4];
618 u32 max_enh_size_mult;
619 u32 tot_enh_size_mult = 0;
8dda5b0e 620 u8 wr_rel_set;
ac9da0e0
DSC		 621 int i, pidx, err;
622 ALLOC_CACHE_ALIGN_BUFFER(u8, ext_csd, MMC_MAX_BLOCK_LEN);
623
624 if (mode < MMC_HWPART_CONF_CHECK || mode > MMC_HWPART_CONF_COMPLETE)
625 return -EINVAL;
626
627 if (IS_SD(mmc) || (mmc->version < MMC_VERSION_4_41)) {
628 printf("eMMC >= 4.4 required for enhanced user data area\n");
629 return -EMEDIUMTYPE;
630 }
631
632 if (!(mmc->part_support & PART_SUPPORT)) {
633 printf("Card does not support partitioning\n");
634 return -EMEDIUMTYPE;
635 }
636
637 if (!mmc->hc_wp_grp_size) {
638 printf("Card does not define HC WP group size\n");
639 return -EMEDIUMTYPE;
640 }
641
642 /* check partition alignment and total enhanced size */
643 if (conf->user.enh_size) {
644 if (conf->user.enh_size % mmc->hc_wp_grp_size ||
645 conf->user.enh_start % mmc->hc_wp_grp_size) {
646 printf("User data enhanced area not HC WP group "
647 "size aligned\n");
648 return -EINVAL;
649 }
650 part_attrs |= EXT_CSD_ENH_USR;
651 enh_size_mult = conf->user.enh_size / mmc->hc_wp_grp_size;
652 if (mmc->high_capacity) {
653 enh_start_addr = conf->user.enh_start;
654 } else {
655 enh_start_addr = (conf->user.enh_start << 9);
656 }
657 } else {
658 enh_size_mult = 0;
659 enh_start_addr = 0;
660 }
661 tot_enh_size_mult += enh_size_mult;
662
663 for (pidx = 0; pidx < 4; pidx++) {
664 if (conf->gp_part[pidx].size % mmc->hc_wp_grp_size) {
665 printf("GP%i partition not HC WP group size "
666 "aligned\n", pidx+1);
667 return -EINVAL;
668 }
669 gp_size_mult[pidx] = conf->gp_part[pidx].size / mmc->hc_wp_grp_size;
670 if (conf->gp_part[pidx].size && conf->gp_part[pidx].enhanced) {
671 part_attrs |= EXT_CSD_ENH_GP(pidx);
672 tot_enh_size_mult += gp_size_mult[pidx];
673 }
674 }
675
676 if (part_attrs && ! (mmc->part_support & ENHNCD_SUPPORT)) {
677 printf("Card does not support enhanced attribute\n");
678 return -EMEDIUMTYPE;
679 }
680
681 err = mmc_send_ext_csd(mmc, ext_csd);
682 if (err)
683 return err;
684
685 max_enh_size_mult =
686 (ext_csd[EXT_CSD_MAX_ENH_SIZE_MULT+2] << 16) +
687 (ext_csd[EXT_CSD_MAX_ENH_SIZE_MULT+1] << 8) +
688 ext_csd[EXT_CSD_MAX_ENH_SIZE_MULT];
689 if (tot_enh_size_mult > max_enh_size_mult) {
690 printf("Total enhanced size exceeds maximum (%u > %u)\n",
691 tot_enh_size_mult, max_enh_size_mult);
692 return -EMEDIUMTYPE;
693 }
694
8dda5b0e
DSC		 695 /* The default value of EXT_CSD_WR_REL_SET is device
696 * dependent, the values can only be changed if the
697 * EXT_CSD_HS_CTRL_REL bit is set. The values can be
698 * changed only once and before partitioning is completed. */
699 wr_rel_set = ext_csd[EXT_CSD_WR_REL_SET];
700 if (conf->user.wr_rel_change) {
701 if (conf->user.wr_rel_set)
702 wr_rel_set |= EXT_CSD_WR_DATA_REL_USR;
703 else
704 wr_rel_set &= ~EXT_CSD_WR_DATA_REL_USR;
705 }
706 for (pidx = 0; pidx < 4; pidx++) {
707 if (conf->gp_part[pidx].wr_rel_change) {
708 if (conf->gp_part[pidx].wr_rel_set)
709 wr_rel_set |= EXT_CSD_WR_DATA_REL_GP(pidx);
710 else
711 wr_rel_set &= ~EXT_CSD_WR_DATA_REL_GP(pidx);
712 }
713 }
714
715 if (wr_rel_set != ext_csd[EXT_CSD_WR_REL_SET] &&
716 !(ext_csd[EXT_CSD_WR_REL_PARAM] & EXT_CSD_HS_CTRL_REL)) {
717 puts("Card does not support host controlled partition write "
718 "reliability settings\n");
719 return -EMEDIUMTYPE;
720 }
721
ac9da0e0
DSC		 722 if (ext_csd[EXT_CSD_PARTITION_SETTING] &
723 EXT_CSD_PARTITION_SETTING_COMPLETED) {
724 printf("Card already partitioned\n");
725 return -EPERM;
726 }
727
728 if (mode == MMC_HWPART_CONF_CHECK)
729 return 0;
730
731 /* Partitioning requires high-capacity size definitions */
732 if (!(ext_csd[EXT_CSD_ERASE_GROUP_DEF] & 0x01)) {
733 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
734 EXT_CSD_ERASE_GROUP_DEF, 1);
735
736 if (err)
737 return err;
738
739 ext_csd[EXT_CSD_ERASE_GROUP_DEF] = 1;
740
741 /* update erase group size to be high-capacity */
742 mmc->erase_grp_size =
743 ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE] * 1024;
744
745 }
746
747 /* all OK, write the configuration */
748 for (i = 0; i < 4; i++) {
749 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
750 EXT_CSD_ENH_START_ADDR+i,
751 (enh_start_addr >> (i*8)) & 0xFF);
752 if (err)
753 return err;
754 }
755 for (i = 0; i < 3; i++) {
756 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
757 EXT_CSD_ENH_SIZE_MULT+i,
758 (enh_size_mult >> (i*8)) & 0xFF);
759 if (err)
760 return err;
761 }
762 for (pidx = 0; pidx < 4; pidx++) {
763 for (i = 0; i < 3; i++) {
764 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
765 EXT_CSD_GP_SIZE_MULT+pidx*3+i,
766 (gp_size_mult[pidx] >> (i*8)) & 0xFF);
767 if (err)
768 return err;
769 }
770 }
771 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
772 EXT_CSD_PARTITIONS_ATTRIBUTE, part_attrs);
773 if (err)
774 return err;
775
776 if (mode == MMC_HWPART_CONF_SET)
777 return 0;
778
8dda5b0e
DSC		 779 /* The WR_REL_SET is a write-once register but shall be
780 * written before setting PART_SETTING_COMPLETED. As it is
781 * write-once we can only write it when completing the
782 * partitioning. */
783 if (wr_rel_set != ext_csd[EXT_CSD_WR_REL_SET]) {
784 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
785 EXT_CSD_WR_REL_SET, wr_rel_set);
786 if (err)
787 return err;
788 }
789
ac9da0e0
DSC		 790 /* Setting PART_SETTING_COMPLETED confirms the partition
791 * configuration but it only becomes effective after power
792 * cycle, so we do not adjust the partition related settings
793 * in the mmc struct. */
794
795 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
796 EXT_CSD_PARTITION_SETTING,
797 EXT_CSD_PARTITION_SETTING_COMPLETED);
798 if (err)
799 return err;
800
801 return 0;
802}
803
48972d90
TR		 804int mmc_getcd(struct mmc *mmc)
805{
806 int cd;
807
808 cd = board_mmc_getcd(mmc);
809
d4e1da4e 810 if (cd < 0) {
93bfd616
PA		 811 if (mmc->cfg->ops->getcd)
812 cd = mmc->cfg->ops->getcd(mmc);
d4e1da4e
PK		 813 else
814 cd = 1;
815 }
48972d90
TR		 816
817 return cd;
818}
819
fdbb873e 820static int sd_switch(struct mmc *mmc, int mode, int group, u8 value, u8 *resp)
272cc70b
AF		 821{
822 struct mmc_cmd cmd;
823 struct mmc_data data;
824
825 /* Switch the frequency */
826 cmd.cmdidx = SD_CMD_SWITCH_FUNC;
827 cmd.resp_type = MMC_RSP_R1;
828 cmd.cmdarg = (mode << 31) | 0xffffff;
829 cmd.cmdarg &= ~(0xf << (group * 4));
830 cmd.cmdarg |= value << (group * 4);
272cc70b
AF		 831
832 data.dest = (char *)resp;
833 data.blocksize = 64;
834 data.blocks = 1;
835 data.flags = MMC_DATA_READ;
836
837 return mmc_send_cmd(mmc, &cmd, &data);
838}
839
840
fdbb873e 841static int sd_change_freq(struct mmc *mmc)
272cc70b
AF		 842{
843 int err;
844 struct mmc_cmd cmd;
f781dd38
A		 845 ALLOC_CACHE_ALIGN_BUFFER(uint, scr, 2);
846 ALLOC_CACHE_ALIGN_BUFFER(uint, switch_status, 16);
272cc70b
AF		 847 struct mmc_data data;
848 int timeout;
849
850 mmc->card_caps = 0;
851
d52ebf10
TC		 852 if (mmc_host_is_spi(mmc))
853 return 0;
854
272cc70b
AF		 855 /* Read the SCR to find out if this card supports higher speeds */
856 cmd.cmdidx = MMC_CMD_APP_CMD;
857 cmd.resp_type = MMC_RSP_R1;
858 cmd.cmdarg = mmc->rca << 16;
272cc70b
AF		 859
860 err = mmc_send_cmd(mmc, &cmd, NULL);
861
862 if (err)
863 return err;
864
865 cmd.cmdidx = SD_CMD_APP_SEND_SCR;
866 cmd.resp_type = MMC_RSP_R1;
867 cmd.cmdarg = 0;
272cc70b
AF		 868
869 timeout = 3;
870
871retry_scr:
f781dd38 872 data.dest = (char *)scr;
272cc70b
AF		 873 data.blocksize = 8;
874 data.blocks = 1;
875 data.flags = MMC_DATA_READ;
876
877 err = mmc_send_cmd(mmc, &cmd, &data);
878
879 if (err) {
880 if (timeout--)
881 goto retry_scr;
882
883 return err;
884 }
885
4e3d89ba
YK		 886 mmc->scr[0] = __be32_to_cpu(scr[0]);
887 mmc->scr[1] = __be32_to_cpu(scr[1]);
272cc70b
AF		 888
889 switch ((mmc->scr[0] >> 24) & 0xf) {
890 case 0:
891 mmc->version = SD_VERSION_1_0;
892 break;
893 case 1:
894 mmc->version = SD_VERSION_1_10;
895 break;
896 case 2:
897 mmc->version = SD_VERSION_2;
1741c64d
JC		 898 if ((mmc->scr[0] >> 15) & 0x1)
899 mmc->version = SD_VERSION_3;
272cc70b
AF		 900 break;
901 default:
902 mmc->version = SD_VERSION_1_0;
903 break;
904 }
905
b44c7083
AS		 906 if (mmc->scr[0] & SD_DATA_4BIT)
907 mmc->card_caps |= MMC_MODE_4BIT;
908
272cc70b
AF		 909 /* Version 1.0 doesn't support switching */
910 if (mmc->version == SD_VERSION_1_0)
911 return 0;
912
913 timeout = 4;
914 while (timeout--) {
915 err = sd_switch(mmc, SD_SWITCH_CHECK, 0, 1,
f781dd38 916 (u8 *)switch_status);
272cc70b
AF		 917
918 if (err)
919 return err;
920
921 /* The high-speed function is busy. Try again */
4e3d89ba 922 if (!(__be32_to_cpu(switch_status[7]) & SD_HIGHSPEED_BUSY))
272cc70b
AF		 923 break;
924 }
925
272cc70b 926 /* If high-speed isn't supported, we return */
4e3d89ba 927 if (!(__be32_to_cpu(switch_status[3]) & SD_HIGHSPEED_SUPPORTED))
272cc70b
AF		 928 return 0;
929
2c3fbf4c
ML		 930 /*
931 * If the host doesn't support SD_HIGHSPEED, do not switch card to
932 * HIGHSPEED mode even if the card support SD_HIGHSPPED.
933 * This can avoid furthur problem when the card runs in different
934 * mode between the host.
935 */
93bfd616
PA		 936 if (!((mmc->cfg->host_caps & MMC_MODE_HS_52MHz) &&
937 (mmc->cfg->host_caps & MMC_MODE_HS)))
2c3fbf4c
ML		 938 return 0;
939
f781dd38 940 err = sd_switch(mmc, SD_SWITCH_SWITCH, 0, 1, (u8 *)switch_status);
272cc70b
AF		 941
942 if (err)
943 return err;
944
4e3d89ba 945 if ((__be32_to_cpu(switch_status[4]) & 0x0f000000) == 0x01000000)
272cc70b
AF		 946 mmc->card_caps |= MMC_MODE_HS;
947
948 return 0;
949}
950
951/* frequency bases */
952/* divided by 10 to be nice to platforms without floating point */
5f837c2c 953static const int fbase[] = {
272cc70b
AF		 954 10000,
955 100000,
956 1000000,
957 10000000,
958};
959
960/* Multiplier values for TRAN_SPEED. Multiplied by 10 to be nice
961 * to platforms without floating point.
962 */
5f837c2c 963static const int multipliers[] = {
272cc70b
AF		 964 0, /* reserved */
965 10,
966 12,
967 13,
968 15,
969 20,
970 25,
971 30,
972 35,
973 40,
974 45,
975 50,
976 55,
977 60,
978 70,
979 80,
980};
981
fdbb873e 982static void mmc_set_ios(struct mmc *mmc)
272cc70b 983{
93bfd616
PA		 984 if (mmc->cfg->ops->set_ios)
985 mmc->cfg->ops->set_ios(mmc);
272cc70b
AF		 986}
987
988void mmc_set_clock(struct mmc *mmc, uint clock)
989{
93bfd616
PA		 990 if (clock > mmc->cfg->f_max)
991 clock = mmc->cfg->f_max;
272cc70b 992
93bfd616
PA		 993 if (clock < mmc->cfg->f_min)
994 clock = mmc->cfg->f_min;
272cc70b
AF		 995
996 mmc->clock = clock;
997
998 mmc_set_ios(mmc);
999}
1000
fdbb873e 1001static void mmc_set_bus_width(struct mmc *mmc, uint width)
272cc70b
AF		 1002{
1003 mmc->bus_width = width;
1004
1005 mmc_set_ios(mmc);
1006}
1007
fdbb873e 1008static int mmc_startup(struct mmc *mmc)
272cc70b 1009{
f866a46d 1010 int err, i;
272cc70b 1011 uint mult, freq;
639b7827 1012 u64 cmult, csize, capacity;
272cc70b 1013 struct mmc_cmd cmd;
8bfa195e
SG		 1014 ALLOC_CACHE_ALIGN_BUFFER(u8, ext_csd, MMC_MAX_BLOCK_LEN);
1015 ALLOC_CACHE_ALIGN_BUFFER(u8, test_csd, MMC_MAX_BLOCK_LEN);
5d4fc8d9 1016 int timeout = 1000;
0c453bb7 1017 bool has_parts = false;
8a0cf490 1018 bool part_completed;
272cc70b 1019
d52ebf10
TC		 1020#ifdef CONFIG_MMC_SPI_CRC_ON
1021 if (mmc_host_is_spi(mmc)) { /* enable CRC check for spi */
1022 cmd.cmdidx = MMC_CMD_SPI_CRC_ON_OFF;
1023 cmd.resp_type = MMC_RSP_R1;
1024 cmd.cmdarg = 1;
d52ebf10
TC		 1025 err = mmc_send_cmd(mmc, &cmd, NULL);
1026
1027 if (err)
1028 return err;
1029 }
1030#endif
1031
272cc70b 1032 /* Put the Card in Identify Mode */
d52ebf10
TC		 1033 cmd.cmdidx = mmc_host_is_spi(mmc) ? MMC_CMD_SEND_CID :
1034 MMC_CMD_ALL_SEND_CID; /* cmd not supported in spi */
272cc70b
AF		 1035 cmd.resp_type = MMC_RSP_R2;
1036 cmd.cmdarg = 0;
272cc70b
AF		 1037
1038 err = mmc_send_cmd(mmc, &cmd, NULL);
1039
1040 if (err)
1041 return err;
1042
1043 memcpy(mmc->cid, cmd.response, 16);
1044
1045 /*
1046 * For MMC cards, set the Relative Address.
1047 * For SD cards, get the Relatvie Address.
1048 * This also puts the cards into Standby State
1049 */
d52ebf10
TC		 1050 if (!mmc_host_is_spi(mmc)) { /* cmd not supported in spi */
1051 cmd.cmdidx = SD_CMD_SEND_RELATIVE_ADDR;
1052 cmd.cmdarg = mmc->rca << 16;
1053 cmd.resp_type = MMC_RSP_R6;
272cc70b 1054
d52ebf10 1055 err = mmc_send_cmd(mmc, &cmd, NULL);
272cc70b 1056
d52ebf10
TC		 1057 if (err)
1058 return err;
272cc70b 1059
d52ebf10
TC		 1060 if (IS_SD(mmc))
1061 mmc->rca = (cmd.response[0] >> 16) & 0xffff;
1062 }
272cc70b
AF		 1063
1064 /* Get the Card-Specific Data */
1065 cmd.cmdidx = MMC_CMD_SEND_CSD;
1066 cmd.resp_type = MMC_RSP_R2;
1067 cmd.cmdarg = mmc->rca << 16;
272cc70b
AF		 1068
1069 err = mmc_send_cmd(mmc, &cmd, NULL);
1070
5d4fc8d9
RR		 1071 /* Waiting for the ready status */
1072 mmc_send_status(mmc, timeout);
1073
272cc70b
AF		 1074 if (err)
1075 return err;
1076
998be3dd
RV		 1077 mmc->csd[0] = cmd.response[0];
1078 mmc->csd[1] = cmd.response[1];
1079 mmc->csd[2] = cmd.response[2];
1080 mmc->csd[3] = cmd.response[3];
272cc70b
AF		 1081
1082 if (mmc->version == MMC_VERSION_UNKNOWN) {
0b453ffe 1083 int version = (cmd.response[0] >> 26) & 0xf;
272cc70b
AF		 1084
1085 switch (version) {
1086 case 0:
1087 mmc->version = MMC_VERSION_1_2;
1088 break;
1089 case 1:
1090 mmc->version = MMC_VERSION_1_4;
1091 break;
1092 case 2:
1093 mmc->version = MMC_VERSION_2_2;
1094 break;
1095 case 3:
1096 mmc->version = MMC_VERSION_3;
1097 break;
1098 case 4:
1099 mmc->version = MMC_VERSION_4;
1100 break;
1101 default:
1102 mmc->version = MMC_VERSION_1_2;
1103 break;
1104 }
1105 }
1106
1107 /* divide frequency by 10, since the mults are 10x bigger */
0b453ffe
RV		 1108 freq = fbase[(cmd.response[0] & 0x7)];
1109 mult = multipliers[((cmd.response[0] >> 3) & 0xf)];
272cc70b
AF		 1110
1111 mmc->tran_speed = freq * mult;
1112
ab71188c 1113 mmc->dsr_imp = ((cmd.response[1] >> 12) & 0x1);
998be3dd 1114 mmc->read_bl_len = 1 << ((cmd.response[1] >> 16) & 0xf);
272cc70b
AF		 1115
1116 if (IS_SD(mmc))
1117 mmc->write_bl_len = mmc->read_bl_len;
1118 else
998be3dd 1119 mmc->write_bl_len = 1 << ((cmd.response[3] >> 22) & 0xf);
272cc70b
AF		 1120
1121 if (mmc->high_capacity) {
1122 csize = (mmc->csd[1] & 0x3f) << 16
1123 | (mmc->csd[2] & 0xffff0000) >> 16;
1124 cmult = 8;
1125 } else {
1126 csize = (mmc->csd[1] & 0x3ff) << 2
1127 | (mmc->csd[2] & 0xc0000000) >> 30;
1128 cmult = (mmc->csd[2] & 0x00038000) >> 15;
1129 }
1130
f866a46d
SW		 1131 mmc->capacity_user = (csize + 1) << (cmult + 2);
1132 mmc->capacity_user *= mmc->read_bl_len;
1133 mmc->capacity_boot = 0;
1134 mmc->capacity_rpmb = 0;
1135 for (i = 0; i < 4; i++)
1136 mmc->capacity_gp[i] = 0;
272cc70b 1137
8bfa195e
SG		 1138 if (mmc->read_bl_len > MMC_MAX_BLOCK_LEN)
1139 mmc->read_bl_len = MMC_MAX_BLOCK_LEN;
272cc70b 1140
8bfa195e
SG		 1141 if (mmc->write_bl_len > MMC_MAX_BLOCK_LEN)
1142 mmc->write_bl_len = MMC_MAX_BLOCK_LEN;
272cc70b 1143
ab71188c
MN		 1144 if ((mmc->dsr_imp) && (0xffffffff != mmc->dsr)) {
1145 cmd.cmdidx = MMC_CMD_SET_DSR;
1146 cmd.cmdarg = (mmc->dsr & 0xffff) << 16;
1147 cmd.resp_type = MMC_RSP_NONE;
1148 if (mmc_send_cmd(mmc, &cmd, NULL))
1149 printf("MMC: SET_DSR failed\n");
1150 }
1151
272cc70b 1152 /* Select the card, and put it into Transfer Mode */
d52ebf10
TC		 1153 if (!mmc_host_is_spi(mmc)) { /* cmd not supported in spi */
1154 cmd.cmdidx = MMC_CMD_SELECT_CARD;
fe8f7066 1155 cmd.resp_type = MMC_RSP_R1;
d52ebf10 1156 cmd.cmdarg = mmc->rca << 16;
d52ebf10 1157 err = mmc_send_cmd(mmc, &cmd, NULL);
272cc70b 1158
d52ebf10
TC		 1159 if (err)
1160 return err;
1161 }
272cc70b 1162
e6f99a56
LW		 1163 /*
1164 * For SD, its erase group is always one sector
1165 */
1166 mmc->erase_grp_size = 1;
bc897b1d 1167 mmc->part_config = MMCPART_NOAVAILABLE;
d23e2c09
SG		 1168 if (!IS_SD(mmc) && (mmc->version >= MMC_VERSION_4)) {
1169 /* check ext_csd version and capacity */
1170 err = mmc_send_ext_csd(mmc, ext_csd);
9cf199eb
DSC		 1171 if (err)
1172 return err;
1173 if (ext_csd[EXT_CSD_REV] >= 2) {
639b7827
YS		 1174 /*
1175 * According to the JEDEC Standard, the value of
1176 * ext_csd's capacity is valid if the value is more
1177 * than 2GB
1178 */
0560db18
LW		 1179 capacity = ext_csd[EXT_CSD_SEC_CNT] << 0
1180 | ext_csd[EXT_CSD_SEC_CNT + 1] << 8
1181 | ext_csd[EXT_CSD_SEC_CNT + 2] << 16
1182 | ext_csd[EXT_CSD_SEC_CNT + 3] << 24;
8bfa195e 1183 capacity *= MMC_MAX_BLOCK_LEN;
b1f1e821 1184 if ((capacity >> 20) > 2 * 1024)
f866a46d 1185 mmc->capacity_user = capacity;
d23e2c09 1186 }
bc897b1d 1187
64f4a619
JC		 1188 switch (ext_csd[EXT_CSD_REV]) {
1189 case 1:
1190 mmc->version = MMC_VERSION_4_1;
1191 break;
1192 case 2:
1193 mmc->version = MMC_VERSION_4_2;
1194 break;
1195 case 3:
1196 mmc->version = MMC_VERSION_4_3;
1197 break;
1198 case 5:
1199 mmc->version = MMC_VERSION_4_41;
1200 break;
1201 case 6:
1202 mmc->version = MMC_VERSION_4_5;
1203 break;
edab723b
MN		 1204 case 7:
1205 mmc->version = MMC_VERSION_5_0;
1206 break;
64f4a619
JC		 1207 }
1208
8a0cf490
DSC		 1209 /* The partition data may be non-zero but it is only
1210 * effective if PARTITION_SETTING_COMPLETED is set in
1211 * EXT_CSD, so ignore any data if this bit is not set,
1212 * except for enabling the high-capacity group size
1213 * definition (see below). */
1214 part_completed = !!(ext_csd[EXT_CSD_PARTITION_SETTING] &
1215 EXT_CSD_PARTITION_SETTING_COMPLETED);
1216
0c453bb7
DSC		 1217 /* store the partition info of emmc */
1218 mmc->part_support = ext_csd[EXT_CSD_PARTITIONING_SUPPORT];
1219 if ((ext_csd[EXT_CSD_PARTITIONING_SUPPORT] & PART_SUPPORT) ||
1220 ext_csd[EXT_CSD_BOOT_MULT])
1221 mmc->part_config = ext_csd[EXT_CSD_PART_CONF];
8a0cf490
DSC		 1222 if (part_completed &&
1223 (ext_csd[EXT_CSD_PARTITIONING_SUPPORT] & ENHNCD_SUPPORT))
0c453bb7
DSC		 1224 mmc->part_attr = ext_csd[EXT_CSD_PARTITIONS_ATTRIBUTE];
1225
1226 mmc->capacity_boot = ext_csd[EXT_CSD_BOOT_MULT] << 17;
1227
1228 mmc->capacity_rpmb = ext_csd[EXT_CSD_RPMB_MULT] << 17;
1229
1230 for (i = 0; i < 4; i++) {
1231 int idx = EXT_CSD_GP_SIZE_MULT + i * 3;
8a0cf490 1232 uint mult = (ext_csd[idx + 2] << 16) +
0c453bb7 1233 (ext_csd[idx + 1] << 8) + ext_csd[idx];
8a0cf490
DSC		 1234 if (mult)
1235 has_parts = true;
1236 if (!part_completed)
1237 continue;
1238 mmc->capacity_gp[i] = mult;
0c453bb7
DSC		 1239 mmc->capacity_gp[i] *=
1240 ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE];
1241 mmc->capacity_gp[i] *= ext_csd[EXT_CSD_HC_WP_GRP_SIZE];
f8e89d67 1242 mmc->capacity_gp[i] <<= 19;
0c453bb7
DSC		 1243 }
1244
8a0cf490
DSC		 1245 if (part_completed) {
1246 mmc->enh_user_size =
1247 (ext_csd[EXT_CSD_ENH_SIZE_MULT+2] << 16) +
1248 (ext_csd[EXT_CSD_ENH_SIZE_MULT+1] << 8) +
1249 ext_csd[EXT_CSD_ENH_SIZE_MULT];
1250 mmc->enh_user_size *= ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE];
1251 mmc->enh_user_size *= ext_csd[EXT_CSD_HC_WP_GRP_SIZE];
1252 mmc->enh_user_size <<= 19;
1253 mmc->enh_user_start =
1254 (ext_csd[EXT_CSD_ENH_START_ADDR+3] << 24) +
1255 (ext_csd[EXT_CSD_ENH_START_ADDR+2] << 16) +
1256 (ext_csd[EXT_CSD_ENH_START_ADDR+1] << 8) +
1257 ext_csd[EXT_CSD_ENH_START_ADDR];
1258 if (mmc->high_capacity)
1259 mmc->enh_user_start <<= 9;
1260 }
a7f852b6 1261
e6f99a56 1262 /*
1937e5aa
OM		 1263 * Host needs to enable ERASE_GRP_DEF bit if device is
1264 * partitioned. This bit will be lost every time after a reset
1265 * or power off. This will affect erase size.
e6f99a56 1266 */
8a0cf490 1267 if (part_completed)
0c453bb7 1268 has_parts = true;
1937e5aa 1269 if ((ext_csd[EXT_CSD_PARTITIONING_SUPPORT] & PART_SUPPORT) &&
0c453bb7
DSC		 1270 (ext_csd[EXT_CSD_PARTITIONS_ATTRIBUTE] & PART_ENH_ATTRIB))
1271 has_parts = true;
1272 if (has_parts) {
1937e5aa
OM		 1273 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
1274 EXT_CSD_ERASE_GROUP_DEF, 1);
1275
1276 if (err)
1277 return err;
021a8055
HP		 1278 else
1279 ext_csd[EXT_CSD_ERASE_GROUP_DEF] = 1;
037dc0ab 1280 }
1937e5aa 1281
037dc0ab 1282 if (ext_csd[EXT_CSD_ERASE_GROUP_DEF] & 0x01) {
1937e5aa 1283 /* Read out group size from ext_csd */
0560db18 1284 mmc->erase_grp_size =
a4ff9f83 1285 ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE] * 1024;
d7b29129
MN		 1286 /*
1287 * if high capacity and partition setting completed
1288 * SEC_COUNT is valid even if it is smaller than 2 GiB
1289 * JEDEC Standard JESD84-B45, 6.2.4
1290 */
8a0cf490 1291 if (mmc->high_capacity && part_completed) {
d7b29129
MN		 1292 capacity = (ext_csd[EXT_CSD_SEC_CNT]) |
1293 (ext_csd[EXT_CSD_SEC_CNT + 1] << 8) |
1294 (ext_csd[EXT_CSD_SEC_CNT + 2] << 16) |
1295 (ext_csd[EXT_CSD_SEC_CNT + 3] << 24);
1296 capacity *= MMC_MAX_BLOCK_LEN;
1297 mmc->capacity_user = capacity;
1298 }
8bfa195e 1299 } else {
1937e5aa 1300 /* Calculate the group size from the csd value. */
e6f99a56
LW		 1301 int erase_gsz, erase_gmul;
1302 erase_gsz = (mmc->csd[2] & 0x00007c00) >> 10;
1303 erase_gmul = (mmc->csd[2] & 0x000003e0) >> 5;
1304 mmc->erase_grp_size = (erase_gsz + 1)
1305 * (erase_gmul + 1);
1306 }
037dc0ab
DSC		 1307
1308 mmc->hc_wp_grp_size = 1024
1309 * ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE]
1310 * ext_csd[EXT_CSD_HC_WP_GRP_SIZE];
9e41a00b
DSC		 1311
1312 mmc->wr_rel_set = ext_csd[EXT_CSD_WR_REL_SET];
d23e2c09
SG		 1313 }
1314
f866a46d
SW		 1315 err = mmc_set_capacity(mmc, mmc->part_num);
1316 if (err)
1317 return err;
1318
272cc70b
AF		 1319 if (IS_SD(mmc))
1320 err = sd_change_freq(mmc);
1321 else
1322 err = mmc_change_freq(mmc);
1323
1324 if (err)
1325 return err;
1326
1327 /* Restrict card's capabilities by what the host can do */
93bfd616 1328 mmc->card_caps &= mmc->cfg->host_caps;
272cc70b
AF		 1329
1330 if (IS_SD(mmc)) {
1331 if (mmc->card_caps & MMC_MODE_4BIT) {
1332 cmd.cmdidx = MMC_CMD_APP_CMD;
1333 cmd.resp_type = MMC_RSP_R1;
1334 cmd.cmdarg = mmc->rca << 16;
272cc70b
AF		 1335
1336 err = mmc_send_cmd(mmc, &cmd, NULL);
1337 if (err)
1338 return err;
1339
1340 cmd.cmdidx = SD_CMD_APP_SET_BUS_WIDTH;
1341 cmd.resp_type = MMC_RSP_R1;
1342 cmd.cmdarg = 2;
272cc70b
AF		 1343 err = mmc_send_cmd(mmc, &cmd, NULL);
1344 if (err)
1345 return err;
1346
1347 mmc_set_bus_width(mmc, 4);
1348 }
1349
1350 if (mmc->card_caps & MMC_MODE_HS)
ad5fd922 1351 mmc->tran_speed = 50000000;
272cc70b 1352 else
ad5fd922 1353 mmc->tran_speed = 25000000;
fc5b32fb
AG		 1354 } else if (mmc->version >= MMC_VERSION_4) {
1355 /* Only version 4 of MMC supports wider bus widths */
7798f6db
AF		 1356 int idx;
1357
1358 /* An array of possible bus widths in order of preference */
1359 static unsigned ext_csd_bits[] = {
d22e3d46
JC		 1360 EXT_CSD_DDR_BUS_WIDTH_8,
1361 EXT_CSD_DDR_BUS_WIDTH_4,
7798f6db
AF		 1362 EXT_CSD_BUS_WIDTH_8,
1363 EXT_CSD_BUS_WIDTH_4,
1364 EXT_CSD_BUS_WIDTH_1,
1365 };
1366
1367 /* An array to map CSD bus widths to host cap bits */
1368 static unsigned ext_to_hostcaps[] = {
786e8f81
AG		 1369 [EXT_CSD_DDR_BUS_WIDTH_4] =
1370 MMC_MODE_DDR_52MHz | MMC_MODE_4BIT,
1371 [EXT_CSD_DDR_BUS_WIDTH_8] =
1372 MMC_MODE_DDR_52MHz | MMC_MODE_8BIT,
7798f6db
AF		 1373 [EXT_CSD_BUS_WIDTH_4] = MMC_MODE_4BIT,
1374 [EXT_CSD_BUS_WIDTH_8] = MMC_MODE_8BIT,
1375 };
1376
1377 /* An array to map chosen bus width to an integer */
1378 static unsigned widths[] = {
d22e3d46 1379 8, 4, 8, 4, 1,
7798f6db
AF		 1380 };
1381
1382 for (idx=0; idx < ARRAY_SIZE(ext_csd_bits); idx++) {
1383 unsigned int extw = ext_csd_bits[idx];
786e8f81 1384 unsigned int caps = ext_to_hostcaps[extw];
7798f6db 1385
bf477073
AG		 1386 /*
1387 * If the bus width is still not changed,
1388 * don't try to set the default again.
1389 * Otherwise, recover from switch attempts
1390 * by switching to 1-bit bus width.
1391 */
1392 if (extw == EXT_CSD_BUS_WIDTH_1 &&
1393 mmc->bus_width == 1) {
1394 err = 0;
1395 break;
1396 }
1397
7798f6db 1398 /*
786e8f81
AG		 1399 * Check to make sure the card and controller support
1400 * these capabilities
7798f6db 1401 */
786e8f81 1402 if ((mmc->card_caps & caps) != caps)
7798f6db
AF		 1403 continue;
1404
272cc70b 1405 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
7798f6db 1406 EXT_CSD_BUS_WIDTH, extw);
272cc70b
AF		 1407
1408 if (err)
4137894e 1409 continue;
272cc70b 1410
786e8f81 1411 mmc->ddr_mode = (caps & MMC_MODE_DDR_52MHz) ? 1 : 0;
7798f6db 1412 mmc_set_bus_width(mmc, widths[idx]);
4137894e
LW		 1413
1414 err = mmc_send_ext_csd(mmc, test_csd);
786e8f81
AG		 1415
1416 if (err)
1417 continue;
1418
786a27b7 1419 /* Only compare read only fields */
786e8f81
AG		 1420 if (ext_csd[EXT_CSD_PARTITIONING_SUPPORT]
1421 == test_csd[EXT_CSD_PARTITIONING_SUPPORT] &&
1422 ext_csd[EXT_CSD_HC_WP_GRP_SIZE]
1423 == test_csd[EXT_CSD_HC_WP_GRP_SIZE] &&
1424 ext_csd[EXT_CSD_REV]
1425 == test_csd[EXT_CSD_REV] &&
1426 ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE]
1427 == test_csd[EXT_CSD_HC_ERASE_GRP_SIZE] &&
1428 memcmp(&ext_csd[EXT_CSD_SEC_CNT],
1429 &test_csd[EXT_CSD_SEC_CNT], 4) == 0)
4137894e 1430 break;
786e8f81
AG		 1431 else
1432 err = SWITCH_ERR;
272cc70b
AF		 1433 }
1434
786e8f81
AG		 1435 if (err)
1436 return err;
1437
272cc70b
AF		 1438 if (mmc->card_caps & MMC_MODE_HS) {
1439 if (mmc->card_caps & MMC_MODE_HS_52MHz)
ad5fd922 1440 mmc->tran_speed = 52000000;
272cc70b 1441 else
ad5fd922
JC		 1442 mmc->tran_speed = 26000000;
1443 }
272cc70b
AF		 1444 }
1445
ad5fd922
JC		 1446 mmc_set_clock(mmc, mmc->tran_speed);
1447
5af8f45c
AG		 1448 /* Fix the block length for DDR mode */
1449 if (mmc->ddr_mode) {
1450 mmc->read_bl_len = MMC_MAX_BLOCK_LEN;
1451 mmc->write_bl_len = MMC_MAX_BLOCK_LEN;
1452 }
1453
272cc70b
AF		 1454 /* fill in device description */
1455 mmc->block_dev.lun = 0;
1456 mmc->block_dev.type = 0;
1457 mmc->block_dev.blksz = mmc->read_bl_len;
0472fbfd 1458 mmc->block_dev.log2blksz = LOG2(mmc->block_dev.blksz);
9b1f942c 1459 mmc->block_dev.lba = lldiv(mmc->capacity, mmc->read_bl_len);
56196826 1460#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
babce5f6
TH		 1461 sprintf(mmc->block_dev.vendor, "Man %06x Snr %04x%04x",
1462 mmc->cid[0] >> 24, (mmc->cid[2] & 0xffff),
1463 (mmc->cid[3] >> 16) & 0xffff);
1464 sprintf(mmc->block_dev.product, "%c%c%c%c%c%c", mmc->cid[0] & 0xff,
1465 (mmc->cid[1] >> 24), (mmc->cid[1] >> 16) & 0xff,
1466 (mmc->cid[1] >> 8) & 0xff, mmc->cid[1] & 0xff,
1467 (mmc->cid[2] >> 24) & 0xff);
1468 sprintf(mmc->block_dev.revision, "%d.%d", (mmc->cid[2] >> 20) & 0xf,
1469 (mmc->cid[2] >> 16) & 0xf);
56196826
PB		 1470#else
1471 mmc->block_dev.vendor[0] = 0;
1472 mmc->block_dev.product[0] = 0;
1473 mmc->block_dev.revision[0] = 0;
1474#endif
122efd43 1475#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBDISK_SUPPORT)
272cc70b 1476 init_part(&mmc->block_dev);
122efd43 1477#endif
272cc70b
AF		 1478
1479 return 0;
1480}
1481
fdbb873e 1482static int mmc_send_if_cond(struct mmc *mmc)
272cc70b
AF		 1483{
1484 struct mmc_cmd cmd;
1485 int err;
1486
1487 cmd.cmdidx = SD_CMD_SEND_IF_COND;
1488 /* We set the bit if the host supports voltages between 2.7 and 3.6 V */
93bfd616 1489 cmd.cmdarg = ((mmc->cfg->voltages & 0xff8000) != 0) << 8 | 0xaa;
272cc70b 1490 cmd.resp_type = MMC_RSP_R7;
272cc70b
AF		 1491
1492 err = mmc_send_cmd(mmc, &cmd, NULL);
1493
1494 if (err)
1495 return err;
1496
998be3dd 1497 if ((cmd.response[0] & 0xff) != 0xaa)
272cc70b
AF		 1498 return UNUSABLE_ERR;
1499 else
1500 mmc->version = SD_VERSION_2;
1501
1502 return 0;
1503}
1504
93bfd616
PA		 1505/* not used any more */
1506int __deprecated mmc_register(struct mmc *mmc)
1507{
1508#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
1509 printf("%s is deprecated! use mmc_create() instead.\n", __func__);
1510#endif
1511 return -1;
1512}
1513
1514struct mmc *mmc_create(const struct mmc_config *cfg, void *priv)
272cc70b 1515{
93bfd616
PA		 1516 struct mmc *mmc;
1517
1518 /* quick validation */
1519 if (cfg == NULL || cfg->ops == NULL || cfg->ops->send_cmd == NULL ||
1520 cfg->f_min == 0 || cfg->f_max == 0 || cfg->b_max == 0)
1521 return NULL;
1522
1523 mmc = calloc(1, sizeof(*mmc));
1524 if (mmc == NULL)
1525 return NULL;
1526
1527 mmc->cfg = cfg;
1528 mmc->priv = priv;
1529
1530 /* the following chunk was mmc_register() */
1531
ab71188c
MN		 1532 /* Setup dsr related values */
1533 mmc->dsr_imp = 0;
1534 mmc->dsr = 0xffffffff;
272cc70b
AF		 1535 /* Setup the universal parts of the block interface just once */
1536 mmc->block_dev.if_type = IF_TYPE_MMC;
1537 mmc->block_dev.dev = cur_dev_num++;
1538 mmc->block_dev.removable = 1;
1539 mmc->block_dev.block_read = mmc_bread;
1540 mmc->block_dev.block_write = mmc_bwrite;
e6f99a56 1541 mmc->block_dev.block_erase = mmc_berase;
272cc70b 1542
93bfd616
PA		 1543 /* setup initial part type */
1544 mmc->block_dev.part_type = mmc->cfg->part_type;
272cc70b 1545
93bfd616 1546 INIT_LIST_HEAD(&mmc->link);
272cc70b 1547
93bfd616
PA		 1548 list_add_tail(&mmc->link, &mmc_devices);
1549
1550 return mmc;
1551}
1552
1553void mmc_destroy(struct mmc *mmc)
1554{
1555 /* only freeing memory for now */
1556 free(mmc);
272cc70b
AF		 1557}
1558
df3fc526 1559#ifdef CONFIG_PARTITIONS
272cc70b
AF		 1560block_dev_desc_t *mmc_get_dev(int dev)
1561{
1562 struct mmc *mmc = find_mmc_device(dev);
6bb4b4bc 1563 if (!mmc || mmc_init(mmc))
40242bc3 1564 return NULL;
272cc70b 1565
40242bc3 1566 return &mmc->block_dev;
272cc70b 1567}
df3fc526 1568#endif
272cc70b 1569
95de9ab2
PK		 1570/* board-specific MMC power initializations. */
1571__weak void board_mmc_power_init(void)
1572{
1573}
1574
e9550449 1575int mmc_start_init(struct mmc *mmc)
272cc70b 1576{
afd5932b 1577 int err;
272cc70b 1578
ab769f22 1579 /* we pretend there's no card when init is NULL */
93bfd616 1580 if (mmc_getcd(mmc) == 0 || mmc->cfg->ops->init == NULL) {
48972d90 1581 mmc->has_init = 0;
56196826 1582#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
48972d90 1583 printf("MMC: no card present\n");
56196826 1584#endif
48972d90
TR		 1585 return NO_CARD_ERR;
1586 }
1587
bc897b1d
LW		 1588 if (mmc->has_init)
1589 return 0;
1590
95de9ab2
PK		 1591 board_mmc_power_init();
1592
ab769f22 1593 /* made sure it's not NULL earlier */
93bfd616 1594 err = mmc->cfg->ops->init(mmc);
272cc70b
AF		 1595
1596 if (err)
1597 return err;
1598
786e8f81 1599 mmc->ddr_mode = 0;
b86b85e2
IY		 1600 mmc_set_bus_width(mmc, 1);
1601 mmc_set_clock(mmc, 1);
1602
272cc70b
AF		 1603 /* Reset the Card */
1604 err = mmc_go_idle(mmc);
1605
1606 if (err)
1607 return err;
1608
bc897b1d
LW		 1609 /* The internal partition reset to user partition(0) at every CMD0*/
1610 mmc->part_num = 0;
1611
272cc70b 1612 /* Test for SD version 2 */
afd5932b 1613 err = mmc_send_if_cond(mmc);
272cc70b 1614
272cc70b
AF		 1615 /* Now try to get the SD card's operating condition */
1616 err = sd_send_op_cond(mmc);
1617
1618 /* If the command timed out, we check for an MMC card */
1619 if (err == TIMEOUT) {
1620 err = mmc_send_op_cond(mmc);
1621
e9550449 1622 if (err && err != IN_PROGRESS) {
56196826 1623#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
272cc70b 1624 printf("Card did not respond to voltage select!\n");
56196826 1625#endif
272cc70b
AF		 1626 return UNUSABLE_ERR;
1627 }
1628 }
1629
e9550449
CLC		 1630 if (err == IN_PROGRESS)
1631 mmc->init_in_progress = 1;
1632
1633 return err;
1634}
1635
1636static int mmc_complete_init(struct mmc *mmc)
1637{
1638 int err = 0;
1639
1640 if (mmc->op_cond_pending)
1641 err = mmc_complete_op_cond(mmc);
1642
1643 if (!err)
1644 err = mmc_startup(mmc);
bc897b1d
LW		 1645 if (err)
1646 mmc->has_init = 0;
1647 else
1648 mmc->has_init = 1;
e9550449
CLC		 1649 mmc->init_in_progress = 0;
1650 return err;
1651}
1652
1653int mmc_init(struct mmc *mmc)
1654{
1655 int err = IN_PROGRESS;
d803fea5 1656 unsigned start;
e9550449
CLC		 1657
1658 if (mmc->has_init)
1659 return 0;
d803fea5
MZ		 1660
1661 start = get_timer(0);
1662
e9550449
CLC		 1663 if (!mmc->init_in_progress)
1664 err = mmc_start_init(mmc);
1665
1666 if (!err || err == IN_PROGRESS)
1667 err = mmc_complete_init(mmc);
1668 debug("%s: %d, time %lu\n", __func__, err, get_timer(start));
bc897b1d 1669 return err;
272cc70b
AF		 1670}
1671
ab71188c
MN		 1672int mmc_set_dsr(struct mmc *mmc, u16 val)
1673{
1674 mmc->dsr = val;
1675 return 0;
1676}
1677
cee9ab7c
JH		 1678/* CPU-specific MMC initializations */
1679__weak int cpu_mmc_init(bd_t *bis)
272cc70b
AF		 1680{
1681 return -1;
1682}
1683
cee9ab7c
JH		 1684/* board-specific MMC initializations. */
1685__weak int board_mmc_init(bd_t *bis)
1686{
1687 return -1;
1688}
272cc70b 1689
56196826
PB		 1690#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
1691
272cc70b
AF		 1692void print_mmc_devices(char separator)
1693{
1694 struct mmc *m;
1695 struct list_head *entry;
34dd9284 1696 char *mmc_type;
272cc70b
AF		 1697
1698 list_for_each(entry, &mmc_devices) {
1699 m = list_entry(entry, struct mmc, link);
1700
34dd9284
PM		 1701 if (m->has_init)
1702 mmc_type = IS_SD(m) ? "SD" : "eMMC";
1703 else
1704 mmc_type = NULL;
1705
93bfd616 1706 printf("%s: %d", m->cfg->name, m->block_dev.dev);
34dd9284
PM		 1707 if (mmc_type)
1708 printf(" (%s)", mmc_type);
272cc70b 1709
e75eaf10
LP		 1710 if (entry->next != &mmc_devices) {
1711 printf("%c", separator);
1712 if (separator != '\n')
1713 puts (" ");
1714 }
272cc70b
AF		 1715 }
1716
1717 printf("\n");
1718}
1719
56196826
PB		 1720#else
1721void print_mmc_devices(char separator) { }
1722#endif
1723
ea6ebe21
LW		 1724int get_mmc_num(void)
1725{
1726 return cur_dev_num;
1727}
1728
e9550449
CLC		 1729void mmc_set_preinit(struct mmc *mmc, int preinit)
1730{
1731 mmc->preinit = preinit;
1732}
1733
1734static void do_preinit(void)
1735{
1736 struct mmc *m;
1737 struct list_head *entry;
1738
1739 list_for_each(entry, &mmc_devices) {
1740 m = list_entry(entry, struct mmc, link);
1741
1742 if (m->preinit)
1743 mmc_start_init(m);
1744 }
1745}
1746
1747
272cc70b
AF		 1748int mmc_initialize(bd_t *bis)
1749{
1750 INIT_LIST_HEAD (&mmc_devices);
1751 cur_dev_num = 0;
1752
1753 if (board_mmc_init(bis) < 0)
1754 cpu_mmc_init(bis);
1755
bb0dc108 1756#ifndef CONFIG_SPL_BUILD
272cc70b 1757 print_mmc_devices(',');
bb0dc108 1758#endif
272cc70b 1759
e9550449 1760 do_preinit();
272cc70b
AF		 1761 return 0;
1762}
3690d6d6
A		 1763
1764#ifdef CONFIG_SUPPORT_EMMC_BOOT
1765/*
1766 * This function changes the size of boot partition and the size of rpmb
1767 * partition present on EMMC devices.
1768 *
1769 * Input Parameters:
1770 * struct *mmc: pointer for the mmc device strcuture
1771 * bootsize: size of boot partition
1772 * rpmbsize: size of rpmb partition
1773 *
1774 * Returns 0 on success.
1775 */
1776
1777int mmc_boot_partition_size_change(struct mmc *mmc, unsigned long bootsize,
1778 unsigned long rpmbsize)
1779{
1780 int err;
1781 struct mmc_cmd cmd;
1782
1783 /* Only use this command for raw EMMC moviNAND. Enter backdoor mode */
1784 cmd.cmdidx = MMC_CMD_RES_MAN;
1785 cmd.resp_type = MMC_RSP_R1b;
1786 cmd.cmdarg = MMC_CMD62_ARG1;
1787
1788 err = mmc_send_cmd(mmc, &cmd, NULL);
1789 if (err) {
1790 debug("mmc_boot_partition_size_change: Error1 = %d\n", err);
1791 return err;
1792 }
1793
1794 /* Boot partition changing mode */
1795 cmd.cmdidx = MMC_CMD_RES_MAN;
1796 cmd.resp_type = MMC_RSP_R1b;
1797 cmd.cmdarg = MMC_CMD62_ARG2;
1798
1799 err = mmc_send_cmd(mmc, &cmd, NULL);
1800 if (err) {
1801 debug("mmc_boot_partition_size_change: Error2 = %d\n", err);
1802 return err;
1803 }
1804 /* boot partition size is multiple of 128KB */
1805 bootsize = (bootsize * 1024) / 128;
1806
1807 /* Arg: boot partition size */
1808 cmd.cmdidx = MMC_CMD_RES_MAN;
1809 cmd.resp_type = MMC_RSP_R1b;
1810 cmd.cmdarg = bootsize;
1811
1812 err = mmc_send_cmd(mmc, &cmd, NULL);
1813 if (err) {
1814 debug("mmc_boot_partition_size_change: Error3 = %d\n", err);
1815 return err;
1816 }
1817 /* RPMB partition size is multiple of 128KB */
1818 rpmbsize = (rpmbsize * 1024) / 128;
1819 /* Arg: RPMB partition size */
1820 cmd.cmdidx = MMC_CMD_RES_MAN;
1821 cmd.resp_type = MMC_RSP_R1b;
1822 cmd.cmdarg = rpmbsize;
1823
1824 err = mmc_send_cmd(mmc, &cmd, NULL);
1825 if (err) {
1826 debug("mmc_boot_partition_size_change: Error4 = %d\n", err);
1827 return err;
1828 }
1829 return 0;
1830}
1831
5a99b9de
TR		 1832/*
1833 * Modify EXT_CSD[177] which is BOOT_BUS_WIDTH
1834 * based on the passed in values for BOOT_BUS_WIDTH, RESET_BOOT_BUS_WIDTH
1835 * and BOOT_MODE.
1836 *
1837 * Returns 0 on success.
1838 */
1839int mmc_set_boot_bus_width(struct mmc *mmc, u8 width, u8 reset, u8 mode)
1840{
1841 int err;
1842
1843 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_BOOT_BUS_WIDTH,
1844 EXT_CSD_BOOT_BUS_WIDTH_MODE(mode) |
1845 EXT_CSD_BOOT_BUS_WIDTH_RESET(reset) |
1846 EXT_CSD_BOOT_BUS_WIDTH_WIDTH(width));
1847
1848 if (err)
1849 return err;
1850 return 0;
1851}
1852
792970b0
TR		 1853/*
1854 * Modify EXT_CSD[179] which is PARTITION_CONFIG (formerly BOOT_CONFIG)
1855 * based on the passed in values for BOOT_ACK, BOOT_PARTITION_ENABLE and
1856 * PARTITION_ACCESS.
1857 *
1858 * Returns 0 on success.
1859 */
1860int mmc_set_part_conf(struct mmc *mmc, u8 ack, u8 part_num, u8 access)
1861{
1862 int err;
1863
1864 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_PART_CONF,
1865 EXT_CSD_BOOT_ACK(ack) |
1866 EXT_CSD_BOOT_PART_NUM(part_num) |
1867 EXT_CSD_PARTITION_ACCESS(access));
1868
1869 if (err)
1870 return err;
1871 return 0;
1872}
33ace362
TR		 1873
1874/*
1875 * Modify EXT_CSD[162] which is RST_n_FUNCTION based on the given value
1876 * for enable. Note that this is a write-once field for non-zero values.
1877 *
1878 * Returns 0 on success.
1879 */
1880int mmc_set_rst_n_function(struct mmc *mmc, u8 enable)
1881{
1882 return mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_RST_N_FUNCTION,
1883 enable);
1884}
3690d6d6 1885#endif
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