[thirdparty/u-boot.git] / drivers / mmc / mxcmmc.c

/*
 *  This is a driver for the SDHC controller found in Freescale MX2/MX3
 *  SoCs. It is basically the same hardware as found on MX1 (imxmmc.c).
 *  Unlike the hardware found on MX1, this hardware just works and does
 *  not need all the quirks found in imxmmc.c, hence the seperate driver.
 *
 *  Copyright (C) 2009 Ilya Yanok, <yanok@emcraft.com>
 *  Copyright (C) 2008 Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>
 *  Copyright (C) 2006 Pavel Pisa, PiKRON <ppisa@pikron.com>
 *
 *  derived from pxamci.c by Russell King
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 */

#include <config.h>
#include <common.h>
#include <command.h>
#include <mmc.h>
#include <part.h>
#include <malloc.h>
#include <mmc.h>
#include <time.h>
#include <linux/errno.h>
#include <asm/io.h>
#include <asm/arch/clock.h>

#define DRIVER_NAME "mxc-mmc"

struct mxcmci_regs {
	u32 str_stp_clk;
	u32 status;
	u32 clk_rate;
	u32 cmd_dat_cont;
	u32 res_to;
	u32 read_to;
	u32 blk_len;
	u32 nob;
	u32 rev_no;
	u32 int_cntr;
	u32 cmd;
	u32 arg;
	u32 pad;
	u32 res_fifo;
	u32 buffer_access;
};

#define STR_STP_CLK_RESET               (1 << 3)
#define STR_STP_CLK_START_CLK           (1 << 1)
#define STR_STP_CLK_STOP_CLK            (1 << 0)

#define STATUS_CARD_INSERTION		(1 << 31)
#define STATUS_CARD_REMOVAL		(1 << 30)
#define STATUS_YBUF_EMPTY		(1 << 29)
#define STATUS_XBUF_EMPTY		(1 << 28)
#define STATUS_YBUF_FULL		(1 << 27)
#define STATUS_XBUF_FULL		(1 << 26)
#define STATUS_BUF_UND_RUN		(1 << 25)
#define STATUS_BUF_OVFL			(1 << 24)
#define STATUS_SDIO_INT_ACTIVE		(1 << 14)
#define STATUS_END_CMD_RESP		(1 << 13)
#define STATUS_WRITE_OP_DONE		(1 << 12)
#define STATUS_DATA_TRANS_DONE		(1 << 11)
#define STATUS_READ_OP_DONE		(1 << 11)
#define STATUS_WR_CRC_ERROR_CODE_MASK	(3 << 10)
#define STATUS_CARD_BUS_CLK_RUN		(1 << 8)
#define STATUS_BUF_READ_RDY		(1 << 7)
#define STATUS_BUF_WRITE_RDY		(1 << 6)
#define STATUS_RESP_CRC_ERR		(1 << 5)
#define STATUS_CRC_READ_ERR		(1 << 3)
#define STATUS_CRC_WRITE_ERR		(1 << 2)
#define STATUS_TIME_OUT_RESP		(1 << 1)
#define STATUS_TIME_OUT_READ		(1 << 0)
#define STATUS_ERR_MASK			0x2f

#define CMD_DAT_CONT_CMD_RESP_LONG_OFF	(1 << 12)
#define CMD_DAT_CONT_STOP_READWAIT	(1 << 11)
#define CMD_DAT_CONT_START_READWAIT	(1 << 10)
#define CMD_DAT_CONT_BUS_WIDTH_4	(2 << 8)
#define CMD_DAT_CONT_INIT		(1 << 7)
#define CMD_DAT_CONT_WRITE		(1 << 4)
#define CMD_DAT_CONT_DATA_ENABLE	(1 << 3)
#define CMD_DAT_CONT_RESPONSE_48BIT_CRC	(1 << 0)
#define CMD_DAT_CONT_RESPONSE_136BIT	(2 << 0)
#define CMD_DAT_CONT_RESPONSE_48BIT	(3 << 0)

#define INT_SDIO_INT_WKP_EN		(1 << 18)
#define INT_CARD_INSERTION_WKP_EN	(1 << 17)
#define INT_CARD_REMOVAL_WKP_EN		(1 << 16)
#define INT_CARD_INSERTION_EN		(1 << 15)
#define INT_CARD_REMOVAL_EN		(1 << 14)
#define INT_SDIO_IRQ_EN			(1 << 13)
#define INT_DAT0_EN			(1 << 12)
#define INT_BUF_READ_EN			(1 << 4)
#define INT_BUF_WRITE_EN		(1 << 3)
#define INT_END_CMD_RES_EN		(1 << 2)
#define INT_WRITE_OP_DONE_EN		(1 << 1)
#define INT_READ_OP_EN			(1 << 0)

struct mxcmci_host {
	struct mmc		*mmc;
	struct mxcmci_regs	*base;
	int			irq;
	int			detect_irq;
	int			dma;
	int			do_dma;
	unsigned int		power_mode;

	struct mmc_cmd		*cmd;
	struct mmc_data		*data;

	unsigned int		dma_nents;
	unsigned int		datasize;
	unsigned int		dma_dir;

	u16			rev_no;
	unsigned int		cmdat;

	int			clock;
};

static struct mxcmci_host mxcmci_host;

/* maintainer note: do we really want to have a global host pointer? */
static struct mxcmci_host *host = &mxcmci_host;

static inline int mxcmci_use_dma(struct mxcmci_host *host)
{
	return host->do_dma;
}

static void mxcmci_softreset(struct mxcmci_host *host)
{
	int i;

	/* reset sequence */
	writel(STR_STP_CLK_RESET, &host->base->str_stp_clk);
	writel(STR_STP_CLK_RESET | STR_STP_CLK_START_CLK,
			&host->base->str_stp_clk);

	for (i = 0; i < 8; i++)
		writel(STR_STP_CLK_START_CLK, &host->base->str_stp_clk);

	writel(0xff, &host->base->res_to);
}

static void mxcmci_setup_data(struct mxcmci_host *host, struct mmc_data *data)
{
	unsigned int nob = data->blocks;
	unsigned int blksz = data->blocksize;
	unsigned int datasize = nob * blksz;

	host->data = data;

	writel(nob, &host->base->nob);
	writel(blksz, &host->base->blk_len);
	host->datasize = datasize;
}

static int mxcmci_start_cmd(struct mxcmci_host *host, struct mmc_cmd *cmd,
		unsigned int cmdat)
{
	if (host->cmd != NULL)
		printf("mxcmci: error!\n");
	host->cmd = cmd;

	switch (cmd->resp_type) {
	case MMC_RSP_R1: /* short CRC, OPCODE */
	case MMC_RSP_R1b:/* short CRC, OPCODE, BUSY */
		cmdat |= CMD_DAT_CONT_RESPONSE_48BIT_CRC;
		break;
	case MMC_RSP_R2: /* long 136 bit + CRC */
		cmdat |= CMD_DAT_CONT_RESPONSE_136BIT;
		break;
	case MMC_RSP_R3: /* short */
		cmdat |= CMD_DAT_CONT_RESPONSE_48BIT;
		break;
	case MMC_RSP_NONE:
		break;
	default:
		printf("mxcmci: unhandled response type 0x%x\n",
				cmd->resp_type);
		return -EINVAL;
	}

	writel(cmd->cmdidx, &host->base->cmd);
	writel(cmd->cmdarg, &host->base->arg);
	writel(cmdat, &host->base->cmd_dat_cont);

	return 0;
}

static void mxcmci_finish_request(struct mxcmci_host *host,
		struct mmc_cmd *cmd, struct mmc_data *data)
{
	host->cmd = NULL;
	host->data = NULL;
}

static int mxcmci_finish_data(struct mxcmci_host *host, unsigned int stat)
{
	int data_error = 0;

	if (stat & STATUS_ERR_MASK) {
		printf("request failed. status: 0x%08x\n",
				stat);
		if (stat & STATUS_CRC_READ_ERR) {
			data_error = -EILSEQ;
		} else if (stat & STATUS_CRC_WRITE_ERR) {
			u32 err_code = (stat >> 9) & 0x3;
			if (err_code == 2) /* No CRC response */
				data_error = -ETIMEDOUT;
			else
				data_error = -EILSEQ;
		} else if (stat & STATUS_TIME_OUT_READ) {
			data_error = -ETIMEDOUT;
		} else {
			data_error = -EIO;
		}
	}

	host->data = NULL;

	return data_error;
}

static int mxcmci_read_response(struct mxcmci_host *host, unsigned int stat)
{
	struct mmc_cmd *cmd = host->cmd;
	int i;
	u32 a, b, c;
	u32 *resp = (u32 *)cmd->response;

	if (!cmd)
		return 0;

	if (stat & STATUS_TIME_OUT_RESP) {
		printf("CMD TIMEOUT\n");
		return -ETIMEDOUT;
	} else if (stat & STATUS_RESP_CRC_ERR && cmd->resp_type & MMC_RSP_CRC) {
		printf("cmd crc error\n");
		return -EILSEQ;
	}

	if (cmd->resp_type & MMC_RSP_PRESENT) {
		if (cmd->resp_type & MMC_RSP_136) {
			for (i = 0; i < 4; i++) {
				a = readl(&host->base->res_fifo) & 0xFFFF;
				b = readl(&host->base->res_fifo) & 0xFFFF;
				resp[i] = a << 16 | b;
			}
		} else {
			a = readl(&host->base->res_fifo) & 0xFFFF;
			b = readl(&host->base->res_fifo) & 0xFFFF;
			c = readl(&host->base->res_fifo) & 0xFFFF;
			resp[0] = a << 24 | b << 8 | c >> 8;
		}
	}
	return 0;
}

static int mxcmci_poll_status(struct mxcmci_host *host, u32 mask)
{
	u32 stat;
	unsigned long timeout = get_ticks() + CONFIG_SYS_HZ;

	do {
		stat = readl(&host->base->status);
		if (stat & STATUS_ERR_MASK)
			return stat;
		if (timeout < get_ticks())
			return STATUS_TIME_OUT_READ;
		if (stat & mask)
			return 0;
	} while (1);
}

static int mxcmci_pull(struct mxcmci_host *host, void *_buf, int bytes)
{
	unsigned int stat;
	u32 *buf = _buf;

	while (bytes > 3) {
		stat = mxcmci_poll_status(host,
				STATUS_BUF_READ_RDY | STATUS_READ_OP_DONE);
		if (stat)
			return stat;
		*buf++ = readl(&host->base->buffer_access);
		bytes -= 4;
	}

	if (bytes) {
		u8 *b = (u8 *)buf;
		u32 tmp;

		stat = mxcmci_poll_status(host,
				STATUS_BUF_READ_RDY | STATUS_READ_OP_DONE);
		if (stat)
			return stat;
		tmp = readl(&host->base->buffer_access);
		memcpy(b, &tmp, bytes);
	}

	return 0;
}

static int mxcmci_push(struct mxcmci_host *host, const void *_buf, int bytes)
{
	unsigned int stat;
	const u32 *buf = _buf;

	while (bytes > 3) {
		stat = mxcmci_poll_status(host, STATUS_BUF_WRITE_RDY);
		if (stat)
			return stat;
		writel(*buf++, &host->base->buffer_access);
		bytes -= 4;
	}

	if (bytes) {
		const u8 *b = (u8 *)buf;
		u32 tmp;

		stat = mxcmci_poll_status(host, STATUS_BUF_WRITE_RDY);
		if (stat)
			return stat;

		memcpy(&tmp, b, bytes);
		writel(tmp, &host->base->buffer_access);
	}

	stat = mxcmci_poll_status(host, STATUS_BUF_WRITE_RDY);
	if (stat)
		return stat;

	return 0;
}

static int mxcmci_transfer_data(struct mxcmci_host *host)
{
	struct mmc_data *data = host->data;
	int stat;
	unsigned long length;

	length = data->blocks * data->blocksize;
	host->datasize = 0;

	if (data->flags & MMC_DATA_READ) {
		stat = mxcmci_pull(host, data->dest, length);
		if (stat)
			return stat;
		host->datasize += length;
	} else {
		stat = mxcmci_push(host, (const void *)(data->src), length);
		if (stat)
			return stat;
		host->datasize += length;
		stat = mxcmci_poll_status(host, STATUS_WRITE_OP_DONE);
		if (stat)
			return stat;
	}
	return 0;
}

static int mxcmci_cmd_done(struct mxcmci_host *host, unsigned int stat)
{
	int datastat;
	int ret;

	ret = mxcmci_read_response(host, stat);

	if (ret) {
		mxcmci_finish_request(host, host->cmd, host->data);
		return ret;
	}

	if (!host->data) {
		mxcmci_finish_request(host, host->cmd, host->data);
		return 0;
	}

	datastat = mxcmci_transfer_data(host);
	ret = mxcmci_finish_data(host, datastat);
	mxcmci_finish_request(host, host->cmd, host->data);
	return ret;
}

static int mxcmci_request(struct mmc *mmc, struct mmc_cmd *cmd,
		struct mmc_data *data)
{
	struct mxcmci_host *host = mmc->priv;
	unsigned int cmdat = host->cmdat;
	u32 stat;
	int ret;

	host->cmdat &= ~CMD_DAT_CONT_INIT;
	if (data) {
		mxcmci_setup_data(host, data);

		cmdat |= CMD_DAT_CONT_DATA_ENABLE;

		if (data->flags & MMC_DATA_WRITE)
			cmdat |= CMD_DAT_CONT_WRITE;
	}

	if ((ret = mxcmci_start_cmd(host, cmd, cmdat))) {
		mxcmci_finish_request(host, cmd, data);
		return ret;
	}

	do {
		stat = readl(&host->base->status);
		writel(stat, &host->base->status);
	} while (!(stat & STATUS_END_CMD_RESP));

	return mxcmci_cmd_done(host, stat);
}

static void mxcmci_set_clk_rate(struct mxcmci_host *host, unsigned int clk_ios)
{
	unsigned int divider;
	int prescaler = 0;
	unsigned long clk_in = mxc_get_clock(MXC_ESDHC_CLK);

	while (prescaler <= 0x800) {
		for (divider = 1; divider <= 0xF; divider++) {
			int x;

			x = (clk_in / (divider + 1));

			if (prescaler)
				x /= (prescaler * 2);

			if (x <= clk_ios)
				break;
		}
		if (divider < 0x10)
			break;

		if (prescaler == 0)
			prescaler = 1;
		else
			prescaler <<= 1;
	}

	writel((prescaler << 4) | divider, &host->base->clk_rate);
}

static int mxcmci_set_ios(struct mmc *mmc)
{
	struct mxcmci_host *host = mmc->priv;
	if (mmc->bus_width == 4)
		host->cmdat |= CMD_DAT_CONT_BUS_WIDTH_4;
	else
		host->cmdat &= ~CMD_DAT_CONT_BUS_WIDTH_4;

	if (mmc->clock) {
		mxcmci_set_clk_rate(host, mmc->clock);
		writel(STR_STP_CLK_START_CLK, &host->base->str_stp_clk);
	} else {
		writel(STR_STP_CLK_STOP_CLK, &host->base->str_stp_clk);
	}

	host->clock = mmc->clock;

	return 0;
}

static int mxcmci_init(struct mmc *mmc)
{
	struct mxcmci_host *host = mmc->priv;

	mxcmci_softreset(host);

	host->rev_no = readl(&host->base->rev_no);
	if (host->rev_no != 0x400) {
		printf("wrong rev.no. 0x%08x. aborting.\n",
			host->rev_no);
		return -ENODEV;
	}

	/* recommended in data sheet */
	writel(0x2db4, &host->base->read_to);

	writel(0, &host->base->int_cntr);

	return 0;
}

static const struct mmc_ops mxcmci_ops = {
	.send_cmd	= mxcmci_request,
	.set_ios	= mxcmci_set_ios,
	.init		= mxcmci_init,
};

static struct mmc_config mxcmci_cfg = {
	.name		= "MXC MCI",
	.ops		= &mxcmci_ops,
	.host_caps	= MMC_MODE_4BIT,
	.voltages	= MMC_VDD_32_33 | MMC_VDD_33_34,
	.b_max		= CONFIG_SYS_MMC_MAX_BLK_COUNT,
};

static int mxcmci_initialize(struct bd_info *bis)
{
	host->base = (struct mxcmci_regs *)CONFIG_MXC_MCI_REGS_BASE;

	mxcmci_cfg.f_min = mxc_get_clock(MXC_ESDHC_CLK) >> 7;
	mxcmci_cfg.f_max = mxc_get_clock(MXC_ESDHC_CLK) >> 1;

	host->mmc = mmc_create(&mxcmci_cfg, host);
	if (host->mmc == NULL)
		return -1;

	return 0;
}

int mxc_mmc_init(struct bd_info *bis)
{
	return mxcmci_initialize(bis);
}
Commit	Line	Data
ba3dbaf2 IY	1	/*
	2	* This is a driver for the SDHC controller found in Freescale MX2/MX3
	3	* SoCs. It is basically the same hardware as found on MX1 (imxmmc.c).
	4	* Unlike the hardware found on MX1, this hardware just works and does
	5	* not need all the quirks found in imxmmc.c, hence the seperate driver.
	6	*
	7	* Copyright (C) 2009 Ilya Yanok, <yanok@emcraft.com>
	8	* Copyright (C) 2008 Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>
	9	* Copyright (C) 2006 Pavel Pisa, PiKRON <ppisa@pikron.com>
	10	*
	11	* derived from pxamci.c by Russell King
	12	*
	13	* This program is free software; you can redistribute it and/or modify
	14	* it under the terms of the GNU General Public License version 2 as
	15	* published by the Free Software Foundation.
	16	*
	17	*/
	18
	19	#include <config.h>
d678a59d	20	#include <common.h>
ba3dbaf2 IY	21	#include <command.h>
	22	#include <mmc.h>
	23	#include <part.h>
	24	#include <malloc.h>
	25	#include <mmc.h>
1045315d	26	#include <time.h>
1221ce45	27	#include <linux/errno.h>
ba3dbaf2	28	#include <asm/io.h>
ba3dbaf2	29	#include <asm/arch/clock.h>
ba3dbaf2 IY	30
	31	#define DRIVER_NAME "mxc-mmc"
	32
	33	struct mxcmci_regs {
	34	u32 str_stp_clk;
	35	u32 status;
	36	u32 clk_rate;
	37	u32 cmd_dat_cont;
	38	u32 res_to;
	39	u32 read_to;
	40	u32 blk_len;
	41	u32 nob;
	42	u32 rev_no;
	43	u32 int_cntr;
	44	u32 cmd;
	45	u32 arg;
	46	u32 pad;
	47	u32 res_fifo;
	48	u32 buffer_access;
	49	};
	50
	51	#define STR_STP_CLK_RESET (1 << 3)
	52	#define STR_STP_CLK_START_CLK (1 << 1)
	53	#define STR_STP_CLK_STOP_CLK (1 << 0)
	54
	55	#define STATUS_CARD_INSERTION (1 << 31)
	56	#define STATUS_CARD_REMOVAL (1 << 30)
	57	#define STATUS_YBUF_EMPTY (1 << 29)
	58	#define STATUS_XBUF_EMPTY (1 << 28)
	59	#define STATUS_YBUF_FULL (1 << 27)
	60	#define STATUS_XBUF_FULL (1 << 26)
	61	#define STATUS_BUF_UND_RUN (1 << 25)
	62	#define STATUS_BUF_OVFL (1 << 24)
	63	#define STATUS_SDIO_INT_ACTIVE (1 << 14)
	64	#define STATUS_END_CMD_RESP (1 << 13)
	65	#define STATUS_WRITE_OP_DONE (1 << 12)
	66	#define STATUS_DATA_TRANS_DONE (1 << 11)
	67	#define STATUS_READ_OP_DONE (1 << 11)
	68	#define STATUS_WR_CRC_ERROR_CODE_MASK (3 << 10)
	69	#define STATUS_CARD_BUS_CLK_RUN (1 << 8)
	70	#define STATUS_BUF_READ_RDY (1 << 7)
	71	#define STATUS_BUF_WRITE_RDY (1 << 6)
	72	#define STATUS_RESP_CRC_ERR (1 << 5)
	73	#define STATUS_CRC_READ_ERR (1 << 3)
	74	#define STATUS_CRC_WRITE_ERR (1 << 2)
	75	#define STATUS_TIME_OUT_RESP (1 << 1)
	76	#define STATUS_TIME_OUT_READ (1 << 0)
	77	#define STATUS_ERR_MASK 0x2f
	78
	79	#define CMD_DAT_CONT_CMD_RESP_LONG_OFF (1 << 12)
	80	#define CMD_DAT_CONT_STOP_READWAIT (1 << 11)
	81	#define CMD_DAT_CONT_START_READWAIT (1 << 10)
	82	#define CMD_DAT_CONT_BUS_WIDTH_4 (2 << 8)
	83	#define CMD_DAT_CONT_INIT (1 << 7)
	84	#define CMD_DAT_CONT_WRITE (1 << 4)
	85	#define CMD_DAT_CONT_DATA_ENABLE (1 << 3)
	86	#define CMD_DAT_CONT_RESPONSE_48BIT_CRC (1 << 0)
	87	#define CMD_DAT_CONT_RESPONSE_136BIT (2 << 0)
	88	#define CMD_DAT_CONT_RESPONSE_48BIT (3 << 0)
	89
	90	#define INT_SDIO_INT_WKP_EN (1 << 18)
	91	#define INT_CARD_INSERTION_WKP_EN (1 << 17)
	92	#define INT_CARD_REMOVAL_WKP_EN (1 << 16)
	93	#define INT_CARD_INSERTION_EN (1 << 15)
94	#define INT_CARD_REMOVAL_EN (1 << 14)
95	#define INT_SDIO_IRQ_EN (1 << 13)
96	#define INT_DAT0_EN (1 << 12)
97	#define INT_BUF_READ_EN (1 << 4)
98	#define INT_BUF_WRITE_EN (1 << 3)
99	#define INT_END_CMD_RES_EN (1 << 2)
100	#define INT_WRITE_OP_DONE_EN (1 << 1)
101	#define INT_READ_OP_EN (1 << 0)
102
103	struct mxcmci_host {
104	struct mmc *mmc;
105	struct mxcmci_regs *base;
106	int irq;
107	int detect_irq;
108	int dma;
109	int do_dma;
110	unsigned int power_mode;
111
112	struct mmc_cmd *cmd;
113	struct mmc_data *data;
114
115	unsigned int dma_nents;
116	unsigned int datasize;
117	unsigned int dma_dir;
118
119	u16 rev_no;
120	unsigned int cmdat;
121
122	int clock;
123	};
124
125	static struct mxcmci_host mxcmci_host;
93bfd616 PA	126
93bfd616 PA	127	/* maintainer note: do we really want to have a global host pointer? */
ba3dbaf2 IY	128	static struct mxcmci_host *host = &mxcmci_host;
	129
	130	static inline int mxcmci_use_dma(struct mxcmci_host *host)
	131	{
	132	return host->do_dma;
	133	}
	134
	135	static void mxcmci_softreset(struct mxcmci_host *host)
	136	{
	137	int i;
	138
	139	/* reset sequence */
99c006a3 SB	140	writel(STR_STP_CLK_RESET, &host->base->str_stp_clk);
99c006a3 SB	141	writel(STR_STP_CLK_RESET \| STR_STP_CLK_START_CLK,
ba3dbaf2 IY	142	&host->base->str_stp_clk);
	143
	144	for (i = 0; i < 8; i++)
99c006a3	145	writel(STR_STP_CLK_START_CLK, &host->base->str_stp_clk);
ba3dbaf2	146
99c006a3	147	writel(0xff, &host->base->res_to);
ba3dbaf2 IY	148	}
	149
	150	static void mxcmci_setup_data(struct mxcmci_host host, struct mmc_data data)
	151	{
	152	unsigned int nob = data->blocks;
	153	unsigned int blksz = data->blocksize;
	154	unsigned int datasize = nob * blksz;
	155
	156	host->data = data;
	157
99c006a3 SB	158	writel(nob, &host->base->nob);
99c006a3 SB	159	writel(blksz, &host->base->blk_len);
ba3dbaf2 IY	160	host->datasize = datasize;
	161	}
	162
	163	static int mxcmci_start_cmd(struct mxcmci_host host, struct mmc_cmd cmd,
	164	unsigned int cmdat)
	165	{
	166	if (host->cmd != NULL)
	167	printf("mxcmci: error!\n");
	168	host->cmd = cmd;
	169
	170	switch (cmd->resp_type) {
	171	case MMC_RSP_R1: /* short CRC, OPCODE */
	172	case MMC_RSP_R1b:/* short CRC, OPCODE, BUSY */
	173	cmdat \|= CMD_DAT_CONT_RESPONSE_48BIT_CRC;
	174	break;
	175	case MMC_RSP_R2: /* long 136 bit + CRC */
	176	cmdat \|= CMD_DAT_CONT_RESPONSE_136BIT;
	177	break;
	178	case MMC_RSP_R3: /* short */
	179	cmdat \|= CMD_DAT_CONT_RESPONSE_48BIT;
	180	break;
	181	case MMC_RSP_NONE:
	182	break;
	183	default:
	184	printf("mxcmci: unhandled response type 0x%x\n",
	185	cmd->resp_type);
	186	return -EINVAL;
	187	}
	188
99c006a3	189	writel(cmd->cmdidx, &host->base->cmd);
ba3dbaf2	190	writel(cmd->cmdarg, &host->base->arg);
99c006a3	191	writel(cmdat, &host->base->cmd_dat_cont);
ba3dbaf2 IY	192
	193	return 0;
	194	}
	195
	196	static void mxcmci_finish_request(struct mxcmci_host *host,
	197	struct mmc_cmd cmd, struct mmc_data data)
	198	{
	199	host->cmd = NULL;
	200	host->data = NULL;
	201	}
	202
	203	static int mxcmci_finish_data(struct mxcmci_host *host, unsigned int stat)
	204	{
	205	int data_error = 0;
	206
	207	if (stat & STATUS_ERR_MASK) {
	208	printf("request failed. status: 0x%08x\n",
	209	stat);
	210	if (stat & STATUS_CRC_READ_ERR) {
	211	data_error = -EILSEQ;
	212	} else if (stat & STATUS_CRC_WRITE_ERR) {
	213	u32 err_code = (stat >> 9) & 0x3;
	214	if (err_code == 2) /* No CRC response */
915ffa52	215	data_error = -ETIMEDOUT;
ba3dbaf2 IY	216	else
	217	data_error = -EILSEQ;
	218	} else if (stat & STATUS_TIME_OUT_READ) {
915ffa52	219	data_error = -ETIMEDOUT;
ba3dbaf2 IY	220	} else {
	221	data_error = -EIO;
	222	}
	223	}
	224
	225	host->data = NULL;
	226
	227	return data_error;
	228	}
	229
	230	static int mxcmci_read_response(struct mxcmci_host *host, unsigned int stat)
	231	{
	232	struct mmc_cmd *cmd = host->cmd;
	233	int i;
	234	u32 a, b, c;
	235	u32 resp = (u32 )cmd->response;
	236
	237	if (!cmd)
	238	return 0;
	239
	240	if (stat & STATUS_TIME_OUT_RESP) {
	241	printf("CMD TIMEOUT\n");
915ffa52	242	return -ETIMEDOUT;
ba3dbaf2 IY	243	} else if (stat & STATUS_RESP_CRC_ERR && cmd->resp_type & MMC_RSP_CRC) {
	244	printf("cmd crc error\n");
	245	return -EILSEQ;
	246	}
	247
	248	if (cmd->resp_type & MMC_RSP_PRESENT) {
	249	if (cmd->resp_type & MMC_RSP_136) {
	250	for (i = 0; i < 4; i++) {
99c006a3 SB	251	a = readl(&host->base->res_fifo) & 0xFFFF;
99c006a3 SB	252	b = readl(&host->base->res_fifo) & 0xFFFF;
ba3dbaf2 IY	253	resp[i] = a << 16 \| b;
	254	}
	255	} else {
99c006a3 SB	256	a = readl(&host->base->res_fifo) & 0xFFFF;
	257	b = readl(&host->base->res_fifo) & 0xFFFF;
	258	c = readl(&host->base->res_fifo) & 0xFFFF;
ba3dbaf2 IY	259	resp[0] = a << 24 \| b << 8 \| c >> 8;
	260	}
	261	}
	262	return 0;
	263	}
	264
	265	static int mxcmci_poll_status(struct mxcmci_host *host, u32 mask)
	266	{
	267	u32 stat;
	268	unsigned long timeout = get_ticks() + CONFIG_SYS_HZ;
	269
	270	do {
	271	stat = readl(&host->base->status);
	272	if (stat & STATUS_ERR_MASK)
	273	return stat;
	274	if (timeout < get_ticks())
	275	return STATUS_TIME_OUT_READ;
	276	if (stat & mask)
	277	return 0;
	278	} while (1);
	279	}
	280
	281	static int mxcmci_pull(struct mxcmci_host host, void _buf, int bytes)
	282	{
	283	unsigned int stat;
	284	u32 *buf = _buf;
	285
	286	while (bytes > 3) {
	287	stat = mxcmci_poll_status(host,
	288	STATUS_BUF_READ_RDY \| STATUS_READ_OP_DONE);
	289	if (stat)
	290	return stat;
	291	*buf++ = readl(&host->base->buffer_access);
	292	bytes -= 4;
	293	}
	294
	295	if (bytes) {
	296	u8 b = (u8 )buf;
	297	u32 tmp;
	298
	299	stat = mxcmci_poll_status(host,
	300	STATUS_BUF_READ_RDY \| STATUS_READ_OP_DONE);
	301	if (stat)
	302	return stat;
	303	tmp = readl(&host->base->buffer_access);
	304	memcpy(b, &tmp, bytes);
	305	}
	306
	307	return 0;
	308	}
	309
	310	static int mxcmci_push(struct mxcmci_host host, const void _buf, int bytes)
	311	{
	312	unsigned int stat;
	313	const u32 *buf = _buf;
	314
	315	while (bytes > 3) {
	316	stat = mxcmci_poll_status(host, STATUS_BUF_WRITE_RDY);
	317	if (stat)
	318	return stat;
	319	writel(*buf++, &host->base->buffer_access);
	320	bytes -= 4;
	321	}
	322
323	if (bytes) {
324	const u8 b = (u8 )buf;
325	u32 tmp;
326
327	stat = mxcmci_poll_status(host, STATUS_BUF_WRITE_RDY);
328	if (stat)
329	return stat;
330
331	memcpy(&tmp, b, bytes);
332	writel(tmp, &host->base->buffer_access);
333	}
334
335	stat = mxcmci_poll_status(host, STATUS_BUF_WRITE_RDY);
336	if (stat)
337	return stat;
338
339	return 0;
340	}
341
342	static int mxcmci_transfer_data(struct mxcmci_host *host)
343	{
344	struct mmc_data *data = host->data;
345	int stat;
346	unsigned long length;
347
348	length = data->blocks * data->blocksize;
349	host->datasize = 0;
350
351	if (data->flags & MMC_DATA_READ) {
352	stat = mxcmci_pull(host, data->dest, length);
353	if (stat)
354	return stat;
355	host->datasize += length;
356	} else {
357	stat = mxcmci_push(host, (const void *)(data->src), length);
358	if (stat)
359	return stat;
360	host->datasize += length;
361	stat = mxcmci_poll_status(host, STATUS_WRITE_OP_DONE);
362	if (stat)
363	return stat;
364	}
365	return 0;
366	}
367
368	static int mxcmci_cmd_done(struct mxcmci_host *host, unsigned int stat)
369	{
370	int datastat;
371	int ret;
372
373	ret = mxcmci_read_response(host, stat);
374
375	if (ret) {
376	mxcmci_finish_request(host, host->cmd, host->data);
377	return ret;
378	}
379
380	if (!host->data) {
381	mxcmci_finish_request(host, host->cmd, host->data);
382	return 0;
383	}
384
385	datastat = mxcmci_transfer_data(host);
386	ret = mxcmci_finish_data(host, datastat);
387	mxcmci_finish_request(host, host->cmd, host->data);
388	return ret;
389	}
390
391	static int mxcmci_request(struct mmc mmc, struct mmc_cmd cmd,
392	struct mmc_data *data)
393	{
394	struct mxcmci_host *host = mmc->priv;
395	unsigned int cmdat = host->cmdat;
396	u32 stat;
397	int ret;
398
399	host->cmdat &= ~CMD_DAT_CONT_INIT;
400	if (data) {
401	mxcmci_setup_data(host, data);
402
403	cmdat \|= CMD_DAT_CONT_DATA_ENABLE;
404
405	if (data->flags & MMC_DATA_WRITE)
406	cmdat \|= CMD_DAT_CONT_WRITE;
407	}
408
409	if ((ret = mxcmci_start_cmd(host, cmd, cmdat))) {
410	mxcmci_finish_request(host, cmd, data);
411	return ret;
412	}
413
414	do {
415	stat = readl(&host->base->status);
416	writel(stat, &host->base->status);
417	} while (!(stat & STATUS_END_CMD_RESP));
418
419	return mxcmci_cmd_done(host, stat);
420	}
421
422	static void mxcmci_set_clk_rate(struct mxcmci_host *host, unsigned int clk_ios)
423	{
424	unsigned int divider;
425	int prescaler = 0;
fa47a286	426	unsigned long clk_in = mxc_get_clock(MXC_ESDHC_CLK);
ba3dbaf2 IY	427
	428	while (prescaler <= 0x800) {
	429	for (divider = 1; divider <= 0xF; divider++) {
	430	int x;
	431
	432	x = (clk_in / (divider + 1));
	433
	434	if (prescaler)
	435	x /= (prescaler * 2);
	436
	437	if (x <= clk_ios)
	438	break;
	439	}
	440	if (divider < 0x10)
	441	break;
	442
	443	if (prescaler == 0)
	444	prescaler = 1;
	445	else
	446	prescaler <<= 1;
	447	}
	448
99c006a3	449	writel((prescaler << 4) \| divider, &host->base->clk_rate);
ba3dbaf2 IY	450	}
ba3dbaf2 IY	451
07b0b9c0	452	static int mxcmci_set_ios(struct mmc *mmc)
ba3dbaf2 IY	453	{
	454	struct mxcmci_host *host = mmc->priv;
	455	if (mmc->bus_width == 4)
	456	host->cmdat \|= CMD_DAT_CONT_BUS_WIDTH_4;
	457	else
	458	host->cmdat &= ~CMD_DAT_CONT_BUS_WIDTH_4;
	459
	460	if (mmc->clock) {
	461	mxcmci_set_clk_rate(host, mmc->clock);
99c006a3	462	writel(STR_STP_CLK_START_CLK, &host->base->str_stp_clk);
ba3dbaf2	463	} else {
99c006a3	464	writel(STR_STP_CLK_STOP_CLK, &host->base->str_stp_clk);
ba3dbaf2 IY	465	}
	466
	467	host->clock = mmc->clock;
07b0b9c0 JC	468
07b0b9c0 JC	469	return 0;
ba3dbaf2 IY	470	}
	471
	472	static int mxcmci_init(struct mmc *mmc)
	473	{
	474	struct mxcmci_host *host = mmc->priv;
	475
	476	mxcmci_softreset(host);
	477
99c006a3	478	host->rev_no = readl(&host->base->rev_no);
ba3dbaf2 IY	479	if (host->rev_no != 0x400) {
	480	printf("wrong rev.no. 0x%08x. aborting.\n",
	481	host->rev_no);
	482	return -ENODEV;
	483	}
	484
	485	/* recommended in data sheet */
99c006a3	486	writel(0x2db4, &host->base->read_to);
ba3dbaf2 IY	487
	488	writel(0, &host->base->int_cntr);
	489
	490	return 0;
	491	}
	492
ab769f22 PA	493	static const struct mmc_ops mxcmci_ops = {
	494	.send_cmd = mxcmci_request,
	495	.set_ios = mxcmci_set_ios,
	496	.init = mxcmci_init,
	497	};
	498
93bfd616 PA	499	static struct mmc_config mxcmci_cfg = {
	500	.name = "MXC MCI",
	501	.ops = &mxcmci_ops,
	502	.host_caps = MMC_MODE_4BIT,
	503	.voltages = MMC_VDD_32_33 \| MMC_VDD_33_34,
	504	.b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT,
	505	};
	506
b75d8dc5	507	static int mxcmci_initialize(struct bd_info *bis)
ba3dbaf2	508	{
ba3dbaf2	509	host->base = (struct mxcmci_regs *)CONFIG_MXC_MCI_REGS_BASE;
ba3dbaf2	510
93bfd616 PA	511	mxcmci_cfg.f_min = mxc_get_clock(MXC_ESDHC_CLK) >> 7;
93bfd616 PA	512	mxcmci_cfg.f_max = mxc_get_clock(MXC_ESDHC_CLK) >> 1;
8feafcc4	513
93bfd616 PA	514	host->mmc = mmc_create(&mxcmci_cfg, host);
	515	if (host->mmc == NULL)
	516	return -1;
ba3dbaf2 IY	517
	518	return 0;
	519	}
	520
b75d8dc5	521	int mxc_mmc_init(struct bd_info *bis)
ba3dbaf2 IY	522	{
	523	return mxcmci_initialize(bis);
	524	}